1bebd4c79SHawking Zhang /* 2bebd4c79SHawking Zhang * Copyright 2020 Advanced Micro Devices, Inc. 3bebd4c79SHawking Zhang * 4bebd4c79SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5bebd4c79SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6bebd4c79SHawking Zhang * to deal in the Software without restriction, including without limitation 7bebd4c79SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8bebd4c79SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9bebd4c79SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10bebd4c79SHawking Zhang * 11bebd4c79SHawking Zhang * The above copyright notice and this permission notice shall be included in 12bebd4c79SHawking Zhang * all copies or substantial portions of the Software. 13bebd4c79SHawking Zhang * 14bebd4c79SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15bebd4c79SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16bebd4c79SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17bebd4c79SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18bebd4c79SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19bebd4c79SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20bebd4c79SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21bebd4c79SHawking Zhang * 22bebd4c79SHawking Zhang */ 23bebd4c79SHawking Zhang 24bebd4c79SHawking Zhang #include <linux/pci.h> 25bebd4c79SHawking Zhang 26bebd4c79SHawking Zhang #include "amdgpu.h" 27bebd4c79SHawking Zhang #include "amdgpu_ih.h" 28bebd4c79SHawking Zhang #include "soc15.h" 29bebd4c79SHawking Zhang 30bebd4c79SHawking Zhang #include "oss/osssys_4_2_0_offset.h" 31bebd4c79SHawking Zhang #include "oss/osssys_4_2_0_sh_mask.h" 32bebd4c79SHawking Zhang 33bebd4c79SHawking Zhang #include "soc15_common.h" 34bebd4c79SHawking Zhang #include "vega20_ih.h" 35bebd4c79SHawking Zhang 36bebd4c79SHawking Zhang #define MAX_REARM_RETRY 10 37bebd4c79SHawking Zhang 38bebd4c79SHawking Zhang static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev); 39bebd4c79SHawking Zhang 40bebd4c79SHawking Zhang /** 41bebd4c79SHawking Zhang * vega20_ih_init_register_offset - Initialize register offset for ih rings 42bebd4c79SHawking Zhang * 43bebd4c79SHawking Zhang * @adev: amdgpu_device pointer 44bebd4c79SHawking Zhang * 45bebd4c79SHawking Zhang * Initialize register offset ih rings (VEGA20). 46bebd4c79SHawking Zhang */ 47bebd4c79SHawking Zhang static void vega20_ih_init_register_offset(struct amdgpu_device *adev) 48bebd4c79SHawking Zhang { 49bebd4c79SHawking Zhang struct amdgpu_ih_regs *ih_regs; 50bebd4c79SHawking Zhang 51bebd4c79SHawking Zhang if (adev->irq.ih.ring_size) { 52bebd4c79SHawking Zhang ih_regs = &adev->irq.ih.ih_regs; 53bebd4c79SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); 54bebd4c79SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); 55bebd4c79SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 56bebd4c79SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 57bebd4c79SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 58bebd4c79SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); 59bebd4c79SHawking Zhang ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); 60bebd4c79SHawking Zhang ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); 61bebd4c79SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; 62bebd4c79SHawking Zhang } 63bebd4c79SHawking Zhang 64bebd4c79SHawking Zhang if (adev->irq.ih1.ring_size) { 65bebd4c79SHawking Zhang ih_regs = &adev->irq.ih1.ih_regs; 66bebd4c79SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); 67bebd4c79SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); 68bebd4c79SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 69bebd4c79SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 70bebd4c79SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 71bebd4c79SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1); 72bebd4c79SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; 73bebd4c79SHawking Zhang } 74bebd4c79SHawking Zhang 75bebd4c79SHawking Zhang if (adev->irq.ih2.ring_size) { 76bebd4c79SHawking Zhang ih_regs = &adev->irq.ih2.ih_regs; 77bebd4c79SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); 78bebd4c79SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2); 79bebd4c79SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 80bebd4c79SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 81bebd4c79SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 82bebd4c79SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2); 83bebd4c79SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2; 84bebd4c79SHawking Zhang } 85bebd4c79SHawking Zhang } 86bebd4c79SHawking Zhang 87bebd4c79SHawking Zhang /** 88bebd4c79SHawking Zhang * vega20_ih_toggle_ring_interrupts - toggle the interrupt ring buffer 89bebd4c79SHawking Zhang * 90bebd4c79SHawking Zhang * @adev: amdgpu_device pointer 91*93a2ba14SLee Jones * @ih: amdgpu_ih_ring pointer 92bebd4c79SHawking Zhang * @enable: true - enable the interrupts, false - disable the interrupts 93bebd4c79SHawking Zhang * 94bebd4c79SHawking Zhang * Toggle the interrupt ring buffer (VEGA20) 95bebd4c79SHawking Zhang */ 96bebd4c79SHawking Zhang static int vega20_ih_toggle_ring_interrupts(struct amdgpu_device *adev, 97bebd4c79SHawking Zhang struct amdgpu_ih_ring *ih, 98bebd4c79SHawking Zhang bool enable) 99bebd4c79SHawking Zhang { 100bebd4c79SHawking Zhang struct amdgpu_ih_regs *ih_regs; 101bebd4c79SHawking Zhang uint32_t tmp; 102bebd4c79SHawking Zhang 103bebd4c79SHawking Zhang ih_regs = &ih->ih_regs; 104bebd4c79SHawking Zhang 105bebd4c79SHawking Zhang tmp = RREG32(ih_regs->ih_rb_cntl); 106bebd4c79SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); 107bebd4c79SHawking Zhang /* enable_intr field is only valid in ring0 */ 108bebd4c79SHawking Zhang if (ih == &adev->irq.ih) 109bebd4c79SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); 110bebd4c79SHawking Zhang if (amdgpu_sriov_vf(adev)) { 111bebd4c79SHawking Zhang if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 112bebd4c79SHawking Zhang dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 113bebd4c79SHawking Zhang return -ETIMEDOUT; 114bebd4c79SHawking Zhang } 115bebd4c79SHawking Zhang } else { 116bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_cntl, tmp); 117bebd4c79SHawking Zhang } 118bebd4c79SHawking Zhang 119bebd4c79SHawking Zhang if (enable) { 120bebd4c79SHawking Zhang ih->enabled = true; 121bebd4c79SHawking Zhang } else { 122bebd4c79SHawking Zhang /* set rptr, wptr to 0 */ 123bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_rptr, 0); 124bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_wptr, 0); 125bebd4c79SHawking Zhang ih->enabled = false; 126bebd4c79SHawking Zhang ih->rptr = 0; 127bebd4c79SHawking Zhang } 128bebd4c79SHawking Zhang 129bebd4c79SHawking Zhang return 0; 130bebd4c79SHawking Zhang } 131bebd4c79SHawking Zhang 132bebd4c79SHawking Zhang /** 133bebd4c79SHawking Zhang * vega20_ih_toggle_interrupts - Toggle all the available interrupt ring buffers 134bebd4c79SHawking Zhang * 135bebd4c79SHawking Zhang * @adev: amdgpu_device pointer 136bebd4c79SHawking Zhang * @enable: enable or disable interrupt ring buffers 137bebd4c79SHawking Zhang * 138bebd4c79SHawking Zhang * Toggle all the available interrupt ring buffers (VEGA20). 139bebd4c79SHawking Zhang */ 140bebd4c79SHawking Zhang static int vega20_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable) 141bebd4c79SHawking Zhang { 142bebd4c79SHawking Zhang struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 143bebd4c79SHawking Zhang int i; 144bebd4c79SHawking Zhang int r; 145bebd4c79SHawking Zhang 146bebd4c79SHawking Zhang for (i = 0; i < ARRAY_SIZE(ih); i++) { 147bebd4c79SHawking Zhang if (ih[i]->ring_size) { 148bebd4c79SHawking Zhang r = vega20_ih_toggle_ring_interrupts(adev, ih[i], enable); 149bebd4c79SHawking Zhang if (r) 150bebd4c79SHawking Zhang return r; 151bebd4c79SHawking Zhang } 152bebd4c79SHawking Zhang } 153bebd4c79SHawking Zhang 154bebd4c79SHawking Zhang return 0; 155bebd4c79SHawking Zhang } 156bebd4c79SHawking Zhang 157bebd4c79SHawking Zhang static uint32_t vega20_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 158bebd4c79SHawking Zhang { 159bebd4c79SHawking Zhang int rb_bufsz = order_base_2(ih->ring_size / 4); 160bebd4c79SHawking Zhang 161bebd4c79SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 162bebd4c79SHawking Zhang MC_SPACE, ih->use_bus_addr ? 1 : 4); 163bebd4c79SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 164bebd4c79SHawking Zhang WPTR_OVERFLOW_CLEAR, 1); 165bebd4c79SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 166bebd4c79SHawking Zhang WPTR_OVERFLOW_ENABLE, 1); 167bebd4c79SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 168bebd4c79SHawking Zhang /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 169bebd4c79SHawking Zhang * value is written to memory 170bebd4c79SHawking Zhang */ 171bebd4c79SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 172bebd4c79SHawking Zhang WPTR_WRITEBACK_ENABLE, 1); 173bebd4c79SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 174bebd4c79SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 175bebd4c79SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 176bebd4c79SHawking Zhang 177bebd4c79SHawking Zhang return ih_rb_cntl; 178bebd4c79SHawking Zhang } 179bebd4c79SHawking Zhang 180bebd4c79SHawking Zhang static uint32_t vega20_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 181bebd4c79SHawking Zhang { 182bebd4c79SHawking Zhang u32 ih_doorbell_rtpr = 0; 183bebd4c79SHawking Zhang 184bebd4c79SHawking Zhang if (ih->use_doorbell) { 185bebd4c79SHawking Zhang ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 186bebd4c79SHawking Zhang IH_DOORBELL_RPTR, OFFSET, 187bebd4c79SHawking Zhang ih->doorbell_index); 188bebd4c79SHawking Zhang ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 189bebd4c79SHawking Zhang IH_DOORBELL_RPTR, 190bebd4c79SHawking Zhang ENABLE, 1); 191bebd4c79SHawking Zhang } else { 192bebd4c79SHawking Zhang ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 193bebd4c79SHawking Zhang IH_DOORBELL_RPTR, 194bebd4c79SHawking Zhang ENABLE, 0); 195bebd4c79SHawking Zhang } 196bebd4c79SHawking Zhang return ih_doorbell_rtpr; 197bebd4c79SHawking Zhang } 198bebd4c79SHawking Zhang 199bebd4c79SHawking Zhang /** 200bebd4c79SHawking Zhang * vega20_ih_enable_ring - enable an ih ring buffer 201bebd4c79SHawking Zhang * 202bebd4c79SHawking Zhang * @adev: amdgpu_device pointer 203bebd4c79SHawking Zhang * @ih: amdgpu_ih_ring pointer 204bebd4c79SHawking Zhang * 205bebd4c79SHawking Zhang * Enable an ih ring buffer (VEGA20) 206bebd4c79SHawking Zhang */ 207bebd4c79SHawking Zhang static int vega20_ih_enable_ring(struct amdgpu_device *adev, 208bebd4c79SHawking Zhang struct amdgpu_ih_ring *ih) 209bebd4c79SHawking Zhang { 210bebd4c79SHawking Zhang struct amdgpu_ih_regs *ih_regs; 211bebd4c79SHawking Zhang uint32_t tmp; 212bebd4c79SHawking Zhang 213bebd4c79SHawking Zhang ih_regs = &ih->ih_regs; 214bebd4c79SHawking Zhang 215bebd4c79SHawking Zhang /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 216bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); 217bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); 218bebd4c79SHawking Zhang 219bebd4c79SHawking Zhang tmp = RREG32(ih_regs->ih_rb_cntl); 220bebd4c79SHawking Zhang tmp = vega20_ih_rb_cntl(ih, tmp); 221bebd4c79SHawking Zhang if (ih == &adev->irq.ih) 222bebd4c79SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); 223bebd4c79SHawking Zhang if (ih == &adev->irq.ih1) { 224bebd4c79SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0); 225bebd4c79SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); 226bebd4c79SHawking Zhang } 227bebd4c79SHawking Zhang if (amdgpu_sriov_vf(adev)) { 228bebd4c79SHawking Zhang if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 229bebd4c79SHawking Zhang dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 230bebd4c79SHawking Zhang return -ETIMEDOUT; 231bebd4c79SHawking Zhang } 232bebd4c79SHawking Zhang } else { 233bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_cntl, tmp); 234bebd4c79SHawking Zhang } 235bebd4c79SHawking Zhang 236bebd4c79SHawking Zhang if (ih == &adev->irq.ih) { 237bebd4c79SHawking Zhang /* set the ih ring 0 writeback address whether it's enabled or not */ 238bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); 239bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); 240bebd4c79SHawking Zhang } 241bebd4c79SHawking Zhang 242bebd4c79SHawking Zhang /* set rptr, wptr to 0 */ 243bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_wptr, 0); 244bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_rptr, 0); 245bebd4c79SHawking Zhang 246bebd4c79SHawking Zhang WREG32(ih_regs->ih_doorbell_rptr, vega20_ih_doorbell_rptr(ih)); 247bebd4c79SHawking Zhang 248bebd4c79SHawking Zhang return 0; 249bebd4c79SHawking Zhang } 250bebd4c79SHawking Zhang 251bebd4c79SHawking Zhang /** 252726e5b37SHawking Zhang * vega20_ih_reroute_ih - reroute VMC/UTCL2 ih to an ih ring 253726e5b37SHawking Zhang * 254726e5b37SHawking Zhang * @adev: amdgpu_device pointer 255726e5b37SHawking Zhang * 256726e5b37SHawking Zhang * Reroute VMC and UMC interrupts on primary ih ring to 257726e5b37SHawking Zhang * ih ring 1 so they won't lose when bunches of page faults 258726e5b37SHawking Zhang * interrupts overwhelms the interrupt handler(VEGA20) 259726e5b37SHawking Zhang */ 260726e5b37SHawking Zhang static void vega20_ih_reroute_ih(struct amdgpu_device *adev) 261726e5b37SHawking Zhang { 262726e5b37SHawking Zhang uint32_t tmp; 263726e5b37SHawking Zhang 264726e5b37SHawking Zhang /* vega20 ih reroute will go through psp 265726e5b37SHawking Zhang * this function is only used for arcturus 266726e5b37SHawking Zhang */ 267726e5b37SHawking Zhang if (adev->asic_type == CHIP_ARCTURUS) { 268726e5b37SHawking Zhang /* Reroute to IH ring 1 for VMC */ 269726e5b37SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x12); 270726e5b37SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); 271726e5b37SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); 272726e5b37SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 273726e5b37SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); 274726e5b37SHawking Zhang 275726e5b37SHawking Zhang /* Reroute IH ring 1 for UTCL2 */ 276726e5b37SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x1B); 277726e5b37SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); 278726e5b37SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 279726e5b37SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); 280726e5b37SHawking Zhang } 281726e5b37SHawking Zhang } 282726e5b37SHawking Zhang 283726e5b37SHawking Zhang /** 284bebd4c79SHawking Zhang * vega20_ih_irq_init - init and enable the interrupt ring 285bebd4c79SHawking Zhang * 286bebd4c79SHawking Zhang * @adev: amdgpu_device pointer 287bebd4c79SHawking Zhang * 288bebd4c79SHawking Zhang * Allocate a ring buffer for the interrupt controller, 289bebd4c79SHawking Zhang * enable the RLC, disable interrupts, enable the IH 290bebd4c79SHawking Zhang * ring buffer and enable it (VI). 291bebd4c79SHawking Zhang * Called at device load and reume. 292bebd4c79SHawking Zhang * Returns 0 for success, errors for failure. 293bebd4c79SHawking Zhang */ 294bebd4c79SHawking Zhang static int vega20_ih_irq_init(struct amdgpu_device *adev) 295bebd4c79SHawking Zhang { 296bebd4c79SHawking Zhang struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 297bebd4c79SHawking Zhang u32 ih_chicken; 298bebd4c79SHawking Zhang int ret; 299bebd4c79SHawking Zhang int i; 300bebd4c79SHawking Zhang u32 tmp; 301bebd4c79SHawking Zhang 302bebd4c79SHawking Zhang /* disable irqs */ 303bebd4c79SHawking Zhang ret = vega20_ih_toggle_interrupts(adev, false); 304bebd4c79SHawking Zhang if (ret) 305bebd4c79SHawking Zhang return ret; 306bebd4c79SHawking Zhang 307bebd4c79SHawking Zhang adev->nbio.funcs->ih_control(adev); 308bebd4c79SHawking Zhang 309bebd4c79SHawking Zhang if (adev->asic_type == CHIP_ARCTURUS && 310bebd4c79SHawking Zhang adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 311bebd4c79SHawking Zhang ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 312bebd4c79SHawking Zhang if (adev->irq.ih.use_bus_addr) { 313bebd4c79SHawking Zhang ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 314bebd4c79SHawking Zhang MC_SPACE_GPA_ENABLE, 1); 315bebd4c79SHawking Zhang } 316bebd4c79SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 317bebd4c79SHawking Zhang } 318bebd4c79SHawking Zhang 319bebd4c79SHawking Zhang for (i = 0; i < ARRAY_SIZE(ih); i++) { 320bebd4c79SHawking Zhang if (ih[i]->ring_size) { 321726e5b37SHawking Zhang if (i == 1) 322726e5b37SHawking Zhang vega20_ih_reroute_ih(adev); 323bebd4c79SHawking Zhang ret = vega20_ih_enable_ring(adev, ih[i]); 324bebd4c79SHawking Zhang if (ret) 325bebd4c79SHawking Zhang return ret; 326bebd4c79SHawking Zhang } 327bebd4c79SHawking Zhang } 328bebd4c79SHawking Zhang 329bebd4c79SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 330bebd4c79SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 331bebd4c79SHawking Zhang CLIENT18_IS_STORM_CLIENT, 1); 332bebd4c79SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 333bebd4c79SHawking Zhang 334bebd4c79SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 335bebd4c79SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 336bebd4c79SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 337bebd4c79SHawking Zhang 338bebd4c79SHawking Zhang pci_set_master(adev->pdev); 339bebd4c79SHawking Zhang 340bebd4c79SHawking Zhang /* enable interrupts */ 341bebd4c79SHawking Zhang ret = vega20_ih_toggle_interrupts(adev, true); 342bebd4c79SHawking Zhang if (ret) 343bebd4c79SHawking Zhang return ret; 344bebd4c79SHawking Zhang 345f44a6c76SHawking Zhang if (adev->irq.ih_soft.ring_size) 346f44a6c76SHawking Zhang adev->irq.ih_soft.enabled = true; 347f44a6c76SHawking Zhang 348bebd4c79SHawking Zhang return 0; 349bebd4c79SHawking Zhang } 350bebd4c79SHawking Zhang 351bebd4c79SHawking Zhang /** 352bebd4c79SHawking Zhang * vega20_ih_irq_disable - disable interrupts 353bebd4c79SHawking Zhang * 354bebd4c79SHawking Zhang * @adev: amdgpu_device pointer 355bebd4c79SHawking Zhang * 356bebd4c79SHawking Zhang * Disable interrupts on the hw (VEGA20). 357bebd4c79SHawking Zhang */ 358bebd4c79SHawking Zhang static void vega20_ih_irq_disable(struct amdgpu_device *adev) 359bebd4c79SHawking Zhang { 360bebd4c79SHawking Zhang vega20_ih_toggle_interrupts(adev, false); 361bebd4c79SHawking Zhang 362bebd4c79SHawking Zhang /* Wait and acknowledge irq */ 363bebd4c79SHawking Zhang mdelay(1); 364bebd4c79SHawking Zhang } 365bebd4c79SHawking Zhang 366bebd4c79SHawking Zhang /** 367bebd4c79SHawking Zhang * vega20_ih_get_wptr - get the IH ring buffer wptr 368bebd4c79SHawking Zhang * 369bebd4c79SHawking Zhang * @adev: amdgpu_device pointer 370*93a2ba14SLee Jones * @ih: amdgpu_ih_ring pointer 371bebd4c79SHawking Zhang * 372bebd4c79SHawking Zhang * Get the IH ring buffer wptr from either the register 373bebd4c79SHawking Zhang * or the writeback memory buffer (VEGA20). Also check for 374bebd4c79SHawking Zhang * ring buffer overflow and deal with it. 375bebd4c79SHawking Zhang * Returns the value of the wptr. 376bebd4c79SHawking Zhang */ 377bebd4c79SHawking Zhang static u32 vega20_ih_get_wptr(struct amdgpu_device *adev, 378bebd4c79SHawking Zhang struct amdgpu_ih_ring *ih) 379bebd4c79SHawking Zhang { 380bebd4c79SHawking Zhang u32 wptr, tmp; 381bebd4c79SHawking Zhang struct amdgpu_ih_regs *ih_regs; 382bebd4c79SHawking Zhang 383bebd4c79SHawking Zhang wptr = le32_to_cpu(*ih->wptr_cpu); 384bebd4c79SHawking Zhang ih_regs = &ih->ih_regs; 385bebd4c79SHawking Zhang 386bebd4c79SHawking Zhang if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 387bebd4c79SHawking Zhang goto out; 388bebd4c79SHawking Zhang 389bebd4c79SHawking Zhang /* Double check that the overflow wasn't already cleared. */ 390bebd4c79SHawking Zhang wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); 391bebd4c79SHawking Zhang if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 392bebd4c79SHawking Zhang goto out; 393bebd4c79SHawking Zhang 394bebd4c79SHawking Zhang wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 395bebd4c79SHawking Zhang 396bebd4c79SHawking Zhang /* When a ring buffer overflow happen start parsing interrupt 397bebd4c79SHawking Zhang * from the last not overwritten vector (wptr + 32). Hopefully 398bebd4c79SHawking Zhang * this should allow us to catchup. 399bebd4c79SHawking Zhang */ 400bebd4c79SHawking Zhang tmp = (wptr + 32) & ih->ptr_mask; 401bebd4c79SHawking Zhang dev_warn(adev->dev, "IH ring buffer overflow " 402bebd4c79SHawking Zhang "(0x%08X, 0x%08X, 0x%08X)\n", 403bebd4c79SHawking Zhang wptr, ih->rptr, tmp); 404bebd4c79SHawking Zhang ih->rptr = tmp; 405bebd4c79SHawking Zhang 406bebd4c79SHawking Zhang tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); 407bebd4c79SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 408bebd4c79SHawking Zhang WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 409bebd4c79SHawking Zhang 410bebd4c79SHawking Zhang out: 411bebd4c79SHawking Zhang return (wptr & ih->ptr_mask); 412bebd4c79SHawking Zhang } 413bebd4c79SHawking Zhang 414bebd4c79SHawking Zhang /** 415bebd4c79SHawking Zhang * vega20_ih_irq_rearm - rearm IRQ if lost 416bebd4c79SHawking Zhang * 417bebd4c79SHawking Zhang * @adev: amdgpu_device pointer 418*93a2ba14SLee Jones * @ih: amdgpu_ih_ring pointer 419bebd4c79SHawking Zhang * 420bebd4c79SHawking Zhang */ 421bebd4c79SHawking Zhang static void vega20_ih_irq_rearm(struct amdgpu_device *adev, 422bebd4c79SHawking Zhang struct amdgpu_ih_ring *ih) 423bebd4c79SHawking Zhang { 424bebd4c79SHawking Zhang uint32_t v = 0; 425bebd4c79SHawking Zhang uint32_t i = 0; 426bebd4c79SHawking Zhang struct amdgpu_ih_regs *ih_regs; 427bebd4c79SHawking Zhang 428bebd4c79SHawking Zhang ih_regs = &ih->ih_regs; 429bebd4c79SHawking Zhang 430bebd4c79SHawking Zhang /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */ 431bebd4c79SHawking Zhang for (i = 0; i < MAX_REARM_RETRY; i++) { 432bebd4c79SHawking Zhang v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); 433bebd4c79SHawking Zhang if ((v < ih->ring_size) && (v != ih->rptr)) 434bebd4c79SHawking Zhang WDOORBELL32(ih->doorbell_index, ih->rptr); 435bebd4c79SHawking Zhang else 436bebd4c79SHawking Zhang break; 437bebd4c79SHawking Zhang } 438bebd4c79SHawking Zhang } 439bebd4c79SHawking Zhang 440bebd4c79SHawking Zhang /** 441bebd4c79SHawking Zhang * vega20_ih_set_rptr - set the IH ring buffer rptr 442bebd4c79SHawking Zhang * 443bebd4c79SHawking Zhang * @adev: amdgpu_device pointer 444*93a2ba14SLee Jones * @ih: amdgpu_ih_ring pointer 445bebd4c79SHawking Zhang * 446bebd4c79SHawking Zhang * Set the IH ring buffer rptr. 447bebd4c79SHawking Zhang */ 448bebd4c79SHawking Zhang static void vega20_ih_set_rptr(struct amdgpu_device *adev, 449bebd4c79SHawking Zhang struct amdgpu_ih_ring *ih) 450bebd4c79SHawking Zhang { 451bebd4c79SHawking Zhang struct amdgpu_ih_regs *ih_regs; 452bebd4c79SHawking Zhang 453bebd4c79SHawking Zhang if (ih->use_doorbell) { 454bebd4c79SHawking Zhang /* XXX check if swapping is necessary on BE */ 455bebd4c79SHawking Zhang *ih->rptr_cpu = ih->rptr; 456bebd4c79SHawking Zhang WDOORBELL32(ih->doorbell_index, ih->rptr); 457bebd4c79SHawking Zhang 458bebd4c79SHawking Zhang if (amdgpu_sriov_vf(adev)) 459bebd4c79SHawking Zhang vega20_ih_irq_rearm(adev, ih); 460bebd4c79SHawking Zhang } else { 461bebd4c79SHawking Zhang ih_regs = &ih->ih_regs; 462bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_rptr, ih->rptr); 463bebd4c79SHawking Zhang } 464bebd4c79SHawking Zhang } 465bebd4c79SHawking Zhang 466bebd4c79SHawking Zhang /** 467bebd4c79SHawking Zhang * vega20_ih_self_irq - dispatch work for ring 1 and 2 468bebd4c79SHawking Zhang * 469bebd4c79SHawking Zhang * @adev: amdgpu_device pointer 470bebd4c79SHawking Zhang * @source: irq source 471bebd4c79SHawking Zhang * @entry: IV with WPTR update 472bebd4c79SHawking Zhang * 473bebd4c79SHawking Zhang * Update the WPTR from the IV and schedule work to handle the entries. 474bebd4c79SHawking Zhang */ 475bebd4c79SHawking Zhang static int vega20_ih_self_irq(struct amdgpu_device *adev, 476bebd4c79SHawking Zhang struct amdgpu_irq_src *source, 477bebd4c79SHawking Zhang struct amdgpu_iv_entry *entry) 478bebd4c79SHawking Zhang { 479bebd4c79SHawking Zhang uint32_t wptr = cpu_to_le32(entry->src_data[0]); 480bebd4c79SHawking Zhang 481bebd4c79SHawking Zhang switch (entry->ring_id) { 482bebd4c79SHawking Zhang case 1: 483bebd4c79SHawking Zhang *adev->irq.ih1.wptr_cpu = wptr; 484bebd4c79SHawking Zhang schedule_work(&adev->irq.ih1_work); 485bebd4c79SHawking Zhang break; 486bebd4c79SHawking Zhang case 2: 487bebd4c79SHawking Zhang *adev->irq.ih2.wptr_cpu = wptr; 488bebd4c79SHawking Zhang schedule_work(&adev->irq.ih2_work); 489bebd4c79SHawking Zhang break; 490bebd4c79SHawking Zhang default: break; 491bebd4c79SHawking Zhang } 492bebd4c79SHawking Zhang return 0; 493bebd4c79SHawking Zhang } 494bebd4c79SHawking Zhang 495bebd4c79SHawking Zhang static const struct amdgpu_irq_src_funcs vega20_ih_self_irq_funcs = { 496bebd4c79SHawking Zhang .process = vega20_ih_self_irq, 497bebd4c79SHawking Zhang }; 498bebd4c79SHawking Zhang 499bebd4c79SHawking Zhang static void vega20_ih_set_self_irq_funcs(struct amdgpu_device *adev) 500bebd4c79SHawking Zhang { 501bebd4c79SHawking Zhang adev->irq.self_irq.num_types = 0; 502bebd4c79SHawking Zhang adev->irq.self_irq.funcs = &vega20_ih_self_irq_funcs; 503bebd4c79SHawking Zhang } 504bebd4c79SHawking Zhang 505bebd4c79SHawking Zhang static int vega20_ih_early_init(void *handle) 506bebd4c79SHawking Zhang { 507bebd4c79SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 508bebd4c79SHawking Zhang 509bebd4c79SHawking Zhang vega20_ih_set_interrupt_funcs(adev); 510bebd4c79SHawking Zhang vega20_ih_set_self_irq_funcs(adev); 511bebd4c79SHawking Zhang return 0; 512bebd4c79SHawking Zhang } 513bebd4c79SHawking Zhang 514bebd4c79SHawking Zhang static int vega20_ih_sw_init(void *handle) 515bebd4c79SHawking Zhang { 516bebd4c79SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 517bebd4c79SHawking Zhang int r; 518bebd4c79SHawking Zhang 519bebd4c79SHawking Zhang r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 520bebd4c79SHawking Zhang &adev->irq.self_irq); 521bebd4c79SHawking Zhang if (r) 522bebd4c79SHawking Zhang return r; 523bebd4c79SHawking Zhang 524bebd4c79SHawking Zhang r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true); 525bebd4c79SHawking Zhang if (r) 526bebd4c79SHawking Zhang return r; 527bebd4c79SHawking Zhang 528bebd4c79SHawking Zhang adev->irq.ih.use_doorbell = true; 529bebd4c79SHawking Zhang adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 530bebd4c79SHawking Zhang 531bebd4c79SHawking Zhang r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 532bebd4c79SHawking Zhang if (r) 533bebd4c79SHawking Zhang return r; 534bebd4c79SHawking Zhang 535bebd4c79SHawking Zhang adev->irq.ih1.use_doorbell = true; 536bebd4c79SHawking Zhang adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; 537bebd4c79SHawking Zhang 538bebd4c79SHawking Zhang r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 539bebd4c79SHawking Zhang if (r) 540bebd4c79SHawking Zhang return r; 541bebd4c79SHawking Zhang 542bebd4c79SHawking Zhang adev->irq.ih2.use_doorbell = true; 543bebd4c79SHawking Zhang adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1; 544bebd4c79SHawking Zhang 545bebd4c79SHawking Zhang /* initialize ih control registers offset */ 546bebd4c79SHawking Zhang vega20_ih_init_register_offset(adev); 547bebd4c79SHawking Zhang 548f44a6c76SHawking Zhang r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); 549f44a6c76SHawking Zhang if (r) 550f44a6c76SHawking Zhang return r; 551f44a6c76SHawking Zhang 552bebd4c79SHawking Zhang r = amdgpu_irq_init(adev); 553bebd4c79SHawking Zhang 554bebd4c79SHawking Zhang return r; 555bebd4c79SHawking Zhang } 556bebd4c79SHawking Zhang 557bebd4c79SHawking Zhang static int vega20_ih_sw_fini(void *handle) 558bebd4c79SHawking Zhang { 559bebd4c79SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 560bebd4c79SHawking Zhang 561bebd4c79SHawking Zhang amdgpu_irq_fini(adev); 5624a0a0d6dSHawking Zhang amdgpu_ih_ring_fini(adev, &adev->irq.ih_soft); 563bebd4c79SHawking Zhang amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 564bebd4c79SHawking Zhang amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 565bebd4c79SHawking Zhang amdgpu_ih_ring_fini(adev, &adev->irq.ih); 566bebd4c79SHawking Zhang 567bebd4c79SHawking Zhang return 0; 568bebd4c79SHawking Zhang } 569bebd4c79SHawking Zhang 570bebd4c79SHawking Zhang static int vega20_ih_hw_init(void *handle) 571bebd4c79SHawking Zhang { 572bebd4c79SHawking Zhang int r; 573bebd4c79SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 574bebd4c79SHawking Zhang 575bebd4c79SHawking Zhang r = vega20_ih_irq_init(adev); 576bebd4c79SHawking Zhang if (r) 577bebd4c79SHawking Zhang return r; 578bebd4c79SHawking Zhang 579bebd4c79SHawking Zhang return 0; 580bebd4c79SHawking Zhang } 581bebd4c79SHawking Zhang 582bebd4c79SHawking Zhang static int vega20_ih_hw_fini(void *handle) 583bebd4c79SHawking Zhang { 584bebd4c79SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 585bebd4c79SHawking Zhang 586bebd4c79SHawking Zhang vega20_ih_irq_disable(adev); 587bebd4c79SHawking Zhang 588bebd4c79SHawking Zhang return 0; 589bebd4c79SHawking Zhang } 590bebd4c79SHawking Zhang 591bebd4c79SHawking Zhang static int vega20_ih_suspend(void *handle) 592bebd4c79SHawking Zhang { 593bebd4c79SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 594bebd4c79SHawking Zhang 595bebd4c79SHawking Zhang return vega20_ih_hw_fini(adev); 596bebd4c79SHawking Zhang } 597bebd4c79SHawking Zhang 598bebd4c79SHawking Zhang static int vega20_ih_resume(void *handle) 599bebd4c79SHawking Zhang { 600bebd4c79SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 601bebd4c79SHawking Zhang 602bebd4c79SHawking Zhang return vega20_ih_hw_init(adev); 603bebd4c79SHawking Zhang } 604bebd4c79SHawking Zhang 605bebd4c79SHawking Zhang static bool vega20_ih_is_idle(void *handle) 606bebd4c79SHawking Zhang { 607bebd4c79SHawking Zhang /* todo */ 608bebd4c79SHawking Zhang return true; 609bebd4c79SHawking Zhang } 610bebd4c79SHawking Zhang 611bebd4c79SHawking Zhang static int vega20_ih_wait_for_idle(void *handle) 612bebd4c79SHawking Zhang { 613bebd4c79SHawking Zhang /* todo */ 614bebd4c79SHawking Zhang return -ETIMEDOUT; 615bebd4c79SHawking Zhang } 616bebd4c79SHawking Zhang 617bebd4c79SHawking Zhang static int vega20_ih_soft_reset(void *handle) 618bebd4c79SHawking Zhang { 619bebd4c79SHawking Zhang /* todo */ 620bebd4c79SHawking Zhang 621bebd4c79SHawking Zhang return 0; 622bebd4c79SHawking Zhang } 623bebd4c79SHawking Zhang 624bebd4c79SHawking Zhang static void vega20_ih_update_clockgating_state(struct amdgpu_device *adev, 625bebd4c79SHawking Zhang bool enable) 626bebd4c79SHawking Zhang { 627bebd4c79SHawking Zhang uint32_t data, def, field_val; 628bebd4c79SHawking Zhang 629bebd4c79SHawking Zhang if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 630bebd4c79SHawking Zhang def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 631bebd4c79SHawking Zhang field_val = enable ? 0 : 1; 632bebd4c79SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 633bebd4c79SHawking Zhang IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE, field_val); 634bebd4c79SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 635bebd4c79SHawking Zhang IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val); 636bebd4c79SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 637bebd4c79SHawking Zhang DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 638bebd4c79SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 639bebd4c79SHawking Zhang OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 640bebd4c79SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 641bebd4c79SHawking Zhang LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 642bebd4c79SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 643bebd4c79SHawking Zhang DYN_CLK_SOFT_OVERRIDE, field_val); 644bebd4c79SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 645bebd4c79SHawking Zhang REG_CLK_SOFT_OVERRIDE, field_val); 646bebd4c79SHawking Zhang if (def != data) 647bebd4c79SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 648bebd4c79SHawking Zhang } 649bebd4c79SHawking Zhang } 650bebd4c79SHawking Zhang 651bebd4c79SHawking Zhang static int vega20_ih_set_clockgating_state(void *handle, 652bebd4c79SHawking Zhang enum amd_clockgating_state state) 653bebd4c79SHawking Zhang { 654bebd4c79SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 655bebd4c79SHawking Zhang 656bebd4c79SHawking Zhang vega20_ih_update_clockgating_state(adev, 657bebd4c79SHawking Zhang state == AMD_CG_STATE_GATE); 658bebd4c79SHawking Zhang return 0; 659bebd4c79SHawking Zhang 660bebd4c79SHawking Zhang } 661bebd4c79SHawking Zhang 662bebd4c79SHawking Zhang static int vega20_ih_set_powergating_state(void *handle, 663bebd4c79SHawking Zhang enum amd_powergating_state state) 664bebd4c79SHawking Zhang { 665bebd4c79SHawking Zhang return 0; 666bebd4c79SHawking Zhang } 667bebd4c79SHawking Zhang 668bebd4c79SHawking Zhang const struct amd_ip_funcs vega20_ih_ip_funcs = { 669bebd4c79SHawking Zhang .name = "vega20_ih", 670bebd4c79SHawking Zhang .early_init = vega20_ih_early_init, 671bebd4c79SHawking Zhang .late_init = NULL, 672bebd4c79SHawking Zhang .sw_init = vega20_ih_sw_init, 673bebd4c79SHawking Zhang .sw_fini = vega20_ih_sw_fini, 674bebd4c79SHawking Zhang .hw_init = vega20_ih_hw_init, 675bebd4c79SHawking Zhang .hw_fini = vega20_ih_hw_fini, 676bebd4c79SHawking Zhang .suspend = vega20_ih_suspend, 677bebd4c79SHawking Zhang .resume = vega20_ih_resume, 678bebd4c79SHawking Zhang .is_idle = vega20_ih_is_idle, 679bebd4c79SHawking Zhang .wait_for_idle = vega20_ih_wait_for_idle, 680bebd4c79SHawking Zhang .soft_reset = vega20_ih_soft_reset, 681bebd4c79SHawking Zhang .set_clockgating_state = vega20_ih_set_clockgating_state, 682bebd4c79SHawking Zhang .set_powergating_state = vega20_ih_set_powergating_state, 683bebd4c79SHawking Zhang }; 684bebd4c79SHawking Zhang 685bebd4c79SHawking Zhang static const struct amdgpu_ih_funcs vega20_ih_funcs = { 686bebd4c79SHawking Zhang .get_wptr = vega20_ih_get_wptr, 687bebd4c79SHawking Zhang .decode_iv = amdgpu_ih_decode_iv_helper, 688bebd4c79SHawking Zhang .set_rptr = vega20_ih_set_rptr 689bebd4c79SHawking Zhang }; 690bebd4c79SHawking Zhang 691bebd4c79SHawking Zhang static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev) 692bebd4c79SHawking Zhang { 693bebd4c79SHawking Zhang adev->irq.ih_funcs = &vega20_ih_funcs; 694bebd4c79SHawking Zhang } 695bebd4c79SHawking Zhang 696bebd4c79SHawking Zhang const struct amdgpu_ip_block_version vega20_ih_ip_block = 697bebd4c79SHawking Zhang { 698bebd4c79SHawking Zhang .type = AMD_IP_BLOCK_TYPE_IH, 699bebd4c79SHawking Zhang .major = 4, 700bebd4c79SHawking Zhang .minor = 2, 701bebd4c79SHawking Zhang .rev = 0, 702bebd4c79SHawking Zhang .funcs = &vega20_ih_ip_funcs, 703bebd4c79SHawking Zhang }; 704