1bebd4c79SHawking Zhang /* 2bebd4c79SHawking Zhang * Copyright 2020 Advanced Micro Devices, Inc. 3bebd4c79SHawking Zhang * 4bebd4c79SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5bebd4c79SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6bebd4c79SHawking Zhang * to deal in the Software without restriction, including without limitation 7bebd4c79SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8bebd4c79SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9bebd4c79SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10bebd4c79SHawking Zhang * 11bebd4c79SHawking Zhang * The above copyright notice and this permission notice shall be included in 12bebd4c79SHawking Zhang * all copies or substantial portions of the Software. 13bebd4c79SHawking Zhang * 14bebd4c79SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15bebd4c79SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16bebd4c79SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17bebd4c79SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18bebd4c79SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19bebd4c79SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20bebd4c79SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21bebd4c79SHawking Zhang * 22bebd4c79SHawking Zhang */ 23bebd4c79SHawking Zhang 24bebd4c79SHawking Zhang #include <linux/pci.h> 25bebd4c79SHawking Zhang 26bebd4c79SHawking Zhang #include "amdgpu.h" 27bebd4c79SHawking Zhang #include "amdgpu_ih.h" 28bebd4c79SHawking Zhang #include "soc15.h" 29bebd4c79SHawking Zhang 30bebd4c79SHawking Zhang #include "oss/osssys_4_2_0_offset.h" 31bebd4c79SHawking Zhang #include "oss/osssys_4_2_0_sh_mask.h" 32bebd4c79SHawking Zhang 33bebd4c79SHawking Zhang #include "soc15_common.h" 34bebd4c79SHawking Zhang #include "vega20_ih.h" 35bebd4c79SHawking Zhang 36bebd4c79SHawking Zhang #define MAX_REARM_RETRY 10 37bebd4c79SHawking Zhang 38eed4bbd3SHawking Zhang #define mmIH_CHICKEN_ALDEBARAN 0x18d 39eed4bbd3SHawking Zhang #define mmIH_CHICKEN_ALDEBARAN_BASE_IDX 0 40eed4bbd3SHawking Zhang 41bebd4c79SHawking Zhang static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev); 42bebd4c79SHawking Zhang 43bebd4c79SHawking Zhang /** 44bebd4c79SHawking Zhang * vega20_ih_init_register_offset - Initialize register offset for ih rings 45bebd4c79SHawking Zhang * 46bebd4c79SHawking Zhang * @adev: amdgpu_device pointer 47bebd4c79SHawking Zhang * 48bebd4c79SHawking Zhang * Initialize register offset ih rings (VEGA20). 49bebd4c79SHawking Zhang */ 50bebd4c79SHawking Zhang static void vega20_ih_init_register_offset(struct amdgpu_device *adev) 51bebd4c79SHawking Zhang { 52bebd4c79SHawking Zhang struct amdgpu_ih_regs *ih_regs; 53bebd4c79SHawking Zhang 54bebd4c79SHawking Zhang if (adev->irq.ih.ring_size) { 55bebd4c79SHawking Zhang ih_regs = &adev->irq.ih.ih_regs; 56bebd4c79SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); 57bebd4c79SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); 58bebd4c79SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 59bebd4c79SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 60bebd4c79SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 61bebd4c79SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); 62bebd4c79SHawking Zhang ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); 63bebd4c79SHawking Zhang ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); 64bebd4c79SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; 65bebd4c79SHawking Zhang } 66bebd4c79SHawking Zhang 67bebd4c79SHawking Zhang if (adev->irq.ih1.ring_size) { 68bebd4c79SHawking Zhang ih_regs = &adev->irq.ih1.ih_regs; 69bebd4c79SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); 70bebd4c79SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); 71bebd4c79SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 72bebd4c79SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 73bebd4c79SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 74bebd4c79SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1); 75bebd4c79SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; 76bebd4c79SHawking Zhang } 77bebd4c79SHawking Zhang 78bebd4c79SHawking Zhang if (adev->irq.ih2.ring_size) { 79bebd4c79SHawking Zhang ih_regs = &adev->irq.ih2.ih_regs; 80bebd4c79SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); 81bebd4c79SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2); 82bebd4c79SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 83bebd4c79SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 84bebd4c79SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 85bebd4c79SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2); 86bebd4c79SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2; 87bebd4c79SHawking Zhang } 88bebd4c79SHawking Zhang } 89bebd4c79SHawking Zhang 90bebd4c79SHawking Zhang /** 91bebd4c79SHawking Zhang * vega20_ih_toggle_ring_interrupts - toggle the interrupt ring buffer 92bebd4c79SHawking Zhang * 93bebd4c79SHawking Zhang * @adev: amdgpu_device pointer 9493a2ba14SLee Jones * @ih: amdgpu_ih_ring pointer 95bebd4c79SHawking Zhang * @enable: true - enable the interrupts, false - disable the interrupts 96bebd4c79SHawking Zhang * 97bebd4c79SHawking Zhang * Toggle the interrupt ring buffer (VEGA20) 98bebd4c79SHawking Zhang */ 99bebd4c79SHawking Zhang static int vega20_ih_toggle_ring_interrupts(struct amdgpu_device *adev, 100bebd4c79SHawking Zhang struct amdgpu_ih_ring *ih, 101bebd4c79SHawking Zhang bool enable) 102bebd4c79SHawking Zhang { 103bebd4c79SHawking Zhang struct amdgpu_ih_regs *ih_regs; 104bebd4c79SHawking Zhang uint32_t tmp; 105bebd4c79SHawking Zhang 106bebd4c79SHawking Zhang ih_regs = &ih->ih_regs; 107bebd4c79SHawking Zhang 108bebd4c79SHawking Zhang tmp = RREG32(ih_regs->ih_rb_cntl); 109bebd4c79SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); 1109a9c59a8SAlex Sierra tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1); 1119a9c59a8SAlex Sierra 112bebd4c79SHawking Zhang /* enable_intr field is only valid in ring0 */ 113bebd4c79SHawking Zhang if (ih == &adev->irq.ih) 114bebd4c79SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); 115bebd4c79SHawking Zhang if (amdgpu_sriov_vf(adev)) { 116bebd4c79SHawking Zhang if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 117bebd4c79SHawking Zhang dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 118bebd4c79SHawking Zhang return -ETIMEDOUT; 119bebd4c79SHawking Zhang } 120bebd4c79SHawking Zhang } else { 121bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_cntl, tmp); 122bebd4c79SHawking Zhang } 123bebd4c79SHawking Zhang 124bebd4c79SHawking Zhang if (enable) { 125bebd4c79SHawking Zhang ih->enabled = true; 126bebd4c79SHawking Zhang } else { 127bebd4c79SHawking Zhang /* set rptr, wptr to 0 */ 128bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_rptr, 0); 129bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_wptr, 0); 130bebd4c79SHawking Zhang ih->enabled = false; 131bebd4c79SHawking Zhang ih->rptr = 0; 132bebd4c79SHawking Zhang } 133bebd4c79SHawking Zhang 134bebd4c79SHawking Zhang return 0; 135bebd4c79SHawking Zhang } 136bebd4c79SHawking Zhang 137bebd4c79SHawking Zhang /** 138bebd4c79SHawking Zhang * vega20_ih_toggle_interrupts - Toggle all the available interrupt ring buffers 139bebd4c79SHawking Zhang * 140bebd4c79SHawking Zhang * @adev: amdgpu_device pointer 141bebd4c79SHawking Zhang * @enable: enable or disable interrupt ring buffers 142bebd4c79SHawking Zhang * 143bebd4c79SHawking Zhang * Toggle all the available interrupt ring buffers (VEGA20). 144bebd4c79SHawking Zhang */ 145bebd4c79SHawking Zhang static int vega20_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable) 146bebd4c79SHawking Zhang { 147bebd4c79SHawking Zhang struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 148bebd4c79SHawking Zhang int i; 149bebd4c79SHawking Zhang int r; 150bebd4c79SHawking Zhang 151bebd4c79SHawking Zhang for (i = 0; i < ARRAY_SIZE(ih); i++) { 152bebd4c79SHawking Zhang if (ih[i]->ring_size) { 153bebd4c79SHawking Zhang r = vega20_ih_toggle_ring_interrupts(adev, ih[i], enable); 154bebd4c79SHawking Zhang if (r) 155bebd4c79SHawking Zhang return r; 156bebd4c79SHawking Zhang } 157bebd4c79SHawking Zhang } 158bebd4c79SHawking Zhang 159bebd4c79SHawking Zhang return 0; 160bebd4c79SHawking Zhang } 161bebd4c79SHawking Zhang 162bebd4c79SHawking Zhang static uint32_t vega20_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 163bebd4c79SHawking Zhang { 164bebd4c79SHawking Zhang int rb_bufsz = order_base_2(ih->ring_size / 4); 165bebd4c79SHawking Zhang 166bebd4c79SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 167bebd4c79SHawking Zhang MC_SPACE, ih->use_bus_addr ? 1 : 4); 168bebd4c79SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 169bebd4c79SHawking Zhang WPTR_OVERFLOW_CLEAR, 1); 170bebd4c79SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 171bebd4c79SHawking Zhang WPTR_OVERFLOW_ENABLE, 1); 172bebd4c79SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 173bebd4c79SHawking Zhang /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 174bebd4c79SHawking Zhang * value is written to memory 175bebd4c79SHawking Zhang */ 176bebd4c79SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 177bebd4c79SHawking Zhang WPTR_WRITEBACK_ENABLE, 1); 178bebd4c79SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 179bebd4c79SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 180bebd4c79SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 181bebd4c79SHawking Zhang 182bebd4c79SHawking Zhang return ih_rb_cntl; 183bebd4c79SHawking Zhang } 184bebd4c79SHawking Zhang 185bebd4c79SHawking Zhang static uint32_t vega20_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 186bebd4c79SHawking Zhang { 187bebd4c79SHawking Zhang u32 ih_doorbell_rtpr = 0; 188bebd4c79SHawking Zhang 189bebd4c79SHawking Zhang if (ih->use_doorbell) { 190bebd4c79SHawking Zhang ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 191bebd4c79SHawking Zhang IH_DOORBELL_RPTR, OFFSET, 192bebd4c79SHawking Zhang ih->doorbell_index); 193bebd4c79SHawking Zhang ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 194bebd4c79SHawking Zhang IH_DOORBELL_RPTR, 195bebd4c79SHawking Zhang ENABLE, 1); 196bebd4c79SHawking Zhang } else { 197bebd4c79SHawking Zhang ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 198bebd4c79SHawking Zhang IH_DOORBELL_RPTR, 199bebd4c79SHawking Zhang ENABLE, 0); 200bebd4c79SHawking Zhang } 201bebd4c79SHawking Zhang return ih_doorbell_rtpr; 202bebd4c79SHawking Zhang } 203bebd4c79SHawking Zhang 204bebd4c79SHawking Zhang /** 205bebd4c79SHawking Zhang * vega20_ih_enable_ring - enable an ih ring buffer 206bebd4c79SHawking Zhang * 207bebd4c79SHawking Zhang * @adev: amdgpu_device pointer 208bebd4c79SHawking Zhang * @ih: amdgpu_ih_ring pointer 209bebd4c79SHawking Zhang * 210bebd4c79SHawking Zhang * Enable an ih ring buffer (VEGA20) 211bebd4c79SHawking Zhang */ 212bebd4c79SHawking Zhang static int vega20_ih_enable_ring(struct amdgpu_device *adev, 213bebd4c79SHawking Zhang struct amdgpu_ih_ring *ih) 214bebd4c79SHawking Zhang { 215bebd4c79SHawking Zhang struct amdgpu_ih_regs *ih_regs; 216bebd4c79SHawking Zhang uint32_t tmp; 217bebd4c79SHawking Zhang 218bebd4c79SHawking Zhang ih_regs = &ih->ih_regs; 219bebd4c79SHawking Zhang 220bebd4c79SHawking Zhang /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 221bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); 222bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); 223bebd4c79SHawking Zhang 224bebd4c79SHawking Zhang tmp = RREG32(ih_regs->ih_rb_cntl); 225bebd4c79SHawking Zhang tmp = vega20_ih_rb_cntl(ih, tmp); 226bebd4c79SHawking Zhang if (ih == &adev->irq.ih) 227bebd4c79SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); 228b672cb1eSPhilip Yang if (ih == &adev->irq.ih1) 229bebd4c79SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); 230bebd4c79SHawking Zhang if (amdgpu_sriov_vf(adev)) { 231bebd4c79SHawking Zhang if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 232bebd4c79SHawking Zhang dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 233bebd4c79SHawking Zhang return -ETIMEDOUT; 234bebd4c79SHawking Zhang } 235bebd4c79SHawking Zhang } else { 236bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_cntl, tmp); 237bebd4c79SHawking Zhang } 238bebd4c79SHawking Zhang 239bebd4c79SHawking Zhang if (ih == &adev->irq.ih) { 240bebd4c79SHawking Zhang /* set the ih ring 0 writeback address whether it's enabled or not */ 241bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); 242bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); 243bebd4c79SHawking Zhang } 244bebd4c79SHawking Zhang 245bebd4c79SHawking Zhang /* set rptr, wptr to 0 */ 246bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_wptr, 0); 247bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_rptr, 0); 248bebd4c79SHawking Zhang 249bebd4c79SHawking Zhang WREG32(ih_regs->ih_doorbell_rptr, vega20_ih_doorbell_rptr(ih)); 250bebd4c79SHawking Zhang 251bebd4c79SHawking Zhang return 0; 252bebd4c79SHawking Zhang } 253bebd4c79SHawking Zhang 254bebd4c79SHawking Zhang /** 255726e5b37SHawking Zhang * vega20_ih_reroute_ih - reroute VMC/UTCL2 ih to an ih ring 256726e5b37SHawking Zhang * 257726e5b37SHawking Zhang * @adev: amdgpu_device pointer 258726e5b37SHawking Zhang * 259726e5b37SHawking Zhang * Reroute VMC and UMC interrupts on primary ih ring to 260726e5b37SHawking Zhang * ih ring 1 so they won't lose when bunches of page faults 261726e5b37SHawking Zhang * interrupts overwhelms the interrupt handler(VEGA20) 262726e5b37SHawking Zhang */ 263726e5b37SHawking Zhang static void vega20_ih_reroute_ih(struct amdgpu_device *adev) 264726e5b37SHawking Zhang { 265726e5b37SHawking Zhang uint32_t tmp; 266726e5b37SHawking Zhang 26703e70a02SAlex Sierra /* vega20 ih reroute will go through psp this 26803e70a02SAlex Sierra * function is used for newer asics starting arcturus 269726e5b37SHawking Zhang */ 270*886f1816SAlex Deucher if (adev->ip_versions[OSSSYS_HWIP][0] >= IP_VERSION(4, 2, 1)) { 271726e5b37SHawking Zhang /* Reroute to IH ring 1 for VMC */ 272726e5b37SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x12); 273726e5b37SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); 274726e5b37SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); 275726e5b37SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 276726e5b37SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); 277726e5b37SHawking Zhang 278726e5b37SHawking Zhang /* Reroute IH ring 1 for UTCL2 */ 279726e5b37SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x1B); 280726e5b37SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); 281726e5b37SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 282726e5b37SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); 283726e5b37SHawking Zhang } 284726e5b37SHawking Zhang } 285726e5b37SHawking Zhang 286726e5b37SHawking Zhang /** 287bebd4c79SHawking Zhang * vega20_ih_irq_init - init and enable the interrupt ring 288bebd4c79SHawking Zhang * 289bebd4c79SHawking Zhang * @adev: amdgpu_device pointer 290bebd4c79SHawking Zhang * 291bebd4c79SHawking Zhang * Allocate a ring buffer for the interrupt controller, 292bebd4c79SHawking Zhang * enable the RLC, disable interrupts, enable the IH 293bebd4c79SHawking Zhang * ring buffer and enable it (VI). 294bebd4c79SHawking Zhang * Called at device load and reume. 295bebd4c79SHawking Zhang * Returns 0 for success, errors for failure. 296bebd4c79SHawking Zhang */ 297bebd4c79SHawking Zhang static int vega20_ih_irq_init(struct amdgpu_device *adev) 298bebd4c79SHawking Zhang { 299bebd4c79SHawking Zhang struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 300bebd4c79SHawking Zhang u32 ih_chicken; 301bebd4c79SHawking Zhang int ret; 302bebd4c79SHawking Zhang int i; 303bebd4c79SHawking Zhang 304bebd4c79SHawking Zhang /* disable irqs */ 305bebd4c79SHawking Zhang ret = vega20_ih_toggle_interrupts(adev, false); 306bebd4c79SHawking Zhang if (ret) 307bebd4c79SHawking Zhang return ret; 308bebd4c79SHawking Zhang 309bebd4c79SHawking Zhang adev->nbio.funcs->ih_control(adev); 310bebd4c79SHawking Zhang 311*886f1816SAlex Deucher if ((adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 2, 1)) && 312bebd4c79SHawking Zhang adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 313bebd4c79SHawking Zhang ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 314bebd4c79SHawking Zhang if (adev->irq.ih.use_bus_addr) { 315bebd4c79SHawking Zhang ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 316bebd4c79SHawking Zhang MC_SPACE_GPA_ENABLE, 1); 317bebd4c79SHawking Zhang } 318bebd4c79SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 319bebd4c79SHawking Zhang } 320bebd4c79SHawking Zhang 321eed4bbd3SHawking Zhang /* psp firmware won't program IH_CHICKEN for aldebaran 322eed4bbd3SHawking Zhang * driver needs to program it properly according to 323eed4bbd3SHawking Zhang * MC_SPACE type in IH_RB_CNTL */ 324*886f1816SAlex Deucher if (adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 4, 0)) { 325eed4bbd3SHawking Zhang ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_ALDEBARAN); 326eed4bbd3SHawking Zhang if (adev->irq.ih.use_bus_addr) { 327eed4bbd3SHawking Zhang ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 328eed4bbd3SHawking Zhang MC_SPACE_GPA_ENABLE, 1); 329eed4bbd3SHawking Zhang } 330eed4bbd3SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_ALDEBARAN, ih_chicken); 331eed4bbd3SHawking Zhang } 332eed4bbd3SHawking Zhang 333bebd4c79SHawking Zhang for (i = 0; i < ARRAY_SIZE(ih); i++) { 334bebd4c79SHawking Zhang if (ih[i]->ring_size) { 335726e5b37SHawking Zhang if (i == 1) 336726e5b37SHawking Zhang vega20_ih_reroute_ih(adev); 337bebd4c79SHawking Zhang ret = vega20_ih_enable_ring(adev, ih[i]); 338bebd4c79SHawking Zhang if (ret) 339bebd4c79SHawking Zhang return ret; 340bebd4c79SHawking Zhang } 341bebd4c79SHawking Zhang } 342bebd4c79SHawking Zhang 343dc1d85cbSAlex Deucher if (!amdgpu_sriov_vf(adev)) 344dc1d85cbSAlex Deucher adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, 345dc1d85cbSAlex Deucher adev->irq.ih.doorbell_index); 346dc1d85cbSAlex Deucher 347bebd4c79SHawking Zhang pci_set_master(adev->pdev); 348bebd4c79SHawking Zhang 349bebd4c79SHawking Zhang /* enable interrupts */ 350bebd4c79SHawking Zhang ret = vega20_ih_toggle_interrupts(adev, true); 351bebd4c79SHawking Zhang if (ret) 352bebd4c79SHawking Zhang return ret; 353bebd4c79SHawking Zhang 354f44a6c76SHawking Zhang if (adev->irq.ih_soft.ring_size) 355f44a6c76SHawking Zhang adev->irq.ih_soft.enabled = true; 356f44a6c76SHawking Zhang 357bebd4c79SHawking Zhang return 0; 358bebd4c79SHawking Zhang } 359bebd4c79SHawking Zhang 360bebd4c79SHawking Zhang /** 361bebd4c79SHawking Zhang * vega20_ih_irq_disable - disable interrupts 362bebd4c79SHawking Zhang * 363bebd4c79SHawking Zhang * @adev: amdgpu_device pointer 364bebd4c79SHawking Zhang * 365bebd4c79SHawking Zhang * Disable interrupts on the hw (VEGA20). 366bebd4c79SHawking Zhang */ 367bebd4c79SHawking Zhang static void vega20_ih_irq_disable(struct amdgpu_device *adev) 368bebd4c79SHawking Zhang { 369bebd4c79SHawking Zhang vega20_ih_toggle_interrupts(adev, false); 370bebd4c79SHawking Zhang 371bebd4c79SHawking Zhang /* Wait and acknowledge irq */ 372bebd4c79SHawking Zhang mdelay(1); 373bebd4c79SHawking Zhang } 374bebd4c79SHawking Zhang 375bebd4c79SHawking Zhang /** 376bebd4c79SHawking Zhang * vega20_ih_get_wptr - get the IH ring buffer wptr 377bebd4c79SHawking Zhang * 378bebd4c79SHawking Zhang * @adev: amdgpu_device pointer 37993a2ba14SLee Jones * @ih: amdgpu_ih_ring pointer 380bebd4c79SHawking Zhang * 381bebd4c79SHawking Zhang * Get the IH ring buffer wptr from either the register 382bebd4c79SHawking Zhang * or the writeback memory buffer (VEGA20). Also check for 383bebd4c79SHawking Zhang * ring buffer overflow and deal with it. 384bebd4c79SHawking Zhang * Returns the value of the wptr. 385bebd4c79SHawking Zhang */ 386bebd4c79SHawking Zhang static u32 vega20_ih_get_wptr(struct amdgpu_device *adev, 387bebd4c79SHawking Zhang struct amdgpu_ih_ring *ih) 388bebd4c79SHawking Zhang { 389bebd4c79SHawking Zhang u32 wptr, tmp; 390bebd4c79SHawking Zhang struct amdgpu_ih_regs *ih_regs; 391bebd4c79SHawking Zhang 392de8341eeSMukul Joshi if (ih == &adev->irq.ih || ih == &adev->irq.ih_soft) { 393b672cb1eSPhilip Yang /* Only ring0 supports writeback. On other rings fall back 394b672cb1eSPhilip Yang * to register-based code with overflow checking below. 395de8341eeSMukul Joshi * ih_soft ring doesn't have any backing hardware registers, 396de8341eeSMukul Joshi * update wptr and return. 397b672cb1eSPhilip Yang */ 398bebd4c79SHawking Zhang wptr = le32_to_cpu(*ih->wptr_cpu); 399bebd4c79SHawking Zhang 400bebd4c79SHawking Zhang if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 401bebd4c79SHawking Zhang goto out; 402b672cb1eSPhilip Yang } 403b672cb1eSPhilip Yang 404b672cb1eSPhilip Yang ih_regs = &ih->ih_regs; 405bebd4c79SHawking Zhang 406bebd4c79SHawking Zhang /* Double check that the overflow wasn't already cleared. */ 407bebd4c79SHawking Zhang wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); 408bebd4c79SHawking Zhang if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 409bebd4c79SHawking Zhang goto out; 410bebd4c79SHawking Zhang 411bebd4c79SHawking Zhang wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 412bebd4c79SHawking Zhang 413bebd4c79SHawking Zhang /* When a ring buffer overflow happen start parsing interrupt 414bebd4c79SHawking Zhang * from the last not overwritten vector (wptr + 32). Hopefully 415bebd4c79SHawking Zhang * this should allow us to catchup. 416bebd4c79SHawking Zhang */ 417bebd4c79SHawking Zhang tmp = (wptr + 32) & ih->ptr_mask; 418bebd4c79SHawking Zhang dev_warn(adev->dev, "IH ring buffer overflow " 419bebd4c79SHawking Zhang "(0x%08X, 0x%08X, 0x%08X)\n", 420bebd4c79SHawking Zhang wptr, ih->rptr, tmp); 421bebd4c79SHawking Zhang ih->rptr = tmp; 422bebd4c79SHawking Zhang 423bebd4c79SHawking Zhang tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); 424bebd4c79SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 425bebd4c79SHawking Zhang WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 426bebd4c79SHawking Zhang 427bebd4c79SHawking Zhang out: 428bebd4c79SHawking Zhang return (wptr & ih->ptr_mask); 429bebd4c79SHawking Zhang } 430bebd4c79SHawking Zhang 431bebd4c79SHawking Zhang /** 432bebd4c79SHawking Zhang * vega20_ih_irq_rearm - rearm IRQ if lost 433bebd4c79SHawking Zhang * 434bebd4c79SHawking Zhang * @adev: amdgpu_device pointer 43593a2ba14SLee Jones * @ih: amdgpu_ih_ring pointer 436bebd4c79SHawking Zhang * 437bebd4c79SHawking Zhang */ 438bebd4c79SHawking Zhang static void vega20_ih_irq_rearm(struct amdgpu_device *adev, 439bebd4c79SHawking Zhang struct amdgpu_ih_ring *ih) 440bebd4c79SHawking Zhang { 441bebd4c79SHawking Zhang uint32_t v = 0; 442bebd4c79SHawking Zhang uint32_t i = 0; 443bebd4c79SHawking Zhang struct amdgpu_ih_regs *ih_regs; 444bebd4c79SHawking Zhang 445bebd4c79SHawking Zhang ih_regs = &ih->ih_regs; 446bebd4c79SHawking Zhang 447bebd4c79SHawking Zhang /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */ 448bebd4c79SHawking Zhang for (i = 0; i < MAX_REARM_RETRY; i++) { 449bebd4c79SHawking Zhang v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); 450bebd4c79SHawking Zhang if ((v < ih->ring_size) && (v != ih->rptr)) 451bebd4c79SHawking Zhang WDOORBELL32(ih->doorbell_index, ih->rptr); 452bebd4c79SHawking Zhang else 453bebd4c79SHawking Zhang break; 454bebd4c79SHawking Zhang } 455bebd4c79SHawking Zhang } 456bebd4c79SHawking Zhang 457bebd4c79SHawking Zhang /** 458bebd4c79SHawking Zhang * vega20_ih_set_rptr - set the IH ring buffer rptr 459bebd4c79SHawking Zhang * 460bebd4c79SHawking Zhang * @adev: amdgpu_device pointer 46193a2ba14SLee Jones * @ih: amdgpu_ih_ring pointer 462bebd4c79SHawking Zhang * 463bebd4c79SHawking Zhang * Set the IH ring buffer rptr. 464bebd4c79SHawking Zhang */ 465bebd4c79SHawking Zhang static void vega20_ih_set_rptr(struct amdgpu_device *adev, 466bebd4c79SHawking Zhang struct amdgpu_ih_ring *ih) 467bebd4c79SHawking Zhang { 468bebd4c79SHawking Zhang struct amdgpu_ih_regs *ih_regs; 469bebd4c79SHawking Zhang 470de8341eeSMukul Joshi if (ih == &adev->irq.ih_soft) 471de8341eeSMukul Joshi return; 472de8341eeSMukul Joshi 473bebd4c79SHawking Zhang if (ih->use_doorbell) { 474bebd4c79SHawking Zhang /* XXX check if swapping is necessary on BE */ 475bebd4c79SHawking Zhang *ih->rptr_cpu = ih->rptr; 476bebd4c79SHawking Zhang WDOORBELL32(ih->doorbell_index, ih->rptr); 477bebd4c79SHawking Zhang 478bebd4c79SHawking Zhang if (amdgpu_sriov_vf(adev)) 479bebd4c79SHawking Zhang vega20_ih_irq_rearm(adev, ih); 480bebd4c79SHawking Zhang } else { 481bebd4c79SHawking Zhang ih_regs = &ih->ih_regs; 482bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_rptr, ih->rptr); 483bebd4c79SHawking Zhang } 484bebd4c79SHawking Zhang } 485bebd4c79SHawking Zhang 486bebd4c79SHawking Zhang /** 487bebd4c79SHawking Zhang * vega20_ih_self_irq - dispatch work for ring 1 and 2 488bebd4c79SHawking Zhang * 489bebd4c79SHawking Zhang * @adev: amdgpu_device pointer 490bebd4c79SHawking Zhang * @source: irq source 491bebd4c79SHawking Zhang * @entry: IV with WPTR update 492bebd4c79SHawking Zhang * 493bebd4c79SHawking Zhang * Update the WPTR from the IV and schedule work to handle the entries. 494bebd4c79SHawking Zhang */ 495bebd4c79SHawking Zhang static int vega20_ih_self_irq(struct amdgpu_device *adev, 496bebd4c79SHawking Zhang struct amdgpu_irq_src *source, 497bebd4c79SHawking Zhang struct amdgpu_iv_entry *entry) 498bebd4c79SHawking Zhang { 499bebd4c79SHawking Zhang switch (entry->ring_id) { 500bebd4c79SHawking Zhang case 1: 501bebd4c79SHawking Zhang schedule_work(&adev->irq.ih1_work); 502bebd4c79SHawking Zhang break; 503bebd4c79SHawking Zhang case 2: 504bebd4c79SHawking Zhang schedule_work(&adev->irq.ih2_work); 505bebd4c79SHawking Zhang break; 506bebd4c79SHawking Zhang default: break; 507bebd4c79SHawking Zhang } 508bebd4c79SHawking Zhang return 0; 509bebd4c79SHawking Zhang } 510bebd4c79SHawking Zhang 511bebd4c79SHawking Zhang static const struct amdgpu_irq_src_funcs vega20_ih_self_irq_funcs = { 512bebd4c79SHawking Zhang .process = vega20_ih_self_irq, 513bebd4c79SHawking Zhang }; 514bebd4c79SHawking Zhang 515bebd4c79SHawking Zhang static void vega20_ih_set_self_irq_funcs(struct amdgpu_device *adev) 516bebd4c79SHawking Zhang { 517bebd4c79SHawking Zhang adev->irq.self_irq.num_types = 0; 518bebd4c79SHawking Zhang adev->irq.self_irq.funcs = &vega20_ih_self_irq_funcs; 519bebd4c79SHawking Zhang } 520bebd4c79SHawking Zhang 521bebd4c79SHawking Zhang static int vega20_ih_early_init(void *handle) 522bebd4c79SHawking Zhang { 523bebd4c79SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 524bebd4c79SHawking Zhang 525bebd4c79SHawking Zhang vega20_ih_set_interrupt_funcs(adev); 526bebd4c79SHawking Zhang vega20_ih_set_self_irq_funcs(adev); 527bebd4c79SHawking Zhang return 0; 528bebd4c79SHawking Zhang } 529bebd4c79SHawking Zhang 530bebd4c79SHawking Zhang static int vega20_ih_sw_init(void *handle) 531bebd4c79SHawking Zhang { 532bebd4c79SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 533bebd4c79SHawking Zhang int r; 534bebd4c79SHawking Zhang 535bebd4c79SHawking Zhang r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 536bebd4c79SHawking Zhang &adev->irq.self_irq); 537bebd4c79SHawking Zhang if (r) 538bebd4c79SHawking Zhang return r; 539bebd4c79SHawking Zhang 540bebd4c79SHawking Zhang r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true); 541bebd4c79SHawking Zhang if (r) 542bebd4c79SHawking Zhang return r; 543bebd4c79SHawking Zhang 544bebd4c79SHawking Zhang adev->irq.ih.use_doorbell = true; 545bebd4c79SHawking Zhang adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 546bebd4c79SHawking Zhang 547bebd4c79SHawking Zhang r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 548bebd4c79SHawking Zhang if (r) 549bebd4c79SHawking Zhang return r; 550bebd4c79SHawking Zhang 551bebd4c79SHawking Zhang adev->irq.ih1.use_doorbell = true; 552bebd4c79SHawking Zhang adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; 553bebd4c79SHawking Zhang 554bebd4c79SHawking Zhang r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 555bebd4c79SHawking Zhang if (r) 556bebd4c79SHawking Zhang return r; 557bebd4c79SHawking Zhang 558bebd4c79SHawking Zhang adev->irq.ih2.use_doorbell = true; 559bebd4c79SHawking Zhang adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1; 560bebd4c79SHawking Zhang 561bebd4c79SHawking Zhang /* initialize ih control registers offset */ 562bebd4c79SHawking Zhang vega20_ih_init_register_offset(adev); 563bebd4c79SHawking Zhang 564f44a6c76SHawking Zhang r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); 565f44a6c76SHawking Zhang if (r) 566f44a6c76SHawking Zhang return r; 567f44a6c76SHawking Zhang 568bebd4c79SHawking Zhang r = amdgpu_irq_init(adev); 569bebd4c79SHawking Zhang 570bebd4c79SHawking Zhang return r; 571bebd4c79SHawking Zhang } 572bebd4c79SHawking Zhang 573bebd4c79SHawking Zhang static int vega20_ih_sw_fini(void *handle) 574bebd4c79SHawking Zhang { 575bebd4c79SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 576bebd4c79SHawking Zhang 57772c8c97bSAndrey Grodzovsky amdgpu_irq_fini_sw(adev); 578bebd4c79SHawking Zhang 579bebd4c79SHawking Zhang return 0; 580bebd4c79SHawking Zhang } 581bebd4c79SHawking Zhang 582bebd4c79SHawking Zhang static int vega20_ih_hw_init(void *handle) 583bebd4c79SHawking Zhang { 584bebd4c79SHawking Zhang int r; 585bebd4c79SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 586bebd4c79SHawking Zhang 587bebd4c79SHawking Zhang r = vega20_ih_irq_init(adev); 588bebd4c79SHawking Zhang if (r) 589bebd4c79SHawking Zhang return r; 590bebd4c79SHawking Zhang 591bebd4c79SHawking Zhang return 0; 592bebd4c79SHawking Zhang } 593bebd4c79SHawking Zhang 594bebd4c79SHawking Zhang static int vega20_ih_hw_fini(void *handle) 595bebd4c79SHawking Zhang { 596bebd4c79SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 597bebd4c79SHawking Zhang 598bebd4c79SHawking Zhang vega20_ih_irq_disable(adev); 599bebd4c79SHawking Zhang 600bebd4c79SHawking Zhang return 0; 601bebd4c79SHawking Zhang } 602bebd4c79SHawking Zhang 603bebd4c79SHawking Zhang static int vega20_ih_suspend(void *handle) 604bebd4c79SHawking Zhang { 605bebd4c79SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 606bebd4c79SHawking Zhang 607bebd4c79SHawking Zhang return vega20_ih_hw_fini(adev); 608bebd4c79SHawking Zhang } 609bebd4c79SHawking Zhang 610bebd4c79SHawking Zhang static int vega20_ih_resume(void *handle) 611bebd4c79SHawking Zhang { 612bebd4c79SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 613bebd4c79SHawking Zhang 614bebd4c79SHawking Zhang return vega20_ih_hw_init(adev); 615bebd4c79SHawking Zhang } 616bebd4c79SHawking Zhang 617bebd4c79SHawking Zhang static bool vega20_ih_is_idle(void *handle) 618bebd4c79SHawking Zhang { 619bebd4c79SHawking Zhang /* todo */ 620bebd4c79SHawking Zhang return true; 621bebd4c79SHawking Zhang } 622bebd4c79SHawking Zhang 623bebd4c79SHawking Zhang static int vega20_ih_wait_for_idle(void *handle) 624bebd4c79SHawking Zhang { 625bebd4c79SHawking Zhang /* todo */ 626bebd4c79SHawking Zhang return -ETIMEDOUT; 627bebd4c79SHawking Zhang } 628bebd4c79SHawking Zhang 629bebd4c79SHawking Zhang static int vega20_ih_soft_reset(void *handle) 630bebd4c79SHawking Zhang { 631bebd4c79SHawking Zhang /* todo */ 632bebd4c79SHawking Zhang 633bebd4c79SHawking Zhang return 0; 634bebd4c79SHawking Zhang } 635bebd4c79SHawking Zhang 636bebd4c79SHawking Zhang static void vega20_ih_update_clockgating_state(struct amdgpu_device *adev, 637bebd4c79SHawking Zhang bool enable) 638bebd4c79SHawking Zhang { 639bebd4c79SHawking Zhang uint32_t data, def, field_val; 640bebd4c79SHawking Zhang 641bebd4c79SHawking Zhang if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 642bebd4c79SHawking Zhang def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 643bebd4c79SHawking Zhang field_val = enable ? 0 : 1; 644bebd4c79SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 645bebd4c79SHawking Zhang IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE, field_val); 646bebd4c79SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 647bebd4c79SHawking Zhang IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val); 648bebd4c79SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 649bebd4c79SHawking Zhang DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 650bebd4c79SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 651bebd4c79SHawking Zhang OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 652bebd4c79SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 653bebd4c79SHawking Zhang LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 654bebd4c79SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 655bebd4c79SHawking Zhang DYN_CLK_SOFT_OVERRIDE, field_val); 656bebd4c79SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 657bebd4c79SHawking Zhang REG_CLK_SOFT_OVERRIDE, field_val); 658bebd4c79SHawking Zhang if (def != data) 659bebd4c79SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 660bebd4c79SHawking Zhang } 661bebd4c79SHawking Zhang } 662bebd4c79SHawking Zhang 663bebd4c79SHawking Zhang static int vega20_ih_set_clockgating_state(void *handle, 664bebd4c79SHawking Zhang enum amd_clockgating_state state) 665bebd4c79SHawking Zhang { 666bebd4c79SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 667bebd4c79SHawking Zhang 668bebd4c79SHawking Zhang vega20_ih_update_clockgating_state(adev, 669bebd4c79SHawking Zhang state == AMD_CG_STATE_GATE); 670bebd4c79SHawking Zhang return 0; 671bebd4c79SHawking Zhang 672bebd4c79SHawking Zhang } 673bebd4c79SHawking Zhang 674bebd4c79SHawking Zhang static int vega20_ih_set_powergating_state(void *handle, 675bebd4c79SHawking Zhang enum amd_powergating_state state) 676bebd4c79SHawking Zhang { 677bebd4c79SHawking Zhang return 0; 678bebd4c79SHawking Zhang } 679bebd4c79SHawking Zhang 680bebd4c79SHawking Zhang const struct amd_ip_funcs vega20_ih_ip_funcs = { 681bebd4c79SHawking Zhang .name = "vega20_ih", 682bebd4c79SHawking Zhang .early_init = vega20_ih_early_init, 683bebd4c79SHawking Zhang .late_init = NULL, 684bebd4c79SHawking Zhang .sw_init = vega20_ih_sw_init, 685bebd4c79SHawking Zhang .sw_fini = vega20_ih_sw_fini, 686bebd4c79SHawking Zhang .hw_init = vega20_ih_hw_init, 687bebd4c79SHawking Zhang .hw_fini = vega20_ih_hw_fini, 688bebd4c79SHawking Zhang .suspend = vega20_ih_suspend, 689bebd4c79SHawking Zhang .resume = vega20_ih_resume, 690bebd4c79SHawking Zhang .is_idle = vega20_ih_is_idle, 691bebd4c79SHawking Zhang .wait_for_idle = vega20_ih_wait_for_idle, 692bebd4c79SHawking Zhang .soft_reset = vega20_ih_soft_reset, 693bebd4c79SHawking Zhang .set_clockgating_state = vega20_ih_set_clockgating_state, 694bebd4c79SHawking Zhang .set_powergating_state = vega20_ih_set_powergating_state, 695bebd4c79SHawking Zhang }; 696bebd4c79SHawking Zhang 697bebd4c79SHawking Zhang static const struct amdgpu_ih_funcs vega20_ih_funcs = { 698bebd4c79SHawking Zhang .get_wptr = vega20_ih_get_wptr, 699bebd4c79SHawking Zhang .decode_iv = amdgpu_ih_decode_iv_helper, 7003c2d6ea2SPhilip Yang .decode_iv_ts = amdgpu_ih_decode_iv_ts_helper, 701bebd4c79SHawking Zhang .set_rptr = vega20_ih_set_rptr 702bebd4c79SHawking Zhang }; 703bebd4c79SHawking Zhang 704bebd4c79SHawking Zhang static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev) 705bebd4c79SHawking Zhang { 706bebd4c79SHawking Zhang adev->irq.ih_funcs = &vega20_ih_funcs; 707bebd4c79SHawking Zhang } 708bebd4c79SHawking Zhang 709bebd4c79SHawking Zhang const struct amdgpu_ip_block_version vega20_ih_ip_block = 710bebd4c79SHawking Zhang { 711bebd4c79SHawking Zhang .type = AMD_IP_BLOCK_TYPE_IH, 712bebd4c79SHawking Zhang .major = 4, 713bebd4c79SHawking Zhang .minor = 2, 714bebd4c79SHawking Zhang .rev = 0, 715bebd4c79SHawking Zhang .funcs = &vega20_ih_ip_funcs, 716bebd4c79SHawking Zhang }; 717