1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 #include "soc15.h" 29 30 #include "oss/osssys_4_0_offset.h" 31 #include "oss/osssys_4_0_sh_mask.h" 32 33 #include "soc15_common.h" 34 #include "vega10_ih.h" 35 36 #define MAX_REARM_RETRY 10 37 38 static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 39 40 /** 41 * vega10_ih_init_register_offset - Initialize register offset for ih rings 42 * 43 * @adev: amdgpu_device pointer 44 * 45 * Initialize register offset ih rings (VEGA10). 46 */ 47 static void vega10_ih_init_register_offset(struct amdgpu_device *adev) 48 { 49 struct amdgpu_ih_regs *ih_regs; 50 51 if (adev->irq.ih.ring_size) { 52 ih_regs = &adev->irq.ih.ih_regs; 53 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); 54 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); 55 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 56 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 57 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 58 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); 59 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); 60 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); 61 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; 62 } 63 64 if (adev->irq.ih1.ring_size) { 65 ih_regs = &adev->irq.ih1.ih_regs; 66 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); 67 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); 68 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 69 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 70 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 71 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1); 72 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; 73 } 74 75 if (adev->irq.ih2.ring_size) { 76 ih_regs = &adev->irq.ih2.ih_regs; 77 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); 78 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2); 79 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 80 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 81 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 82 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2); 83 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2; 84 } 85 } 86 87 /** 88 * vega10_ih_enable_interrupts - Enable the interrupt ring buffer 89 * 90 * @adev: amdgpu_device pointer 91 * 92 * Enable the interrupt ring buffer (VEGA10). 93 */ 94 static void vega10_ih_enable_interrupts(struct amdgpu_device *adev) 95 { 96 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 97 98 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); 99 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); 100 if (amdgpu_sriov_vf(adev)) { 101 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 102 DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 103 return; 104 } 105 } else { 106 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 107 } 108 adev->irq.ih.enabled = true; 109 110 if (adev->irq.ih1.ring_size) { 111 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 112 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 113 RB_ENABLE, 1); 114 if (amdgpu_sriov_vf(adev)) { 115 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 116 ih_rb_cntl)) { 117 DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 118 return; 119 } 120 } else { 121 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 122 } 123 adev->irq.ih1.enabled = true; 124 } 125 126 if (adev->irq.ih2.ring_size) { 127 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 128 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 129 RB_ENABLE, 1); 130 if (amdgpu_sriov_vf(adev)) { 131 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 132 ih_rb_cntl)) { 133 DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 134 return; 135 } 136 } else { 137 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 138 } 139 adev->irq.ih2.enabled = true; 140 } 141 142 if (adev->irq.ih_soft.ring_size) 143 adev->irq.ih_soft.enabled = true; 144 } 145 146 /** 147 * vega10_ih_disable_interrupts - Disable the interrupt ring buffer 148 * 149 * @adev: amdgpu_device pointer 150 * 151 * Disable the interrupt ring buffer (VEGA10). 152 */ 153 static void vega10_ih_disable_interrupts(struct amdgpu_device *adev) 154 { 155 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 156 157 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); 158 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); 159 if (amdgpu_sriov_vf(adev)) { 160 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 161 DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 162 return; 163 } 164 } else { 165 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 166 } 167 168 /* set rptr, wptr to 0 */ 169 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 170 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 171 adev->irq.ih.enabled = false; 172 adev->irq.ih.rptr = 0; 173 174 if (adev->irq.ih1.ring_size) { 175 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 176 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 177 RB_ENABLE, 0); 178 if (amdgpu_sriov_vf(adev)) { 179 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 180 ih_rb_cntl)) { 181 DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 182 return; 183 } 184 } else { 185 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 186 } 187 /* set rptr, wptr to 0 */ 188 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 189 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 190 adev->irq.ih1.enabled = false; 191 adev->irq.ih1.rptr = 0; 192 } 193 194 if (adev->irq.ih2.ring_size) { 195 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 196 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 197 RB_ENABLE, 0); 198 if (amdgpu_sriov_vf(adev)) { 199 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 200 ih_rb_cntl)) { 201 DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 202 return; 203 } 204 } else { 205 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 206 } 207 208 /* set rptr, wptr to 0 */ 209 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 210 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 211 adev->irq.ih2.enabled = false; 212 adev->irq.ih2.rptr = 0; 213 } 214 } 215 216 static uint32_t vega10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 217 { 218 int rb_bufsz = order_base_2(ih->ring_size / 4); 219 220 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 221 MC_SPACE, ih->use_bus_addr ? 1 : 4); 222 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 223 WPTR_OVERFLOW_CLEAR, 1); 224 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 225 WPTR_OVERFLOW_ENABLE, 1); 226 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 227 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 228 * value is written to memory 229 */ 230 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 231 WPTR_WRITEBACK_ENABLE, 1); 232 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 233 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 234 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 235 236 return ih_rb_cntl; 237 } 238 239 static uint32_t vega10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 240 { 241 u32 ih_doorbell_rtpr = 0; 242 243 if (ih->use_doorbell) { 244 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 245 IH_DOORBELL_RPTR, OFFSET, 246 ih->doorbell_index); 247 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 248 IH_DOORBELL_RPTR, 249 ENABLE, 1); 250 } else { 251 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 252 IH_DOORBELL_RPTR, 253 ENABLE, 0); 254 } 255 return ih_doorbell_rtpr; 256 } 257 258 /** 259 * vega10_ih_enable_ring - enable an ih ring buffer 260 * 261 * @adev: amdgpu_device pointer 262 * @ih: amdgpu_ih_ring pointer 263 * 264 * Enable an ih ring buffer (VEGA10) 265 */ 266 static int vega10_ih_enable_ring(struct amdgpu_device *adev, 267 struct amdgpu_ih_ring *ih) 268 { 269 struct amdgpu_ih_regs *ih_regs; 270 uint32_t tmp; 271 272 ih_regs = &ih->ih_regs; 273 274 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 275 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); 276 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); 277 278 tmp = RREG32(ih_regs->ih_rb_cntl); 279 tmp = vega10_ih_rb_cntl(ih, tmp); 280 if (ih == &adev->irq.ih) 281 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); 282 if (ih == &adev->irq.ih1) { 283 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0); 284 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); 285 } 286 if (amdgpu_sriov_vf(adev)) { 287 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 288 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 289 return -ETIMEDOUT; 290 } 291 } else { 292 WREG32(ih_regs->ih_rb_cntl, tmp); 293 } 294 295 if (ih == &adev->irq.ih) { 296 /* set the ih ring 0 writeback address whether it's enabled or not */ 297 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); 298 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); 299 } 300 301 /* set rptr, wptr to 0 */ 302 WREG32(ih_regs->ih_rb_wptr, 0); 303 WREG32(ih_regs->ih_rb_rptr, 0); 304 305 WREG32(ih_regs->ih_doorbell_rptr, vega10_ih_doorbell_rptr(ih)); 306 307 return 0; 308 } 309 310 /** 311 * vega10_ih_irq_init - init and enable the interrupt ring 312 * 313 * @adev: amdgpu_device pointer 314 * 315 * Allocate a ring buffer for the interrupt controller, 316 * enable the RLC, disable interrupts, enable the IH 317 * ring buffer and enable it (VI). 318 * Called at device load and reume. 319 * Returns 0 for success, errors for failure. 320 */ 321 static int vega10_ih_irq_init(struct amdgpu_device *adev) 322 { 323 struct amdgpu_ih_ring *ih; 324 u32 ih_rb_cntl, ih_chicken; 325 int ret = 0; 326 u32 tmp; 327 328 /* disable irqs */ 329 vega10_ih_disable_interrupts(adev); 330 331 adev->nbio.funcs->ih_control(adev); 332 333 ih = &adev->irq.ih; 334 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 335 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8); 336 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff); 337 338 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 339 ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl); 340 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 341 !!adev->irq.msi_enabled); 342 if (amdgpu_sriov_vf(adev)) { 343 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 344 DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 345 return -ETIMEDOUT; 346 } 347 } else { 348 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 349 } 350 351 if ((adev->asic_type == CHIP_ARCTURUS && 352 adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) || 353 adev->asic_type == CHIP_RENOIR) { 354 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 355 if (adev->irq.ih.use_bus_addr) { 356 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 357 MC_SPACE_GPA_ENABLE, 1); 358 } else { 359 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 360 MC_SPACE_FBPA_ENABLE, 1); 361 } 362 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 363 } 364 365 /* set the writeback address whether it's enabled or not */ 366 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, 367 lower_32_bits(ih->wptr_addr)); 368 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, 369 upper_32_bits(ih->wptr_addr) & 0xFFFF); 370 371 /* set rptr, wptr to 0 */ 372 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 373 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 374 375 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, 376 vega10_ih_doorbell_rptr(ih)); 377 378 ih = &adev->irq.ih1; 379 if (ih->ring_size) { 380 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING1, ih->gpu_addr >> 8); 381 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING1, 382 (ih->gpu_addr >> 40) & 0xff); 383 384 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 385 ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl); 386 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 387 WPTR_OVERFLOW_ENABLE, 0); 388 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 389 RB_FULL_DRAIN_ENABLE, 1); 390 if (amdgpu_sriov_vf(adev)) { 391 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 392 ih_rb_cntl)) { 393 DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 394 return -ETIMEDOUT; 395 } 396 } else { 397 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 398 } 399 400 /* set rptr, wptr to 0 */ 401 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 402 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 403 404 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1, 405 vega10_ih_doorbell_rptr(ih)); 406 } 407 408 ih = &adev->irq.ih2; 409 if (ih->ring_size) { 410 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING2, ih->gpu_addr >> 8); 411 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING2, 412 (ih->gpu_addr >> 40) & 0xff); 413 414 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 415 ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl); 416 417 if (amdgpu_sriov_vf(adev)) { 418 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 419 ih_rb_cntl)) { 420 DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 421 return -ETIMEDOUT; 422 } 423 } else { 424 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 425 } 426 427 /* set rptr, wptr to 0 */ 428 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 429 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 430 431 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2, 432 vega10_ih_doorbell_rptr(ih)); 433 } 434 435 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 436 tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 437 CLIENT18_IS_STORM_CLIENT, 1); 438 WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 439 440 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 441 tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 442 WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 443 444 pci_set_master(adev->pdev); 445 446 /* enable interrupts */ 447 vega10_ih_enable_interrupts(adev); 448 449 return ret; 450 } 451 452 /** 453 * vega10_ih_irq_disable - disable interrupts 454 * 455 * @adev: amdgpu_device pointer 456 * 457 * Disable interrupts on the hw (VEGA10). 458 */ 459 static void vega10_ih_irq_disable(struct amdgpu_device *adev) 460 { 461 vega10_ih_disable_interrupts(adev); 462 463 /* Wait and acknowledge irq */ 464 mdelay(1); 465 } 466 467 /** 468 * vega10_ih_get_wptr - get the IH ring buffer wptr 469 * 470 * @adev: amdgpu_device pointer 471 * @ih: IH ring buffer to fetch wptr 472 * 473 * Get the IH ring buffer wptr from either the register 474 * or the writeback memory buffer (VEGA10). Also check for 475 * ring buffer overflow and deal with it. 476 * Returns the value of the wptr. 477 */ 478 static u32 vega10_ih_get_wptr(struct amdgpu_device *adev, 479 struct amdgpu_ih_ring *ih) 480 { 481 u32 wptr, reg, tmp; 482 483 wptr = le32_to_cpu(*ih->wptr_cpu); 484 485 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 486 goto out; 487 488 /* Double check that the overflow wasn't already cleared. */ 489 490 if (ih == &adev->irq.ih) 491 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 492 else if (ih == &adev->irq.ih1) 493 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 494 else if (ih == &adev->irq.ih2) 495 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 496 else 497 BUG(); 498 499 wptr = RREG32_NO_KIQ(reg); 500 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 501 goto out; 502 503 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 504 505 /* When a ring buffer overflow happen start parsing interrupt 506 * from the last not overwritten vector (wptr + 32). Hopefully 507 * this should allow us to catchup. 508 */ 509 tmp = (wptr + 32) & ih->ptr_mask; 510 dev_warn(adev->dev, "IH ring buffer overflow " 511 "(0x%08X, 0x%08X, 0x%08X)\n", 512 wptr, ih->rptr, tmp); 513 ih->rptr = tmp; 514 515 if (ih == &adev->irq.ih) 516 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 517 else if (ih == &adev->irq.ih1) 518 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 519 else if (ih == &adev->irq.ih2) 520 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 521 else 522 BUG(); 523 524 tmp = RREG32_NO_KIQ(reg); 525 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 526 WREG32_NO_KIQ(reg, tmp); 527 528 out: 529 return (wptr & ih->ptr_mask); 530 } 531 532 /** 533 * vega10_ih_decode_iv - decode an interrupt vector 534 * 535 * @adev: amdgpu_device pointer 536 * @ih: IH ring buffer to decode 537 * @entry: IV entry to place decoded information into 538 * 539 * Decodes the interrupt vector at the current rptr 540 * position and also advance the position. 541 */ 542 static void vega10_ih_decode_iv(struct amdgpu_device *adev, 543 struct amdgpu_ih_ring *ih, 544 struct amdgpu_iv_entry *entry) 545 { 546 /* wptr/rptr are in bytes! */ 547 u32 ring_index = ih->rptr >> 2; 548 uint32_t dw[8]; 549 550 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 551 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 552 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 553 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 554 dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); 555 dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); 556 dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); 557 dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); 558 559 entry->client_id = dw[0] & 0xff; 560 entry->src_id = (dw[0] >> 8) & 0xff; 561 entry->ring_id = (dw[0] >> 16) & 0xff; 562 entry->vmid = (dw[0] >> 24) & 0xf; 563 entry->vmid_src = (dw[0] >> 31); 564 entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); 565 entry->timestamp_src = dw[2] >> 31; 566 entry->pasid = dw[3] & 0xffff; 567 entry->pasid_src = dw[3] >> 31; 568 entry->src_data[0] = dw[4]; 569 entry->src_data[1] = dw[5]; 570 entry->src_data[2] = dw[6]; 571 entry->src_data[3] = dw[7]; 572 573 /* wptr/rptr are in bytes! */ 574 ih->rptr += 32; 575 } 576 577 /** 578 * vega10_ih_irq_rearm - rearm IRQ if lost 579 * 580 * @adev: amdgpu_device pointer 581 * @ih: IH ring to match 582 * 583 */ 584 static void vega10_ih_irq_rearm(struct amdgpu_device *adev, 585 struct amdgpu_ih_ring *ih) 586 { 587 uint32_t reg_rptr = 0; 588 uint32_t v = 0; 589 uint32_t i = 0; 590 591 if (ih == &adev->irq.ih) 592 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 593 else if (ih == &adev->irq.ih1) 594 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 595 else if (ih == &adev->irq.ih2) 596 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 597 else 598 return; 599 600 /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */ 601 for (i = 0; i < MAX_REARM_RETRY; i++) { 602 v = RREG32_NO_KIQ(reg_rptr); 603 if ((v < ih->ring_size) && (v != ih->rptr)) 604 WDOORBELL32(ih->doorbell_index, ih->rptr); 605 else 606 break; 607 } 608 } 609 610 /** 611 * vega10_ih_set_rptr - set the IH ring buffer rptr 612 * 613 * @adev: amdgpu_device pointer 614 * @ih: IH ring buffer to set rptr 615 * 616 * Set the IH ring buffer rptr. 617 */ 618 static void vega10_ih_set_rptr(struct amdgpu_device *adev, 619 struct amdgpu_ih_ring *ih) 620 { 621 if (ih->use_doorbell) { 622 /* XXX check if swapping is necessary on BE */ 623 *ih->rptr_cpu = ih->rptr; 624 WDOORBELL32(ih->doorbell_index, ih->rptr); 625 626 if (amdgpu_sriov_vf(adev)) 627 vega10_ih_irq_rearm(adev, ih); 628 } else if (ih == &adev->irq.ih) { 629 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr); 630 } else if (ih == &adev->irq.ih1) { 631 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, ih->rptr); 632 } else if (ih == &adev->irq.ih2) { 633 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, ih->rptr); 634 } 635 } 636 637 /** 638 * vega10_ih_self_irq - dispatch work for ring 1 and 2 639 * 640 * @adev: amdgpu_device pointer 641 * @source: irq source 642 * @entry: IV with WPTR update 643 * 644 * Update the WPTR from the IV and schedule work to handle the entries. 645 */ 646 static int vega10_ih_self_irq(struct amdgpu_device *adev, 647 struct amdgpu_irq_src *source, 648 struct amdgpu_iv_entry *entry) 649 { 650 uint32_t wptr = cpu_to_le32(entry->src_data[0]); 651 652 switch (entry->ring_id) { 653 case 1: 654 *adev->irq.ih1.wptr_cpu = wptr; 655 schedule_work(&adev->irq.ih1_work); 656 break; 657 case 2: 658 *adev->irq.ih2.wptr_cpu = wptr; 659 schedule_work(&adev->irq.ih2_work); 660 break; 661 default: break; 662 } 663 return 0; 664 } 665 666 static const struct amdgpu_irq_src_funcs vega10_ih_self_irq_funcs = { 667 .process = vega10_ih_self_irq, 668 }; 669 670 static void vega10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 671 { 672 adev->irq.self_irq.num_types = 0; 673 adev->irq.self_irq.funcs = &vega10_ih_self_irq_funcs; 674 } 675 676 static int vega10_ih_early_init(void *handle) 677 { 678 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 679 680 vega10_ih_set_interrupt_funcs(adev); 681 vega10_ih_set_self_irq_funcs(adev); 682 return 0; 683 } 684 685 static int vega10_ih_sw_init(void *handle) 686 { 687 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 688 int r; 689 690 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 691 &adev->irq.self_irq); 692 if (r) 693 return r; 694 695 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true); 696 if (r) 697 return r; 698 699 adev->irq.ih.use_doorbell = true; 700 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 701 702 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 703 if (r) 704 return r; 705 706 adev->irq.ih1.use_doorbell = true; 707 adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; 708 709 r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 710 if (r) 711 return r; 712 713 adev->irq.ih2.use_doorbell = true; 714 adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1; 715 716 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); 717 if (r) 718 return r; 719 720 r = amdgpu_irq_init(adev); 721 722 return r; 723 } 724 725 static int vega10_ih_sw_fini(void *handle) 726 { 727 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 728 729 amdgpu_irq_fini(adev); 730 amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 731 amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 732 amdgpu_ih_ring_fini(adev, &adev->irq.ih); 733 734 return 0; 735 } 736 737 static int vega10_ih_hw_init(void *handle) 738 { 739 int r; 740 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 741 742 r = vega10_ih_irq_init(adev); 743 if (r) 744 return r; 745 746 return 0; 747 } 748 749 static int vega10_ih_hw_fini(void *handle) 750 { 751 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 752 753 vega10_ih_irq_disable(adev); 754 755 return 0; 756 } 757 758 static int vega10_ih_suspend(void *handle) 759 { 760 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 761 762 return vega10_ih_hw_fini(adev); 763 } 764 765 static int vega10_ih_resume(void *handle) 766 { 767 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 768 769 return vega10_ih_hw_init(adev); 770 } 771 772 static bool vega10_ih_is_idle(void *handle) 773 { 774 /* todo */ 775 return true; 776 } 777 778 static int vega10_ih_wait_for_idle(void *handle) 779 { 780 /* todo */ 781 return -ETIMEDOUT; 782 } 783 784 static int vega10_ih_soft_reset(void *handle) 785 { 786 /* todo */ 787 788 return 0; 789 } 790 791 static void vega10_ih_update_clockgating_state(struct amdgpu_device *adev, 792 bool enable) 793 { 794 uint32_t data, def, field_val; 795 796 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 797 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 798 field_val = enable ? 0 : 1; 799 /** 800 * Vega10 does not have IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE 801 * and IH_BUFFER_MEM_CLK_SOFT_OVERRIDE field. 802 */ 803 if (adev->asic_type > CHIP_VEGA10) { 804 data = REG_SET_FIELD(data, IH_CLK_CTRL, 805 IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE, field_val); 806 data = REG_SET_FIELD(data, IH_CLK_CTRL, 807 IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val); 808 } 809 810 data = REG_SET_FIELD(data, IH_CLK_CTRL, 811 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 812 data = REG_SET_FIELD(data, IH_CLK_CTRL, 813 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 814 data = REG_SET_FIELD(data, IH_CLK_CTRL, 815 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 816 data = REG_SET_FIELD(data, IH_CLK_CTRL, 817 DYN_CLK_SOFT_OVERRIDE, field_val); 818 data = REG_SET_FIELD(data, IH_CLK_CTRL, 819 REG_CLK_SOFT_OVERRIDE, field_val); 820 if (def != data) 821 WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 822 } 823 } 824 825 static int vega10_ih_set_clockgating_state(void *handle, 826 enum amd_clockgating_state state) 827 { 828 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 829 830 vega10_ih_update_clockgating_state(adev, 831 state == AMD_CG_STATE_GATE); 832 return 0; 833 834 } 835 836 static int vega10_ih_set_powergating_state(void *handle, 837 enum amd_powergating_state state) 838 { 839 return 0; 840 } 841 842 const struct amd_ip_funcs vega10_ih_ip_funcs = { 843 .name = "vega10_ih", 844 .early_init = vega10_ih_early_init, 845 .late_init = NULL, 846 .sw_init = vega10_ih_sw_init, 847 .sw_fini = vega10_ih_sw_fini, 848 .hw_init = vega10_ih_hw_init, 849 .hw_fini = vega10_ih_hw_fini, 850 .suspend = vega10_ih_suspend, 851 .resume = vega10_ih_resume, 852 .is_idle = vega10_ih_is_idle, 853 .wait_for_idle = vega10_ih_wait_for_idle, 854 .soft_reset = vega10_ih_soft_reset, 855 .set_clockgating_state = vega10_ih_set_clockgating_state, 856 .set_powergating_state = vega10_ih_set_powergating_state, 857 }; 858 859 static const struct amdgpu_ih_funcs vega10_ih_funcs = { 860 .get_wptr = vega10_ih_get_wptr, 861 .decode_iv = vega10_ih_decode_iv, 862 .set_rptr = vega10_ih_set_rptr 863 }; 864 865 static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 866 { 867 adev->irq.ih_funcs = &vega10_ih_funcs; 868 } 869 870 const struct amdgpu_ip_block_version vega10_ih_ip_block = 871 { 872 .type = AMD_IP_BLOCK_TYPE_IH, 873 .major = 4, 874 .minor = 0, 875 .rev = 0, 876 .funcs = &vega10_ih_ip_funcs, 877 }; 878