1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 #include "soc15.h" 29 30 #include "oss/osssys_4_0_offset.h" 31 #include "oss/osssys_4_0_sh_mask.h" 32 33 #include "soc15_common.h" 34 #include "vega10_ih.h" 35 36 #define MAX_REARM_RETRY 10 37 38 static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 39 40 /** 41 * vega10_ih_init_register_offset - Initialize register offset for ih rings 42 * 43 * @adev: amdgpu_device pointer 44 * 45 * Initialize register offset ih rings (VEGA10). 46 */ 47 static void vega10_ih_init_register_offset(struct amdgpu_device *adev) 48 { 49 struct amdgpu_ih_regs *ih_regs; 50 51 if (adev->irq.ih.ring_size) { 52 ih_regs = &adev->irq.ih.ih_regs; 53 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); 54 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); 55 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 56 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 57 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 58 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); 59 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); 60 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); 61 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; 62 } 63 64 if (adev->irq.ih1.ring_size) { 65 ih_regs = &adev->irq.ih1.ih_regs; 66 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); 67 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); 68 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 69 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 70 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 71 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1); 72 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; 73 } 74 75 if (adev->irq.ih2.ring_size) { 76 ih_regs = &adev->irq.ih2.ih_regs; 77 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); 78 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2); 79 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 80 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 81 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 82 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2); 83 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2; 84 } 85 } 86 87 /** 88 * vega10_ih_toggle_ring_interrupts - toggle the interrupt ring buffer 89 * 90 * @adev: amdgpu_device pointer 91 * @ih: amdgpu_ih_ring pointet 92 * @enable: true - enable the interrupts, false - disable the interrupts 93 * 94 * Toggle the interrupt ring buffer (VEGA10) 95 */ 96 static int vega10_ih_toggle_ring_interrupts(struct amdgpu_device *adev, 97 struct amdgpu_ih_ring *ih, 98 bool enable) 99 { 100 struct amdgpu_ih_regs *ih_regs; 101 uint32_t tmp; 102 103 ih_regs = &ih->ih_regs; 104 105 tmp = RREG32(ih_regs->ih_rb_cntl); 106 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); 107 /* enable_intr field is only valid in ring0 */ 108 if (ih == &adev->irq.ih) 109 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); 110 if (amdgpu_sriov_vf(adev)) { 111 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 112 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 113 return -ETIMEDOUT; 114 } 115 } else { 116 WREG32(ih_regs->ih_rb_cntl, tmp); 117 } 118 119 if (enable) { 120 ih->enabled = true; 121 } else { 122 /* set rptr, wptr to 0 */ 123 WREG32(ih_regs->ih_rb_rptr, 0); 124 WREG32(ih_regs->ih_rb_wptr, 0); 125 ih->enabled = false; 126 ih->rptr = 0; 127 } 128 129 return 0; 130 } 131 132 /** 133 * vega10_ih_toggle_interrupts - Toggle all the available interrupt ring buffers 134 * 135 * @adev: amdgpu_device pointer 136 * @enable: enable or disable interrupt ring buffers 137 * 138 * Toggle all the available interrupt ring buffers (VEGA10). 139 */ 140 static int vega10_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable) 141 { 142 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 143 int i; 144 int r; 145 146 for (i = 0; i < ARRAY_SIZE(ih); i++) { 147 if (ih[i]->ring_size) { 148 r = vega10_ih_toggle_ring_interrupts(adev, ih[i], enable); 149 if (r) 150 return r; 151 } 152 } 153 154 return 0; 155 } 156 157 static uint32_t vega10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 158 { 159 int rb_bufsz = order_base_2(ih->ring_size / 4); 160 161 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 162 MC_SPACE, ih->use_bus_addr ? 1 : 4); 163 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 164 WPTR_OVERFLOW_CLEAR, 1); 165 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 166 WPTR_OVERFLOW_ENABLE, 1); 167 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 168 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 169 * value is written to memory 170 */ 171 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 172 WPTR_WRITEBACK_ENABLE, 1); 173 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 174 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 175 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 176 177 return ih_rb_cntl; 178 } 179 180 static uint32_t vega10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 181 { 182 u32 ih_doorbell_rtpr = 0; 183 184 if (ih->use_doorbell) { 185 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 186 IH_DOORBELL_RPTR, OFFSET, 187 ih->doorbell_index); 188 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 189 IH_DOORBELL_RPTR, 190 ENABLE, 1); 191 } else { 192 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 193 IH_DOORBELL_RPTR, 194 ENABLE, 0); 195 } 196 return ih_doorbell_rtpr; 197 } 198 199 /** 200 * vega10_ih_enable_ring - enable an ih ring buffer 201 * 202 * @adev: amdgpu_device pointer 203 * @ih: amdgpu_ih_ring pointer 204 * 205 * Enable an ih ring buffer (VEGA10) 206 */ 207 static int vega10_ih_enable_ring(struct amdgpu_device *adev, 208 struct amdgpu_ih_ring *ih) 209 { 210 struct amdgpu_ih_regs *ih_regs; 211 uint32_t tmp; 212 213 ih_regs = &ih->ih_regs; 214 215 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 216 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); 217 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); 218 219 tmp = RREG32(ih_regs->ih_rb_cntl); 220 tmp = vega10_ih_rb_cntl(ih, tmp); 221 if (ih == &adev->irq.ih) 222 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); 223 if (ih == &adev->irq.ih1) { 224 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0); 225 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); 226 } 227 if (amdgpu_sriov_vf(adev)) { 228 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 229 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 230 return -ETIMEDOUT; 231 } 232 } else { 233 WREG32(ih_regs->ih_rb_cntl, tmp); 234 } 235 236 if (ih == &adev->irq.ih) { 237 /* set the ih ring 0 writeback address whether it's enabled or not */ 238 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); 239 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); 240 } 241 242 /* set rptr, wptr to 0 */ 243 WREG32(ih_regs->ih_rb_wptr, 0); 244 WREG32(ih_regs->ih_rb_rptr, 0); 245 246 WREG32(ih_regs->ih_doorbell_rptr, vega10_ih_doorbell_rptr(ih)); 247 248 return 0; 249 } 250 251 /** 252 * vega10_ih_irq_init - init and enable the interrupt ring 253 * 254 * @adev: amdgpu_device pointer 255 * 256 * Allocate a ring buffer for the interrupt controller, 257 * enable the RLC, disable interrupts, enable the IH 258 * ring buffer and enable it (VI). 259 * Called at device load and reume. 260 * Returns 0 for success, errors for failure. 261 */ 262 static int vega10_ih_irq_init(struct amdgpu_device *adev) 263 { 264 struct amdgpu_ih_ring *ih; 265 u32 ih_rb_cntl, ih_chicken; 266 int ret; 267 u32 tmp; 268 269 /* disable irqs */ 270 ret = vega10_ih_toggle_interrupts(adev, false); 271 if (ret) 272 return ret; 273 274 adev->nbio.funcs->ih_control(adev); 275 276 ih = &adev->irq.ih; 277 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 278 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8); 279 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff); 280 281 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 282 ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl); 283 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 284 !!adev->irq.msi_enabled); 285 if (amdgpu_sriov_vf(adev)) { 286 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 287 DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 288 return -ETIMEDOUT; 289 } 290 } else { 291 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 292 } 293 294 if ((adev->asic_type == CHIP_ARCTURUS && 295 adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) || 296 adev->asic_type == CHIP_RENOIR) { 297 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 298 if (adev->irq.ih.use_bus_addr) { 299 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 300 MC_SPACE_GPA_ENABLE, 1); 301 } else { 302 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 303 MC_SPACE_FBPA_ENABLE, 1); 304 } 305 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 306 } 307 308 /* set the writeback address whether it's enabled or not */ 309 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, 310 lower_32_bits(ih->wptr_addr)); 311 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, 312 upper_32_bits(ih->wptr_addr) & 0xFFFF); 313 314 /* set rptr, wptr to 0 */ 315 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 316 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 317 318 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, 319 vega10_ih_doorbell_rptr(ih)); 320 321 ih = &adev->irq.ih1; 322 if (ih->ring_size) { 323 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING1, ih->gpu_addr >> 8); 324 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING1, 325 (ih->gpu_addr >> 40) & 0xff); 326 327 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 328 ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl); 329 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 330 WPTR_OVERFLOW_ENABLE, 0); 331 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 332 RB_FULL_DRAIN_ENABLE, 1); 333 if (amdgpu_sriov_vf(adev)) { 334 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 335 ih_rb_cntl)) { 336 DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 337 return -ETIMEDOUT; 338 } 339 } else { 340 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 341 } 342 343 /* set rptr, wptr to 0 */ 344 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 345 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 346 347 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1, 348 vega10_ih_doorbell_rptr(ih)); 349 } 350 351 ih = &adev->irq.ih2; 352 if (ih->ring_size) { 353 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING2, ih->gpu_addr >> 8); 354 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING2, 355 (ih->gpu_addr >> 40) & 0xff); 356 357 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 358 ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl); 359 360 if (amdgpu_sriov_vf(adev)) { 361 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 362 ih_rb_cntl)) { 363 DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 364 return -ETIMEDOUT; 365 } 366 } else { 367 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 368 } 369 370 /* set rptr, wptr to 0 */ 371 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 372 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 373 374 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2, 375 vega10_ih_doorbell_rptr(ih)); 376 } 377 378 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 379 tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 380 CLIENT18_IS_STORM_CLIENT, 1); 381 WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 382 383 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 384 tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 385 WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 386 387 pci_set_master(adev->pdev); 388 389 /* enable interrupts */ 390 ret = vega10_ih_toggle_interrupts(adev, true); 391 if (ret) 392 return ret; 393 394 return 0; 395 } 396 397 /** 398 * vega10_ih_irq_disable - disable interrupts 399 * 400 * @adev: amdgpu_device pointer 401 * 402 * Disable interrupts on the hw (VEGA10). 403 */ 404 static void vega10_ih_irq_disable(struct amdgpu_device *adev) 405 { 406 vega10_ih_toggle_interrupts(adev, false); 407 408 /* Wait and acknowledge irq */ 409 mdelay(1); 410 } 411 412 /** 413 * vega10_ih_get_wptr - get the IH ring buffer wptr 414 * 415 * @adev: amdgpu_device pointer 416 * @ih: IH ring buffer to fetch wptr 417 * 418 * Get the IH ring buffer wptr from either the register 419 * or the writeback memory buffer (VEGA10). Also check for 420 * ring buffer overflow and deal with it. 421 * Returns the value of the wptr. 422 */ 423 static u32 vega10_ih_get_wptr(struct amdgpu_device *adev, 424 struct amdgpu_ih_ring *ih) 425 { 426 u32 wptr, reg, tmp; 427 428 wptr = le32_to_cpu(*ih->wptr_cpu); 429 430 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 431 goto out; 432 433 /* Double check that the overflow wasn't already cleared. */ 434 435 if (ih == &adev->irq.ih) 436 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 437 else if (ih == &adev->irq.ih1) 438 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 439 else if (ih == &adev->irq.ih2) 440 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 441 else 442 BUG(); 443 444 wptr = RREG32_NO_KIQ(reg); 445 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 446 goto out; 447 448 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 449 450 /* When a ring buffer overflow happen start parsing interrupt 451 * from the last not overwritten vector (wptr + 32). Hopefully 452 * this should allow us to catchup. 453 */ 454 tmp = (wptr + 32) & ih->ptr_mask; 455 dev_warn(adev->dev, "IH ring buffer overflow " 456 "(0x%08X, 0x%08X, 0x%08X)\n", 457 wptr, ih->rptr, tmp); 458 ih->rptr = tmp; 459 460 if (ih == &adev->irq.ih) 461 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 462 else if (ih == &adev->irq.ih1) 463 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 464 else if (ih == &adev->irq.ih2) 465 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 466 else 467 BUG(); 468 469 tmp = RREG32_NO_KIQ(reg); 470 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 471 WREG32_NO_KIQ(reg, tmp); 472 473 out: 474 return (wptr & ih->ptr_mask); 475 } 476 477 /** 478 * vega10_ih_decode_iv - decode an interrupt vector 479 * 480 * @adev: amdgpu_device pointer 481 * @ih: IH ring buffer to decode 482 * @entry: IV entry to place decoded information into 483 * 484 * Decodes the interrupt vector at the current rptr 485 * position and also advance the position. 486 */ 487 static void vega10_ih_decode_iv(struct amdgpu_device *adev, 488 struct amdgpu_ih_ring *ih, 489 struct amdgpu_iv_entry *entry) 490 { 491 /* wptr/rptr are in bytes! */ 492 u32 ring_index = ih->rptr >> 2; 493 uint32_t dw[8]; 494 495 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 496 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 497 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 498 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 499 dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); 500 dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); 501 dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); 502 dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); 503 504 entry->client_id = dw[0] & 0xff; 505 entry->src_id = (dw[0] >> 8) & 0xff; 506 entry->ring_id = (dw[0] >> 16) & 0xff; 507 entry->vmid = (dw[0] >> 24) & 0xf; 508 entry->vmid_src = (dw[0] >> 31); 509 entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); 510 entry->timestamp_src = dw[2] >> 31; 511 entry->pasid = dw[3] & 0xffff; 512 entry->pasid_src = dw[3] >> 31; 513 entry->src_data[0] = dw[4]; 514 entry->src_data[1] = dw[5]; 515 entry->src_data[2] = dw[6]; 516 entry->src_data[3] = dw[7]; 517 518 /* wptr/rptr are in bytes! */ 519 ih->rptr += 32; 520 } 521 522 /** 523 * vega10_ih_irq_rearm - rearm IRQ if lost 524 * 525 * @adev: amdgpu_device pointer 526 * @ih: IH ring to match 527 * 528 */ 529 static void vega10_ih_irq_rearm(struct amdgpu_device *adev, 530 struct amdgpu_ih_ring *ih) 531 { 532 uint32_t reg_rptr = 0; 533 uint32_t v = 0; 534 uint32_t i = 0; 535 536 if (ih == &adev->irq.ih) 537 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 538 else if (ih == &adev->irq.ih1) 539 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 540 else if (ih == &adev->irq.ih2) 541 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 542 else 543 return; 544 545 /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */ 546 for (i = 0; i < MAX_REARM_RETRY; i++) { 547 v = RREG32_NO_KIQ(reg_rptr); 548 if ((v < ih->ring_size) && (v != ih->rptr)) 549 WDOORBELL32(ih->doorbell_index, ih->rptr); 550 else 551 break; 552 } 553 } 554 555 /** 556 * vega10_ih_set_rptr - set the IH ring buffer rptr 557 * 558 * @adev: amdgpu_device pointer 559 * @ih: IH ring buffer to set rptr 560 * 561 * Set the IH ring buffer rptr. 562 */ 563 static void vega10_ih_set_rptr(struct amdgpu_device *adev, 564 struct amdgpu_ih_ring *ih) 565 { 566 if (ih->use_doorbell) { 567 /* XXX check if swapping is necessary on BE */ 568 *ih->rptr_cpu = ih->rptr; 569 WDOORBELL32(ih->doorbell_index, ih->rptr); 570 571 if (amdgpu_sriov_vf(adev)) 572 vega10_ih_irq_rearm(adev, ih); 573 } else if (ih == &adev->irq.ih) { 574 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr); 575 } else if (ih == &adev->irq.ih1) { 576 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, ih->rptr); 577 } else if (ih == &adev->irq.ih2) { 578 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, ih->rptr); 579 } 580 } 581 582 /** 583 * vega10_ih_self_irq - dispatch work for ring 1 and 2 584 * 585 * @adev: amdgpu_device pointer 586 * @source: irq source 587 * @entry: IV with WPTR update 588 * 589 * Update the WPTR from the IV and schedule work to handle the entries. 590 */ 591 static int vega10_ih_self_irq(struct amdgpu_device *adev, 592 struct amdgpu_irq_src *source, 593 struct amdgpu_iv_entry *entry) 594 { 595 uint32_t wptr = cpu_to_le32(entry->src_data[0]); 596 597 switch (entry->ring_id) { 598 case 1: 599 *adev->irq.ih1.wptr_cpu = wptr; 600 schedule_work(&adev->irq.ih1_work); 601 break; 602 case 2: 603 *adev->irq.ih2.wptr_cpu = wptr; 604 schedule_work(&adev->irq.ih2_work); 605 break; 606 default: break; 607 } 608 return 0; 609 } 610 611 static const struct amdgpu_irq_src_funcs vega10_ih_self_irq_funcs = { 612 .process = vega10_ih_self_irq, 613 }; 614 615 static void vega10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 616 { 617 adev->irq.self_irq.num_types = 0; 618 adev->irq.self_irq.funcs = &vega10_ih_self_irq_funcs; 619 } 620 621 static int vega10_ih_early_init(void *handle) 622 { 623 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 624 625 vega10_ih_set_interrupt_funcs(adev); 626 vega10_ih_set_self_irq_funcs(adev); 627 return 0; 628 } 629 630 static int vega10_ih_sw_init(void *handle) 631 { 632 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 633 int r; 634 635 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 636 &adev->irq.self_irq); 637 if (r) 638 return r; 639 640 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true); 641 if (r) 642 return r; 643 644 adev->irq.ih.use_doorbell = true; 645 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 646 647 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 648 if (r) 649 return r; 650 651 adev->irq.ih1.use_doorbell = true; 652 adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; 653 654 r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 655 if (r) 656 return r; 657 658 adev->irq.ih2.use_doorbell = true; 659 adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1; 660 661 /* initialize ih control registers offset */ 662 vega10_ih_init_register_offset(adev); 663 664 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); 665 if (r) 666 return r; 667 668 r = amdgpu_irq_init(adev); 669 670 return r; 671 } 672 673 static int vega10_ih_sw_fini(void *handle) 674 { 675 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 676 677 amdgpu_irq_fini(adev); 678 amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 679 amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 680 amdgpu_ih_ring_fini(adev, &adev->irq.ih); 681 682 return 0; 683 } 684 685 static int vega10_ih_hw_init(void *handle) 686 { 687 int r; 688 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 689 690 r = vega10_ih_irq_init(adev); 691 if (r) 692 return r; 693 694 return 0; 695 } 696 697 static int vega10_ih_hw_fini(void *handle) 698 { 699 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 700 701 vega10_ih_irq_disable(adev); 702 703 return 0; 704 } 705 706 static int vega10_ih_suspend(void *handle) 707 { 708 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 709 710 return vega10_ih_hw_fini(adev); 711 } 712 713 static int vega10_ih_resume(void *handle) 714 { 715 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 716 717 return vega10_ih_hw_init(adev); 718 } 719 720 static bool vega10_ih_is_idle(void *handle) 721 { 722 /* todo */ 723 return true; 724 } 725 726 static int vega10_ih_wait_for_idle(void *handle) 727 { 728 /* todo */ 729 return -ETIMEDOUT; 730 } 731 732 static int vega10_ih_soft_reset(void *handle) 733 { 734 /* todo */ 735 736 return 0; 737 } 738 739 static void vega10_ih_update_clockgating_state(struct amdgpu_device *adev, 740 bool enable) 741 { 742 uint32_t data, def, field_val; 743 744 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 745 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 746 field_val = enable ? 0 : 1; 747 /** 748 * Vega10 does not have IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE 749 * and IH_BUFFER_MEM_CLK_SOFT_OVERRIDE field. 750 */ 751 if (adev->asic_type > CHIP_VEGA10) { 752 data = REG_SET_FIELD(data, IH_CLK_CTRL, 753 IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE, field_val); 754 data = REG_SET_FIELD(data, IH_CLK_CTRL, 755 IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val); 756 } 757 758 data = REG_SET_FIELD(data, IH_CLK_CTRL, 759 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 760 data = REG_SET_FIELD(data, IH_CLK_CTRL, 761 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 762 data = REG_SET_FIELD(data, IH_CLK_CTRL, 763 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 764 data = REG_SET_FIELD(data, IH_CLK_CTRL, 765 DYN_CLK_SOFT_OVERRIDE, field_val); 766 data = REG_SET_FIELD(data, IH_CLK_CTRL, 767 REG_CLK_SOFT_OVERRIDE, field_val); 768 if (def != data) 769 WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 770 } 771 } 772 773 static int vega10_ih_set_clockgating_state(void *handle, 774 enum amd_clockgating_state state) 775 { 776 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 777 778 vega10_ih_update_clockgating_state(adev, 779 state == AMD_CG_STATE_GATE); 780 return 0; 781 782 } 783 784 static int vega10_ih_set_powergating_state(void *handle, 785 enum amd_powergating_state state) 786 { 787 return 0; 788 } 789 790 const struct amd_ip_funcs vega10_ih_ip_funcs = { 791 .name = "vega10_ih", 792 .early_init = vega10_ih_early_init, 793 .late_init = NULL, 794 .sw_init = vega10_ih_sw_init, 795 .sw_fini = vega10_ih_sw_fini, 796 .hw_init = vega10_ih_hw_init, 797 .hw_fini = vega10_ih_hw_fini, 798 .suspend = vega10_ih_suspend, 799 .resume = vega10_ih_resume, 800 .is_idle = vega10_ih_is_idle, 801 .wait_for_idle = vega10_ih_wait_for_idle, 802 .soft_reset = vega10_ih_soft_reset, 803 .set_clockgating_state = vega10_ih_set_clockgating_state, 804 .set_powergating_state = vega10_ih_set_powergating_state, 805 }; 806 807 static const struct amdgpu_ih_funcs vega10_ih_funcs = { 808 .get_wptr = vega10_ih_get_wptr, 809 .decode_iv = vega10_ih_decode_iv, 810 .set_rptr = vega10_ih_set_rptr 811 }; 812 813 static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 814 { 815 adev->irq.ih_funcs = &vega10_ih_funcs; 816 } 817 818 const struct amdgpu_ip_block_version vega10_ih_ip_block = 819 { 820 .type = AMD_IP_BLOCK_TYPE_IH, 821 .major = 4, 822 .minor = 0, 823 .rev = 0, 824 .funcs = &vega10_ih_ip_funcs, 825 }; 826