1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <drm/drmP.h> 24 #include "amdgpu.h" 25 #include "amdgpu_ih.h" 26 #include "soc15.h" 27 28 #include "oss/osssys_4_0_offset.h" 29 #include "oss/osssys_4_0_sh_mask.h" 30 31 #include "soc15_common.h" 32 #include "vega10_ih.h" 33 34 35 36 static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 37 38 /** 39 * vega10_ih_enable_interrupts - Enable the interrupt ring buffer 40 * 41 * @adev: amdgpu_device pointer 42 * 43 * Enable the interrupt ring buffer (VEGA10). 44 */ 45 static void vega10_ih_enable_interrupts(struct amdgpu_device *adev) 46 { 47 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 48 49 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); 50 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); 51 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 52 adev->irq.ih.enabled = true; 53 } 54 55 /** 56 * vega10_ih_disable_interrupts - Disable the interrupt ring buffer 57 * 58 * @adev: amdgpu_device pointer 59 * 60 * Disable the interrupt ring buffer (VEGA10). 61 */ 62 static void vega10_ih_disable_interrupts(struct amdgpu_device *adev) 63 { 64 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 65 66 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); 67 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); 68 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 69 /* set rptr, wptr to 0 */ 70 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 71 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 72 adev->irq.ih.enabled = false; 73 adev->irq.ih.rptr = 0; 74 } 75 76 /** 77 * vega10_ih_irq_init - init and enable the interrupt ring 78 * 79 * @adev: amdgpu_device pointer 80 * 81 * Allocate a ring buffer for the interrupt controller, 82 * enable the RLC, disable interrupts, enable the IH 83 * ring buffer and enable it (VI). 84 * Called at device load and reume. 85 * Returns 0 for success, errors for failure. 86 */ 87 static int vega10_ih_irq_init(struct amdgpu_device *adev) 88 { 89 struct amdgpu_ih_ring *ih = &adev->irq.ih; 90 int ret = 0; 91 int rb_bufsz; 92 u32 ih_rb_cntl, ih_doorbell_rtpr; 93 u32 tmp; 94 95 /* disable irqs */ 96 vega10_ih_disable_interrupts(adev); 97 98 adev->nbio_funcs->ih_control(adev); 99 100 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 101 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 102 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); 103 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, 104 (adev->irq.ih.gpu_addr >> 40) & 0xff); 105 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 106 ih->use_bus_addr ? 1 : 4); 107 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); 108 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 109 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1); 110 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 111 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */ 112 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); 113 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 114 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 115 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 116 117 if (adev->irq.msi_enabled) 118 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1); 119 120 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 121 122 /* set the writeback address whether it's enabled or not */ 123 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, 124 lower_32_bits(ih->wptr_addr)); 125 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, 126 upper_32_bits(ih->wptr_addr) & 0xFFFF); 127 128 /* set rptr, wptr to 0 */ 129 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 130 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 131 132 ih_doorbell_rtpr = RREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR); 133 if (adev->irq.ih.use_doorbell) { 134 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, 135 OFFSET, adev->irq.ih.doorbell_index); 136 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, 137 ENABLE, 1); 138 } else { 139 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, 140 ENABLE, 0); 141 } 142 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, ih_doorbell_rtpr); 143 adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, 144 adev->irq.ih.doorbell_index); 145 146 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 147 tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 148 CLIENT18_IS_STORM_CLIENT, 1); 149 WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 150 151 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 152 tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 153 WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 154 155 pci_set_master(adev->pdev); 156 157 /* enable interrupts */ 158 vega10_ih_enable_interrupts(adev); 159 160 return ret; 161 } 162 163 /** 164 * vega10_ih_irq_disable - disable interrupts 165 * 166 * @adev: amdgpu_device pointer 167 * 168 * Disable interrupts on the hw (VEGA10). 169 */ 170 static void vega10_ih_irq_disable(struct amdgpu_device *adev) 171 { 172 vega10_ih_disable_interrupts(adev); 173 174 /* Wait and acknowledge irq */ 175 mdelay(1); 176 } 177 178 /** 179 * vega10_ih_get_wptr - get the IH ring buffer wptr 180 * 181 * @adev: amdgpu_device pointer 182 * 183 * Get the IH ring buffer wptr from either the register 184 * or the writeback memory buffer (VEGA10). Also check for 185 * ring buffer overflow and deal with it. 186 * Returns the value of the wptr. 187 */ 188 static u32 vega10_ih_get_wptr(struct amdgpu_device *adev, 189 struct amdgpu_ih_ring *ih) 190 { 191 u32 wptr, tmp; 192 193 wptr = le32_to_cpu(*ih->wptr_cpu); 194 195 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { 196 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 197 198 /* When a ring buffer overflow happen start parsing interrupt 199 * from the last not overwritten vector (wptr + 32). Hopefully 200 * this should allow us to catchup. 201 */ 202 tmp = (wptr + 32) & ih->ptr_mask; 203 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", 204 wptr, ih->rptr, tmp); 205 ih->rptr = tmp; 206 207 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL)); 208 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 209 WREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), tmp); 210 } 211 return (wptr & ih->ptr_mask); 212 } 213 214 /** 215 * vega10_ih_decode_iv - decode an interrupt vector 216 * 217 * @adev: amdgpu_device pointer 218 * 219 * Decodes the interrupt vector at the current rptr 220 * position and also advance the position. 221 */ 222 static void vega10_ih_decode_iv(struct amdgpu_device *adev, 223 struct amdgpu_ih_ring *ih, 224 struct amdgpu_iv_entry *entry) 225 { 226 /* wptr/rptr are in bytes! */ 227 u32 ring_index = ih->rptr >> 2; 228 uint32_t dw[8]; 229 230 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 231 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 232 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 233 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 234 dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); 235 dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); 236 dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); 237 dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); 238 239 entry->client_id = dw[0] & 0xff; 240 entry->src_id = (dw[0] >> 8) & 0xff; 241 entry->ring_id = (dw[0] >> 16) & 0xff; 242 entry->vmid = (dw[0] >> 24) & 0xf; 243 entry->vmid_src = (dw[0] >> 31); 244 entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); 245 entry->timestamp_src = dw[2] >> 31; 246 entry->pasid = dw[3] & 0xffff; 247 entry->pasid_src = dw[3] >> 31; 248 entry->src_data[0] = dw[4]; 249 entry->src_data[1] = dw[5]; 250 entry->src_data[2] = dw[6]; 251 entry->src_data[3] = dw[7]; 252 253 /* wptr/rptr are in bytes! */ 254 ih->rptr += 32; 255 } 256 257 /** 258 * vega10_ih_set_rptr - set the IH ring buffer rptr 259 * 260 * @adev: amdgpu_device pointer 261 * 262 * Set the IH ring buffer rptr. 263 */ 264 static void vega10_ih_set_rptr(struct amdgpu_device *adev, 265 struct amdgpu_ih_ring *ih) 266 { 267 if (ih->use_doorbell) { 268 /* XXX check if swapping is necessary on BE */ 269 *ih->rptr_cpu = ih->rptr; 270 WDOORBELL32(ih->doorbell_index, ih->rptr); 271 } else { 272 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr); 273 } 274 } 275 276 static int vega10_ih_early_init(void *handle) 277 { 278 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 279 280 vega10_ih_set_interrupt_funcs(adev); 281 return 0; 282 } 283 284 static int vega10_ih_sw_init(void *handle) 285 { 286 int r; 287 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 288 289 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true); 290 if (r) 291 return r; 292 293 adev->irq.ih.use_doorbell = true; 294 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 295 296 r = amdgpu_irq_init(adev); 297 298 return r; 299 } 300 301 static int vega10_ih_sw_fini(void *handle) 302 { 303 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 304 305 amdgpu_irq_fini(adev); 306 amdgpu_ih_ring_fini(adev, &adev->irq.ih); 307 308 return 0; 309 } 310 311 static int vega10_ih_hw_init(void *handle) 312 { 313 int r; 314 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 315 316 r = vega10_ih_irq_init(adev); 317 if (r) 318 return r; 319 320 return 0; 321 } 322 323 static int vega10_ih_hw_fini(void *handle) 324 { 325 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 326 327 vega10_ih_irq_disable(adev); 328 329 return 0; 330 } 331 332 static int vega10_ih_suspend(void *handle) 333 { 334 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 335 336 return vega10_ih_hw_fini(adev); 337 } 338 339 static int vega10_ih_resume(void *handle) 340 { 341 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 342 343 return vega10_ih_hw_init(adev); 344 } 345 346 static bool vega10_ih_is_idle(void *handle) 347 { 348 /* todo */ 349 return true; 350 } 351 352 static int vega10_ih_wait_for_idle(void *handle) 353 { 354 /* todo */ 355 return -ETIMEDOUT; 356 } 357 358 static int vega10_ih_soft_reset(void *handle) 359 { 360 /* todo */ 361 362 return 0; 363 } 364 365 static int vega10_ih_set_clockgating_state(void *handle, 366 enum amd_clockgating_state state) 367 { 368 return 0; 369 } 370 371 static int vega10_ih_set_powergating_state(void *handle, 372 enum amd_powergating_state state) 373 { 374 return 0; 375 } 376 377 const struct amd_ip_funcs vega10_ih_ip_funcs = { 378 .name = "vega10_ih", 379 .early_init = vega10_ih_early_init, 380 .late_init = NULL, 381 .sw_init = vega10_ih_sw_init, 382 .sw_fini = vega10_ih_sw_fini, 383 .hw_init = vega10_ih_hw_init, 384 .hw_fini = vega10_ih_hw_fini, 385 .suspend = vega10_ih_suspend, 386 .resume = vega10_ih_resume, 387 .is_idle = vega10_ih_is_idle, 388 .wait_for_idle = vega10_ih_wait_for_idle, 389 .soft_reset = vega10_ih_soft_reset, 390 .set_clockgating_state = vega10_ih_set_clockgating_state, 391 .set_powergating_state = vega10_ih_set_powergating_state, 392 }; 393 394 static const struct amdgpu_ih_funcs vega10_ih_funcs = { 395 .get_wptr = vega10_ih_get_wptr, 396 .decode_iv = vega10_ih_decode_iv, 397 .set_rptr = vega10_ih_set_rptr 398 }; 399 400 static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 401 { 402 adev->irq.ih_funcs = &vega10_ih_funcs; 403 } 404 405 const struct amdgpu_ip_block_version vega10_ih_ip_block = 406 { 407 .type = AMD_IP_BLOCK_TYPE_IH, 408 .major = 4, 409 .minor = 0, 410 .rev = 0, 411 .funcs = &vega10_ih_ip_funcs, 412 }; 413