1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 #include "soc15.h" 29 30 #include "oss/osssys_4_0_offset.h" 31 #include "oss/osssys_4_0_sh_mask.h" 32 33 #include "soc15_common.h" 34 #include "vega10_ih.h" 35 36 #define MAX_REARM_RETRY 10 37 38 static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 39 40 /** 41 * vega10_ih_enable_interrupts - Enable the interrupt ring buffer 42 * 43 * @adev: amdgpu_device pointer 44 * 45 * Enable the interrupt ring buffer (VEGA10). 46 */ 47 static void vega10_ih_enable_interrupts(struct amdgpu_device *adev) 48 { 49 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 50 51 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); 52 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); 53 if (amdgpu_virt_support_psp_prg_ih_reg(adev)) { 54 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 55 DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 56 return; 57 } 58 } else { 59 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 60 } 61 adev->irq.ih.enabled = true; 62 63 if (adev->irq.ih1.ring_size) { 64 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 65 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 66 RB_ENABLE, 1); 67 if (amdgpu_virt_support_psp_prg_ih_reg(adev)) { 68 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 69 ih_rb_cntl)) { 70 DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 71 return; 72 } 73 } else { 74 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 75 } 76 adev->irq.ih1.enabled = true; 77 } 78 79 if (adev->irq.ih2.ring_size) { 80 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 81 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 82 RB_ENABLE, 1); 83 if (amdgpu_virt_support_psp_prg_ih_reg(adev)) { 84 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 85 ih_rb_cntl)) { 86 DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 87 return; 88 } 89 } else { 90 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 91 } 92 adev->irq.ih2.enabled = true; 93 } 94 } 95 96 /** 97 * vega10_ih_disable_interrupts - Disable the interrupt ring buffer 98 * 99 * @adev: amdgpu_device pointer 100 * 101 * Disable the interrupt ring buffer (VEGA10). 102 */ 103 static void vega10_ih_disable_interrupts(struct amdgpu_device *adev) 104 { 105 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 106 107 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); 108 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); 109 if (amdgpu_virt_support_psp_prg_ih_reg(adev)) { 110 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 111 DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 112 return; 113 } 114 } else { 115 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 116 } 117 118 /* set rptr, wptr to 0 */ 119 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 120 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 121 adev->irq.ih.enabled = false; 122 adev->irq.ih.rptr = 0; 123 124 if (adev->irq.ih1.ring_size) { 125 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 126 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 127 RB_ENABLE, 0); 128 if (amdgpu_virt_support_psp_prg_ih_reg(adev)) { 129 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 130 ih_rb_cntl)) { 131 DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 132 return; 133 } 134 } else { 135 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 136 } 137 /* set rptr, wptr to 0 */ 138 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 139 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 140 adev->irq.ih1.enabled = false; 141 adev->irq.ih1.rptr = 0; 142 } 143 144 if (adev->irq.ih2.ring_size) { 145 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 146 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 147 RB_ENABLE, 0); 148 if (amdgpu_virt_support_psp_prg_ih_reg(adev)) { 149 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 150 ih_rb_cntl)) { 151 DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 152 return; 153 } 154 } else { 155 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 156 } 157 158 /* set rptr, wptr to 0 */ 159 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 160 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 161 adev->irq.ih2.enabled = false; 162 adev->irq.ih2.rptr = 0; 163 } 164 } 165 166 static uint32_t vega10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 167 { 168 int rb_bufsz = order_base_2(ih->ring_size / 4); 169 170 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 171 MC_SPACE, ih->use_bus_addr ? 1 : 4); 172 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 173 WPTR_OVERFLOW_CLEAR, 1); 174 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 175 WPTR_OVERFLOW_ENABLE, 1); 176 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 177 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 178 * value is written to memory 179 */ 180 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 181 WPTR_WRITEBACK_ENABLE, 1); 182 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 183 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 184 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 185 186 return ih_rb_cntl; 187 } 188 189 static uint32_t vega10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 190 { 191 u32 ih_doorbell_rtpr = 0; 192 193 if (ih->use_doorbell) { 194 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 195 IH_DOORBELL_RPTR, OFFSET, 196 ih->doorbell_index); 197 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 198 IH_DOORBELL_RPTR, 199 ENABLE, 1); 200 } else { 201 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 202 IH_DOORBELL_RPTR, 203 ENABLE, 0); 204 } 205 return ih_doorbell_rtpr; 206 } 207 208 /** 209 * vega10_ih_irq_init - init and enable the interrupt ring 210 * 211 * @adev: amdgpu_device pointer 212 * 213 * Allocate a ring buffer for the interrupt controller, 214 * enable the RLC, disable interrupts, enable the IH 215 * ring buffer and enable it (VI). 216 * Called at device load and reume. 217 * Returns 0 for success, errors for failure. 218 */ 219 static int vega10_ih_irq_init(struct amdgpu_device *adev) 220 { 221 struct amdgpu_ih_ring *ih; 222 u32 ih_rb_cntl; 223 int ret = 0; 224 u32 tmp; 225 226 /* disable irqs */ 227 vega10_ih_disable_interrupts(adev); 228 229 adev->nbio_funcs->ih_control(adev); 230 231 ih = &adev->irq.ih; 232 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 233 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8); 234 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff); 235 236 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 237 ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl); 238 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 239 !!adev->irq.msi_enabled); 240 241 if (amdgpu_virt_support_psp_prg_ih_reg(adev)) { 242 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 243 DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 244 return -ETIMEDOUT; 245 } 246 } else { 247 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 248 } 249 250 /* set the writeback address whether it's enabled or not */ 251 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, 252 lower_32_bits(ih->wptr_addr)); 253 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, 254 upper_32_bits(ih->wptr_addr) & 0xFFFF); 255 256 /* set rptr, wptr to 0 */ 257 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 258 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 259 260 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, 261 vega10_ih_doorbell_rptr(ih)); 262 263 ih = &adev->irq.ih1; 264 if (ih->ring_size) { 265 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING1, ih->gpu_addr >> 8); 266 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING1, 267 (ih->gpu_addr >> 40) & 0xff); 268 269 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 270 ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl); 271 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 272 WPTR_OVERFLOW_ENABLE, 0); 273 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 274 RB_FULL_DRAIN_ENABLE, 1); 275 if (amdgpu_virt_support_psp_prg_ih_reg(adev)) { 276 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 277 ih_rb_cntl)) { 278 DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 279 return -ETIMEDOUT; 280 } 281 } else { 282 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 283 } 284 285 /* set rptr, wptr to 0 */ 286 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 287 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 288 289 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1, 290 vega10_ih_doorbell_rptr(ih)); 291 } 292 293 ih = &adev->irq.ih2; 294 if (ih->ring_size) { 295 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING2, ih->gpu_addr >> 8); 296 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING2, 297 (ih->gpu_addr >> 40) & 0xff); 298 299 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 300 ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl); 301 302 if (amdgpu_virt_support_psp_prg_ih_reg(adev)) { 303 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 304 ih_rb_cntl)) { 305 DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 306 return -ETIMEDOUT; 307 } 308 } else { 309 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 310 } 311 312 /* set rptr, wptr to 0 */ 313 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 314 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 315 316 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2, 317 vega10_ih_doorbell_rptr(ih)); 318 } 319 320 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 321 tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 322 CLIENT18_IS_STORM_CLIENT, 1); 323 WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 324 325 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 326 tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 327 WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 328 329 pci_set_master(adev->pdev); 330 331 /* enable interrupts */ 332 vega10_ih_enable_interrupts(adev); 333 334 return ret; 335 } 336 337 /** 338 * vega10_ih_irq_disable - disable interrupts 339 * 340 * @adev: amdgpu_device pointer 341 * 342 * Disable interrupts on the hw (VEGA10). 343 */ 344 static void vega10_ih_irq_disable(struct amdgpu_device *adev) 345 { 346 vega10_ih_disable_interrupts(adev); 347 348 /* Wait and acknowledge irq */ 349 mdelay(1); 350 } 351 352 /** 353 * vega10_ih_get_wptr - get the IH ring buffer wptr 354 * 355 * @adev: amdgpu_device pointer 356 * 357 * Get the IH ring buffer wptr from either the register 358 * or the writeback memory buffer (VEGA10). Also check for 359 * ring buffer overflow and deal with it. 360 * Returns the value of the wptr. 361 */ 362 static u32 vega10_ih_get_wptr(struct amdgpu_device *adev, 363 struct amdgpu_ih_ring *ih) 364 { 365 u32 wptr, reg, tmp; 366 367 wptr = le32_to_cpu(*ih->wptr_cpu); 368 369 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 370 goto out; 371 372 /* Double check that the overflow wasn't already cleared. */ 373 374 if (ih == &adev->irq.ih) 375 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 376 else if (ih == &adev->irq.ih1) 377 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 378 else if (ih == &adev->irq.ih2) 379 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 380 else 381 BUG(); 382 383 wptr = RREG32_NO_KIQ(reg); 384 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 385 goto out; 386 387 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 388 389 /* When a ring buffer overflow happen start parsing interrupt 390 * from the last not overwritten vector (wptr + 32). Hopefully 391 * this should allow us to catchup. 392 */ 393 tmp = (wptr + 32) & ih->ptr_mask; 394 dev_warn(adev->dev, "IH ring buffer overflow " 395 "(0x%08X, 0x%08X, 0x%08X)\n", 396 wptr, ih->rptr, tmp); 397 ih->rptr = tmp; 398 399 if (ih == &adev->irq.ih) 400 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 401 else if (ih == &adev->irq.ih1) 402 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 403 else if (ih == &adev->irq.ih2) 404 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 405 else 406 BUG(); 407 408 tmp = RREG32_NO_KIQ(reg); 409 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 410 WREG32_NO_KIQ(reg, tmp); 411 412 out: 413 return (wptr & ih->ptr_mask); 414 } 415 416 /** 417 * vega10_ih_decode_iv - decode an interrupt vector 418 * 419 * @adev: amdgpu_device pointer 420 * 421 * Decodes the interrupt vector at the current rptr 422 * position and also advance the position. 423 */ 424 static void vega10_ih_decode_iv(struct amdgpu_device *adev, 425 struct amdgpu_ih_ring *ih, 426 struct amdgpu_iv_entry *entry) 427 { 428 /* wptr/rptr are in bytes! */ 429 u32 ring_index = ih->rptr >> 2; 430 uint32_t dw[8]; 431 432 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 433 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 434 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 435 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 436 dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); 437 dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); 438 dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); 439 dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); 440 441 entry->client_id = dw[0] & 0xff; 442 entry->src_id = (dw[0] >> 8) & 0xff; 443 entry->ring_id = (dw[0] >> 16) & 0xff; 444 entry->vmid = (dw[0] >> 24) & 0xf; 445 entry->vmid_src = (dw[0] >> 31); 446 entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); 447 entry->timestamp_src = dw[2] >> 31; 448 entry->pasid = dw[3] & 0xffff; 449 entry->pasid_src = dw[3] >> 31; 450 entry->src_data[0] = dw[4]; 451 entry->src_data[1] = dw[5]; 452 entry->src_data[2] = dw[6]; 453 entry->src_data[3] = dw[7]; 454 455 /* wptr/rptr are in bytes! */ 456 ih->rptr += 32; 457 } 458 459 /** 460 * vega10_ih_irq_rearm - rearm IRQ if lost 461 * 462 * @adev: amdgpu_device pointer 463 * 464 */ 465 static void vega10_ih_irq_rearm(struct amdgpu_device *adev, 466 struct amdgpu_ih_ring *ih) 467 { 468 uint32_t reg_rptr = 0; 469 uint32_t v = 0; 470 uint32_t i = 0; 471 472 if (ih == &adev->irq.ih) 473 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 474 else if (ih == &adev->irq.ih1) 475 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 476 else if (ih == &adev->irq.ih2) 477 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 478 else 479 return; 480 481 /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */ 482 for (i = 0; i < MAX_REARM_RETRY; i++) { 483 v = RREG32_NO_KIQ(reg_rptr); 484 if ((v < ih->ring_size) && (v != ih->rptr)) 485 WDOORBELL32(ih->doorbell_index, ih->rptr); 486 else 487 break; 488 } 489 } 490 491 /** 492 * vega10_ih_set_rptr - set the IH ring buffer rptr 493 * 494 * @adev: amdgpu_device pointer 495 * 496 * Set the IH ring buffer rptr. 497 */ 498 static void vega10_ih_set_rptr(struct amdgpu_device *adev, 499 struct amdgpu_ih_ring *ih) 500 { 501 if (ih->use_doorbell) { 502 /* XXX check if swapping is necessary on BE */ 503 *ih->rptr_cpu = ih->rptr; 504 WDOORBELL32(ih->doorbell_index, ih->rptr); 505 506 if (amdgpu_sriov_vf(adev)) 507 vega10_ih_irq_rearm(adev, ih); 508 } else if (ih == &adev->irq.ih) { 509 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr); 510 } else if (ih == &adev->irq.ih1) { 511 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, ih->rptr); 512 } else if (ih == &adev->irq.ih2) { 513 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, ih->rptr); 514 } 515 } 516 517 /** 518 * vega10_ih_self_irq - dispatch work for ring 1 and 2 519 * 520 * @adev: amdgpu_device pointer 521 * @source: irq source 522 * @entry: IV with WPTR update 523 * 524 * Update the WPTR from the IV and schedule work to handle the entries. 525 */ 526 static int vega10_ih_self_irq(struct amdgpu_device *adev, 527 struct amdgpu_irq_src *source, 528 struct amdgpu_iv_entry *entry) 529 { 530 uint32_t wptr = cpu_to_le32(entry->src_data[0]); 531 532 switch (entry->ring_id) { 533 case 1: 534 *adev->irq.ih1.wptr_cpu = wptr; 535 schedule_work(&adev->irq.ih1_work); 536 break; 537 case 2: 538 *adev->irq.ih2.wptr_cpu = wptr; 539 schedule_work(&adev->irq.ih2_work); 540 break; 541 default: break; 542 } 543 return 0; 544 } 545 546 static const struct amdgpu_irq_src_funcs vega10_ih_self_irq_funcs = { 547 .process = vega10_ih_self_irq, 548 }; 549 550 static void vega10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 551 { 552 adev->irq.self_irq.num_types = 0; 553 adev->irq.self_irq.funcs = &vega10_ih_self_irq_funcs; 554 } 555 556 static int vega10_ih_early_init(void *handle) 557 { 558 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 559 560 vega10_ih_set_interrupt_funcs(adev); 561 vega10_ih_set_self_irq_funcs(adev); 562 return 0; 563 } 564 565 static int vega10_ih_sw_init(void *handle) 566 { 567 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 568 int r; 569 570 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 571 &adev->irq.self_irq); 572 if (r) 573 return r; 574 575 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true); 576 if (r) 577 return r; 578 579 adev->irq.ih.use_doorbell = true; 580 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 581 582 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 583 if (r) 584 return r; 585 586 adev->irq.ih1.use_doorbell = true; 587 adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; 588 589 r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 590 if (r) 591 return r; 592 593 adev->irq.ih2.use_doorbell = true; 594 adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1; 595 596 r = amdgpu_irq_init(adev); 597 598 return r; 599 } 600 601 static int vega10_ih_sw_fini(void *handle) 602 { 603 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 604 605 amdgpu_irq_fini(adev); 606 amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 607 amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 608 amdgpu_ih_ring_fini(adev, &adev->irq.ih); 609 610 return 0; 611 } 612 613 static int vega10_ih_hw_init(void *handle) 614 { 615 int r; 616 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 617 618 r = vega10_ih_irq_init(adev); 619 if (r) 620 return r; 621 622 return 0; 623 } 624 625 static int vega10_ih_hw_fini(void *handle) 626 { 627 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 628 629 vega10_ih_irq_disable(adev); 630 631 return 0; 632 } 633 634 static int vega10_ih_suspend(void *handle) 635 { 636 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 637 638 return vega10_ih_hw_fini(adev); 639 } 640 641 static int vega10_ih_resume(void *handle) 642 { 643 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 644 645 return vega10_ih_hw_init(adev); 646 } 647 648 static bool vega10_ih_is_idle(void *handle) 649 { 650 /* todo */ 651 return true; 652 } 653 654 static int vega10_ih_wait_for_idle(void *handle) 655 { 656 /* todo */ 657 return -ETIMEDOUT; 658 } 659 660 static int vega10_ih_soft_reset(void *handle) 661 { 662 /* todo */ 663 664 return 0; 665 } 666 667 static int vega10_ih_set_clockgating_state(void *handle, 668 enum amd_clockgating_state state) 669 { 670 return 0; 671 } 672 673 static int vega10_ih_set_powergating_state(void *handle, 674 enum amd_powergating_state state) 675 { 676 return 0; 677 } 678 679 const struct amd_ip_funcs vega10_ih_ip_funcs = { 680 .name = "vega10_ih", 681 .early_init = vega10_ih_early_init, 682 .late_init = NULL, 683 .sw_init = vega10_ih_sw_init, 684 .sw_fini = vega10_ih_sw_fini, 685 .hw_init = vega10_ih_hw_init, 686 .hw_fini = vega10_ih_hw_fini, 687 .suspend = vega10_ih_suspend, 688 .resume = vega10_ih_resume, 689 .is_idle = vega10_ih_is_idle, 690 .wait_for_idle = vega10_ih_wait_for_idle, 691 .soft_reset = vega10_ih_soft_reset, 692 .set_clockgating_state = vega10_ih_set_clockgating_state, 693 .set_powergating_state = vega10_ih_set_powergating_state, 694 }; 695 696 static const struct amdgpu_ih_funcs vega10_ih_funcs = { 697 .get_wptr = vega10_ih_get_wptr, 698 .decode_iv = vega10_ih_decode_iv, 699 .set_rptr = vega10_ih_set_rptr 700 }; 701 702 static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 703 { 704 adev->irq.ih_funcs = &vega10_ih_funcs; 705 } 706 707 const struct amdgpu_ip_block_version vega10_ih_ip_block = 708 { 709 .type = AMD_IP_BLOCK_TYPE_IH, 710 .major = 4, 711 .minor = 0, 712 .rev = 0, 713 .funcs = &vega10_ih_ip_funcs, 714 }; 715