1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 #include "soc15.h" 29 30 #include "oss/osssys_4_0_offset.h" 31 #include "oss/osssys_4_0_sh_mask.h" 32 33 #include "soc15_common.h" 34 #include "vega10_ih.h" 35 36 #define MAX_REARM_RETRY 10 37 38 static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 39 40 /** 41 * vega10_ih_init_register_offset - Initialize register offset for ih rings 42 * 43 * @adev: amdgpu_device pointer 44 * 45 * Initialize register offset ih rings (VEGA10). 46 */ 47 static void vega10_ih_init_register_offset(struct amdgpu_device *adev) 48 { 49 struct amdgpu_ih_regs *ih_regs; 50 51 if (adev->irq.ih.ring_size) { 52 ih_regs = &adev->irq.ih.ih_regs; 53 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); 54 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); 55 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 56 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 57 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 58 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); 59 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); 60 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); 61 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; 62 } 63 64 if (adev->irq.ih1.ring_size) { 65 ih_regs = &adev->irq.ih1.ih_regs; 66 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); 67 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); 68 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 69 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 70 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 71 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1); 72 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; 73 } 74 75 if (adev->irq.ih2.ring_size) { 76 ih_regs = &adev->irq.ih2.ih_regs; 77 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); 78 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2); 79 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 80 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 81 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 82 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2); 83 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2; 84 } 85 } 86 87 /** 88 * vega10_ih_toggle_ring_interrupts - toggle the interrupt ring buffer 89 * 90 * @adev: amdgpu_device pointer 91 * @ih: amdgpu_ih_ring pointet 92 * @enable: true - enable the interrupts, false - disable the interrupts 93 * 94 * Toggle the interrupt ring buffer (VEGA10) 95 */ 96 static int vega10_ih_toggle_ring_interrupts(struct amdgpu_device *adev, 97 struct amdgpu_ih_ring *ih, 98 bool enable) 99 { 100 struct amdgpu_ih_regs *ih_regs; 101 uint32_t tmp; 102 103 ih_regs = &ih->ih_regs; 104 105 tmp = RREG32(ih_regs->ih_rb_cntl); 106 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); 107 /* enable_intr field is only valid in ring0 */ 108 if (ih == &adev->irq.ih) 109 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); 110 if (amdgpu_sriov_vf(adev)) { 111 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 112 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 113 return -ETIMEDOUT; 114 } 115 } else { 116 WREG32(ih_regs->ih_rb_cntl, tmp); 117 } 118 119 if (enable) { 120 ih->enabled = true; 121 } else { 122 /* set rptr, wptr to 0 */ 123 WREG32(ih_regs->ih_rb_rptr, 0); 124 WREG32(ih_regs->ih_rb_wptr, 0); 125 ih->enabled = false; 126 ih->rptr = 0; 127 } 128 129 return 0; 130 } 131 132 /** 133 * vega10_ih_toggle_interrupts - Toggle all the available interrupt ring buffers 134 * 135 * @adev: amdgpu_device pointer 136 * @enable: enable or disable interrupt ring buffers 137 * 138 * Toggle all the available interrupt ring buffers (VEGA10). 139 */ 140 static int vega10_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable) 141 { 142 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 143 int i; 144 int r; 145 146 for (i = 0; i < ARRAY_SIZE(ih); i++) { 147 if (ih[i]->ring_size) { 148 r = vega10_ih_toggle_ring_interrupts(adev, ih[i], enable); 149 if (r) 150 return r; 151 } 152 } 153 154 return 0; 155 } 156 157 static uint32_t vega10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 158 { 159 int rb_bufsz = order_base_2(ih->ring_size / 4); 160 161 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 162 MC_SPACE, ih->use_bus_addr ? 1 : 4); 163 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 164 WPTR_OVERFLOW_CLEAR, 1); 165 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 166 WPTR_OVERFLOW_ENABLE, 1); 167 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 168 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 169 * value is written to memory 170 */ 171 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 172 WPTR_WRITEBACK_ENABLE, 1); 173 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 174 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 175 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 176 177 return ih_rb_cntl; 178 } 179 180 static uint32_t vega10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 181 { 182 u32 ih_doorbell_rtpr = 0; 183 184 if (ih->use_doorbell) { 185 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 186 IH_DOORBELL_RPTR, OFFSET, 187 ih->doorbell_index); 188 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 189 IH_DOORBELL_RPTR, 190 ENABLE, 1); 191 } else { 192 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 193 IH_DOORBELL_RPTR, 194 ENABLE, 0); 195 } 196 return ih_doorbell_rtpr; 197 } 198 199 /** 200 * vega10_ih_enable_ring - enable an ih ring buffer 201 * 202 * @adev: amdgpu_device pointer 203 * @ih: amdgpu_ih_ring pointer 204 * 205 * Enable an ih ring buffer (VEGA10) 206 */ 207 static int vega10_ih_enable_ring(struct amdgpu_device *adev, 208 struct amdgpu_ih_ring *ih) 209 { 210 struct amdgpu_ih_regs *ih_regs; 211 uint32_t tmp; 212 213 ih_regs = &ih->ih_regs; 214 215 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 216 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); 217 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); 218 219 tmp = RREG32(ih_regs->ih_rb_cntl); 220 tmp = vega10_ih_rb_cntl(ih, tmp); 221 if (ih == &adev->irq.ih) 222 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); 223 if (ih == &adev->irq.ih1) { 224 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0); 225 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); 226 } 227 if (amdgpu_sriov_vf(adev)) { 228 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 229 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 230 return -ETIMEDOUT; 231 } 232 } else { 233 WREG32(ih_regs->ih_rb_cntl, tmp); 234 } 235 236 if (ih == &adev->irq.ih) { 237 /* set the ih ring 0 writeback address whether it's enabled or not */ 238 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); 239 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); 240 } 241 242 /* set rptr, wptr to 0 */ 243 WREG32(ih_regs->ih_rb_wptr, 0); 244 WREG32(ih_regs->ih_rb_rptr, 0); 245 246 WREG32(ih_regs->ih_doorbell_rptr, vega10_ih_doorbell_rptr(ih)); 247 248 return 0; 249 } 250 251 /** 252 * vega10_ih_irq_init - init and enable the interrupt ring 253 * 254 * @adev: amdgpu_device pointer 255 * 256 * Allocate a ring buffer for the interrupt controller, 257 * enable the RLC, disable interrupts, enable the IH 258 * ring buffer and enable it (VI). 259 * Called at device load and reume. 260 * Returns 0 for success, errors for failure. 261 */ 262 static int vega10_ih_irq_init(struct amdgpu_device *adev) 263 { 264 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 265 u32 ih_chicken; 266 int ret; 267 int i; 268 u32 tmp; 269 270 /* disable irqs */ 271 ret = vega10_ih_toggle_interrupts(adev, false); 272 if (ret) 273 return ret; 274 275 adev->nbio.funcs->ih_control(adev); 276 277 if (adev->asic_type == CHIP_RENOIR) { 278 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 279 if (adev->irq.ih.use_bus_addr) { 280 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 281 MC_SPACE_GPA_ENABLE, 1); 282 } 283 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 284 } 285 286 for (i = 0; i < ARRAY_SIZE(ih); i++) { 287 if (ih[i]->ring_size) { 288 ret = vega10_ih_enable_ring(adev, ih[i]); 289 if (ret) 290 return ret; 291 } 292 } 293 294 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 295 tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 296 CLIENT18_IS_STORM_CLIENT, 1); 297 WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 298 299 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 300 tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 301 WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 302 303 pci_set_master(adev->pdev); 304 305 /* enable interrupts */ 306 ret = vega10_ih_toggle_interrupts(adev, true); 307 if (ret) 308 return ret; 309 310 return 0; 311 } 312 313 /** 314 * vega10_ih_irq_disable - disable interrupts 315 * 316 * @adev: amdgpu_device pointer 317 * 318 * Disable interrupts on the hw (VEGA10). 319 */ 320 static void vega10_ih_irq_disable(struct amdgpu_device *adev) 321 { 322 vega10_ih_toggle_interrupts(adev, false); 323 324 /* Wait and acknowledge irq */ 325 mdelay(1); 326 } 327 328 /** 329 * vega10_ih_get_wptr - get the IH ring buffer wptr 330 * 331 * @adev: amdgpu_device pointer 332 * @ih: IH ring buffer to fetch wptr 333 * 334 * Get the IH ring buffer wptr from either the register 335 * or the writeback memory buffer (VEGA10). Also check for 336 * ring buffer overflow and deal with it. 337 * Returns the value of the wptr. 338 */ 339 static u32 vega10_ih_get_wptr(struct amdgpu_device *adev, 340 struct amdgpu_ih_ring *ih) 341 { 342 u32 wptr, tmp; 343 struct amdgpu_ih_regs *ih_regs; 344 345 wptr = le32_to_cpu(*ih->wptr_cpu); 346 ih_regs = &ih->ih_regs; 347 348 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 349 goto out; 350 351 /* Double check that the overflow wasn't already cleared. */ 352 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); 353 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 354 goto out; 355 356 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 357 358 /* When a ring buffer overflow happen start parsing interrupt 359 * from the last not overwritten vector (wptr + 32). Hopefully 360 * this should allow us to catchup. 361 */ 362 tmp = (wptr + 32) & ih->ptr_mask; 363 dev_warn(adev->dev, "IH ring buffer overflow " 364 "(0x%08X, 0x%08X, 0x%08X)\n", 365 wptr, ih->rptr, tmp); 366 ih->rptr = tmp; 367 368 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); 369 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 370 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 371 372 out: 373 return (wptr & ih->ptr_mask); 374 } 375 376 /** 377 * vega10_ih_irq_rearm - rearm IRQ if lost 378 * 379 * @adev: amdgpu_device pointer 380 * @ih: IH ring to match 381 * 382 */ 383 static void vega10_ih_irq_rearm(struct amdgpu_device *adev, 384 struct amdgpu_ih_ring *ih) 385 { 386 uint32_t v = 0; 387 uint32_t i = 0; 388 struct amdgpu_ih_regs *ih_regs; 389 390 ih_regs = &ih->ih_regs; 391 /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */ 392 for (i = 0; i < MAX_REARM_RETRY; i++) { 393 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); 394 if ((v < ih->ring_size) && (v != ih->rptr)) 395 WDOORBELL32(ih->doorbell_index, ih->rptr); 396 else 397 break; 398 } 399 } 400 401 /** 402 * vega10_ih_set_rptr - set the IH ring buffer rptr 403 * 404 * @adev: amdgpu_device pointer 405 * @ih: IH ring buffer to set rptr 406 * 407 * Set the IH ring buffer rptr. 408 */ 409 static void vega10_ih_set_rptr(struct amdgpu_device *adev, 410 struct amdgpu_ih_ring *ih) 411 { 412 struct amdgpu_ih_regs *ih_regs; 413 414 if (ih->use_doorbell) { 415 /* XXX check if swapping is necessary on BE */ 416 *ih->rptr_cpu = ih->rptr; 417 WDOORBELL32(ih->doorbell_index, ih->rptr); 418 419 if (amdgpu_sriov_vf(adev)) 420 vega10_ih_irq_rearm(adev, ih); 421 } else { 422 ih_regs = &ih->ih_regs; 423 WREG32(ih_regs->ih_rb_rptr, ih->rptr); 424 } 425 } 426 427 /** 428 * vega10_ih_self_irq - dispatch work for ring 1 and 2 429 * 430 * @adev: amdgpu_device pointer 431 * @source: irq source 432 * @entry: IV with WPTR update 433 * 434 * Update the WPTR from the IV and schedule work to handle the entries. 435 */ 436 static int vega10_ih_self_irq(struct amdgpu_device *adev, 437 struct amdgpu_irq_src *source, 438 struct amdgpu_iv_entry *entry) 439 { 440 uint32_t wptr = cpu_to_le32(entry->src_data[0]); 441 442 switch (entry->ring_id) { 443 case 1: 444 *adev->irq.ih1.wptr_cpu = wptr; 445 schedule_work(&adev->irq.ih1_work); 446 break; 447 case 2: 448 *adev->irq.ih2.wptr_cpu = wptr; 449 schedule_work(&adev->irq.ih2_work); 450 break; 451 default: break; 452 } 453 return 0; 454 } 455 456 static const struct amdgpu_irq_src_funcs vega10_ih_self_irq_funcs = { 457 .process = vega10_ih_self_irq, 458 }; 459 460 static void vega10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 461 { 462 adev->irq.self_irq.num_types = 0; 463 adev->irq.self_irq.funcs = &vega10_ih_self_irq_funcs; 464 } 465 466 static int vega10_ih_early_init(void *handle) 467 { 468 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 469 470 vega10_ih_set_interrupt_funcs(adev); 471 vega10_ih_set_self_irq_funcs(adev); 472 return 0; 473 } 474 475 static int vega10_ih_sw_init(void *handle) 476 { 477 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 478 int r; 479 480 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 481 &adev->irq.self_irq); 482 if (r) 483 return r; 484 485 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true); 486 if (r) 487 return r; 488 489 adev->irq.ih.use_doorbell = true; 490 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 491 492 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 493 if (r) 494 return r; 495 496 adev->irq.ih1.use_doorbell = true; 497 adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; 498 499 r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 500 if (r) 501 return r; 502 503 adev->irq.ih2.use_doorbell = true; 504 adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1; 505 506 /* initialize ih control registers offset */ 507 vega10_ih_init_register_offset(adev); 508 509 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); 510 if (r) 511 return r; 512 513 r = amdgpu_irq_init(adev); 514 515 return r; 516 } 517 518 static int vega10_ih_sw_fini(void *handle) 519 { 520 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 521 522 amdgpu_irq_fini(adev); 523 amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 524 amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 525 amdgpu_ih_ring_fini(adev, &adev->irq.ih); 526 527 return 0; 528 } 529 530 static int vega10_ih_hw_init(void *handle) 531 { 532 int r; 533 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 534 535 r = vega10_ih_irq_init(adev); 536 if (r) 537 return r; 538 539 return 0; 540 } 541 542 static int vega10_ih_hw_fini(void *handle) 543 { 544 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 545 546 vega10_ih_irq_disable(adev); 547 548 return 0; 549 } 550 551 static int vega10_ih_suspend(void *handle) 552 { 553 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 554 555 return vega10_ih_hw_fini(adev); 556 } 557 558 static int vega10_ih_resume(void *handle) 559 { 560 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 561 562 return vega10_ih_hw_init(adev); 563 } 564 565 static bool vega10_ih_is_idle(void *handle) 566 { 567 /* todo */ 568 return true; 569 } 570 571 static int vega10_ih_wait_for_idle(void *handle) 572 { 573 /* todo */ 574 return -ETIMEDOUT; 575 } 576 577 static int vega10_ih_soft_reset(void *handle) 578 { 579 /* todo */ 580 581 return 0; 582 } 583 584 static void vega10_ih_update_clockgating_state(struct amdgpu_device *adev, 585 bool enable) 586 { 587 uint32_t data, def, field_val; 588 589 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 590 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 591 field_val = enable ? 0 : 1; 592 /** 593 * Vega10/12 and RAVEN don't have IH_BUFFER_MEM_CLK_SOFT_OVERRIDE field. 594 */ 595 if (adev->asic_type == CHIP_RENOIR) 596 data = REG_SET_FIELD(data, IH_CLK_CTRL, 597 IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val); 598 599 data = REG_SET_FIELD(data, IH_CLK_CTRL, 600 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 601 data = REG_SET_FIELD(data, IH_CLK_CTRL, 602 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 603 data = REG_SET_FIELD(data, IH_CLK_CTRL, 604 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 605 data = REG_SET_FIELD(data, IH_CLK_CTRL, 606 DYN_CLK_SOFT_OVERRIDE, field_val); 607 data = REG_SET_FIELD(data, IH_CLK_CTRL, 608 REG_CLK_SOFT_OVERRIDE, field_val); 609 if (def != data) 610 WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 611 } 612 } 613 614 static int vega10_ih_set_clockgating_state(void *handle, 615 enum amd_clockgating_state state) 616 { 617 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 618 619 vega10_ih_update_clockgating_state(adev, 620 state == AMD_CG_STATE_GATE); 621 return 0; 622 623 } 624 625 static int vega10_ih_set_powergating_state(void *handle, 626 enum amd_powergating_state state) 627 { 628 return 0; 629 } 630 631 const struct amd_ip_funcs vega10_ih_ip_funcs = { 632 .name = "vega10_ih", 633 .early_init = vega10_ih_early_init, 634 .late_init = NULL, 635 .sw_init = vega10_ih_sw_init, 636 .sw_fini = vega10_ih_sw_fini, 637 .hw_init = vega10_ih_hw_init, 638 .hw_fini = vega10_ih_hw_fini, 639 .suspend = vega10_ih_suspend, 640 .resume = vega10_ih_resume, 641 .is_idle = vega10_ih_is_idle, 642 .wait_for_idle = vega10_ih_wait_for_idle, 643 .soft_reset = vega10_ih_soft_reset, 644 .set_clockgating_state = vega10_ih_set_clockgating_state, 645 .set_powergating_state = vega10_ih_set_powergating_state, 646 }; 647 648 static const struct amdgpu_ih_funcs vega10_ih_funcs = { 649 .get_wptr = vega10_ih_get_wptr, 650 .decode_iv = amdgpu_ih_decode_iv_helper, 651 .set_rptr = vega10_ih_set_rptr 652 }; 653 654 static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 655 { 656 adev->irq.ih_funcs = &vega10_ih_funcs; 657 } 658 659 const struct amdgpu_ip_block_version vega10_ih_ip_block = 660 { 661 .type = AMD_IP_BLOCK_TYPE_IH, 662 .major = 4, 663 .minor = 0, 664 .rev = 0, 665 .funcs = &vega10_ih_ip_funcs, 666 }; 667