1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <drm/drmP.h> 24 #include "amdgpu.h" 25 #include "amdgpu_ih.h" 26 #include "soc15.h" 27 28 #include "oss/osssys_4_0_offset.h" 29 #include "oss/osssys_4_0_sh_mask.h" 30 31 #include "soc15_common.h" 32 #include "vega10_ih.h" 33 34 35 36 static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 37 38 /** 39 * vega10_ih_enable_interrupts - Enable the interrupt ring buffer 40 * 41 * @adev: amdgpu_device pointer 42 * 43 * Enable the interrupt ring buffer (VEGA10). 44 */ 45 static void vega10_ih_enable_interrupts(struct amdgpu_device *adev) 46 { 47 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 48 49 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); 50 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); 51 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 52 adev->irq.ih.enabled = true; 53 } 54 55 /** 56 * vega10_ih_disable_interrupts - Disable the interrupt ring buffer 57 * 58 * @adev: amdgpu_device pointer 59 * 60 * Disable the interrupt ring buffer (VEGA10). 61 */ 62 static void vega10_ih_disable_interrupts(struct amdgpu_device *adev) 63 { 64 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 65 66 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); 67 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); 68 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 69 /* set rptr, wptr to 0 */ 70 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 71 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 72 adev->irq.ih.enabled = false; 73 adev->irq.ih.rptr = 0; 74 } 75 76 /** 77 * vega10_ih_irq_init - init and enable the interrupt ring 78 * 79 * @adev: amdgpu_device pointer 80 * 81 * Allocate a ring buffer for the interrupt controller, 82 * enable the RLC, disable interrupts, enable the IH 83 * ring buffer and enable it (VI). 84 * Called at device load and reume. 85 * Returns 0 for success, errors for failure. 86 */ 87 static int vega10_ih_irq_init(struct amdgpu_device *adev) 88 { 89 int ret = 0; 90 int rb_bufsz; 91 u32 ih_rb_cntl, ih_doorbell_rtpr; 92 u32 tmp; 93 u64 wptr_off; 94 95 /* disable irqs */ 96 vega10_ih_disable_interrupts(adev); 97 98 adev->nbio_funcs->ih_control(adev); 99 100 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 101 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 102 if (adev->irq.ih.use_bus_addr) { 103 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, adev->irq.ih.rb_dma_addr >> 8); 104 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, ((u64)adev->irq.ih.rb_dma_addr >> 40) & 0xff); 105 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 1); 106 } else { 107 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); 108 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (adev->irq.ih.gpu_addr >> 40) & 0xff); 109 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 4); 110 } 111 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); 112 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 113 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1); 114 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 115 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */ 116 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); 117 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 118 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 119 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 120 121 if (adev->irq.msi_enabled) 122 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1); 123 124 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 125 126 /* set the writeback address whether it's enabled or not */ 127 if (adev->irq.ih.use_bus_addr) 128 wptr_off = adev->irq.ih.rb_dma_addr + (adev->irq.ih.wptr_offs * 4); 129 else 130 wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); 131 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off)); 132 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFFFF); 133 134 /* set rptr, wptr to 0 */ 135 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 136 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 137 138 ih_doorbell_rtpr = RREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR); 139 if (adev->irq.ih.use_doorbell) { 140 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, 141 OFFSET, adev->irq.ih.doorbell_index); 142 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, 143 ENABLE, 1); 144 } else { 145 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, 146 ENABLE, 0); 147 } 148 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, ih_doorbell_rtpr); 149 adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, 150 adev->irq.ih.doorbell_index); 151 152 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 153 tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 154 CLIENT18_IS_STORM_CLIENT, 1); 155 WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 156 157 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 158 tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 159 WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 160 161 pci_set_master(adev->pdev); 162 163 /* enable interrupts */ 164 vega10_ih_enable_interrupts(adev); 165 166 return ret; 167 } 168 169 /** 170 * vega10_ih_irq_disable - disable interrupts 171 * 172 * @adev: amdgpu_device pointer 173 * 174 * Disable interrupts on the hw (VEGA10). 175 */ 176 static void vega10_ih_irq_disable(struct amdgpu_device *adev) 177 { 178 vega10_ih_disable_interrupts(adev); 179 180 /* Wait and acknowledge irq */ 181 mdelay(1); 182 } 183 184 /** 185 * vega10_ih_get_wptr - get the IH ring buffer wptr 186 * 187 * @adev: amdgpu_device pointer 188 * 189 * Get the IH ring buffer wptr from either the register 190 * or the writeback memory buffer (VEGA10). Also check for 191 * ring buffer overflow and deal with it. 192 * Returns the value of the wptr. 193 */ 194 static u32 vega10_ih_get_wptr(struct amdgpu_device *adev, 195 struct amdgpu_ih_ring *ih) 196 { 197 u32 wptr, tmp; 198 199 if (ih->use_bus_addr) 200 wptr = le32_to_cpu(ih->ring[ih->wptr_offs]); 201 else 202 wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]); 203 204 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { 205 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 206 207 /* When a ring buffer overflow happen start parsing interrupt 208 * from the last not overwritten vector (wptr + 32). Hopefully 209 * this should allow us to catchup. 210 */ 211 tmp = (wptr + 32) & ih->ptr_mask; 212 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", 213 wptr, ih->rptr, tmp); 214 ih->rptr = tmp; 215 216 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL)); 217 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 218 WREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), tmp); 219 } 220 return (wptr & ih->ptr_mask); 221 } 222 223 /** 224 * vega10_ih_decode_iv - decode an interrupt vector 225 * 226 * @adev: amdgpu_device pointer 227 * 228 * Decodes the interrupt vector at the current rptr 229 * position and also advance the position. 230 */ 231 static void vega10_ih_decode_iv(struct amdgpu_device *adev, 232 struct amdgpu_ih_ring *ih, 233 struct amdgpu_iv_entry *entry) 234 { 235 /* wptr/rptr are in bytes! */ 236 u32 ring_index = ih->rptr >> 2; 237 uint32_t dw[8]; 238 239 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 240 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 241 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 242 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 243 dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); 244 dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); 245 dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); 246 dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); 247 248 entry->client_id = dw[0] & 0xff; 249 entry->src_id = (dw[0] >> 8) & 0xff; 250 entry->ring_id = (dw[0] >> 16) & 0xff; 251 entry->vmid = (dw[0] >> 24) & 0xf; 252 entry->vmid_src = (dw[0] >> 31); 253 entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); 254 entry->timestamp_src = dw[2] >> 31; 255 entry->pasid = dw[3] & 0xffff; 256 entry->pasid_src = dw[3] >> 31; 257 entry->src_data[0] = dw[4]; 258 entry->src_data[1] = dw[5]; 259 entry->src_data[2] = dw[6]; 260 entry->src_data[3] = dw[7]; 261 262 /* wptr/rptr are in bytes! */ 263 ih->rptr += 32; 264 } 265 266 /** 267 * vega10_ih_set_rptr - set the IH ring buffer rptr 268 * 269 * @adev: amdgpu_device pointer 270 * 271 * Set the IH ring buffer rptr. 272 */ 273 static void vega10_ih_set_rptr(struct amdgpu_device *adev, 274 struct amdgpu_ih_ring *ih) 275 { 276 if (ih->use_doorbell) { 277 /* XXX check if swapping is necessary on BE */ 278 if (ih->use_bus_addr) 279 ih->ring[ih->rptr_offs] = ih->rptr; 280 else 281 adev->wb.wb[ih->rptr_offs] = ih->rptr; 282 WDOORBELL32(ih->doorbell_index, ih->rptr); 283 } else { 284 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr); 285 } 286 } 287 288 static int vega10_ih_early_init(void *handle) 289 { 290 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 291 292 vega10_ih_set_interrupt_funcs(adev); 293 return 0; 294 } 295 296 static int vega10_ih_sw_init(void *handle) 297 { 298 int r; 299 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 300 301 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true); 302 if (r) 303 return r; 304 305 adev->irq.ih.use_doorbell = true; 306 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 307 308 r = amdgpu_irq_init(adev); 309 310 return r; 311 } 312 313 static int vega10_ih_sw_fini(void *handle) 314 { 315 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 316 317 amdgpu_irq_fini(adev); 318 amdgpu_ih_ring_fini(adev, &adev->irq.ih); 319 320 return 0; 321 } 322 323 static int vega10_ih_hw_init(void *handle) 324 { 325 int r; 326 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 327 328 r = vega10_ih_irq_init(adev); 329 if (r) 330 return r; 331 332 return 0; 333 } 334 335 static int vega10_ih_hw_fini(void *handle) 336 { 337 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 338 339 vega10_ih_irq_disable(adev); 340 341 return 0; 342 } 343 344 static int vega10_ih_suspend(void *handle) 345 { 346 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 347 348 return vega10_ih_hw_fini(adev); 349 } 350 351 static int vega10_ih_resume(void *handle) 352 { 353 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 354 355 return vega10_ih_hw_init(adev); 356 } 357 358 static bool vega10_ih_is_idle(void *handle) 359 { 360 /* todo */ 361 return true; 362 } 363 364 static int vega10_ih_wait_for_idle(void *handle) 365 { 366 /* todo */ 367 return -ETIMEDOUT; 368 } 369 370 static int vega10_ih_soft_reset(void *handle) 371 { 372 /* todo */ 373 374 return 0; 375 } 376 377 static int vega10_ih_set_clockgating_state(void *handle, 378 enum amd_clockgating_state state) 379 { 380 return 0; 381 } 382 383 static int vega10_ih_set_powergating_state(void *handle, 384 enum amd_powergating_state state) 385 { 386 return 0; 387 } 388 389 const struct amd_ip_funcs vega10_ih_ip_funcs = { 390 .name = "vega10_ih", 391 .early_init = vega10_ih_early_init, 392 .late_init = NULL, 393 .sw_init = vega10_ih_sw_init, 394 .sw_fini = vega10_ih_sw_fini, 395 .hw_init = vega10_ih_hw_init, 396 .hw_fini = vega10_ih_hw_fini, 397 .suspend = vega10_ih_suspend, 398 .resume = vega10_ih_resume, 399 .is_idle = vega10_ih_is_idle, 400 .wait_for_idle = vega10_ih_wait_for_idle, 401 .soft_reset = vega10_ih_soft_reset, 402 .set_clockgating_state = vega10_ih_set_clockgating_state, 403 .set_powergating_state = vega10_ih_set_powergating_state, 404 }; 405 406 static const struct amdgpu_ih_funcs vega10_ih_funcs = { 407 .get_wptr = vega10_ih_get_wptr, 408 .decode_iv = vega10_ih_decode_iv, 409 .set_rptr = vega10_ih_set_rptr 410 }; 411 412 static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 413 { 414 adev->irq.ih_funcs = &vega10_ih_funcs; 415 } 416 417 const struct amdgpu_ip_block_version vega10_ih_ip_block = 418 { 419 .type = AMD_IP_BLOCK_TYPE_IH, 420 .major = 4, 421 .minor = 0, 422 .rev = 0, 423 .funcs = &vega10_ih_ip_funcs, 424 }; 425