1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <drm/drmP.h> 24 #include "amdgpu.h" 25 #include "amdgpu_ih.h" 26 #include "soc15.h" 27 28 #include "oss/osssys_4_0_offset.h" 29 #include "oss/osssys_4_0_sh_mask.h" 30 31 #include "soc15_common.h" 32 #include "vega10_ih.h" 33 34 35 36 static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 37 38 /** 39 * vega10_ih_enable_interrupts - Enable the interrupt ring buffer 40 * 41 * @adev: amdgpu_device pointer 42 * 43 * Enable the interrupt ring buffer (VEGA10). 44 */ 45 static void vega10_ih_enable_interrupts(struct amdgpu_device *adev) 46 { 47 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 48 49 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); 50 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); 51 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 52 adev->irq.ih.enabled = true; 53 } 54 55 /** 56 * vega10_ih_disable_interrupts - Disable the interrupt ring buffer 57 * 58 * @adev: amdgpu_device pointer 59 * 60 * Disable the interrupt ring buffer (VEGA10). 61 */ 62 static void vega10_ih_disable_interrupts(struct amdgpu_device *adev) 63 { 64 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 65 66 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); 67 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); 68 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 69 /* set rptr, wptr to 0 */ 70 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 71 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 72 adev->irq.ih.enabled = false; 73 adev->irq.ih.rptr = 0; 74 } 75 76 /** 77 * vega10_ih_irq_init - init and enable the interrupt ring 78 * 79 * @adev: amdgpu_device pointer 80 * 81 * Allocate a ring buffer for the interrupt controller, 82 * enable the RLC, disable interrupts, enable the IH 83 * ring buffer and enable it (VI). 84 * Called at device load and reume. 85 * Returns 0 for success, errors for failure. 86 */ 87 static int vega10_ih_irq_init(struct amdgpu_device *adev) 88 { 89 struct amdgpu_ih_ring *ih = &adev->irq.ih; 90 int ret = 0; 91 int rb_bufsz; 92 u32 ih_rb_cntl, ih_doorbell_rtpr; 93 u32 tmp; 94 95 /* disable irqs */ 96 vega10_ih_disable_interrupts(adev); 97 98 adev->nbio_funcs->ih_control(adev); 99 100 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 101 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 102 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); 103 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, 104 (adev->irq.ih.gpu_addr >> 40) & 0xff); 105 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 106 ih->use_bus_addr ? 1 : 4); 107 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); 108 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 109 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1); 110 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 111 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */ 112 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); 113 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 114 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 115 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 116 117 if (adev->irq.msi_enabled) 118 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1); 119 120 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 121 122 /* set the writeback address whether it's enabled or not */ 123 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, 124 lower_32_bits(ih->wptr_addr)); 125 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, 126 upper_32_bits(ih->wptr_addr) & 0xFFFF); 127 128 /* set rptr, wptr to 0 */ 129 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 130 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 131 132 ih_doorbell_rtpr = RREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR); 133 if (adev->irq.ih.use_doorbell) { 134 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, 135 OFFSET, adev->irq.ih.doorbell_index); 136 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, 137 ENABLE, 1); 138 } else { 139 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, 140 ENABLE, 0); 141 } 142 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, ih_doorbell_rtpr); 143 144 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 145 tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 146 CLIENT18_IS_STORM_CLIENT, 1); 147 WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 148 149 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 150 tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 151 WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 152 153 pci_set_master(adev->pdev); 154 155 /* enable interrupts */ 156 vega10_ih_enable_interrupts(adev); 157 158 return ret; 159 } 160 161 /** 162 * vega10_ih_irq_disable - disable interrupts 163 * 164 * @adev: amdgpu_device pointer 165 * 166 * Disable interrupts on the hw (VEGA10). 167 */ 168 static void vega10_ih_irq_disable(struct amdgpu_device *adev) 169 { 170 vega10_ih_disable_interrupts(adev); 171 172 /* Wait and acknowledge irq */ 173 mdelay(1); 174 } 175 176 /** 177 * vega10_ih_get_wptr - get the IH ring buffer wptr 178 * 179 * @adev: amdgpu_device pointer 180 * 181 * Get the IH ring buffer wptr from either the register 182 * or the writeback memory buffer (VEGA10). Also check for 183 * ring buffer overflow and deal with it. 184 * Returns the value of the wptr. 185 */ 186 static u32 vega10_ih_get_wptr(struct amdgpu_device *adev, 187 struct amdgpu_ih_ring *ih) 188 { 189 u32 wptr, tmp; 190 191 wptr = le32_to_cpu(*ih->wptr_cpu); 192 193 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 194 goto out; 195 196 /* Double check that the overflow wasn't already cleared. */ 197 wptr = RREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR)); 198 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 199 goto out; 200 201 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 202 203 /* When a ring buffer overflow happen start parsing interrupt 204 * from the last not overwritten vector (wptr + 32). Hopefully 205 * this should allow us to catchup. 206 */ 207 tmp = (wptr + 32) & ih->ptr_mask; 208 dev_warn(adev->dev, "IH ring buffer overflow " 209 "(0x%08X, 0x%08X, 0x%08X)\n", 210 wptr, ih->rptr, tmp); 211 ih->rptr = tmp; 212 213 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL)); 214 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 215 WREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), tmp); 216 217 out: 218 return (wptr & ih->ptr_mask); 219 } 220 221 /** 222 * vega10_ih_decode_iv - decode an interrupt vector 223 * 224 * @adev: amdgpu_device pointer 225 * 226 * Decodes the interrupt vector at the current rptr 227 * position and also advance the position. 228 */ 229 static void vega10_ih_decode_iv(struct amdgpu_device *adev, 230 struct amdgpu_ih_ring *ih, 231 struct amdgpu_iv_entry *entry) 232 { 233 /* wptr/rptr are in bytes! */ 234 u32 ring_index = ih->rptr >> 2; 235 uint32_t dw[8]; 236 237 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 238 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 239 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 240 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 241 dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); 242 dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); 243 dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); 244 dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); 245 246 entry->client_id = dw[0] & 0xff; 247 entry->src_id = (dw[0] >> 8) & 0xff; 248 entry->ring_id = (dw[0] >> 16) & 0xff; 249 entry->vmid = (dw[0] >> 24) & 0xf; 250 entry->vmid_src = (dw[0] >> 31); 251 entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); 252 entry->timestamp_src = dw[2] >> 31; 253 entry->pasid = dw[3] & 0xffff; 254 entry->pasid_src = dw[3] >> 31; 255 entry->src_data[0] = dw[4]; 256 entry->src_data[1] = dw[5]; 257 entry->src_data[2] = dw[6]; 258 entry->src_data[3] = dw[7]; 259 260 /* wptr/rptr are in bytes! */ 261 ih->rptr += 32; 262 } 263 264 /** 265 * vega10_ih_set_rptr - set the IH ring buffer rptr 266 * 267 * @adev: amdgpu_device pointer 268 * 269 * Set the IH ring buffer rptr. 270 */ 271 static void vega10_ih_set_rptr(struct amdgpu_device *adev, 272 struct amdgpu_ih_ring *ih) 273 { 274 if (ih->use_doorbell) { 275 /* XXX check if swapping is necessary on BE */ 276 *ih->rptr_cpu = ih->rptr; 277 WDOORBELL32(ih->doorbell_index, ih->rptr); 278 } else { 279 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr); 280 } 281 } 282 283 static int vega10_ih_early_init(void *handle) 284 { 285 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 286 287 vega10_ih_set_interrupt_funcs(adev); 288 return 0; 289 } 290 291 static int vega10_ih_sw_init(void *handle) 292 { 293 int r; 294 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 295 296 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true); 297 if (r) 298 return r; 299 300 adev->irq.ih.use_doorbell = true; 301 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 302 303 r = amdgpu_irq_init(adev); 304 305 return r; 306 } 307 308 static int vega10_ih_sw_fini(void *handle) 309 { 310 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 311 312 amdgpu_irq_fini(adev); 313 amdgpu_ih_ring_fini(adev, &adev->irq.ih); 314 315 return 0; 316 } 317 318 static int vega10_ih_hw_init(void *handle) 319 { 320 int r; 321 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 322 323 r = vega10_ih_irq_init(adev); 324 if (r) 325 return r; 326 327 return 0; 328 } 329 330 static int vega10_ih_hw_fini(void *handle) 331 { 332 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 333 334 vega10_ih_irq_disable(adev); 335 336 return 0; 337 } 338 339 static int vega10_ih_suspend(void *handle) 340 { 341 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 342 343 return vega10_ih_hw_fini(adev); 344 } 345 346 static int vega10_ih_resume(void *handle) 347 { 348 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 349 350 return vega10_ih_hw_init(adev); 351 } 352 353 static bool vega10_ih_is_idle(void *handle) 354 { 355 /* todo */ 356 return true; 357 } 358 359 static int vega10_ih_wait_for_idle(void *handle) 360 { 361 /* todo */ 362 return -ETIMEDOUT; 363 } 364 365 static int vega10_ih_soft_reset(void *handle) 366 { 367 /* todo */ 368 369 return 0; 370 } 371 372 static int vega10_ih_set_clockgating_state(void *handle, 373 enum amd_clockgating_state state) 374 { 375 return 0; 376 } 377 378 static int vega10_ih_set_powergating_state(void *handle, 379 enum amd_powergating_state state) 380 { 381 return 0; 382 } 383 384 const struct amd_ip_funcs vega10_ih_ip_funcs = { 385 .name = "vega10_ih", 386 .early_init = vega10_ih_early_init, 387 .late_init = NULL, 388 .sw_init = vega10_ih_sw_init, 389 .sw_fini = vega10_ih_sw_fini, 390 .hw_init = vega10_ih_hw_init, 391 .hw_fini = vega10_ih_hw_fini, 392 .suspend = vega10_ih_suspend, 393 .resume = vega10_ih_resume, 394 .is_idle = vega10_ih_is_idle, 395 .wait_for_idle = vega10_ih_wait_for_idle, 396 .soft_reset = vega10_ih_soft_reset, 397 .set_clockgating_state = vega10_ih_set_clockgating_state, 398 .set_powergating_state = vega10_ih_set_powergating_state, 399 }; 400 401 static const struct amdgpu_ih_funcs vega10_ih_funcs = { 402 .get_wptr = vega10_ih_get_wptr, 403 .decode_iv = vega10_ih_decode_iv, 404 .set_rptr = vega10_ih_set_rptr 405 }; 406 407 static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 408 { 409 adev->irq.ih_funcs = &vega10_ih_funcs; 410 } 411 412 const struct amdgpu_ip_block_version vega10_ih_ip_block = 413 { 414 .type = AMD_IP_BLOCK_TYPE_IH, 415 .major = 4, 416 .minor = 0, 417 .rev = 0, 418 .funcs = &vega10_ih_ip_funcs, 419 }; 420