1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <drm/drmP.h> 24 #include "amdgpu.h" 25 #include "amdgpu_ih.h" 26 #include "soc15.h" 27 28 #include "oss/osssys_4_0_offset.h" 29 #include "oss/osssys_4_0_sh_mask.h" 30 31 #include "soc15_common.h" 32 #include "vega10_ih.h" 33 34 35 36 static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 37 38 /** 39 * vega10_ih_enable_interrupts - Enable the interrupt ring buffer 40 * 41 * @adev: amdgpu_device pointer 42 * 43 * Enable the interrupt ring buffer (VEGA10). 44 */ 45 static void vega10_ih_enable_interrupts(struct amdgpu_device *adev) 46 { 47 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 48 49 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); 50 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); 51 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 52 adev->irq.ih.enabled = true; 53 } 54 55 /** 56 * vega10_ih_disable_interrupts - Disable the interrupt ring buffer 57 * 58 * @adev: amdgpu_device pointer 59 * 60 * Disable the interrupt ring buffer (VEGA10). 61 */ 62 static void vega10_ih_disable_interrupts(struct amdgpu_device *adev) 63 { 64 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 65 66 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); 67 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); 68 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 69 /* set rptr, wptr to 0 */ 70 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 71 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 72 adev->irq.ih.enabled = false; 73 adev->irq.ih.rptr = 0; 74 } 75 76 /** 77 * vega10_ih_irq_init - init and enable the interrupt ring 78 * 79 * @adev: amdgpu_device pointer 80 * 81 * Allocate a ring buffer for the interrupt controller, 82 * enable the RLC, disable interrupts, enable the IH 83 * ring buffer and enable it (VI). 84 * Called at device load and reume. 85 * Returns 0 for success, errors for failure. 86 */ 87 static int vega10_ih_irq_init(struct amdgpu_device *adev) 88 { 89 int ret = 0; 90 int rb_bufsz; 91 u32 ih_rb_cntl, ih_doorbell_rtpr; 92 u32 tmp; 93 u64 wptr_off; 94 95 /* disable irqs */ 96 vega10_ih_disable_interrupts(adev); 97 98 if (adev->flags & AMD_IS_APU) 99 nbio_v7_0_ih_control(adev); 100 else 101 nbio_v6_1_ih_control(adev); 102 103 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 104 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 105 if (adev->irq.ih.use_bus_addr) { 106 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, adev->irq.ih.rb_dma_addr >> 8); 107 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, ((u64)adev->irq.ih.rb_dma_addr >> 40) & 0xff); 108 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 1); 109 } else { 110 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); 111 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (adev->irq.ih.gpu_addr >> 40) & 0xff); 112 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 4); 113 } 114 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); 115 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 116 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1); 117 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 118 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */ 119 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); 120 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 121 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 122 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 123 124 if (adev->irq.msi_enabled) 125 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1); 126 127 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 128 129 /* set the writeback address whether it's enabled or not */ 130 if (adev->irq.ih.use_bus_addr) 131 wptr_off = adev->irq.ih.rb_dma_addr + (adev->irq.ih.wptr_offs * 4); 132 else 133 wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); 134 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off)); 135 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF); 136 137 /* set rptr, wptr to 0 */ 138 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 139 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 140 141 ih_doorbell_rtpr = RREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR); 142 if (adev->irq.ih.use_doorbell) { 143 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, 144 OFFSET, adev->irq.ih.doorbell_index); 145 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, 146 ENABLE, 1); 147 } else { 148 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, 149 ENABLE, 0); 150 } 151 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, ih_doorbell_rtpr); 152 if (adev->flags & AMD_IS_APU) 153 nbio_v7_0_ih_doorbell_range(adev, adev->irq.ih.use_doorbell, adev->irq.ih.doorbell_index); 154 else 155 nbio_v6_1_ih_doorbell_range(adev, adev->irq.ih.use_doorbell, adev->irq.ih.doorbell_index); 156 157 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 158 tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 159 CLIENT18_IS_STORM_CLIENT, 1); 160 WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 161 162 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 163 tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 164 WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 165 166 pci_set_master(adev->pdev); 167 168 /* enable interrupts */ 169 vega10_ih_enable_interrupts(adev); 170 171 return ret; 172 } 173 174 /** 175 * vega10_ih_irq_disable - disable interrupts 176 * 177 * @adev: amdgpu_device pointer 178 * 179 * Disable interrupts on the hw (VEGA10). 180 */ 181 static void vega10_ih_irq_disable(struct amdgpu_device *adev) 182 { 183 vega10_ih_disable_interrupts(adev); 184 185 /* Wait and acknowledge irq */ 186 mdelay(1); 187 } 188 189 /** 190 * vega10_ih_get_wptr - get the IH ring buffer wptr 191 * 192 * @adev: amdgpu_device pointer 193 * 194 * Get the IH ring buffer wptr from either the register 195 * or the writeback memory buffer (VEGA10). Also check for 196 * ring buffer overflow and deal with it. 197 * Returns the value of the wptr. 198 */ 199 static u32 vega10_ih_get_wptr(struct amdgpu_device *adev) 200 { 201 u32 wptr, tmp; 202 203 if (adev->irq.ih.use_bus_addr) 204 wptr = le32_to_cpu(adev->irq.ih.ring[adev->irq.ih.wptr_offs]); 205 else 206 wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); 207 208 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { 209 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 210 211 /* When a ring buffer overflow happen start parsing interrupt 212 * from the last not overwritten vector (wptr + 32). Hopefully 213 * this should allow us to catchup. 214 */ 215 tmp = (wptr + 32) & adev->irq.ih.ptr_mask; 216 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", 217 wptr, adev->irq.ih.rptr, tmp); 218 adev->irq.ih.rptr = tmp; 219 220 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL)); 221 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 222 WREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), tmp); 223 } 224 return (wptr & adev->irq.ih.ptr_mask); 225 } 226 227 /** 228 * vega10_ih_prescreen_iv - prescreen an interrupt vector 229 * 230 * @adev: amdgpu_device pointer 231 * 232 * Returns true if the interrupt vector should be further processed. 233 */ 234 static bool vega10_ih_prescreen_iv(struct amdgpu_device *adev) 235 { 236 u32 ring_index = adev->irq.ih.rptr >> 2; 237 u32 dw0, dw3, dw4, dw5; 238 u16 pasid; 239 u64 addr, key; 240 struct amdgpu_vm *vm; 241 int r; 242 243 dw0 = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]); 244 dw3 = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]); 245 dw4 = le32_to_cpu(adev->irq.ih.ring[ring_index + 4]); 246 dw5 = le32_to_cpu(adev->irq.ih.ring[ring_index + 5]); 247 248 /* Filter retry page faults, let only the first one pass. If 249 * there are too many outstanding faults, ignore them until 250 * some faults get cleared. 251 */ 252 switch (dw0 & 0xff) { 253 case AMDGPU_IH_CLIENTID_VMC: 254 case AMDGPU_IH_CLIENTID_UTCL2: 255 break; 256 default: 257 /* Not a VM fault */ 258 return true; 259 } 260 261 pasid = dw3 & 0xffff; 262 /* No PASID, can't identify faulting process */ 263 if (!pasid) 264 return true; 265 266 /* Not a retry fault, check fault credit */ 267 if (!(dw5 & 0x80)) { 268 if (!amdgpu_vm_pasid_fault_credit(adev, pasid)) 269 goto ignore_iv; 270 return true; 271 } 272 273 addr = ((u64)(dw5 & 0xf) << 44) | ((u64)dw4 << 12); 274 key = AMDGPU_VM_FAULT(pasid, addr); 275 r = amdgpu_ih_add_fault(adev, key); 276 277 /* Hash table is full or the fault is already being processed, 278 * ignore further page faults 279 */ 280 if (r != 0) 281 goto ignore_iv; 282 283 /* Track retry faults in per-VM fault FIFO. */ 284 spin_lock(&adev->vm_manager.pasid_lock); 285 vm = idr_find(&adev->vm_manager.pasid_idr, pasid); 286 spin_unlock(&adev->vm_manager.pasid_lock); 287 if (WARN_ON_ONCE(!vm)) { 288 /* VM not found, process it normally */ 289 amdgpu_ih_clear_fault(adev, key); 290 return true; 291 } 292 /* No locking required with single writer and single reader */ 293 r = kfifo_put(&vm->faults, key); 294 if (!r) { 295 /* FIFO is full. Ignore it until there is space */ 296 amdgpu_ih_clear_fault(adev, key); 297 goto ignore_iv; 298 } 299 300 /* It's the first fault for this address, process it normally */ 301 return true; 302 303 ignore_iv: 304 adev->irq.ih.rptr += 32; 305 return false; 306 } 307 308 /** 309 * vega10_ih_decode_iv - decode an interrupt vector 310 * 311 * @adev: amdgpu_device pointer 312 * 313 * Decodes the interrupt vector at the current rptr 314 * position and also advance the position. 315 */ 316 static void vega10_ih_decode_iv(struct amdgpu_device *adev, 317 struct amdgpu_iv_entry *entry) 318 { 319 /* wptr/rptr are in bytes! */ 320 u32 ring_index = adev->irq.ih.rptr >> 2; 321 uint32_t dw[8]; 322 323 dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]); 324 dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]); 325 dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]); 326 dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]); 327 dw[4] = le32_to_cpu(adev->irq.ih.ring[ring_index + 4]); 328 dw[5] = le32_to_cpu(adev->irq.ih.ring[ring_index + 5]); 329 dw[6] = le32_to_cpu(adev->irq.ih.ring[ring_index + 6]); 330 dw[7] = le32_to_cpu(adev->irq.ih.ring[ring_index + 7]); 331 332 entry->client_id = dw[0] & 0xff; 333 entry->src_id = (dw[0] >> 8) & 0xff; 334 entry->ring_id = (dw[0] >> 16) & 0xff; 335 entry->vm_id = (dw[0] >> 24) & 0xf; 336 entry->vm_id_src = (dw[0] >> 31); 337 entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); 338 entry->timestamp_src = dw[2] >> 31; 339 entry->pas_id = dw[3] & 0xffff; 340 entry->pasid_src = dw[3] >> 31; 341 entry->src_data[0] = dw[4]; 342 entry->src_data[1] = dw[5]; 343 entry->src_data[2] = dw[6]; 344 entry->src_data[3] = dw[7]; 345 346 347 /* wptr/rptr are in bytes! */ 348 adev->irq.ih.rptr += 32; 349 } 350 351 /** 352 * vega10_ih_set_rptr - set the IH ring buffer rptr 353 * 354 * @adev: amdgpu_device pointer 355 * 356 * Set the IH ring buffer rptr. 357 */ 358 static void vega10_ih_set_rptr(struct amdgpu_device *adev) 359 { 360 if (adev->irq.ih.use_doorbell) { 361 /* XXX check if swapping is necessary on BE */ 362 if (adev->irq.ih.use_bus_addr) 363 adev->irq.ih.ring[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr; 364 else 365 adev->wb.wb[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr; 366 WDOORBELL32(adev->irq.ih.doorbell_index, adev->irq.ih.rptr); 367 } else { 368 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, adev->irq.ih.rptr); 369 } 370 } 371 372 static int vega10_ih_early_init(void *handle) 373 { 374 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 375 376 vega10_ih_set_interrupt_funcs(adev); 377 return 0; 378 } 379 380 static int vega10_ih_sw_init(void *handle) 381 { 382 int r; 383 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 384 385 r = amdgpu_ih_ring_init(adev, 256 * 1024, true); 386 if (r) 387 return r; 388 389 adev->irq.ih.use_doorbell = true; 390 adev->irq.ih.doorbell_index = AMDGPU_DOORBELL64_IH << 1; 391 392 adev->irq.ih.faults = kmalloc(sizeof(*adev->irq.ih.faults), GFP_KERNEL); 393 if (!adev->irq.ih.faults) 394 return -ENOMEM; 395 INIT_CHASH_TABLE(adev->irq.ih.faults->hash, 396 AMDGPU_PAGEFAULT_HASH_BITS, 8, 0); 397 spin_lock_init(&adev->irq.ih.faults->lock); 398 adev->irq.ih.faults->count = 0; 399 400 r = amdgpu_irq_init(adev); 401 402 return r; 403 } 404 405 static int vega10_ih_sw_fini(void *handle) 406 { 407 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 408 409 amdgpu_irq_fini(adev); 410 amdgpu_ih_ring_fini(adev); 411 412 kfree(adev->irq.ih.faults); 413 adev->irq.ih.faults = NULL; 414 415 return 0; 416 } 417 418 static int vega10_ih_hw_init(void *handle) 419 { 420 int r; 421 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 422 423 r = vega10_ih_irq_init(adev); 424 if (r) 425 return r; 426 427 return 0; 428 } 429 430 static int vega10_ih_hw_fini(void *handle) 431 { 432 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 433 434 vega10_ih_irq_disable(adev); 435 436 return 0; 437 } 438 439 static int vega10_ih_suspend(void *handle) 440 { 441 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 442 443 return vega10_ih_hw_fini(adev); 444 } 445 446 static int vega10_ih_resume(void *handle) 447 { 448 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 449 450 return vega10_ih_hw_init(adev); 451 } 452 453 static bool vega10_ih_is_idle(void *handle) 454 { 455 /* todo */ 456 return true; 457 } 458 459 static int vega10_ih_wait_for_idle(void *handle) 460 { 461 /* todo */ 462 return -ETIMEDOUT; 463 } 464 465 static int vega10_ih_soft_reset(void *handle) 466 { 467 /* todo */ 468 469 return 0; 470 } 471 472 static int vega10_ih_set_clockgating_state(void *handle, 473 enum amd_clockgating_state state) 474 { 475 return 0; 476 } 477 478 static int vega10_ih_set_powergating_state(void *handle, 479 enum amd_powergating_state state) 480 { 481 return 0; 482 } 483 484 const struct amd_ip_funcs vega10_ih_ip_funcs = { 485 .name = "vega10_ih", 486 .early_init = vega10_ih_early_init, 487 .late_init = NULL, 488 .sw_init = vega10_ih_sw_init, 489 .sw_fini = vega10_ih_sw_fini, 490 .hw_init = vega10_ih_hw_init, 491 .hw_fini = vega10_ih_hw_fini, 492 .suspend = vega10_ih_suspend, 493 .resume = vega10_ih_resume, 494 .is_idle = vega10_ih_is_idle, 495 .wait_for_idle = vega10_ih_wait_for_idle, 496 .soft_reset = vega10_ih_soft_reset, 497 .set_clockgating_state = vega10_ih_set_clockgating_state, 498 .set_powergating_state = vega10_ih_set_powergating_state, 499 }; 500 501 static const struct amdgpu_ih_funcs vega10_ih_funcs = { 502 .get_wptr = vega10_ih_get_wptr, 503 .prescreen_iv = vega10_ih_prescreen_iv, 504 .decode_iv = vega10_ih_decode_iv, 505 .set_rptr = vega10_ih_set_rptr 506 }; 507 508 static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 509 { 510 if (adev->irq.ih_funcs == NULL) 511 adev->irq.ih_funcs = &vega10_ih_funcs; 512 } 513 514 const struct amdgpu_ip_block_version vega10_ih_ip_block = 515 { 516 .type = AMD_IP_BLOCK_TYPE_IH, 517 .major = 4, 518 .minor = 0, 519 .rev = 0, 520 .funcs = &vega10_ih_ip_funcs, 521 }; 522