1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 #include "soc15.h" 29 30 #include "oss/osssys_4_0_offset.h" 31 #include "oss/osssys_4_0_sh_mask.h" 32 33 #include "soc15_common.h" 34 #include "vega10_ih.h" 35 36 #define MAX_REARM_RETRY 10 37 38 static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 39 40 /** 41 * vega10_ih_init_register_offset - Initialize register offset for ih rings 42 * 43 * @adev: amdgpu_device pointer 44 * 45 * Initialize register offset ih rings (VEGA10). 46 */ 47 static void vega10_ih_init_register_offset(struct amdgpu_device *adev) 48 { 49 struct amdgpu_ih_regs *ih_regs; 50 51 if (adev->irq.ih.ring_size) { 52 ih_regs = &adev->irq.ih.ih_regs; 53 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); 54 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); 55 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 56 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 57 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 58 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); 59 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); 60 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); 61 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; 62 } 63 64 if (adev->irq.ih1.ring_size) { 65 ih_regs = &adev->irq.ih1.ih_regs; 66 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); 67 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); 68 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 69 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 70 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 71 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1); 72 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; 73 } 74 75 if (adev->irq.ih2.ring_size) { 76 ih_regs = &adev->irq.ih2.ih_regs; 77 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); 78 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2); 79 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 80 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 81 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 82 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2); 83 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2; 84 } 85 } 86 87 /** 88 * vega10_ih_toggle_ring_interrupts - toggle the interrupt ring buffer 89 * 90 * @adev: amdgpu_device pointer 91 * @ih: amdgpu_ih_ring pointet 92 * @enable: true - enable the interrupts, false - disable the interrupts 93 * 94 * Toggle the interrupt ring buffer (VEGA10) 95 */ 96 static int vega10_ih_toggle_ring_interrupts(struct amdgpu_device *adev, 97 struct amdgpu_ih_ring *ih, 98 bool enable) 99 { 100 struct amdgpu_ih_regs *ih_regs; 101 uint32_t tmp; 102 103 ih_regs = &ih->ih_regs; 104 105 tmp = RREG32(ih_regs->ih_rb_cntl); 106 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); 107 /* enable_intr field is only valid in ring0 */ 108 if (ih == &adev->irq.ih) 109 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); 110 if (amdgpu_sriov_vf(adev)) { 111 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 112 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 113 return -ETIMEDOUT; 114 } 115 } else { 116 WREG32(ih_regs->ih_rb_cntl, tmp); 117 } 118 119 if (enable) { 120 ih->enabled = true; 121 } else { 122 /* set rptr, wptr to 0 */ 123 WREG32(ih_regs->ih_rb_rptr, 0); 124 WREG32(ih_regs->ih_rb_wptr, 0); 125 ih->enabled = false; 126 ih->rptr = 0; 127 } 128 129 return 0; 130 } 131 132 /** 133 * vega10_ih_toggle_interrupts - Toggle all the available interrupt ring buffers 134 * 135 * @adev: amdgpu_device pointer 136 * @enable: enable or disable interrupt ring buffers 137 * 138 * Toggle all the available interrupt ring buffers (VEGA10). 139 */ 140 static int vega10_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable) 141 { 142 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 143 int i; 144 int r; 145 146 for (i = 0; i < ARRAY_SIZE(ih); i++) { 147 if (ih[i]->ring_size) { 148 r = vega10_ih_toggle_ring_interrupts(adev, ih[i], enable); 149 if (r) 150 return r; 151 } 152 } 153 154 return 0; 155 } 156 157 static uint32_t vega10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 158 { 159 int rb_bufsz = order_base_2(ih->ring_size / 4); 160 161 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 162 MC_SPACE, ih->use_bus_addr ? 1 : 4); 163 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 164 WPTR_OVERFLOW_CLEAR, 1); 165 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 166 WPTR_OVERFLOW_ENABLE, 1); 167 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 168 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 169 * value is written to memory 170 */ 171 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 172 WPTR_WRITEBACK_ENABLE, 1); 173 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 174 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 175 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 176 177 return ih_rb_cntl; 178 } 179 180 static uint32_t vega10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 181 { 182 u32 ih_doorbell_rtpr = 0; 183 184 if (ih->use_doorbell) { 185 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 186 IH_DOORBELL_RPTR, OFFSET, 187 ih->doorbell_index); 188 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 189 IH_DOORBELL_RPTR, 190 ENABLE, 1); 191 } else { 192 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 193 IH_DOORBELL_RPTR, 194 ENABLE, 0); 195 } 196 return ih_doorbell_rtpr; 197 } 198 199 /** 200 * vega10_ih_enable_ring - enable an ih ring buffer 201 * 202 * @adev: amdgpu_device pointer 203 * @ih: amdgpu_ih_ring pointer 204 * 205 * Enable an ih ring buffer (VEGA10) 206 */ 207 static int vega10_ih_enable_ring(struct amdgpu_device *adev, 208 struct amdgpu_ih_ring *ih) 209 { 210 struct amdgpu_ih_regs *ih_regs; 211 uint32_t tmp; 212 213 ih_regs = &ih->ih_regs; 214 215 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 216 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); 217 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); 218 219 tmp = RREG32(ih_regs->ih_rb_cntl); 220 tmp = vega10_ih_rb_cntl(ih, tmp); 221 if (ih == &adev->irq.ih) 222 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); 223 if (ih == &adev->irq.ih1) { 224 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0); 225 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); 226 } 227 if (amdgpu_sriov_vf(adev)) { 228 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 229 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 230 return -ETIMEDOUT; 231 } 232 } else { 233 WREG32(ih_regs->ih_rb_cntl, tmp); 234 } 235 236 if (ih == &adev->irq.ih) { 237 /* set the ih ring 0 writeback address whether it's enabled or not */ 238 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); 239 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); 240 } 241 242 /* set rptr, wptr to 0 */ 243 WREG32(ih_regs->ih_rb_wptr, 0); 244 WREG32(ih_regs->ih_rb_rptr, 0); 245 246 WREG32(ih_regs->ih_doorbell_rptr, vega10_ih_doorbell_rptr(ih)); 247 248 return 0; 249 } 250 251 /** 252 * vega10_ih_irq_init - init and enable the interrupt ring 253 * 254 * @adev: amdgpu_device pointer 255 * 256 * Allocate a ring buffer for the interrupt controller, 257 * enable the RLC, disable interrupts, enable the IH 258 * ring buffer and enable it (VI). 259 * Called at device load and reume. 260 * Returns 0 for success, errors for failure. 261 */ 262 static int vega10_ih_irq_init(struct amdgpu_device *adev) 263 { 264 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 265 u32 ih_chicken; 266 int ret; 267 int i; 268 u32 tmp; 269 270 /* disable irqs */ 271 ret = vega10_ih_toggle_interrupts(adev, false); 272 if (ret) 273 return ret; 274 275 adev->nbio.funcs->ih_control(adev); 276 277 if ((adev->asic_type == CHIP_ARCTURUS && 278 adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) || 279 adev->asic_type == CHIP_RENOIR) { 280 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 281 if (adev->irq.ih.use_bus_addr) { 282 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 283 MC_SPACE_GPA_ENABLE, 1); 284 } else { 285 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 286 MC_SPACE_FBPA_ENABLE, 1); 287 } 288 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 289 } 290 291 for (i = 0; i < ARRAY_SIZE(ih); i++) { 292 if (ih[i]->ring_size) { 293 ret = vega10_ih_enable_ring(adev, ih[i]); 294 if (ret) 295 return ret; 296 } 297 } 298 299 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 300 tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 301 CLIENT18_IS_STORM_CLIENT, 1); 302 WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 303 304 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 305 tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 306 WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 307 308 pci_set_master(adev->pdev); 309 310 /* enable interrupts */ 311 ret = vega10_ih_toggle_interrupts(adev, true); 312 if (ret) 313 return ret; 314 315 return 0; 316 } 317 318 /** 319 * vega10_ih_irq_disable - disable interrupts 320 * 321 * @adev: amdgpu_device pointer 322 * 323 * Disable interrupts on the hw (VEGA10). 324 */ 325 static void vega10_ih_irq_disable(struct amdgpu_device *adev) 326 { 327 vega10_ih_toggle_interrupts(adev, false); 328 329 /* Wait and acknowledge irq */ 330 mdelay(1); 331 } 332 333 /** 334 * vega10_ih_get_wptr - get the IH ring buffer wptr 335 * 336 * @adev: amdgpu_device pointer 337 * @ih: IH ring buffer to fetch wptr 338 * 339 * Get the IH ring buffer wptr from either the register 340 * or the writeback memory buffer (VEGA10). Also check for 341 * ring buffer overflow and deal with it. 342 * Returns the value of the wptr. 343 */ 344 static u32 vega10_ih_get_wptr(struct amdgpu_device *adev, 345 struct amdgpu_ih_ring *ih) 346 { 347 u32 wptr, tmp; 348 struct amdgpu_ih_regs *ih_regs; 349 350 wptr = le32_to_cpu(*ih->wptr_cpu); 351 ih_regs = &ih->ih_regs; 352 353 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 354 goto out; 355 356 /* Double check that the overflow wasn't already cleared. */ 357 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); 358 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 359 goto out; 360 361 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 362 363 /* When a ring buffer overflow happen start parsing interrupt 364 * from the last not overwritten vector (wptr + 32). Hopefully 365 * this should allow us to catchup. 366 */ 367 tmp = (wptr + 32) & ih->ptr_mask; 368 dev_warn(adev->dev, "IH ring buffer overflow " 369 "(0x%08X, 0x%08X, 0x%08X)\n", 370 wptr, ih->rptr, tmp); 371 ih->rptr = tmp; 372 373 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); 374 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 375 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 376 377 out: 378 return (wptr & ih->ptr_mask); 379 } 380 381 /** 382 * vega10_ih_decode_iv - decode an interrupt vector 383 * 384 * @adev: amdgpu_device pointer 385 * @ih: IH ring buffer to decode 386 * @entry: IV entry to place decoded information into 387 * 388 * Decodes the interrupt vector at the current rptr 389 * position and also advance the position. 390 */ 391 static void vega10_ih_decode_iv(struct amdgpu_device *adev, 392 struct amdgpu_ih_ring *ih, 393 struct amdgpu_iv_entry *entry) 394 { 395 /* wptr/rptr are in bytes! */ 396 u32 ring_index = ih->rptr >> 2; 397 uint32_t dw[8]; 398 399 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 400 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 401 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 402 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 403 dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); 404 dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); 405 dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); 406 dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); 407 408 entry->client_id = dw[0] & 0xff; 409 entry->src_id = (dw[0] >> 8) & 0xff; 410 entry->ring_id = (dw[0] >> 16) & 0xff; 411 entry->vmid = (dw[0] >> 24) & 0xf; 412 entry->vmid_src = (dw[0] >> 31); 413 entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); 414 entry->timestamp_src = dw[2] >> 31; 415 entry->pasid = dw[3] & 0xffff; 416 entry->pasid_src = dw[3] >> 31; 417 entry->src_data[0] = dw[4]; 418 entry->src_data[1] = dw[5]; 419 entry->src_data[2] = dw[6]; 420 entry->src_data[3] = dw[7]; 421 422 /* wptr/rptr are in bytes! */ 423 ih->rptr += 32; 424 } 425 426 /** 427 * vega10_ih_irq_rearm - rearm IRQ if lost 428 * 429 * @adev: amdgpu_device pointer 430 * @ih: IH ring to match 431 * 432 */ 433 static void vega10_ih_irq_rearm(struct amdgpu_device *adev, 434 struct amdgpu_ih_ring *ih) 435 { 436 uint32_t v = 0; 437 uint32_t i = 0; 438 struct amdgpu_ih_regs *ih_regs; 439 440 ih_regs = &ih->ih_regs; 441 /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */ 442 for (i = 0; i < MAX_REARM_RETRY; i++) { 443 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); 444 if ((v < ih->ring_size) && (v != ih->rptr)) 445 WDOORBELL32(ih->doorbell_index, ih->rptr); 446 else 447 break; 448 } 449 } 450 451 /** 452 * vega10_ih_set_rptr - set the IH ring buffer rptr 453 * 454 * @adev: amdgpu_device pointer 455 * @ih: IH ring buffer to set rptr 456 * 457 * Set the IH ring buffer rptr. 458 */ 459 static void vega10_ih_set_rptr(struct amdgpu_device *adev, 460 struct amdgpu_ih_ring *ih) 461 { 462 struct amdgpu_ih_regs *ih_regs; 463 464 if (ih->use_doorbell) { 465 /* XXX check if swapping is necessary on BE */ 466 *ih->rptr_cpu = ih->rptr; 467 WDOORBELL32(ih->doorbell_index, ih->rptr); 468 469 if (amdgpu_sriov_vf(adev)) 470 vega10_ih_irq_rearm(adev, ih); 471 } else { 472 ih_regs = &ih->ih_regs; 473 WREG32(ih_regs->ih_rb_rptr, ih->rptr); 474 } 475 } 476 477 /** 478 * vega10_ih_self_irq - dispatch work for ring 1 and 2 479 * 480 * @adev: amdgpu_device pointer 481 * @source: irq source 482 * @entry: IV with WPTR update 483 * 484 * Update the WPTR from the IV and schedule work to handle the entries. 485 */ 486 static int vega10_ih_self_irq(struct amdgpu_device *adev, 487 struct amdgpu_irq_src *source, 488 struct amdgpu_iv_entry *entry) 489 { 490 uint32_t wptr = cpu_to_le32(entry->src_data[0]); 491 492 switch (entry->ring_id) { 493 case 1: 494 *adev->irq.ih1.wptr_cpu = wptr; 495 schedule_work(&adev->irq.ih1_work); 496 break; 497 case 2: 498 *adev->irq.ih2.wptr_cpu = wptr; 499 schedule_work(&adev->irq.ih2_work); 500 break; 501 default: break; 502 } 503 return 0; 504 } 505 506 static const struct amdgpu_irq_src_funcs vega10_ih_self_irq_funcs = { 507 .process = vega10_ih_self_irq, 508 }; 509 510 static void vega10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 511 { 512 adev->irq.self_irq.num_types = 0; 513 adev->irq.self_irq.funcs = &vega10_ih_self_irq_funcs; 514 } 515 516 static int vega10_ih_early_init(void *handle) 517 { 518 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 519 520 vega10_ih_set_interrupt_funcs(adev); 521 vega10_ih_set_self_irq_funcs(adev); 522 return 0; 523 } 524 525 static int vega10_ih_sw_init(void *handle) 526 { 527 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 528 int r; 529 530 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 531 &adev->irq.self_irq); 532 if (r) 533 return r; 534 535 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true); 536 if (r) 537 return r; 538 539 adev->irq.ih.use_doorbell = true; 540 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 541 542 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 543 if (r) 544 return r; 545 546 adev->irq.ih1.use_doorbell = true; 547 adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; 548 549 r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 550 if (r) 551 return r; 552 553 adev->irq.ih2.use_doorbell = true; 554 adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1; 555 556 /* initialize ih control registers offset */ 557 vega10_ih_init_register_offset(adev); 558 559 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); 560 if (r) 561 return r; 562 563 r = amdgpu_irq_init(adev); 564 565 return r; 566 } 567 568 static int vega10_ih_sw_fini(void *handle) 569 { 570 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 571 572 amdgpu_irq_fini(adev); 573 amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 574 amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 575 amdgpu_ih_ring_fini(adev, &adev->irq.ih); 576 577 return 0; 578 } 579 580 static int vega10_ih_hw_init(void *handle) 581 { 582 int r; 583 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 584 585 r = vega10_ih_irq_init(adev); 586 if (r) 587 return r; 588 589 return 0; 590 } 591 592 static int vega10_ih_hw_fini(void *handle) 593 { 594 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 595 596 vega10_ih_irq_disable(adev); 597 598 return 0; 599 } 600 601 static int vega10_ih_suspend(void *handle) 602 { 603 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 604 605 return vega10_ih_hw_fini(adev); 606 } 607 608 static int vega10_ih_resume(void *handle) 609 { 610 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 611 612 return vega10_ih_hw_init(adev); 613 } 614 615 static bool vega10_ih_is_idle(void *handle) 616 { 617 /* todo */ 618 return true; 619 } 620 621 static int vega10_ih_wait_for_idle(void *handle) 622 { 623 /* todo */ 624 return -ETIMEDOUT; 625 } 626 627 static int vega10_ih_soft_reset(void *handle) 628 { 629 /* todo */ 630 631 return 0; 632 } 633 634 static void vega10_ih_update_clockgating_state(struct amdgpu_device *adev, 635 bool enable) 636 { 637 uint32_t data, def, field_val; 638 639 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 640 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 641 field_val = enable ? 0 : 1; 642 /** 643 * Vega10/12 and RAVEN don't have IH_BUFFER_MEM_CLK_SOFT_OVERRIDE field. 644 */ 645 if (adev->asic_type == CHIP_RENOIR) 646 data = REG_SET_FIELD(data, IH_CLK_CTRL, 647 IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val); 648 649 data = REG_SET_FIELD(data, IH_CLK_CTRL, 650 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 651 data = REG_SET_FIELD(data, IH_CLK_CTRL, 652 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 653 data = REG_SET_FIELD(data, IH_CLK_CTRL, 654 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 655 data = REG_SET_FIELD(data, IH_CLK_CTRL, 656 DYN_CLK_SOFT_OVERRIDE, field_val); 657 data = REG_SET_FIELD(data, IH_CLK_CTRL, 658 REG_CLK_SOFT_OVERRIDE, field_val); 659 if (def != data) 660 WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 661 } 662 } 663 664 static int vega10_ih_set_clockgating_state(void *handle, 665 enum amd_clockgating_state state) 666 { 667 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 668 669 vega10_ih_update_clockgating_state(adev, 670 state == AMD_CG_STATE_GATE); 671 return 0; 672 673 } 674 675 static int vega10_ih_set_powergating_state(void *handle, 676 enum amd_powergating_state state) 677 { 678 return 0; 679 } 680 681 const struct amd_ip_funcs vega10_ih_ip_funcs = { 682 .name = "vega10_ih", 683 .early_init = vega10_ih_early_init, 684 .late_init = NULL, 685 .sw_init = vega10_ih_sw_init, 686 .sw_fini = vega10_ih_sw_fini, 687 .hw_init = vega10_ih_hw_init, 688 .hw_fini = vega10_ih_hw_fini, 689 .suspend = vega10_ih_suspend, 690 .resume = vega10_ih_resume, 691 .is_idle = vega10_ih_is_idle, 692 .wait_for_idle = vega10_ih_wait_for_idle, 693 .soft_reset = vega10_ih_soft_reset, 694 .set_clockgating_state = vega10_ih_set_clockgating_state, 695 .set_powergating_state = vega10_ih_set_powergating_state, 696 }; 697 698 static const struct amdgpu_ih_funcs vega10_ih_funcs = { 699 .get_wptr = vega10_ih_get_wptr, 700 .decode_iv = vega10_ih_decode_iv, 701 .set_rptr = vega10_ih_set_rptr 702 }; 703 704 static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 705 { 706 adev->irq.ih_funcs = &vega10_ih_funcs; 707 } 708 709 const struct amdgpu_ip_block_version vega10_ih_ip_block = 710 { 711 .type = AMD_IP_BLOCK_TYPE_IH, 712 .major = 4, 713 .minor = 0, 714 .rev = 0, 715 .funcs = &vega10_ih_ip_funcs, 716 }; 717