1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 #include "soc15.h" 29 30 #include "oss/osssys_4_0_offset.h" 31 #include "oss/osssys_4_0_sh_mask.h" 32 33 #include "soc15_common.h" 34 #include "vega10_ih.h" 35 36 #define MAX_REARM_RETRY 10 37 38 static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 39 40 /** 41 * vega10_ih_init_register_offset - Initialize register offset for ih rings 42 * 43 * @adev: amdgpu_device pointer 44 * 45 * Initialize register offset ih rings (VEGA10). 46 */ 47 static void vega10_ih_init_register_offset(struct amdgpu_device *adev) 48 { 49 struct amdgpu_ih_regs *ih_regs; 50 51 if (adev->irq.ih.ring_size) { 52 ih_regs = &adev->irq.ih.ih_regs; 53 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); 54 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); 55 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 56 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 57 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 58 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); 59 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); 60 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); 61 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; 62 } 63 64 if (adev->irq.ih1.ring_size) { 65 ih_regs = &adev->irq.ih1.ih_regs; 66 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); 67 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); 68 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 69 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 70 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 71 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1); 72 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; 73 } 74 75 if (adev->irq.ih2.ring_size) { 76 ih_regs = &adev->irq.ih2.ih_regs; 77 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); 78 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2); 79 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 80 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 81 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 82 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2); 83 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2; 84 } 85 } 86 87 /** 88 * vega10_ih_toggle_ring_interrupts - toggle the interrupt ring buffer 89 * 90 * @adev: amdgpu_device pointer 91 * @ih: amdgpu_ih_ring pointet 92 * @enable: true - enable the interrupts, false - disable the interrupts 93 * 94 * Toggle the interrupt ring buffer (VEGA10) 95 */ 96 static int vega10_ih_toggle_ring_interrupts(struct amdgpu_device *adev, 97 struct amdgpu_ih_ring *ih, 98 bool enable) 99 { 100 struct amdgpu_ih_regs *ih_regs; 101 uint32_t tmp; 102 103 ih_regs = &ih->ih_regs; 104 105 tmp = RREG32(ih_regs->ih_rb_cntl); 106 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); 107 /* enable_intr field is only valid in ring0 */ 108 if (ih == &adev->irq.ih) 109 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); 110 if (amdgpu_sriov_vf(adev)) { 111 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 112 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 113 return -ETIMEDOUT; 114 } 115 } else { 116 WREG32(ih_regs->ih_rb_cntl, tmp); 117 } 118 119 if (enable) { 120 ih->enabled = true; 121 } else { 122 /* set rptr, wptr to 0 */ 123 WREG32(ih_regs->ih_rb_rptr, 0); 124 WREG32(ih_regs->ih_rb_wptr, 0); 125 ih->enabled = false; 126 ih->rptr = 0; 127 } 128 129 return 0; 130 } 131 132 /** 133 * vega10_ih_toggle_interrupts - Toggle all the available interrupt ring buffers 134 * 135 * @adev: amdgpu_device pointer 136 * @enable: enable or disable interrupt ring buffers 137 * 138 * Toggle all the available interrupt ring buffers (VEGA10). 139 */ 140 static int vega10_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable) 141 { 142 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 143 int i; 144 int r; 145 146 for (i = 0; i < ARRAY_SIZE(ih); i++) { 147 if (ih[i]->ring_size) { 148 r = vega10_ih_toggle_ring_interrupts(adev, ih[i], enable); 149 if (r) 150 return r; 151 } 152 } 153 154 return 0; 155 } 156 157 static uint32_t vega10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 158 { 159 int rb_bufsz = order_base_2(ih->ring_size / 4); 160 161 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 162 MC_SPACE, ih->use_bus_addr ? 1 : 4); 163 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 164 WPTR_OVERFLOW_CLEAR, 1); 165 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 166 WPTR_OVERFLOW_ENABLE, 1); 167 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 168 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 169 * value is written to memory 170 */ 171 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 172 WPTR_WRITEBACK_ENABLE, 1); 173 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 174 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 175 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 176 177 return ih_rb_cntl; 178 } 179 180 static uint32_t vega10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 181 { 182 u32 ih_doorbell_rtpr = 0; 183 184 if (ih->use_doorbell) { 185 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 186 IH_DOORBELL_RPTR, OFFSET, 187 ih->doorbell_index); 188 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 189 IH_DOORBELL_RPTR, 190 ENABLE, 1); 191 } else { 192 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 193 IH_DOORBELL_RPTR, 194 ENABLE, 0); 195 } 196 return ih_doorbell_rtpr; 197 } 198 199 /** 200 * vega10_ih_enable_ring - enable an ih ring buffer 201 * 202 * @adev: amdgpu_device pointer 203 * @ih: amdgpu_ih_ring pointer 204 * 205 * Enable an ih ring buffer (VEGA10) 206 */ 207 static int vega10_ih_enable_ring(struct amdgpu_device *adev, 208 struct amdgpu_ih_ring *ih) 209 { 210 struct amdgpu_ih_regs *ih_regs; 211 uint32_t tmp; 212 213 ih_regs = &ih->ih_regs; 214 215 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 216 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); 217 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); 218 219 tmp = RREG32(ih_regs->ih_rb_cntl); 220 tmp = vega10_ih_rb_cntl(ih, tmp); 221 if (ih == &adev->irq.ih) 222 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); 223 if (ih == &adev->irq.ih1) 224 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); 225 if (amdgpu_sriov_vf(adev)) { 226 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 227 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 228 return -ETIMEDOUT; 229 } 230 } else { 231 WREG32(ih_regs->ih_rb_cntl, tmp); 232 } 233 234 if (ih == &adev->irq.ih) { 235 /* set the ih ring 0 writeback address whether it's enabled or not */ 236 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); 237 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); 238 } 239 240 /* set rptr, wptr to 0 */ 241 WREG32(ih_regs->ih_rb_wptr, 0); 242 WREG32(ih_regs->ih_rb_rptr, 0); 243 244 WREG32(ih_regs->ih_doorbell_rptr, vega10_ih_doorbell_rptr(ih)); 245 246 return 0; 247 } 248 249 /** 250 * vega10_ih_irq_init - init and enable the interrupt ring 251 * 252 * @adev: amdgpu_device pointer 253 * 254 * Allocate a ring buffer for the interrupt controller, 255 * enable the RLC, disable interrupts, enable the IH 256 * ring buffer and enable it (VI). 257 * Called at device load and reume. 258 * Returns 0 for success, errors for failure. 259 */ 260 static int vega10_ih_irq_init(struct amdgpu_device *adev) 261 { 262 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 263 u32 ih_chicken; 264 int ret; 265 int i; 266 267 /* disable irqs */ 268 ret = vega10_ih_toggle_interrupts(adev, false); 269 if (ret) 270 return ret; 271 272 adev->nbio.funcs->ih_control(adev); 273 274 if (adev->asic_type == CHIP_RENOIR) { 275 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 276 if (adev->irq.ih.use_bus_addr) { 277 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 278 MC_SPACE_GPA_ENABLE, 1); 279 } 280 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 281 } 282 283 for (i = 0; i < ARRAY_SIZE(ih); i++) { 284 if (ih[i]->ring_size) { 285 ret = vega10_ih_enable_ring(adev, ih[i]); 286 if (ret) 287 return ret; 288 } 289 } 290 291 pci_set_master(adev->pdev); 292 293 /* enable interrupts */ 294 ret = vega10_ih_toggle_interrupts(adev, true); 295 if (ret) 296 return ret; 297 298 if (adev->irq.ih_soft.ring_size) 299 adev->irq.ih_soft.enabled = true; 300 301 return 0; 302 } 303 304 /** 305 * vega10_ih_irq_disable - disable interrupts 306 * 307 * @adev: amdgpu_device pointer 308 * 309 * Disable interrupts on the hw (VEGA10). 310 */ 311 static void vega10_ih_irq_disable(struct amdgpu_device *adev) 312 { 313 vega10_ih_toggle_interrupts(adev, false); 314 315 /* Wait and acknowledge irq */ 316 mdelay(1); 317 } 318 319 /** 320 * vega10_ih_get_wptr - get the IH ring buffer wptr 321 * 322 * @adev: amdgpu_device pointer 323 * @ih: IH ring buffer to fetch wptr 324 * 325 * Get the IH ring buffer wptr from either the register 326 * or the writeback memory buffer (VEGA10). Also check for 327 * ring buffer overflow and deal with it. 328 * Returns the value of the wptr. 329 */ 330 static u32 vega10_ih_get_wptr(struct amdgpu_device *adev, 331 struct amdgpu_ih_ring *ih) 332 { 333 u32 wptr, tmp; 334 struct amdgpu_ih_regs *ih_regs; 335 336 if (ih == &adev->irq.ih) { 337 /* Only ring0 supports writeback. On other rings fall back 338 * to register-based code with overflow checking below. 339 */ 340 wptr = le32_to_cpu(*ih->wptr_cpu); 341 342 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 343 goto out; 344 } 345 346 ih_regs = &ih->ih_regs; 347 348 /* Double check that the overflow wasn't already cleared. */ 349 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); 350 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 351 goto out; 352 353 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 354 355 /* When a ring buffer overflow happen start parsing interrupt 356 * from the last not overwritten vector (wptr + 32). Hopefully 357 * this should allow us to catchup. 358 */ 359 tmp = (wptr + 32) & ih->ptr_mask; 360 dev_warn(adev->dev, "IH ring buffer overflow " 361 "(0x%08X, 0x%08X, 0x%08X)\n", 362 wptr, ih->rptr, tmp); 363 ih->rptr = tmp; 364 365 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); 366 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 367 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 368 369 out: 370 return (wptr & ih->ptr_mask); 371 } 372 373 /** 374 * vega10_ih_irq_rearm - rearm IRQ if lost 375 * 376 * @adev: amdgpu_device pointer 377 * @ih: IH ring to match 378 * 379 */ 380 static void vega10_ih_irq_rearm(struct amdgpu_device *adev, 381 struct amdgpu_ih_ring *ih) 382 { 383 uint32_t v = 0; 384 uint32_t i = 0; 385 struct amdgpu_ih_regs *ih_regs; 386 387 ih_regs = &ih->ih_regs; 388 /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */ 389 for (i = 0; i < MAX_REARM_RETRY; i++) { 390 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); 391 if ((v < ih->ring_size) && (v != ih->rptr)) 392 WDOORBELL32(ih->doorbell_index, ih->rptr); 393 else 394 break; 395 } 396 } 397 398 /** 399 * vega10_ih_set_rptr - set the IH ring buffer rptr 400 * 401 * @adev: amdgpu_device pointer 402 * @ih: IH ring buffer to set rptr 403 * 404 * Set the IH ring buffer rptr. 405 */ 406 static void vega10_ih_set_rptr(struct amdgpu_device *adev, 407 struct amdgpu_ih_ring *ih) 408 { 409 struct amdgpu_ih_regs *ih_regs; 410 411 if (ih->use_doorbell) { 412 /* XXX check if swapping is necessary on BE */ 413 *ih->rptr_cpu = ih->rptr; 414 WDOORBELL32(ih->doorbell_index, ih->rptr); 415 416 if (amdgpu_sriov_vf(adev)) 417 vega10_ih_irq_rearm(adev, ih); 418 } else { 419 ih_regs = &ih->ih_regs; 420 WREG32(ih_regs->ih_rb_rptr, ih->rptr); 421 } 422 } 423 424 /** 425 * vega10_ih_self_irq - dispatch work for ring 1 and 2 426 * 427 * @adev: amdgpu_device pointer 428 * @source: irq source 429 * @entry: IV with WPTR update 430 * 431 * Update the WPTR from the IV and schedule work to handle the entries. 432 */ 433 static int vega10_ih_self_irq(struct amdgpu_device *adev, 434 struct amdgpu_irq_src *source, 435 struct amdgpu_iv_entry *entry) 436 { 437 switch (entry->ring_id) { 438 case 1: 439 schedule_work(&adev->irq.ih1_work); 440 break; 441 case 2: 442 schedule_work(&adev->irq.ih2_work); 443 break; 444 default: break; 445 } 446 return 0; 447 } 448 449 static const struct amdgpu_irq_src_funcs vega10_ih_self_irq_funcs = { 450 .process = vega10_ih_self_irq, 451 }; 452 453 static void vega10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 454 { 455 adev->irq.self_irq.num_types = 0; 456 adev->irq.self_irq.funcs = &vega10_ih_self_irq_funcs; 457 } 458 459 static int vega10_ih_early_init(void *handle) 460 { 461 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 462 463 vega10_ih_set_interrupt_funcs(adev); 464 vega10_ih_set_self_irq_funcs(adev); 465 return 0; 466 } 467 468 static int vega10_ih_sw_init(void *handle) 469 { 470 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 471 int r; 472 473 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 474 &adev->irq.self_irq); 475 if (r) 476 return r; 477 478 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true); 479 if (r) 480 return r; 481 482 adev->irq.ih.use_doorbell = true; 483 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 484 485 if (!(adev->flags & AMD_IS_APU)) { 486 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 487 if (r) 488 return r; 489 490 adev->irq.ih1.use_doorbell = true; 491 adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; 492 493 r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 494 if (r) 495 return r; 496 497 adev->irq.ih2.use_doorbell = true; 498 adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1; 499 } 500 /* initialize ih control registers offset */ 501 vega10_ih_init_register_offset(adev); 502 503 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); 504 if (r) 505 return r; 506 507 r = amdgpu_irq_init(adev); 508 509 return r; 510 } 511 512 static int vega10_ih_sw_fini(void *handle) 513 { 514 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 515 516 amdgpu_irq_fini(adev); 517 amdgpu_ih_ring_fini(adev, &adev->irq.ih_soft); 518 amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 519 amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 520 amdgpu_ih_ring_fini(adev, &adev->irq.ih); 521 522 return 0; 523 } 524 525 static int vega10_ih_hw_init(void *handle) 526 { 527 int r; 528 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 529 530 r = vega10_ih_irq_init(adev); 531 if (r) 532 return r; 533 534 return 0; 535 } 536 537 static int vega10_ih_hw_fini(void *handle) 538 { 539 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 540 541 vega10_ih_irq_disable(adev); 542 543 return 0; 544 } 545 546 static int vega10_ih_suspend(void *handle) 547 { 548 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 549 550 return vega10_ih_hw_fini(adev); 551 } 552 553 static int vega10_ih_resume(void *handle) 554 { 555 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 556 557 return vega10_ih_hw_init(adev); 558 } 559 560 static bool vega10_ih_is_idle(void *handle) 561 { 562 /* todo */ 563 return true; 564 } 565 566 static int vega10_ih_wait_for_idle(void *handle) 567 { 568 /* todo */ 569 return -ETIMEDOUT; 570 } 571 572 static int vega10_ih_soft_reset(void *handle) 573 { 574 /* todo */ 575 576 return 0; 577 } 578 579 static void vega10_ih_update_clockgating_state(struct amdgpu_device *adev, 580 bool enable) 581 { 582 uint32_t data, def, field_val; 583 584 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 585 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 586 field_val = enable ? 0 : 1; 587 /** 588 * Vega10/12 and RAVEN don't have IH_BUFFER_MEM_CLK_SOFT_OVERRIDE field. 589 */ 590 if (adev->asic_type == CHIP_RENOIR) 591 data = REG_SET_FIELD(data, IH_CLK_CTRL, 592 IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val); 593 594 data = REG_SET_FIELD(data, IH_CLK_CTRL, 595 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 596 data = REG_SET_FIELD(data, IH_CLK_CTRL, 597 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 598 data = REG_SET_FIELD(data, IH_CLK_CTRL, 599 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 600 data = REG_SET_FIELD(data, IH_CLK_CTRL, 601 DYN_CLK_SOFT_OVERRIDE, field_val); 602 data = REG_SET_FIELD(data, IH_CLK_CTRL, 603 REG_CLK_SOFT_OVERRIDE, field_val); 604 if (def != data) 605 WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 606 } 607 } 608 609 static int vega10_ih_set_clockgating_state(void *handle, 610 enum amd_clockgating_state state) 611 { 612 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 613 614 vega10_ih_update_clockgating_state(adev, 615 state == AMD_CG_STATE_GATE); 616 return 0; 617 618 } 619 620 static int vega10_ih_set_powergating_state(void *handle, 621 enum amd_powergating_state state) 622 { 623 return 0; 624 } 625 626 const struct amd_ip_funcs vega10_ih_ip_funcs = { 627 .name = "vega10_ih", 628 .early_init = vega10_ih_early_init, 629 .late_init = NULL, 630 .sw_init = vega10_ih_sw_init, 631 .sw_fini = vega10_ih_sw_fini, 632 .hw_init = vega10_ih_hw_init, 633 .hw_fini = vega10_ih_hw_fini, 634 .suspend = vega10_ih_suspend, 635 .resume = vega10_ih_resume, 636 .is_idle = vega10_ih_is_idle, 637 .wait_for_idle = vega10_ih_wait_for_idle, 638 .soft_reset = vega10_ih_soft_reset, 639 .set_clockgating_state = vega10_ih_set_clockgating_state, 640 .set_powergating_state = vega10_ih_set_powergating_state, 641 }; 642 643 static const struct amdgpu_ih_funcs vega10_ih_funcs = { 644 .get_wptr = vega10_ih_get_wptr, 645 .decode_iv = amdgpu_ih_decode_iv_helper, 646 .set_rptr = vega10_ih_set_rptr 647 }; 648 649 static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 650 { 651 adev->irq.ih_funcs = &vega10_ih_funcs; 652 } 653 654 const struct amdgpu_ip_block_version vega10_ih_ip_block = 655 { 656 .type = AMD_IP_BLOCK_TYPE_IH, 657 .major = 4, 658 .minor = 0, 659 .rev = 0, 660 .funcs = &vega10_ih_ip_funcs, 661 }; 662