1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 #include "soc15.h" 29 30 #include "oss/osssys_4_0_offset.h" 31 #include "oss/osssys_4_0_sh_mask.h" 32 33 #include "soc15_common.h" 34 #include "vega10_ih.h" 35 36 #define MAX_REARM_RETRY 10 37 38 static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 39 40 /** 41 * vega10_ih_init_register_offset - Initialize register offset for ih rings 42 * 43 * @adev: amdgpu_device pointer 44 * 45 * Initialize register offset ih rings (VEGA10). 46 */ 47 static void vega10_ih_init_register_offset(struct amdgpu_device *adev) 48 { 49 struct amdgpu_ih_regs *ih_regs; 50 51 if (adev->irq.ih.ring_size) { 52 ih_regs = &adev->irq.ih.ih_regs; 53 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); 54 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); 55 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 56 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 57 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 58 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); 59 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); 60 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); 61 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; 62 } 63 64 if (adev->irq.ih1.ring_size) { 65 ih_regs = &adev->irq.ih1.ih_regs; 66 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); 67 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); 68 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 69 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 70 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 71 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1); 72 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; 73 } 74 75 if (adev->irq.ih2.ring_size) { 76 ih_regs = &adev->irq.ih2.ih_regs; 77 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); 78 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2); 79 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 80 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 81 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 82 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2); 83 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2; 84 } 85 } 86 87 /** 88 * vega10_ih_toggle_ring_interrupts - toggle the interrupt ring buffer 89 * 90 * @adev: amdgpu_device pointer 91 * @ih: amdgpu_ih_ring pointet 92 * @enable: true - enable the interrupts, false - disable the interrupts 93 * 94 * Toggle the interrupt ring buffer (VEGA10) 95 */ 96 static int vega10_ih_toggle_ring_interrupts(struct amdgpu_device *adev, 97 struct amdgpu_ih_ring *ih, 98 bool enable) 99 { 100 struct amdgpu_ih_regs *ih_regs; 101 uint32_t tmp; 102 103 ih_regs = &ih->ih_regs; 104 105 tmp = RREG32(ih_regs->ih_rb_cntl); 106 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); 107 /* enable_intr field is only valid in ring0 */ 108 if (ih == &adev->irq.ih) 109 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); 110 if (amdgpu_sriov_vf(adev)) { 111 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 112 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 113 return -ETIMEDOUT; 114 } 115 } else { 116 WREG32(ih_regs->ih_rb_cntl, tmp); 117 } 118 119 if (enable) { 120 ih->enabled = true; 121 } else { 122 /* set rptr, wptr to 0 */ 123 WREG32(ih_regs->ih_rb_rptr, 0); 124 WREG32(ih_regs->ih_rb_wptr, 0); 125 ih->enabled = false; 126 ih->rptr = 0; 127 } 128 129 return 0; 130 } 131 132 /** 133 * vega10_ih_toggle_interrupts - Toggle all the available interrupt ring buffers 134 * 135 * @adev: amdgpu_device pointer 136 * @enable: enable or disable interrupt ring buffers 137 * 138 * Toggle all the available interrupt ring buffers (VEGA10). 139 */ 140 static int vega10_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable) 141 { 142 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 143 int i; 144 int r; 145 146 for (i = 0; i < ARRAY_SIZE(ih); i++) { 147 if (ih[i]->ring_size) { 148 r = vega10_ih_toggle_ring_interrupts(adev, ih[i], enable); 149 if (r) 150 return r; 151 } 152 } 153 154 return 0; 155 } 156 157 static uint32_t vega10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 158 { 159 int rb_bufsz = order_base_2(ih->ring_size / 4); 160 161 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 162 MC_SPACE, ih->use_bus_addr ? 1 : 4); 163 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 164 WPTR_OVERFLOW_CLEAR, 1); 165 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 166 WPTR_OVERFLOW_ENABLE, 1); 167 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 168 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 169 * value is written to memory 170 */ 171 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 172 WPTR_WRITEBACK_ENABLE, 1); 173 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 174 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 175 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 176 177 return ih_rb_cntl; 178 } 179 180 static uint32_t vega10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 181 { 182 u32 ih_doorbell_rtpr = 0; 183 184 if (ih->use_doorbell) { 185 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 186 IH_DOORBELL_RPTR, OFFSET, 187 ih->doorbell_index); 188 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 189 IH_DOORBELL_RPTR, 190 ENABLE, 1); 191 } else { 192 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 193 IH_DOORBELL_RPTR, 194 ENABLE, 0); 195 } 196 return ih_doorbell_rtpr; 197 } 198 199 /** 200 * vega10_ih_enable_ring - enable an ih ring buffer 201 * 202 * @adev: amdgpu_device pointer 203 * @ih: amdgpu_ih_ring pointer 204 * 205 * Enable an ih ring buffer (VEGA10) 206 */ 207 static int vega10_ih_enable_ring(struct amdgpu_device *adev, 208 struct amdgpu_ih_ring *ih) 209 { 210 struct amdgpu_ih_regs *ih_regs; 211 uint32_t tmp; 212 213 ih_regs = &ih->ih_regs; 214 215 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 216 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); 217 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); 218 219 tmp = RREG32(ih_regs->ih_rb_cntl); 220 tmp = vega10_ih_rb_cntl(ih, tmp); 221 if (ih == &adev->irq.ih) 222 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); 223 if (ih == &adev->irq.ih1) { 224 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0); 225 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); 226 } 227 if (amdgpu_sriov_vf(adev)) { 228 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 229 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 230 return -ETIMEDOUT; 231 } 232 } else { 233 WREG32(ih_regs->ih_rb_cntl, tmp); 234 } 235 236 if (ih == &adev->irq.ih) { 237 /* set the ih ring 0 writeback address whether it's enabled or not */ 238 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); 239 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); 240 } 241 242 /* set rptr, wptr to 0 */ 243 WREG32(ih_regs->ih_rb_wptr, 0); 244 WREG32(ih_regs->ih_rb_rptr, 0); 245 246 WREG32(ih_regs->ih_doorbell_rptr, vega10_ih_doorbell_rptr(ih)); 247 248 return 0; 249 } 250 251 /** 252 * vega10_ih_irq_init - init and enable the interrupt ring 253 * 254 * @adev: amdgpu_device pointer 255 * 256 * Allocate a ring buffer for the interrupt controller, 257 * enable the RLC, disable interrupts, enable the IH 258 * ring buffer and enable it (VI). 259 * Called at device load and reume. 260 * Returns 0 for success, errors for failure. 261 */ 262 static int vega10_ih_irq_init(struct amdgpu_device *adev) 263 { 264 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 265 u32 ih_chicken; 266 int ret; 267 int i; 268 u32 tmp; 269 270 /* disable irqs */ 271 ret = vega10_ih_toggle_interrupts(adev, false); 272 if (ret) 273 return ret; 274 275 adev->nbio.funcs->ih_control(adev); 276 277 if ((adev->asic_type == CHIP_ARCTURUS && 278 adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) || 279 adev->asic_type == CHIP_RENOIR) { 280 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 281 if (adev->irq.ih.use_bus_addr) { 282 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 283 MC_SPACE_GPA_ENABLE, 1); 284 } else { 285 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 286 MC_SPACE_FBPA_ENABLE, 1); 287 } 288 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 289 } 290 291 for (i = 0; i < ARRAY_SIZE(ih); i++) { 292 if (ih[i]->ring_size) { 293 ret = vega10_ih_enable_ring(adev, ih[i]); 294 if (ret) 295 return ret; 296 } 297 } 298 299 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 300 tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 301 CLIENT18_IS_STORM_CLIENT, 1); 302 WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 303 304 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 305 tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 306 WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 307 308 pci_set_master(adev->pdev); 309 310 /* enable interrupts */ 311 ret = vega10_ih_toggle_interrupts(adev, true); 312 if (ret) 313 return ret; 314 315 return 0; 316 } 317 318 /** 319 * vega10_ih_irq_disable - disable interrupts 320 * 321 * @adev: amdgpu_device pointer 322 * 323 * Disable interrupts on the hw (VEGA10). 324 */ 325 static void vega10_ih_irq_disable(struct amdgpu_device *adev) 326 { 327 vega10_ih_toggle_interrupts(adev, false); 328 329 /* Wait and acknowledge irq */ 330 mdelay(1); 331 } 332 333 /** 334 * vega10_ih_get_wptr - get the IH ring buffer wptr 335 * 336 * @adev: amdgpu_device pointer 337 * @ih: IH ring buffer to fetch wptr 338 * 339 * Get the IH ring buffer wptr from either the register 340 * or the writeback memory buffer (VEGA10). Also check for 341 * ring buffer overflow and deal with it. 342 * Returns the value of the wptr. 343 */ 344 static u32 vega10_ih_get_wptr(struct amdgpu_device *adev, 345 struct amdgpu_ih_ring *ih) 346 { 347 u32 wptr, reg, tmp; 348 349 wptr = le32_to_cpu(*ih->wptr_cpu); 350 351 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 352 goto out; 353 354 /* Double check that the overflow wasn't already cleared. */ 355 356 if (ih == &adev->irq.ih) 357 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 358 else if (ih == &adev->irq.ih1) 359 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 360 else if (ih == &adev->irq.ih2) 361 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 362 else 363 BUG(); 364 365 wptr = RREG32_NO_KIQ(reg); 366 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 367 goto out; 368 369 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 370 371 /* When a ring buffer overflow happen start parsing interrupt 372 * from the last not overwritten vector (wptr + 32). Hopefully 373 * this should allow us to catchup. 374 */ 375 tmp = (wptr + 32) & ih->ptr_mask; 376 dev_warn(adev->dev, "IH ring buffer overflow " 377 "(0x%08X, 0x%08X, 0x%08X)\n", 378 wptr, ih->rptr, tmp); 379 ih->rptr = tmp; 380 381 if (ih == &adev->irq.ih) 382 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 383 else if (ih == &adev->irq.ih1) 384 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 385 else if (ih == &adev->irq.ih2) 386 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 387 else 388 BUG(); 389 390 tmp = RREG32_NO_KIQ(reg); 391 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 392 WREG32_NO_KIQ(reg, tmp); 393 394 out: 395 return (wptr & ih->ptr_mask); 396 } 397 398 /** 399 * vega10_ih_decode_iv - decode an interrupt vector 400 * 401 * @adev: amdgpu_device pointer 402 * @ih: IH ring buffer to decode 403 * @entry: IV entry to place decoded information into 404 * 405 * Decodes the interrupt vector at the current rptr 406 * position and also advance the position. 407 */ 408 static void vega10_ih_decode_iv(struct amdgpu_device *adev, 409 struct amdgpu_ih_ring *ih, 410 struct amdgpu_iv_entry *entry) 411 { 412 /* wptr/rptr are in bytes! */ 413 u32 ring_index = ih->rptr >> 2; 414 uint32_t dw[8]; 415 416 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 417 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 418 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 419 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 420 dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); 421 dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); 422 dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); 423 dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); 424 425 entry->client_id = dw[0] & 0xff; 426 entry->src_id = (dw[0] >> 8) & 0xff; 427 entry->ring_id = (dw[0] >> 16) & 0xff; 428 entry->vmid = (dw[0] >> 24) & 0xf; 429 entry->vmid_src = (dw[0] >> 31); 430 entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); 431 entry->timestamp_src = dw[2] >> 31; 432 entry->pasid = dw[3] & 0xffff; 433 entry->pasid_src = dw[3] >> 31; 434 entry->src_data[0] = dw[4]; 435 entry->src_data[1] = dw[5]; 436 entry->src_data[2] = dw[6]; 437 entry->src_data[3] = dw[7]; 438 439 /* wptr/rptr are in bytes! */ 440 ih->rptr += 32; 441 } 442 443 /** 444 * vega10_ih_irq_rearm - rearm IRQ if lost 445 * 446 * @adev: amdgpu_device pointer 447 * @ih: IH ring to match 448 * 449 */ 450 static void vega10_ih_irq_rearm(struct amdgpu_device *adev, 451 struct amdgpu_ih_ring *ih) 452 { 453 uint32_t reg_rptr = 0; 454 uint32_t v = 0; 455 uint32_t i = 0; 456 457 if (ih == &adev->irq.ih) 458 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 459 else if (ih == &adev->irq.ih1) 460 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 461 else if (ih == &adev->irq.ih2) 462 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 463 else 464 return; 465 466 /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */ 467 for (i = 0; i < MAX_REARM_RETRY; i++) { 468 v = RREG32_NO_KIQ(reg_rptr); 469 if ((v < ih->ring_size) && (v != ih->rptr)) 470 WDOORBELL32(ih->doorbell_index, ih->rptr); 471 else 472 break; 473 } 474 } 475 476 /** 477 * vega10_ih_set_rptr - set the IH ring buffer rptr 478 * 479 * @adev: amdgpu_device pointer 480 * @ih: IH ring buffer to set rptr 481 * 482 * Set the IH ring buffer rptr. 483 */ 484 static void vega10_ih_set_rptr(struct amdgpu_device *adev, 485 struct amdgpu_ih_ring *ih) 486 { 487 if (ih->use_doorbell) { 488 /* XXX check if swapping is necessary on BE */ 489 *ih->rptr_cpu = ih->rptr; 490 WDOORBELL32(ih->doorbell_index, ih->rptr); 491 492 if (amdgpu_sriov_vf(adev)) 493 vega10_ih_irq_rearm(adev, ih); 494 } else if (ih == &adev->irq.ih) { 495 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr); 496 } else if (ih == &adev->irq.ih1) { 497 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, ih->rptr); 498 } else if (ih == &adev->irq.ih2) { 499 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, ih->rptr); 500 } 501 } 502 503 /** 504 * vega10_ih_self_irq - dispatch work for ring 1 and 2 505 * 506 * @adev: amdgpu_device pointer 507 * @source: irq source 508 * @entry: IV with WPTR update 509 * 510 * Update the WPTR from the IV and schedule work to handle the entries. 511 */ 512 static int vega10_ih_self_irq(struct amdgpu_device *adev, 513 struct amdgpu_irq_src *source, 514 struct amdgpu_iv_entry *entry) 515 { 516 uint32_t wptr = cpu_to_le32(entry->src_data[0]); 517 518 switch (entry->ring_id) { 519 case 1: 520 *adev->irq.ih1.wptr_cpu = wptr; 521 schedule_work(&adev->irq.ih1_work); 522 break; 523 case 2: 524 *adev->irq.ih2.wptr_cpu = wptr; 525 schedule_work(&adev->irq.ih2_work); 526 break; 527 default: break; 528 } 529 return 0; 530 } 531 532 static const struct amdgpu_irq_src_funcs vega10_ih_self_irq_funcs = { 533 .process = vega10_ih_self_irq, 534 }; 535 536 static void vega10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 537 { 538 adev->irq.self_irq.num_types = 0; 539 adev->irq.self_irq.funcs = &vega10_ih_self_irq_funcs; 540 } 541 542 static int vega10_ih_early_init(void *handle) 543 { 544 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 545 546 vega10_ih_set_interrupt_funcs(adev); 547 vega10_ih_set_self_irq_funcs(adev); 548 return 0; 549 } 550 551 static int vega10_ih_sw_init(void *handle) 552 { 553 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 554 int r; 555 556 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 557 &adev->irq.self_irq); 558 if (r) 559 return r; 560 561 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true); 562 if (r) 563 return r; 564 565 adev->irq.ih.use_doorbell = true; 566 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 567 568 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 569 if (r) 570 return r; 571 572 adev->irq.ih1.use_doorbell = true; 573 adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; 574 575 r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 576 if (r) 577 return r; 578 579 adev->irq.ih2.use_doorbell = true; 580 adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1; 581 582 /* initialize ih control registers offset */ 583 vega10_ih_init_register_offset(adev); 584 585 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); 586 if (r) 587 return r; 588 589 r = amdgpu_irq_init(adev); 590 591 return r; 592 } 593 594 static int vega10_ih_sw_fini(void *handle) 595 { 596 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 597 598 amdgpu_irq_fini(adev); 599 amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 600 amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 601 amdgpu_ih_ring_fini(adev, &adev->irq.ih); 602 603 return 0; 604 } 605 606 static int vega10_ih_hw_init(void *handle) 607 { 608 int r; 609 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 610 611 r = vega10_ih_irq_init(adev); 612 if (r) 613 return r; 614 615 return 0; 616 } 617 618 static int vega10_ih_hw_fini(void *handle) 619 { 620 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 621 622 vega10_ih_irq_disable(adev); 623 624 return 0; 625 } 626 627 static int vega10_ih_suspend(void *handle) 628 { 629 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 630 631 return vega10_ih_hw_fini(adev); 632 } 633 634 static int vega10_ih_resume(void *handle) 635 { 636 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 637 638 return vega10_ih_hw_init(adev); 639 } 640 641 static bool vega10_ih_is_idle(void *handle) 642 { 643 /* todo */ 644 return true; 645 } 646 647 static int vega10_ih_wait_for_idle(void *handle) 648 { 649 /* todo */ 650 return -ETIMEDOUT; 651 } 652 653 static int vega10_ih_soft_reset(void *handle) 654 { 655 /* todo */ 656 657 return 0; 658 } 659 660 static void vega10_ih_update_clockgating_state(struct amdgpu_device *adev, 661 bool enable) 662 { 663 uint32_t data, def, field_val; 664 665 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 666 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 667 field_val = enable ? 0 : 1; 668 /** 669 * Vega10 does not have IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE 670 * and IH_BUFFER_MEM_CLK_SOFT_OVERRIDE field. 671 */ 672 if (adev->asic_type > CHIP_VEGA10) { 673 data = REG_SET_FIELD(data, IH_CLK_CTRL, 674 IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE, field_val); 675 data = REG_SET_FIELD(data, IH_CLK_CTRL, 676 IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val); 677 } 678 679 data = REG_SET_FIELD(data, IH_CLK_CTRL, 680 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 681 data = REG_SET_FIELD(data, IH_CLK_CTRL, 682 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 683 data = REG_SET_FIELD(data, IH_CLK_CTRL, 684 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 685 data = REG_SET_FIELD(data, IH_CLK_CTRL, 686 DYN_CLK_SOFT_OVERRIDE, field_val); 687 data = REG_SET_FIELD(data, IH_CLK_CTRL, 688 REG_CLK_SOFT_OVERRIDE, field_val); 689 if (def != data) 690 WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 691 } 692 } 693 694 static int vega10_ih_set_clockgating_state(void *handle, 695 enum amd_clockgating_state state) 696 { 697 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 698 699 vega10_ih_update_clockgating_state(adev, 700 state == AMD_CG_STATE_GATE); 701 return 0; 702 703 } 704 705 static int vega10_ih_set_powergating_state(void *handle, 706 enum amd_powergating_state state) 707 { 708 return 0; 709 } 710 711 const struct amd_ip_funcs vega10_ih_ip_funcs = { 712 .name = "vega10_ih", 713 .early_init = vega10_ih_early_init, 714 .late_init = NULL, 715 .sw_init = vega10_ih_sw_init, 716 .sw_fini = vega10_ih_sw_fini, 717 .hw_init = vega10_ih_hw_init, 718 .hw_fini = vega10_ih_hw_fini, 719 .suspend = vega10_ih_suspend, 720 .resume = vega10_ih_resume, 721 .is_idle = vega10_ih_is_idle, 722 .wait_for_idle = vega10_ih_wait_for_idle, 723 .soft_reset = vega10_ih_soft_reset, 724 .set_clockgating_state = vega10_ih_set_clockgating_state, 725 .set_powergating_state = vega10_ih_set_powergating_state, 726 }; 727 728 static const struct amdgpu_ih_funcs vega10_ih_funcs = { 729 .get_wptr = vega10_ih_get_wptr, 730 .decode_iv = vega10_ih_decode_iv, 731 .set_rptr = vega10_ih_set_rptr 732 }; 733 734 static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 735 { 736 adev->irq.ih_funcs = &vega10_ih_funcs; 737 } 738 739 const struct amdgpu_ip_block_version vega10_ih_ip_block = 740 { 741 .type = AMD_IP_BLOCK_TYPE_IH, 742 .major = 4, 743 .minor = 0, 744 .rev = 0, 745 .funcs = &vega10_ih_ip_funcs, 746 }; 747