1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 #include "soc15.h" 29 30 #include "oss/osssys_4_0_offset.h" 31 #include "oss/osssys_4_0_sh_mask.h" 32 33 #include "soc15_common.h" 34 #include "vega10_ih.h" 35 36 #define MAX_REARM_RETRY 10 37 38 static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 39 40 /** 41 * vega10_ih_init_register_offset - Initialize register offset for ih rings 42 * 43 * @adev: amdgpu_device pointer 44 * 45 * Initialize register offset ih rings (VEGA10). 46 */ 47 static void vega10_ih_init_register_offset(struct amdgpu_device *adev) 48 { 49 struct amdgpu_ih_regs *ih_regs; 50 51 if (adev->irq.ih.ring_size) { 52 ih_regs = &adev->irq.ih.ih_regs; 53 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); 54 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); 55 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 56 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 57 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 58 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); 59 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); 60 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); 61 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; 62 } 63 64 if (adev->irq.ih1.ring_size) { 65 ih_regs = &adev->irq.ih1.ih_regs; 66 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); 67 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); 68 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 69 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 70 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 71 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1); 72 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; 73 } 74 75 if (adev->irq.ih2.ring_size) { 76 ih_regs = &adev->irq.ih2.ih_regs; 77 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); 78 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2); 79 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 80 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 81 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 82 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2); 83 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2; 84 } 85 } 86 87 /** 88 * vega10_ih_enable_interrupts - Enable the interrupt ring buffer 89 * 90 * @adev: amdgpu_device pointer 91 * 92 * Enable the interrupt ring buffer (VEGA10). 93 */ 94 static void vega10_ih_enable_interrupts(struct amdgpu_device *adev) 95 { 96 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 97 98 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); 99 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); 100 if (amdgpu_sriov_vf(adev)) { 101 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 102 DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 103 return; 104 } 105 } else { 106 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 107 } 108 adev->irq.ih.enabled = true; 109 110 if (adev->irq.ih1.ring_size) { 111 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 112 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 113 RB_ENABLE, 1); 114 if (amdgpu_sriov_vf(adev)) { 115 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 116 ih_rb_cntl)) { 117 DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 118 return; 119 } 120 } else { 121 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 122 } 123 adev->irq.ih1.enabled = true; 124 } 125 126 if (adev->irq.ih2.ring_size) { 127 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 128 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 129 RB_ENABLE, 1); 130 if (amdgpu_sriov_vf(adev)) { 131 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 132 ih_rb_cntl)) { 133 DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 134 return; 135 } 136 } else { 137 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 138 } 139 adev->irq.ih2.enabled = true; 140 } 141 142 if (adev->irq.ih_soft.ring_size) 143 adev->irq.ih_soft.enabled = true; 144 } 145 146 /** 147 * vega10_ih_disable_interrupts - Disable the interrupt ring buffer 148 * 149 * @adev: amdgpu_device pointer 150 * 151 * Disable the interrupt ring buffer (VEGA10). 152 */ 153 static void vega10_ih_disable_interrupts(struct amdgpu_device *adev) 154 { 155 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 156 157 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); 158 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); 159 if (amdgpu_sriov_vf(adev)) { 160 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 161 DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 162 return; 163 } 164 } else { 165 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 166 } 167 168 /* set rptr, wptr to 0 */ 169 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 170 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 171 adev->irq.ih.enabled = false; 172 adev->irq.ih.rptr = 0; 173 174 if (adev->irq.ih1.ring_size) { 175 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 176 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 177 RB_ENABLE, 0); 178 if (amdgpu_sriov_vf(adev)) { 179 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 180 ih_rb_cntl)) { 181 DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 182 return; 183 } 184 } else { 185 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 186 } 187 /* set rptr, wptr to 0 */ 188 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 189 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 190 adev->irq.ih1.enabled = false; 191 adev->irq.ih1.rptr = 0; 192 } 193 194 if (adev->irq.ih2.ring_size) { 195 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 196 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 197 RB_ENABLE, 0); 198 if (amdgpu_sriov_vf(adev)) { 199 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 200 ih_rb_cntl)) { 201 DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 202 return; 203 } 204 } else { 205 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 206 } 207 208 /* set rptr, wptr to 0 */ 209 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 210 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 211 adev->irq.ih2.enabled = false; 212 adev->irq.ih2.rptr = 0; 213 } 214 } 215 216 static uint32_t vega10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 217 { 218 int rb_bufsz = order_base_2(ih->ring_size / 4); 219 220 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 221 MC_SPACE, ih->use_bus_addr ? 1 : 4); 222 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 223 WPTR_OVERFLOW_CLEAR, 1); 224 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 225 WPTR_OVERFLOW_ENABLE, 1); 226 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 227 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 228 * value is written to memory 229 */ 230 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 231 WPTR_WRITEBACK_ENABLE, 1); 232 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 233 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 234 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 235 236 return ih_rb_cntl; 237 } 238 239 static uint32_t vega10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 240 { 241 u32 ih_doorbell_rtpr = 0; 242 243 if (ih->use_doorbell) { 244 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 245 IH_DOORBELL_RPTR, OFFSET, 246 ih->doorbell_index); 247 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 248 IH_DOORBELL_RPTR, 249 ENABLE, 1); 250 } else { 251 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 252 IH_DOORBELL_RPTR, 253 ENABLE, 0); 254 } 255 return ih_doorbell_rtpr; 256 } 257 258 /** 259 * vega10_ih_irq_init - init and enable the interrupt ring 260 * 261 * @adev: amdgpu_device pointer 262 * 263 * Allocate a ring buffer for the interrupt controller, 264 * enable the RLC, disable interrupts, enable the IH 265 * ring buffer and enable it (VI). 266 * Called at device load and reume. 267 * Returns 0 for success, errors for failure. 268 */ 269 static int vega10_ih_irq_init(struct amdgpu_device *adev) 270 { 271 struct amdgpu_ih_ring *ih; 272 u32 ih_rb_cntl, ih_chicken; 273 int ret = 0; 274 u32 tmp; 275 276 /* disable irqs */ 277 vega10_ih_disable_interrupts(adev); 278 279 adev->nbio.funcs->ih_control(adev); 280 281 ih = &adev->irq.ih; 282 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 283 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8); 284 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff); 285 286 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 287 ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl); 288 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 289 !!adev->irq.msi_enabled); 290 if (amdgpu_sriov_vf(adev)) { 291 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 292 DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 293 return -ETIMEDOUT; 294 } 295 } else { 296 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 297 } 298 299 if ((adev->asic_type == CHIP_ARCTURUS && 300 adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) || 301 adev->asic_type == CHIP_RENOIR) { 302 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 303 if (adev->irq.ih.use_bus_addr) { 304 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 305 MC_SPACE_GPA_ENABLE, 1); 306 } else { 307 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 308 MC_SPACE_FBPA_ENABLE, 1); 309 } 310 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 311 } 312 313 /* set the writeback address whether it's enabled or not */ 314 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, 315 lower_32_bits(ih->wptr_addr)); 316 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, 317 upper_32_bits(ih->wptr_addr) & 0xFFFF); 318 319 /* set rptr, wptr to 0 */ 320 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 321 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 322 323 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, 324 vega10_ih_doorbell_rptr(ih)); 325 326 ih = &adev->irq.ih1; 327 if (ih->ring_size) { 328 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING1, ih->gpu_addr >> 8); 329 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING1, 330 (ih->gpu_addr >> 40) & 0xff); 331 332 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 333 ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl); 334 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 335 WPTR_OVERFLOW_ENABLE, 0); 336 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 337 RB_FULL_DRAIN_ENABLE, 1); 338 if (amdgpu_sriov_vf(adev)) { 339 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 340 ih_rb_cntl)) { 341 DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 342 return -ETIMEDOUT; 343 } 344 } else { 345 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 346 } 347 348 /* set rptr, wptr to 0 */ 349 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 350 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 351 352 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1, 353 vega10_ih_doorbell_rptr(ih)); 354 } 355 356 ih = &adev->irq.ih2; 357 if (ih->ring_size) { 358 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING2, ih->gpu_addr >> 8); 359 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING2, 360 (ih->gpu_addr >> 40) & 0xff); 361 362 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 363 ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl); 364 365 if (amdgpu_sriov_vf(adev)) { 366 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 367 ih_rb_cntl)) { 368 DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 369 return -ETIMEDOUT; 370 } 371 } else { 372 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 373 } 374 375 /* set rptr, wptr to 0 */ 376 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 377 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 378 379 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2, 380 vega10_ih_doorbell_rptr(ih)); 381 } 382 383 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 384 tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 385 CLIENT18_IS_STORM_CLIENT, 1); 386 WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 387 388 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 389 tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 390 WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 391 392 pci_set_master(adev->pdev); 393 394 /* enable interrupts */ 395 vega10_ih_enable_interrupts(adev); 396 397 return ret; 398 } 399 400 /** 401 * vega10_ih_irq_disable - disable interrupts 402 * 403 * @adev: amdgpu_device pointer 404 * 405 * Disable interrupts on the hw (VEGA10). 406 */ 407 static void vega10_ih_irq_disable(struct amdgpu_device *adev) 408 { 409 vega10_ih_disable_interrupts(adev); 410 411 /* Wait and acknowledge irq */ 412 mdelay(1); 413 } 414 415 /** 416 * vega10_ih_get_wptr - get the IH ring buffer wptr 417 * 418 * @adev: amdgpu_device pointer 419 * @ih: IH ring buffer to fetch wptr 420 * 421 * Get the IH ring buffer wptr from either the register 422 * or the writeback memory buffer (VEGA10). Also check for 423 * ring buffer overflow and deal with it. 424 * Returns the value of the wptr. 425 */ 426 static u32 vega10_ih_get_wptr(struct amdgpu_device *adev, 427 struct amdgpu_ih_ring *ih) 428 { 429 u32 wptr, reg, tmp; 430 431 wptr = le32_to_cpu(*ih->wptr_cpu); 432 433 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 434 goto out; 435 436 /* Double check that the overflow wasn't already cleared. */ 437 438 if (ih == &adev->irq.ih) 439 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 440 else if (ih == &adev->irq.ih1) 441 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 442 else if (ih == &adev->irq.ih2) 443 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 444 else 445 BUG(); 446 447 wptr = RREG32_NO_KIQ(reg); 448 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 449 goto out; 450 451 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 452 453 /* When a ring buffer overflow happen start parsing interrupt 454 * from the last not overwritten vector (wptr + 32). Hopefully 455 * this should allow us to catchup. 456 */ 457 tmp = (wptr + 32) & ih->ptr_mask; 458 dev_warn(adev->dev, "IH ring buffer overflow " 459 "(0x%08X, 0x%08X, 0x%08X)\n", 460 wptr, ih->rptr, tmp); 461 ih->rptr = tmp; 462 463 if (ih == &adev->irq.ih) 464 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 465 else if (ih == &adev->irq.ih1) 466 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 467 else if (ih == &adev->irq.ih2) 468 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 469 else 470 BUG(); 471 472 tmp = RREG32_NO_KIQ(reg); 473 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 474 WREG32_NO_KIQ(reg, tmp); 475 476 out: 477 return (wptr & ih->ptr_mask); 478 } 479 480 /** 481 * vega10_ih_decode_iv - decode an interrupt vector 482 * 483 * @adev: amdgpu_device pointer 484 * @ih: IH ring buffer to decode 485 * @entry: IV entry to place decoded information into 486 * 487 * Decodes the interrupt vector at the current rptr 488 * position and also advance the position. 489 */ 490 static void vega10_ih_decode_iv(struct amdgpu_device *adev, 491 struct amdgpu_ih_ring *ih, 492 struct amdgpu_iv_entry *entry) 493 { 494 /* wptr/rptr are in bytes! */ 495 u32 ring_index = ih->rptr >> 2; 496 uint32_t dw[8]; 497 498 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 499 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 500 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 501 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 502 dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); 503 dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); 504 dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); 505 dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); 506 507 entry->client_id = dw[0] & 0xff; 508 entry->src_id = (dw[0] >> 8) & 0xff; 509 entry->ring_id = (dw[0] >> 16) & 0xff; 510 entry->vmid = (dw[0] >> 24) & 0xf; 511 entry->vmid_src = (dw[0] >> 31); 512 entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); 513 entry->timestamp_src = dw[2] >> 31; 514 entry->pasid = dw[3] & 0xffff; 515 entry->pasid_src = dw[3] >> 31; 516 entry->src_data[0] = dw[4]; 517 entry->src_data[1] = dw[5]; 518 entry->src_data[2] = dw[6]; 519 entry->src_data[3] = dw[7]; 520 521 /* wptr/rptr are in bytes! */ 522 ih->rptr += 32; 523 } 524 525 /** 526 * vega10_ih_irq_rearm - rearm IRQ if lost 527 * 528 * @adev: amdgpu_device pointer 529 * @ih: IH ring to match 530 * 531 */ 532 static void vega10_ih_irq_rearm(struct amdgpu_device *adev, 533 struct amdgpu_ih_ring *ih) 534 { 535 uint32_t reg_rptr = 0; 536 uint32_t v = 0; 537 uint32_t i = 0; 538 539 if (ih == &adev->irq.ih) 540 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 541 else if (ih == &adev->irq.ih1) 542 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 543 else if (ih == &adev->irq.ih2) 544 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 545 else 546 return; 547 548 /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */ 549 for (i = 0; i < MAX_REARM_RETRY; i++) { 550 v = RREG32_NO_KIQ(reg_rptr); 551 if ((v < ih->ring_size) && (v != ih->rptr)) 552 WDOORBELL32(ih->doorbell_index, ih->rptr); 553 else 554 break; 555 } 556 } 557 558 /** 559 * vega10_ih_set_rptr - set the IH ring buffer rptr 560 * 561 * @adev: amdgpu_device pointer 562 * @ih: IH ring buffer to set rptr 563 * 564 * Set the IH ring buffer rptr. 565 */ 566 static void vega10_ih_set_rptr(struct amdgpu_device *adev, 567 struct amdgpu_ih_ring *ih) 568 { 569 if (ih->use_doorbell) { 570 /* XXX check if swapping is necessary on BE */ 571 *ih->rptr_cpu = ih->rptr; 572 WDOORBELL32(ih->doorbell_index, ih->rptr); 573 574 if (amdgpu_sriov_vf(adev)) 575 vega10_ih_irq_rearm(adev, ih); 576 } else if (ih == &adev->irq.ih) { 577 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr); 578 } else if (ih == &adev->irq.ih1) { 579 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, ih->rptr); 580 } else if (ih == &adev->irq.ih2) { 581 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, ih->rptr); 582 } 583 } 584 585 /** 586 * vega10_ih_self_irq - dispatch work for ring 1 and 2 587 * 588 * @adev: amdgpu_device pointer 589 * @source: irq source 590 * @entry: IV with WPTR update 591 * 592 * Update the WPTR from the IV and schedule work to handle the entries. 593 */ 594 static int vega10_ih_self_irq(struct amdgpu_device *adev, 595 struct amdgpu_irq_src *source, 596 struct amdgpu_iv_entry *entry) 597 { 598 uint32_t wptr = cpu_to_le32(entry->src_data[0]); 599 600 switch (entry->ring_id) { 601 case 1: 602 *adev->irq.ih1.wptr_cpu = wptr; 603 schedule_work(&adev->irq.ih1_work); 604 break; 605 case 2: 606 *adev->irq.ih2.wptr_cpu = wptr; 607 schedule_work(&adev->irq.ih2_work); 608 break; 609 default: break; 610 } 611 return 0; 612 } 613 614 static const struct amdgpu_irq_src_funcs vega10_ih_self_irq_funcs = { 615 .process = vega10_ih_self_irq, 616 }; 617 618 static void vega10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 619 { 620 adev->irq.self_irq.num_types = 0; 621 adev->irq.self_irq.funcs = &vega10_ih_self_irq_funcs; 622 } 623 624 static int vega10_ih_early_init(void *handle) 625 { 626 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 627 628 vega10_ih_set_interrupt_funcs(adev); 629 vega10_ih_set_self_irq_funcs(adev); 630 return 0; 631 } 632 633 static int vega10_ih_sw_init(void *handle) 634 { 635 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 636 int r; 637 638 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 639 &adev->irq.self_irq); 640 if (r) 641 return r; 642 643 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true); 644 if (r) 645 return r; 646 647 adev->irq.ih.use_doorbell = true; 648 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 649 650 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 651 if (r) 652 return r; 653 654 adev->irq.ih1.use_doorbell = true; 655 adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; 656 657 r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 658 if (r) 659 return r; 660 661 adev->irq.ih2.use_doorbell = true; 662 adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1; 663 664 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); 665 if (r) 666 return r; 667 668 r = amdgpu_irq_init(adev); 669 670 return r; 671 } 672 673 static int vega10_ih_sw_fini(void *handle) 674 { 675 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 676 677 amdgpu_irq_fini(adev); 678 amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 679 amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 680 amdgpu_ih_ring_fini(adev, &adev->irq.ih); 681 682 return 0; 683 } 684 685 static int vega10_ih_hw_init(void *handle) 686 { 687 int r; 688 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 689 690 r = vega10_ih_irq_init(adev); 691 if (r) 692 return r; 693 694 return 0; 695 } 696 697 static int vega10_ih_hw_fini(void *handle) 698 { 699 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 700 701 vega10_ih_irq_disable(adev); 702 703 return 0; 704 } 705 706 static int vega10_ih_suspend(void *handle) 707 { 708 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 709 710 return vega10_ih_hw_fini(adev); 711 } 712 713 static int vega10_ih_resume(void *handle) 714 { 715 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 716 717 return vega10_ih_hw_init(adev); 718 } 719 720 static bool vega10_ih_is_idle(void *handle) 721 { 722 /* todo */ 723 return true; 724 } 725 726 static int vega10_ih_wait_for_idle(void *handle) 727 { 728 /* todo */ 729 return -ETIMEDOUT; 730 } 731 732 static int vega10_ih_soft_reset(void *handle) 733 { 734 /* todo */ 735 736 return 0; 737 } 738 739 static void vega10_ih_update_clockgating_state(struct amdgpu_device *adev, 740 bool enable) 741 { 742 uint32_t data, def, field_val; 743 744 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 745 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 746 field_val = enable ? 0 : 1; 747 /** 748 * Vega10 does not have IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE 749 * and IH_BUFFER_MEM_CLK_SOFT_OVERRIDE field. 750 */ 751 if (adev->asic_type > CHIP_VEGA10) { 752 data = REG_SET_FIELD(data, IH_CLK_CTRL, 753 IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE, field_val); 754 data = REG_SET_FIELD(data, IH_CLK_CTRL, 755 IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val); 756 } 757 758 data = REG_SET_FIELD(data, IH_CLK_CTRL, 759 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 760 data = REG_SET_FIELD(data, IH_CLK_CTRL, 761 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 762 data = REG_SET_FIELD(data, IH_CLK_CTRL, 763 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 764 data = REG_SET_FIELD(data, IH_CLK_CTRL, 765 DYN_CLK_SOFT_OVERRIDE, field_val); 766 data = REG_SET_FIELD(data, IH_CLK_CTRL, 767 REG_CLK_SOFT_OVERRIDE, field_val); 768 if (def != data) 769 WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 770 } 771 } 772 773 static int vega10_ih_set_clockgating_state(void *handle, 774 enum amd_clockgating_state state) 775 { 776 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 777 778 vega10_ih_update_clockgating_state(adev, 779 state == AMD_CG_STATE_GATE); 780 return 0; 781 782 } 783 784 static int vega10_ih_set_powergating_state(void *handle, 785 enum amd_powergating_state state) 786 { 787 return 0; 788 } 789 790 const struct amd_ip_funcs vega10_ih_ip_funcs = { 791 .name = "vega10_ih", 792 .early_init = vega10_ih_early_init, 793 .late_init = NULL, 794 .sw_init = vega10_ih_sw_init, 795 .sw_fini = vega10_ih_sw_fini, 796 .hw_init = vega10_ih_hw_init, 797 .hw_fini = vega10_ih_hw_fini, 798 .suspend = vega10_ih_suspend, 799 .resume = vega10_ih_resume, 800 .is_idle = vega10_ih_is_idle, 801 .wait_for_idle = vega10_ih_wait_for_idle, 802 .soft_reset = vega10_ih_soft_reset, 803 .set_clockgating_state = vega10_ih_set_clockgating_state, 804 .set_powergating_state = vega10_ih_set_powergating_state, 805 }; 806 807 static const struct amdgpu_ih_funcs vega10_ih_funcs = { 808 .get_wptr = vega10_ih_get_wptr, 809 .decode_iv = vega10_ih_decode_iv, 810 .set_rptr = vega10_ih_set_rptr 811 }; 812 813 static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 814 { 815 adev->irq.ih_funcs = &vega10_ih_funcs; 816 } 817 818 const struct amdgpu_ip_block_version vega10_ih_ip_block = 819 { 820 .type = AMD_IP_BLOCK_TYPE_IH, 821 .major = 4, 822 .minor = 0, 823 .rev = 0, 824 .funcs = &vega10_ih_ip_funcs, 825 }; 826