1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 #include "soc15.h" 29 30 #include "oss/osssys_4_0_offset.h" 31 #include "oss/osssys_4_0_sh_mask.h" 32 33 #include "soc15_common.h" 34 #include "vega10_ih.h" 35 36 #define MAX_REARM_RETRY 10 37 38 static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 39 40 /** 41 * vega10_ih_init_register_offset - Initialize register offset for ih rings 42 * 43 * @adev: amdgpu_device pointer 44 * 45 * Initialize register offset ih rings (VEGA10). 46 */ 47 static void vega10_ih_init_register_offset(struct amdgpu_device *adev) 48 { 49 struct amdgpu_ih_regs *ih_regs; 50 51 if (adev->irq.ih.ring_size) { 52 ih_regs = &adev->irq.ih.ih_regs; 53 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); 54 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); 55 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 56 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 57 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 58 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); 59 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); 60 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); 61 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; 62 } 63 64 if (adev->irq.ih1.ring_size) { 65 ih_regs = &adev->irq.ih1.ih_regs; 66 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); 67 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); 68 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 69 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 70 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 71 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1); 72 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; 73 } 74 75 if (adev->irq.ih2.ring_size) { 76 ih_regs = &adev->irq.ih2.ih_regs; 77 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); 78 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2); 79 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 80 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 81 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 82 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2); 83 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2; 84 } 85 } 86 87 /** 88 * vega10_ih_toggle_ring_interrupts - toggle the interrupt ring buffer 89 * 90 * @adev: amdgpu_device pointer 91 * @ih: amdgpu_ih_ring pointet 92 * @enable: true - enable the interrupts, false - disable the interrupts 93 * 94 * Toggle the interrupt ring buffer (VEGA10) 95 */ 96 static int vega10_ih_toggle_ring_interrupts(struct amdgpu_device *adev, 97 struct amdgpu_ih_ring *ih, 98 bool enable) 99 { 100 struct amdgpu_ih_regs *ih_regs; 101 uint32_t tmp; 102 103 ih_regs = &ih->ih_regs; 104 105 tmp = RREG32(ih_regs->ih_rb_cntl); 106 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); 107 /* enable_intr field is only valid in ring0 */ 108 if (ih == &adev->irq.ih) 109 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); 110 if (amdgpu_sriov_vf(adev)) { 111 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 112 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 113 return -ETIMEDOUT; 114 } 115 } else { 116 WREG32(ih_regs->ih_rb_cntl, tmp); 117 } 118 119 if (enable) { 120 ih->enabled = true; 121 } else { 122 /* set rptr, wptr to 0 */ 123 WREG32(ih_regs->ih_rb_rptr, 0); 124 WREG32(ih_regs->ih_rb_wptr, 0); 125 ih->enabled = false; 126 ih->rptr = 0; 127 } 128 129 return 0; 130 } 131 132 /** 133 * vega10_ih_toggle_interrupts - Toggle all the available interrupt ring buffers 134 * 135 * @adev: amdgpu_device pointer 136 * @enable: enable or disable interrupt ring buffers 137 * 138 * Toggle all the available interrupt ring buffers (VEGA10). 139 */ 140 static int vega10_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable) 141 { 142 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 143 int i; 144 int r; 145 146 for (i = 0; i < ARRAY_SIZE(ih); i++) { 147 if (ih[i]->ring_size) { 148 r = vega10_ih_toggle_ring_interrupts(adev, ih[i], enable); 149 if (r) 150 return r; 151 } 152 } 153 154 return 0; 155 } 156 157 static uint32_t vega10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 158 { 159 int rb_bufsz = order_base_2(ih->ring_size / 4); 160 161 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 162 MC_SPACE, ih->use_bus_addr ? 1 : 4); 163 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 164 WPTR_OVERFLOW_CLEAR, 1); 165 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 166 WPTR_OVERFLOW_ENABLE, 1); 167 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 168 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 169 * value is written to memory 170 */ 171 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 172 WPTR_WRITEBACK_ENABLE, 1); 173 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 174 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 175 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 176 177 return ih_rb_cntl; 178 } 179 180 static uint32_t vega10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 181 { 182 u32 ih_doorbell_rtpr = 0; 183 184 if (ih->use_doorbell) { 185 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 186 IH_DOORBELL_RPTR, OFFSET, 187 ih->doorbell_index); 188 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 189 IH_DOORBELL_RPTR, 190 ENABLE, 1); 191 } else { 192 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 193 IH_DOORBELL_RPTR, 194 ENABLE, 0); 195 } 196 return ih_doorbell_rtpr; 197 } 198 199 /** 200 * vega10_ih_enable_ring - enable an ih ring buffer 201 * 202 * @adev: amdgpu_device pointer 203 * @ih: amdgpu_ih_ring pointer 204 * 205 * Enable an ih ring buffer (VEGA10) 206 */ 207 static int vega10_ih_enable_ring(struct amdgpu_device *adev, 208 struct amdgpu_ih_ring *ih) 209 { 210 struct amdgpu_ih_regs *ih_regs; 211 uint32_t tmp; 212 213 ih_regs = &ih->ih_regs; 214 215 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 216 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); 217 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); 218 219 tmp = RREG32(ih_regs->ih_rb_cntl); 220 tmp = vega10_ih_rb_cntl(ih, tmp); 221 if (ih == &adev->irq.ih) 222 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); 223 if (ih == &adev->irq.ih1) { 224 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0); 225 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); 226 } 227 if (amdgpu_sriov_vf(adev)) { 228 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 229 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 230 return -ETIMEDOUT; 231 } 232 } else { 233 WREG32(ih_regs->ih_rb_cntl, tmp); 234 } 235 236 if (ih == &adev->irq.ih) { 237 /* set the ih ring 0 writeback address whether it's enabled or not */ 238 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); 239 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); 240 } 241 242 /* set rptr, wptr to 0 */ 243 WREG32(ih_regs->ih_rb_wptr, 0); 244 WREG32(ih_regs->ih_rb_rptr, 0); 245 246 WREG32(ih_regs->ih_doorbell_rptr, vega10_ih_doorbell_rptr(ih)); 247 248 return 0; 249 } 250 251 /** 252 * vega10_ih_irq_init - init and enable the interrupt ring 253 * 254 * @adev: amdgpu_device pointer 255 * 256 * Allocate a ring buffer for the interrupt controller, 257 * enable the RLC, disable interrupts, enable the IH 258 * ring buffer and enable it (VI). 259 * Called at device load and reume. 260 * Returns 0 for success, errors for failure. 261 */ 262 static int vega10_ih_irq_init(struct amdgpu_device *adev) 263 { 264 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 265 u32 ih_chicken; 266 int ret; 267 int i; 268 u32 tmp; 269 270 /* disable irqs */ 271 ret = vega10_ih_toggle_interrupts(adev, false); 272 if (ret) 273 return ret; 274 275 adev->nbio.funcs->ih_control(adev); 276 277 if ((adev->asic_type == CHIP_ARCTURUS && 278 adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) || 279 adev->asic_type == CHIP_RENOIR) { 280 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 281 if (adev->irq.ih.use_bus_addr) { 282 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 283 MC_SPACE_GPA_ENABLE, 1); 284 } 285 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 286 } 287 288 for (i = 0; i < ARRAY_SIZE(ih); i++) { 289 if (ih[i]->ring_size) { 290 ret = vega10_ih_enable_ring(adev, ih[i]); 291 if (ret) 292 return ret; 293 } 294 } 295 296 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 297 tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 298 CLIENT18_IS_STORM_CLIENT, 1); 299 WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 300 301 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 302 tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 303 WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 304 305 pci_set_master(adev->pdev); 306 307 /* enable interrupts */ 308 ret = vega10_ih_toggle_interrupts(adev, true); 309 if (ret) 310 return ret; 311 312 return 0; 313 } 314 315 /** 316 * vega10_ih_irq_disable - disable interrupts 317 * 318 * @adev: amdgpu_device pointer 319 * 320 * Disable interrupts on the hw (VEGA10). 321 */ 322 static void vega10_ih_irq_disable(struct amdgpu_device *adev) 323 { 324 vega10_ih_toggle_interrupts(adev, false); 325 326 /* Wait and acknowledge irq */ 327 mdelay(1); 328 } 329 330 /** 331 * vega10_ih_get_wptr - get the IH ring buffer wptr 332 * 333 * @adev: amdgpu_device pointer 334 * @ih: IH ring buffer to fetch wptr 335 * 336 * Get the IH ring buffer wptr from either the register 337 * or the writeback memory buffer (VEGA10). Also check for 338 * ring buffer overflow and deal with it. 339 * Returns the value of the wptr. 340 */ 341 static u32 vega10_ih_get_wptr(struct amdgpu_device *adev, 342 struct amdgpu_ih_ring *ih) 343 { 344 u32 wptr, tmp; 345 struct amdgpu_ih_regs *ih_regs; 346 347 wptr = le32_to_cpu(*ih->wptr_cpu); 348 ih_regs = &ih->ih_regs; 349 350 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 351 goto out; 352 353 /* Double check that the overflow wasn't already cleared. */ 354 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); 355 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 356 goto out; 357 358 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 359 360 /* When a ring buffer overflow happen start parsing interrupt 361 * from the last not overwritten vector (wptr + 32). Hopefully 362 * this should allow us to catchup. 363 */ 364 tmp = (wptr + 32) & ih->ptr_mask; 365 dev_warn(adev->dev, "IH ring buffer overflow " 366 "(0x%08X, 0x%08X, 0x%08X)\n", 367 wptr, ih->rptr, tmp); 368 ih->rptr = tmp; 369 370 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); 371 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 372 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 373 374 out: 375 return (wptr & ih->ptr_mask); 376 } 377 378 /** 379 * vega10_ih_irq_rearm - rearm IRQ if lost 380 * 381 * @adev: amdgpu_device pointer 382 * @ih: IH ring to match 383 * 384 */ 385 static void vega10_ih_irq_rearm(struct amdgpu_device *adev, 386 struct amdgpu_ih_ring *ih) 387 { 388 uint32_t v = 0; 389 uint32_t i = 0; 390 struct amdgpu_ih_regs *ih_regs; 391 392 ih_regs = &ih->ih_regs; 393 /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */ 394 for (i = 0; i < MAX_REARM_RETRY; i++) { 395 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); 396 if ((v < ih->ring_size) && (v != ih->rptr)) 397 WDOORBELL32(ih->doorbell_index, ih->rptr); 398 else 399 break; 400 } 401 } 402 403 /** 404 * vega10_ih_set_rptr - set the IH ring buffer rptr 405 * 406 * @adev: amdgpu_device pointer 407 * @ih: IH ring buffer to set rptr 408 * 409 * Set the IH ring buffer rptr. 410 */ 411 static void vega10_ih_set_rptr(struct amdgpu_device *adev, 412 struct amdgpu_ih_ring *ih) 413 { 414 struct amdgpu_ih_regs *ih_regs; 415 416 if (ih->use_doorbell) { 417 /* XXX check if swapping is necessary on BE */ 418 *ih->rptr_cpu = ih->rptr; 419 WDOORBELL32(ih->doorbell_index, ih->rptr); 420 421 if (amdgpu_sriov_vf(adev)) 422 vega10_ih_irq_rearm(adev, ih); 423 } else { 424 ih_regs = &ih->ih_regs; 425 WREG32(ih_regs->ih_rb_rptr, ih->rptr); 426 } 427 } 428 429 /** 430 * vega10_ih_self_irq - dispatch work for ring 1 and 2 431 * 432 * @adev: amdgpu_device pointer 433 * @source: irq source 434 * @entry: IV with WPTR update 435 * 436 * Update the WPTR from the IV and schedule work to handle the entries. 437 */ 438 static int vega10_ih_self_irq(struct amdgpu_device *adev, 439 struct amdgpu_irq_src *source, 440 struct amdgpu_iv_entry *entry) 441 { 442 uint32_t wptr = cpu_to_le32(entry->src_data[0]); 443 444 switch (entry->ring_id) { 445 case 1: 446 *adev->irq.ih1.wptr_cpu = wptr; 447 schedule_work(&adev->irq.ih1_work); 448 break; 449 case 2: 450 *adev->irq.ih2.wptr_cpu = wptr; 451 schedule_work(&adev->irq.ih2_work); 452 break; 453 default: break; 454 } 455 return 0; 456 } 457 458 static const struct amdgpu_irq_src_funcs vega10_ih_self_irq_funcs = { 459 .process = vega10_ih_self_irq, 460 }; 461 462 static void vega10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 463 { 464 adev->irq.self_irq.num_types = 0; 465 adev->irq.self_irq.funcs = &vega10_ih_self_irq_funcs; 466 } 467 468 static int vega10_ih_early_init(void *handle) 469 { 470 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 471 472 vega10_ih_set_interrupt_funcs(adev); 473 vega10_ih_set_self_irq_funcs(adev); 474 return 0; 475 } 476 477 static int vega10_ih_sw_init(void *handle) 478 { 479 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 480 int r; 481 482 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 483 &adev->irq.self_irq); 484 if (r) 485 return r; 486 487 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true); 488 if (r) 489 return r; 490 491 adev->irq.ih.use_doorbell = true; 492 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 493 494 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 495 if (r) 496 return r; 497 498 adev->irq.ih1.use_doorbell = true; 499 adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; 500 501 r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 502 if (r) 503 return r; 504 505 adev->irq.ih2.use_doorbell = true; 506 adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1; 507 508 /* initialize ih control registers offset */ 509 vega10_ih_init_register_offset(adev); 510 511 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); 512 if (r) 513 return r; 514 515 r = amdgpu_irq_init(adev); 516 517 return r; 518 } 519 520 static int vega10_ih_sw_fini(void *handle) 521 { 522 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 523 524 amdgpu_irq_fini(adev); 525 amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 526 amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 527 amdgpu_ih_ring_fini(adev, &adev->irq.ih); 528 529 return 0; 530 } 531 532 static int vega10_ih_hw_init(void *handle) 533 { 534 int r; 535 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 536 537 r = vega10_ih_irq_init(adev); 538 if (r) 539 return r; 540 541 return 0; 542 } 543 544 static int vega10_ih_hw_fini(void *handle) 545 { 546 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 547 548 vega10_ih_irq_disable(adev); 549 550 return 0; 551 } 552 553 static int vega10_ih_suspend(void *handle) 554 { 555 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 556 557 return vega10_ih_hw_fini(adev); 558 } 559 560 static int vega10_ih_resume(void *handle) 561 { 562 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 563 564 return vega10_ih_hw_init(adev); 565 } 566 567 static bool vega10_ih_is_idle(void *handle) 568 { 569 /* todo */ 570 return true; 571 } 572 573 static int vega10_ih_wait_for_idle(void *handle) 574 { 575 /* todo */ 576 return -ETIMEDOUT; 577 } 578 579 static int vega10_ih_soft_reset(void *handle) 580 { 581 /* todo */ 582 583 return 0; 584 } 585 586 static void vega10_ih_update_clockgating_state(struct amdgpu_device *adev, 587 bool enable) 588 { 589 uint32_t data, def, field_val; 590 591 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 592 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 593 field_val = enable ? 0 : 1; 594 /** 595 * Vega10/12 and RAVEN don't have IH_BUFFER_MEM_CLK_SOFT_OVERRIDE field. 596 */ 597 if (adev->asic_type == CHIP_RENOIR) 598 data = REG_SET_FIELD(data, IH_CLK_CTRL, 599 IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val); 600 601 data = REG_SET_FIELD(data, IH_CLK_CTRL, 602 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 603 data = REG_SET_FIELD(data, IH_CLK_CTRL, 604 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 605 data = REG_SET_FIELD(data, IH_CLK_CTRL, 606 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 607 data = REG_SET_FIELD(data, IH_CLK_CTRL, 608 DYN_CLK_SOFT_OVERRIDE, field_val); 609 data = REG_SET_FIELD(data, IH_CLK_CTRL, 610 REG_CLK_SOFT_OVERRIDE, field_val); 611 if (def != data) 612 WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 613 } 614 } 615 616 static int vega10_ih_set_clockgating_state(void *handle, 617 enum amd_clockgating_state state) 618 { 619 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 620 621 vega10_ih_update_clockgating_state(adev, 622 state == AMD_CG_STATE_GATE); 623 return 0; 624 625 } 626 627 static int vega10_ih_set_powergating_state(void *handle, 628 enum amd_powergating_state state) 629 { 630 return 0; 631 } 632 633 const struct amd_ip_funcs vega10_ih_ip_funcs = { 634 .name = "vega10_ih", 635 .early_init = vega10_ih_early_init, 636 .late_init = NULL, 637 .sw_init = vega10_ih_sw_init, 638 .sw_fini = vega10_ih_sw_fini, 639 .hw_init = vega10_ih_hw_init, 640 .hw_fini = vega10_ih_hw_fini, 641 .suspend = vega10_ih_suspend, 642 .resume = vega10_ih_resume, 643 .is_idle = vega10_ih_is_idle, 644 .wait_for_idle = vega10_ih_wait_for_idle, 645 .soft_reset = vega10_ih_soft_reset, 646 .set_clockgating_state = vega10_ih_set_clockgating_state, 647 .set_powergating_state = vega10_ih_set_powergating_state, 648 }; 649 650 static const struct amdgpu_ih_funcs vega10_ih_funcs = { 651 .get_wptr = vega10_ih_get_wptr, 652 .decode_iv = amdgpu_ih_decode_iv_helper, 653 .set_rptr = vega10_ih_set_rptr 654 }; 655 656 static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 657 { 658 adev->irq.ih_funcs = &vega10_ih_funcs; 659 } 660 661 const struct amdgpu_ip_block_version vega10_ih_ip_block = 662 { 663 .type = AMD_IP_BLOCK_TYPE_IH, 664 .major = 4, 665 .minor = 0, 666 .rev = 0, 667 .funcs = &vega10_ih_ip_funcs, 668 }; 669