1282aae55SKen Wang /* 2282aae55SKen Wang * Copyright 2016 Advanced Micro Devices, Inc. 3282aae55SKen Wang * 4282aae55SKen Wang * Permission is hereby granted, free of charge, to any person obtaining a 5282aae55SKen Wang * copy of this software and associated documentation files (the "Software"), 6282aae55SKen Wang * to deal in the Software without restriction, including without limitation 7282aae55SKen Wang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8282aae55SKen Wang * and/or sell copies of the Software, and to permit persons to whom the 9282aae55SKen Wang * Software is furnished to do so, subject to the following conditions: 10282aae55SKen Wang * 11282aae55SKen Wang * The above copyright notice and this permission notice shall be included in 12282aae55SKen Wang * all copies or substantial portions of the Software. 13282aae55SKen Wang * 14282aae55SKen Wang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15282aae55SKen Wang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16282aae55SKen Wang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17282aae55SKen Wang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18282aae55SKen Wang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19282aae55SKen Wang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20282aae55SKen Wang * OTHER DEALINGS IN THE SOFTWARE. 21282aae55SKen Wang * 22282aae55SKen Wang */ 2347b757fbSSam Ravnborg 2447b757fbSSam Ravnborg #include <linux/pci.h> 2547b757fbSSam Ravnborg 26282aae55SKen Wang #include "amdgpu.h" 27282aae55SKen Wang #include "amdgpu_ih.h" 28282aae55SKen Wang #include "soc15.h" 29282aae55SKen Wang 308af7454eSFeifei Xu #include "oss/osssys_4_0_offset.h" 318af7454eSFeifei Xu #include "oss/osssys_4_0_sh_mask.h" 32282aae55SKen Wang 33282aae55SKen Wang #include "soc15_common.h" 34282aae55SKen Wang #include "vega10_ih.h" 35282aae55SKen Wang 3674dcfe74STrigger Huang #define MAX_REARM_RETRY 10 37282aae55SKen Wang 38282aae55SKen Wang static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 39282aae55SKen Wang 40282aae55SKen Wang /** 411ebb4841SHawking Zhang * vega10_ih_init_register_offset - Initialize register offset for ih rings 421ebb4841SHawking Zhang * 431ebb4841SHawking Zhang * @adev: amdgpu_device pointer 441ebb4841SHawking Zhang * 451ebb4841SHawking Zhang * Initialize register offset ih rings (VEGA10). 461ebb4841SHawking Zhang */ 471ebb4841SHawking Zhang static void vega10_ih_init_register_offset(struct amdgpu_device *adev) 481ebb4841SHawking Zhang { 491ebb4841SHawking Zhang struct amdgpu_ih_regs *ih_regs; 501ebb4841SHawking Zhang 511ebb4841SHawking Zhang if (adev->irq.ih.ring_size) { 521ebb4841SHawking Zhang ih_regs = &adev->irq.ih.ih_regs; 531ebb4841SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); 541ebb4841SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); 551ebb4841SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 561ebb4841SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 571ebb4841SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 581ebb4841SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); 591ebb4841SHawking Zhang ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); 601ebb4841SHawking Zhang ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); 611ebb4841SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; 621ebb4841SHawking Zhang } 631ebb4841SHawking Zhang 641ebb4841SHawking Zhang if (adev->irq.ih1.ring_size) { 651ebb4841SHawking Zhang ih_regs = &adev->irq.ih1.ih_regs; 661ebb4841SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); 671ebb4841SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); 681ebb4841SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 691ebb4841SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 701ebb4841SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 711ebb4841SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1); 721ebb4841SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; 731ebb4841SHawking Zhang } 741ebb4841SHawking Zhang 751ebb4841SHawking Zhang if (adev->irq.ih2.ring_size) { 761ebb4841SHawking Zhang ih_regs = &adev->irq.ih2.ih_regs; 771ebb4841SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); 781ebb4841SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2); 791ebb4841SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 801ebb4841SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 811ebb4841SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 821ebb4841SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2); 831ebb4841SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2; 841ebb4841SHawking Zhang } 851ebb4841SHawking Zhang } 861ebb4841SHawking Zhang 871ebb4841SHawking Zhang /** 88c7375032SHawking Zhang * vega10_ih_toggle_ring_interrupts - toggle the interrupt ring buffer 89c7375032SHawking Zhang * 90c7375032SHawking Zhang * @adev: amdgpu_device pointer 91c7375032SHawking Zhang * @ih: amdgpu_ih_ring pointet 92c7375032SHawking Zhang * @enable: true - enable the interrupts, false - disable the interrupts 93c7375032SHawking Zhang * 94c7375032SHawking Zhang * Toggle the interrupt ring buffer (VEGA10) 95c7375032SHawking Zhang */ 96c7375032SHawking Zhang static int vega10_ih_toggle_ring_interrupts(struct amdgpu_device *adev, 97c7375032SHawking Zhang struct amdgpu_ih_ring *ih, 98c7375032SHawking Zhang bool enable) 99c7375032SHawking Zhang { 100c7375032SHawking Zhang struct amdgpu_ih_regs *ih_regs; 101c7375032SHawking Zhang uint32_t tmp; 102c7375032SHawking Zhang 103c7375032SHawking Zhang ih_regs = &ih->ih_regs; 104c7375032SHawking Zhang 105c7375032SHawking Zhang tmp = RREG32(ih_regs->ih_rb_cntl); 106c7375032SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); 107c7375032SHawking Zhang /* enable_intr field is only valid in ring0 */ 108c7375032SHawking Zhang if (ih == &adev->irq.ih) 109c7375032SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); 110c7375032SHawking Zhang if (amdgpu_sriov_vf(adev)) { 111c7375032SHawking Zhang if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 112c7375032SHawking Zhang dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 113c7375032SHawking Zhang return -ETIMEDOUT; 114c7375032SHawking Zhang } 115c7375032SHawking Zhang } else { 116c7375032SHawking Zhang WREG32(ih_regs->ih_rb_cntl, tmp); 117c7375032SHawking Zhang } 118c7375032SHawking Zhang 119c7375032SHawking Zhang if (enable) { 120c7375032SHawking Zhang ih->enabled = true; 121c7375032SHawking Zhang } else { 122c7375032SHawking Zhang /* set rptr, wptr to 0 */ 123c7375032SHawking Zhang WREG32(ih_regs->ih_rb_rptr, 0); 124c7375032SHawking Zhang WREG32(ih_regs->ih_rb_wptr, 0); 125c7375032SHawking Zhang ih->enabled = false; 126c7375032SHawking Zhang ih->rptr = 0; 127c7375032SHawking Zhang } 128c7375032SHawking Zhang 129c7375032SHawking Zhang return 0; 130c7375032SHawking Zhang } 131c7375032SHawking Zhang 132*fd95e1b1SHawking Zhang /** 133*fd95e1b1SHawking Zhang * vega10_ih_toggle_interrupts - Toggle all the available interrupt ring buffers 134*fd95e1b1SHawking Zhang * 135*fd95e1b1SHawking Zhang * @adev: amdgpu_device pointer 136*fd95e1b1SHawking Zhang * @enable: enable or disable interrupt ring buffers 137*fd95e1b1SHawking Zhang * 138*fd95e1b1SHawking Zhang * Toggle all the available interrupt ring buffers (VEGA10). 139*fd95e1b1SHawking Zhang */ 140*fd95e1b1SHawking Zhang static int vega10_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable) 141*fd95e1b1SHawking Zhang { 142*fd95e1b1SHawking Zhang struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 143*fd95e1b1SHawking Zhang int i; 144*fd95e1b1SHawking Zhang int r; 145*fd95e1b1SHawking Zhang 146*fd95e1b1SHawking Zhang for (i = 0; i < ARRAY_SIZE(ih); i++) { 147*fd95e1b1SHawking Zhang if (ih[i]->ring_size) { 148*fd95e1b1SHawking Zhang r = vega10_ih_toggle_ring_interrupts(adev, ih[i], enable); 149*fd95e1b1SHawking Zhang if (r) 150*fd95e1b1SHawking Zhang return r; 151*fd95e1b1SHawking Zhang } 152*fd95e1b1SHawking Zhang } 153*fd95e1b1SHawking Zhang 154*fd95e1b1SHawking Zhang return 0; 155*fd95e1b1SHawking Zhang } 156*fd95e1b1SHawking Zhang 157ad710812SChristian König static uint32_t vega10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 158ad710812SChristian König { 159ad710812SChristian König int rb_bufsz = order_base_2(ih->ring_size / 4); 160ad710812SChristian König 161ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 162ad710812SChristian König MC_SPACE, ih->use_bus_addr ? 1 : 4); 163ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 164ad710812SChristian König WPTR_OVERFLOW_CLEAR, 1); 165ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 166ad710812SChristian König WPTR_OVERFLOW_ENABLE, 1); 167ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 168ad710812SChristian König /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 169ad710812SChristian König * value is written to memory 170ad710812SChristian König */ 171ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 172ad710812SChristian König WPTR_WRITEBACK_ENABLE, 1); 173ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 174ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 175ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 176ad710812SChristian König 177ad710812SChristian König return ih_rb_cntl; 178282aae55SKen Wang } 179282aae55SKen Wang 1801ae64cecSChristian König static uint32_t vega10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 1811ae64cecSChristian König { 1821ae64cecSChristian König u32 ih_doorbell_rtpr = 0; 1831ae64cecSChristian König 1841ae64cecSChristian König if (ih->use_doorbell) { 1851ae64cecSChristian König ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 1861ae64cecSChristian König IH_DOORBELL_RPTR, OFFSET, 1871ae64cecSChristian König ih->doorbell_index); 1881ae64cecSChristian König ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 1891ae64cecSChristian König IH_DOORBELL_RPTR, 1901ae64cecSChristian König ENABLE, 1); 1911ae64cecSChristian König } else { 1921ae64cecSChristian König ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 1931ae64cecSChristian König IH_DOORBELL_RPTR, 1941ae64cecSChristian König ENABLE, 0); 1951ae64cecSChristian König } 1961ae64cecSChristian König return ih_doorbell_rtpr; 1971ae64cecSChristian König } 1981ae64cecSChristian König 199282aae55SKen Wang /** 200ffa02126SHawking Zhang * vega10_ih_enable_ring - enable an ih ring buffer 201ffa02126SHawking Zhang * 202ffa02126SHawking Zhang * @adev: amdgpu_device pointer 203ffa02126SHawking Zhang * @ih: amdgpu_ih_ring pointer 204ffa02126SHawking Zhang * 205ffa02126SHawking Zhang * Enable an ih ring buffer (VEGA10) 206ffa02126SHawking Zhang */ 207ffa02126SHawking Zhang static int vega10_ih_enable_ring(struct amdgpu_device *adev, 208ffa02126SHawking Zhang struct amdgpu_ih_ring *ih) 209ffa02126SHawking Zhang { 210ffa02126SHawking Zhang struct amdgpu_ih_regs *ih_regs; 211ffa02126SHawking Zhang uint32_t tmp; 212ffa02126SHawking Zhang 213ffa02126SHawking Zhang ih_regs = &ih->ih_regs; 214ffa02126SHawking Zhang 215ffa02126SHawking Zhang /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 216ffa02126SHawking Zhang WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); 217ffa02126SHawking Zhang WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); 218ffa02126SHawking Zhang 219ffa02126SHawking Zhang tmp = RREG32(ih_regs->ih_rb_cntl); 220ffa02126SHawking Zhang tmp = vega10_ih_rb_cntl(ih, tmp); 221ffa02126SHawking Zhang if (ih == &adev->irq.ih) 222ffa02126SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); 223ffa02126SHawking Zhang if (ih == &adev->irq.ih1) { 224ffa02126SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0); 225ffa02126SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); 226ffa02126SHawking Zhang } 227ffa02126SHawking Zhang if (amdgpu_sriov_vf(adev)) { 228ffa02126SHawking Zhang if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 229ffa02126SHawking Zhang dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 230ffa02126SHawking Zhang return -ETIMEDOUT; 231ffa02126SHawking Zhang } 232ffa02126SHawking Zhang } else { 233ffa02126SHawking Zhang WREG32(ih_regs->ih_rb_cntl, tmp); 234ffa02126SHawking Zhang } 235ffa02126SHawking Zhang 236ffa02126SHawking Zhang if (ih == &adev->irq.ih) { 237ffa02126SHawking Zhang /* set the ih ring 0 writeback address whether it's enabled or not */ 238ffa02126SHawking Zhang WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); 239ffa02126SHawking Zhang WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); 240ffa02126SHawking Zhang } 241ffa02126SHawking Zhang 242ffa02126SHawking Zhang /* set rptr, wptr to 0 */ 243ffa02126SHawking Zhang WREG32(ih_regs->ih_rb_wptr, 0); 244ffa02126SHawking Zhang WREG32(ih_regs->ih_rb_rptr, 0); 245ffa02126SHawking Zhang 246ffa02126SHawking Zhang WREG32(ih_regs->ih_doorbell_rptr, vega10_ih_doorbell_rptr(ih)); 247ffa02126SHawking Zhang 248ffa02126SHawking Zhang return 0; 249ffa02126SHawking Zhang } 250ffa02126SHawking Zhang 251ffa02126SHawking Zhang /** 252282aae55SKen Wang * vega10_ih_irq_init - init and enable the interrupt ring 253282aae55SKen Wang * 254282aae55SKen Wang * @adev: amdgpu_device pointer 255282aae55SKen Wang * 256282aae55SKen Wang * Allocate a ring buffer for the interrupt controller, 257282aae55SKen Wang * enable the RLC, disable interrupts, enable the IH 258282aae55SKen Wang * ring buffer and enable it (VI). 259282aae55SKen Wang * Called at device load and reume. 260282aae55SKen Wang * Returns 0 for success, errors for failure. 261282aae55SKen Wang */ 262282aae55SKen Wang static int vega10_ih_irq_init(struct amdgpu_device *adev) 263282aae55SKen Wang { 264ad710812SChristian König struct amdgpu_ih_ring *ih; 265f9c84ae5SLe Ma u32 ih_rb_cntl, ih_chicken; 266*fd95e1b1SHawking Zhang int ret; 267282aae55SKen Wang u32 tmp; 268282aae55SKen Wang 269282aae55SKen Wang /* disable irqs */ 270*fd95e1b1SHawking Zhang ret = vega10_ih_toggle_interrupts(adev, false); 271*fd95e1b1SHawking Zhang if (ret) 272*fd95e1b1SHawking Zhang return ret; 273282aae55SKen Wang 274bebc0762SHawking Zhang adev->nbio.funcs->ih_control(adev); 275282aae55SKen Wang 276ad710812SChristian König ih = &adev->irq.ih; 277282aae55SKen Wang /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 278ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8); 279ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff); 280282aae55SKen Wang 281ad710812SChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 282ad710812SChristian König ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl); 283ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 284ad710812SChristian König !!adev->irq.msi_enabled); 2854cd4c5c0SMonk Liu if (amdgpu_sriov_vf(adev)) { 286470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 287470b4250STrigger Huang DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 288470b4250STrigger Huang return -ETIMEDOUT; 289470b4250STrigger Huang } 290470b4250STrigger Huang } else { 291b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 292470b4250STrigger Huang } 293282aae55SKen Wang 29425344d7eSZhigang Luo if ((adev->asic_type == CHIP_ARCTURUS && 29525344d7eSZhigang Luo adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) || 29625344d7eSZhigang Luo adev->asic_type == CHIP_RENOIR) { 29725344d7eSZhigang Luo ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 29825344d7eSZhigang Luo if (adev->irq.ih.use_bus_addr) { 29925344d7eSZhigang Luo ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 30025344d7eSZhigang Luo MC_SPACE_GPA_ENABLE, 1); 30125344d7eSZhigang Luo } else { 30225344d7eSZhigang Luo ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 30325344d7eSZhigang Luo MC_SPACE_FBPA_ENABLE, 1); 30425344d7eSZhigang Luo } 305f9c84ae5SLe Ma WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 30625344d7eSZhigang Luo } 307f9c84ae5SLe Ma 308282aae55SKen Wang /* set the writeback address whether it's enabled or not */ 309d81f78b4SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, 310d81f78b4SChristian König lower_32_bits(ih->wptr_addr)); 311d81f78b4SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, 312d81f78b4SChristian König upper_32_bits(ih->wptr_addr) & 0xFFFF); 313282aae55SKen Wang 314282aae55SKen Wang /* set rptr, wptr to 0 */ 315b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 3161ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 317282aae55SKen Wang 3181ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, 3191ae64cecSChristian König vega10_ih_doorbell_rptr(ih)); 320282aae55SKen Wang 321ad710812SChristian König ih = &adev->irq.ih1; 322ad710812SChristian König if (ih->ring_size) { 323ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING1, ih->gpu_addr >> 8); 324ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING1, 325ad710812SChristian König (ih->gpu_addr >> 40) & 0xff); 326ad710812SChristian König 327ad710812SChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 328ad710812SChristian König ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl); 3290133690eSChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 3300133690eSChristian König WPTR_OVERFLOW_ENABLE, 0); 3310133690eSChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 3320133690eSChristian König RB_FULL_DRAIN_ENABLE, 1); 3334cd4c5c0SMonk Liu if (amdgpu_sriov_vf(adev)) { 334470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 335470b4250STrigger Huang ih_rb_cntl)) { 336470b4250STrigger Huang DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 337470b4250STrigger Huang return -ETIMEDOUT; 338470b4250STrigger Huang } 339470b4250STrigger Huang } else { 340ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 341470b4250STrigger Huang } 342ad710812SChristian König 343ad710812SChristian König /* set rptr, wptr to 0 */ 344ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 3451ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 3461ae64cecSChristian König 3471ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1, 3481ae64cecSChristian König vega10_ih_doorbell_rptr(ih)); 349ad710812SChristian König } 350ad710812SChristian König 351ad710812SChristian König ih = &adev->irq.ih2; 352ad710812SChristian König if (ih->ring_size) { 353ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING2, ih->gpu_addr >> 8); 354ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING2, 355ad710812SChristian König (ih->gpu_addr >> 40) & 0xff); 356ad710812SChristian König 3571ae64cecSChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 358ad710812SChristian König ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl); 359470b4250STrigger Huang 3604cd4c5c0SMonk Liu if (amdgpu_sriov_vf(adev)) { 361470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 362470b4250STrigger Huang ih_rb_cntl)) { 363470b4250STrigger Huang DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 364470b4250STrigger Huang return -ETIMEDOUT; 365470b4250STrigger Huang } 366470b4250STrigger Huang } else { 367ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 368470b4250STrigger Huang } 369ad710812SChristian König 370ad710812SChristian König /* set rptr, wptr to 0 */ 371ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 3721ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 3731ae64cecSChristian König 3741ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2, 3751ae64cecSChristian König vega10_ih_doorbell_rptr(ih)); 376ad710812SChristian König } 377ad710812SChristian König 378b2b7e457SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 379282aae55SKen Wang tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 380282aae55SKen Wang CLIENT18_IS_STORM_CLIENT, 1); 381b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 382282aae55SKen Wang 383b2b7e457SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 384282aae55SKen Wang tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 385b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 386282aae55SKen Wang 387282aae55SKen Wang pci_set_master(adev->pdev); 388282aae55SKen Wang 389282aae55SKen Wang /* enable interrupts */ 390*fd95e1b1SHawking Zhang ret = vega10_ih_toggle_interrupts(adev, true); 391*fd95e1b1SHawking Zhang if (ret) 392282aae55SKen Wang return ret; 393*fd95e1b1SHawking Zhang 394*fd95e1b1SHawking Zhang return 0; 395282aae55SKen Wang } 396282aae55SKen Wang 397282aae55SKen Wang /** 398282aae55SKen Wang * vega10_ih_irq_disable - disable interrupts 399282aae55SKen Wang * 400282aae55SKen Wang * @adev: amdgpu_device pointer 401282aae55SKen Wang * 402282aae55SKen Wang * Disable interrupts on the hw (VEGA10). 403282aae55SKen Wang */ 404282aae55SKen Wang static void vega10_ih_irq_disable(struct amdgpu_device *adev) 405282aae55SKen Wang { 406*fd95e1b1SHawking Zhang vega10_ih_toggle_interrupts(adev, false); 407282aae55SKen Wang 408282aae55SKen Wang /* Wait and acknowledge irq */ 409282aae55SKen Wang mdelay(1); 410282aae55SKen Wang } 411282aae55SKen Wang 412282aae55SKen Wang /** 413282aae55SKen Wang * vega10_ih_get_wptr - get the IH ring buffer wptr 414282aae55SKen Wang * 415282aae55SKen Wang * @adev: amdgpu_device pointer 4165162e40eSLee Jones * @ih: IH ring buffer to fetch wptr 417282aae55SKen Wang * 418282aae55SKen Wang * Get the IH ring buffer wptr from either the register 419282aae55SKen Wang * or the writeback memory buffer (VEGA10). Also check for 420282aae55SKen Wang * ring buffer overflow and deal with it. 421282aae55SKen Wang * Returns the value of the wptr. 422282aae55SKen Wang */ 4238bb9eb48SChristian König static u32 vega10_ih_get_wptr(struct amdgpu_device *adev, 4248bb9eb48SChristian König struct amdgpu_ih_ring *ih) 425282aae55SKen Wang { 426cf67950eSChristian König u32 wptr, reg, tmp; 427282aae55SKen Wang 428d81f78b4SChristian König wptr = le32_to_cpu(*ih->wptr_cpu); 429282aae55SKen Wang 430b8217575SChristian König if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 431b8217575SChristian König goto out; 432b8217575SChristian König 433b8217575SChristian König /* Double check that the overflow wasn't already cleared. */ 434cf67950eSChristian König 435cf67950eSChristian König if (ih == &adev->irq.ih) 436cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 437cf67950eSChristian König else if (ih == &adev->irq.ih1) 438cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 439cf67950eSChristian König else if (ih == &adev->irq.ih2) 440cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 441cf67950eSChristian König else 442cf67950eSChristian König BUG(); 443cf67950eSChristian König 444cf67950eSChristian König wptr = RREG32_NO_KIQ(reg); 445b8217575SChristian König if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 446b8217575SChristian König goto out; 447b8217575SChristian König 448282aae55SKen Wang wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 449282aae55SKen Wang 450282aae55SKen Wang /* When a ring buffer overflow happen start parsing interrupt 451282aae55SKen Wang * from the last not overwritten vector (wptr + 32). Hopefully 452282aae55SKen Wang * this should allow us to catchup. 453282aae55SKen Wang */ 4548bb9eb48SChristian König tmp = (wptr + 32) & ih->ptr_mask; 455b8217575SChristian König dev_warn(adev->dev, "IH ring buffer overflow " 456b8217575SChristian König "(0x%08X, 0x%08X, 0x%08X)\n", 4578bb9eb48SChristian König wptr, ih->rptr, tmp); 4588bb9eb48SChristian König ih->rptr = tmp; 459282aae55SKen Wang 460cf67950eSChristian König if (ih == &adev->irq.ih) 461cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 462cf67950eSChristian König else if (ih == &adev->irq.ih1) 463cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 464cf67950eSChristian König else if (ih == &adev->irq.ih2) 465cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 466cf67950eSChristian König else 467cf67950eSChristian König BUG(); 468cf67950eSChristian König 469cf67950eSChristian König tmp = RREG32_NO_KIQ(reg); 470282aae55SKen Wang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 471cf67950eSChristian König WREG32_NO_KIQ(reg, tmp); 472b8217575SChristian König 473b8217575SChristian König out: 4748bb9eb48SChristian König return (wptr & ih->ptr_mask); 475282aae55SKen Wang } 476282aae55SKen Wang 477282aae55SKen Wang /** 478282aae55SKen Wang * vega10_ih_decode_iv - decode an interrupt vector 479282aae55SKen Wang * 480282aae55SKen Wang * @adev: amdgpu_device pointer 4815162e40eSLee Jones * @ih: IH ring buffer to decode 4825162e40eSLee Jones * @entry: IV entry to place decoded information into 483282aae55SKen Wang * 484282aae55SKen Wang * Decodes the interrupt vector at the current rptr 485282aae55SKen Wang * position and also advance the position. 486282aae55SKen Wang */ 487282aae55SKen Wang static void vega10_ih_decode_iv(struct amdgpu_device *adev, 4888bb9eb48SChristian König struct amdgpu_ih_ring *ih, 489282aae55SKen Wang struct amdgpu_iv_entry *entry) 490282aae55SKen Wang { 491282aae55SKen Wang /* wptr/rptr are in bytes! */ 4928bb9eb48SChristian König u32 ring_index = ih->rptr >> 2; 493282aae55SKen Wang uint32_t dw[8]; 494282aae55SKen Wang 4958bb9eb48SChristian König dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 4968bb9eb48SChristian König dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 4978bb9eb48SChristian König dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 4988bb9eb48SChristian König dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 4998bb9eb48SChristian König dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); 5008bb9eb48SChristian König dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); 5018bb9eb48SChristian König dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); 5028bb9eb48SChristian König dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); 503282aae55SKen Wang 504282aae55SKen Wang entry->client_id = dw[0] & 0xff; 505282aae55SKen Wang entry->src_id = (dw[0] >> 8) & 0xff; 506282aae55SKen Wang entry->ring_id = (dw[0] >> 16) & 0xff; 507c4f46f22SChristian König entry->vmid = (dw[0] >> 24) & 0xf; 508c4f46f22SChristian König entry->vmid_src = (dw[0] >> 31); 509282aae55SKen Wang entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); 510282aae55SKen Wang entry->timestamp_src = dw[2] >> 31; 5113816e42fSChristian König entry->pasid = dw[3] & 0xffff; 512282aae55SKen Wang entry->pasid_src = dw[3] >> 31; 513282aae55SKen Wang entry->src_data[0] = dw[4]; 514282aae55SKen Wang entry->src_data[1] = dw[5]; 515282aae55SKen Wang entry->src_data[2] = dw[6]; 516282aae55SKen Wang entry->src_data[3] = dw[7]; 517282aae55SKen Wang 518282aae55SKen Wang /* wptr/rptr are in bytes! */ 5198bb9eb48SChristian König ih->rptr += 32; 520282aae55SKen Wang } 521282aae55SKen Wang 522282aae55SKen Wang /** 52374dcfe74STrigger Huang * vega10_ih_irq_rearm - rearm IRQ if lost 52474dcfe74STrigger Huang * 52574dcfe74STrigger Huang * @adev: amdgpu_device pointer 5265162e40eSLee Jones * @ih: IH ring to match 52774dcfe74STrigger Huang * 52874dcfe74STrigger Huang */ 52974dcfe74STrigger Huang static void vega10_ih_irq_rearm(struct amdgpu_device *adev, 53074dcfe74STrigger Huang struct amdgpu_ih_ring *ih) 53174dcfe74STrigger Huang { 53274dcfe74STrigger Huang uint32_t reg_rptr = 0; 53374dcfe74STrigger Huang uint32_t v = 0; 53474dcfe74STrigger Huang uint32_t i = 0; 53574dcfe74STrigger Huang 53674dcfe74STrigger Huang if (ih == &adev->irq.ih) 53774dcfe74STrigger Huang reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 53874dcfe74STrigger Huang else if (ih == &adev->irq.ih1) 53974dcfe74STrigger Huang reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 54074dcfe74STrigger Huang else if (ih == &adev->irq.ih2) 54174dcfe74STrigger Huang reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 54274dcfe74STrigger Huang else 54374dcfe74STrigger Huang return; 54474dcfe74STrigger Huang 54574dcfe74STrigger Huang /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */ 54674dcfe74STrigger Huang for (i = 0; i < MAX_REARM_RETRY; i++) { 54774dcfe74STrigger Huang v = RREG32_NO_KIQ(reg_rptr); 54874dcfe74STrigger Huang if ((v < ih->ring_size) && (v != ih->rptr)) 54974dcfe74STrigger Huang WDOORBELL32(ih->doorbell_index, ih->rptr); 55074dcfe74STrigger Huang else 55174dcfe74STrigger Huang break; 55274dcfe74STrigger Huang } 55374dcfe74STrigger Huang } 55474dcfe74STrigger Huang 55574dcfe74STrigger Huang /** 556282aae55SKen Wang * vega10_ih_set_rptr - set the IH ring buffer rptr 557282aae55SKen Wang * 558282aae55SKen Wang * @adev: amdgpu_device pointer 5595162e40eSLee Jones * @ih: IH ring buffer to set rptr 560282aae55SKen Wang * 561282aae55SKen Wang * Set the IH ring buffer rptr. 562282aae55SKen Wang */ 5638bb9eb48SChristian König static void vega10_ih_set_rptr(struct amdgpu_device *adev, 5648bb9eb48SChristian König struct amdgpu_ih_ring *ih) 565282aae55SKen Wang { 5668bb9eb48SChristian König if (ih->use_doorbell) { 567282aae55SKen Wang /* XXX check if swapping is necessary on BE */ 568d81f78b4SChristian König *ih->rptr_cpu = ih->rptr; 5698bb9eb48SChristian König WDOORBELL32(ih->doorbell_index, ih->rptr); 57074dcfe74STrigger Huang 57174dcfe74STrigger Huang if (amdgpu_sriov_vf(adev)) 57274dcfe74STrigger Huang vega10_ih_irq_rearm(adev, ih); 573cf67950eSChristian König } else if (ih == &adev->irq.ih) { 5748bb9eb48SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr); 575cf67950eSChristian König } else if (ih == &adev->irq.ih1) { 576cf67950eSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, ih->rptr); 577cf67950eSChristian König } else if (ih == &adev->irq.ih2) { 578cf67950eSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, ih->rptr); 579282aae55SKen Wang } 580282aae55SKen Wang } 581282aae55SKen Wang 582cf67950eSChristian König /** 583cf67950eSChristian König * vega10_ih_self_irq - dispatch work for ring 1 and 2 584cf67950eSChristian König * 585cf67950eSChristian König * @adev: amdgpu_device pointer 586cf67950eSChristian König * @source: irq source 587cf67950eSChristian König * @entry: IV with WPTR update 588cf67950eSChristian König * 589cf67950eSChristian König * Update the WPTR from the IV and schedule work to handle the entries. 590cf67950eSChristian König */ 591cf67950eSChristian König static int vega10_ih_self_irq(struct amdgpu_device *adev, 592cf67950eSChristian König struct amdgpu_irq_src *source, 593cf67950eSChristian König struct amdgpu_iv_entry *entry) 594cf67950eSChristian König { 595cf67950eSChristian König uint32_t wptr = cpu_to_le32(entry->src_data[0]); 596cf67950eSChristian König 597cf67950eSChristian König switch (entry->ring_id) { 598cf67950eSChristian König case 1: 599cf67950eSChristian König *adev->irq.ih1.wptr_cpu = wptr; 600cf67950eSChristian König schedule_work(&adev->irq.ih1_work); 601cf67950eSChristian König break; 602cf67950eSChristian König case 2: 603cf67950eSChristian König *adev->irq.ih2.wptr_cpu = wptr; 604cf67950eSChristian König schedule_work(&adev->irq.ih2_work); 605cf67950eSChristian König break; 606cf67950eSChristian König default: break; 607cf67950eSChristian König } 608cf67950eSChristian König return 0; 609cf67950eSChristian König } 610cf67950eSChristian König 611cf67950eSChristian König static const struct amdgpu_irq_src_funcs vega10_ih_self_irq_funcs = { 612cf67950eSChristian König .process = vega10_ih_self_irq, 613cf67950eSChristian König }; 614cf67950eSChristian König 615cf67950eSChristian König static void vega10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 616cf67950eSChristian König { 617cf67950eSChristian König adev->irq.self_irq.num_types = 0; 618cf67950eSChristian König adev->irq.self_irq.funcs = &vega10_ih_self_irq_funcs; 619cf67950eSChristian König } 620cf67950eSChristian König 621282aae55SKen Wang static int vega10_ih_early_init(void *handle) 622282aae55SKen Wang { 623282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 624282aae55SKen Wang 625282aae55SKen Wang vega10_ih_set_interrupt_funcs(adev); 626cf67950eSChristian König vega10_ih_set_self_irq_funcs(adev); 627282aae55SKen Wang return 0; 628282aae55SKen Wang } 629282aae55SKen Wang 630282aae55SKen Wang static int vega10_ih_sw_init(void *handle) 631282aae55SKen Wang { 632282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 633cf67950eSChristian König int r; 634cf67950eSChristian König 635cf67950eSChristian König r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 636cf67950eSChristian König &adev->irq.self_irq); 637cf67950eSChristian König if (r) 638cf67950eSChristian König return r; 639282aae55SKen Wang 640425c3143SChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true); 641282aae55SKen Wang if (r) 642282aae55SKen Wang return r; 643282aae55SKen Wang 6441ae64cecSChristian König adev->irq.ih.use_doorbell = true; 6451ae64cecSChristian König adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 6461ae64cecSChristian König 647ad710812SChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 648ad710812SChristian König if (r) 649ad710812SChristian König return r; 650ad710812SChristian König 6511ae64cecSChristian König adev->irq.ih1.use_doorbell = true; 652b51cd19eSChristian König adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; 6531ae64cecSChristian König 654ad710812SChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 655ad710812SChristian König if (r) 656ad710812SChristian König return r; 657ad710812SChristian König 6581ae64cecSChristian König adev->irq.ih2.use_doorbell = true; 659b51cd19eSChristian König adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1; 660282aae55SKen Wang 661f0594717SHawking Zhang /* initialize ih control registers offset */ 662f0594717SHawking Zhang vega10_ih_init_register_offset(adev); 663f0594717SHawking Zhang 66447509189SChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); 66547509189SChristian König if (r) 66647509189SChristian König return r; 66747509189SChristian König 668282aae55SKen Wang r = amdgpu_irq_init(adev); 669282aae55SKen Wang 670282aae55SKen Wang return r; 671282aae55SKen Wang } 672282aae55SKen Wang 673282aae55SKen Wang static int vega10_ih_sw_fini(void *handle) 674282aae55SKen Wang { 675282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 676282aae55SKen Wang 677282aae55SKen Wang amdgpu_irq_fini(adev); 678ad710812SChristian König amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 679ad710812SChristian König amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 680425c3143SChristian König amdgpu_ih_ring_fini(adev, &adev->irq.ih); 681282aae55SKen Wang 682282aae55SKen Wang return 0; 683282aae55SKen Wang } 684282aae55SKen Wang 685282aae55SKen Wang static int vega10_ih_hw_init(void *handle) 686282aae55SKen Wang { 687282aae55SKen Wang int r; 688282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 689282aae55SKen Wang 690282aae55SKen Wang r = vega10_ih_irq_init(adev); 691282aae55SKen Wang if (r) 692282aae55SKen Wang return r; 693282aae55SKen Wang 694282aae55SKen Wang return 0; 695282aae55SKen Wang } 696282aae55SKen Wang 697282aae55SKen Wang static int vega10_ih_hw_fini(void *handle) 698282aae55SKen Wang { 699282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 700282aae55SKen Wang 701282aae55SKen Wang vega10_ih_irq_disable(adev); 702282aae55SKen Wang 703282aae55SKen Wang return 0; 704282aae55SKen Wang } 705282aae55SKen Wang 706282aae55SKen Wang static int vega10_ih_suspend(void *handle) 707282aae55SKen Wang { 708282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 709282aae55SKen Wang 710282aae55SKen Wang return vega10_ih_hw_fini(adev); 711282aae55SKen Wang } 712282aae55SKen Wang 713282aae55SKen Wang static int vega10_ih_resume(void *handle) 714282aae55SKen Wang { 715282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 716282aae55SKen Wang 717282aae55SKen Wang return vega10_ih_hw_init(adev); 718282aae55SKen Wang } 719282aae55SKen Wang 720282aae55SKen Wang static bool vega10_ih_is_idle(void *handle) 721282aae55SKen Wang { 722282aae55SKen Wang /* todo */ 723282aae55SKen Wang return true; 724282aae55SKen Wang } 725282aae55SKen Wang 726282aae55SKen Wang static int vega10_ih_wait_for_idle(void *handle) 727282aae55SKen Wang { 728282aae55SKen Wang /* todo */ 729282aae55SKen Wang return -ETIMEDOUT; 730282aae55SKen Wang } 731282aae55SKen Wang 732282aae55SKen Wang static int vega10_ih_soft_reset(void *handle) 733282aae55SKen Wang { 734282aae55SKen Wang /* todo */ 735282aae55SKen Wang 736282aae55SKen Wang return 0; 737282aae55SKen Wang } 738282aae55SKen Wang 739227f7d58SKenneth Feng static void vega10_ih_update_clockgating_state(struct amdgpu_device *adev, 740227f7d58SKenneth Feng bool enable) 741227f7d58SKenneth Feng { 742227f7d58SKenneth Feng uint32_t data, def, field_val; 743227f7d58SKenneth Feng 744227f7d58SKenneth Feng if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 745227f7d58SKenneth Feng def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 746227f7d58SKenneth Feng field_val = enable ? 0 : 1; 747227f7d58SKenneth Feng /** 748227f7d58SKenneth Feng * Vega10 does not have IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE 749227f7d58SKenneth Feng * and IH_BUFFER_MEM_CLK_SOFT_OVERRIDE field. 750227f7d58SKenneth Feng */ 751227f7d58SKenneth Feng if (adev->asic_type > CHIP_VEGA10) { 752227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 753227f7d58SKenneth Feng IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE, field_val); 754227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 755227f7d58SKenneth Feng IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val); 756227f7d58SKenneth Feng } 757227f7d58SKenneth Feng 758227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 759227f7d58SKenneth Feng DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 760227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 761227f7d58SKenneth Feng OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 762227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 763227f7d58SKenneth Feng LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 764227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 765227f7d58SKenneth Feng DYN_CLK_SOFT_OVERRIDE, field_val); 766227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 767227f7d58SKenneth Feng REG_CLK_SOFT_OVERRIDE, field_val); 768227f7d58SKenneth Feng if (def != data) 769227f7d58SKenneth Feng WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 770227f7d58SKenneth Feng } 771227f7d58SKenneth Feng } 772227f7d58SKenneth Feng 773282aae55SKen Wang static int vega10_ih_set_clockgating_state(void *handle, 774282aae55SKen Wang enum amd_clockgating_state state) 775282aae55SKen Wang { 776227f7d58SKenneth Feng struct amdgpu_device *adev = (struct amdgpu_device *)handle; 777227f7d58SKenneth Feng 778227f7d58SKenneth Feng vega10_ih_update_clockgating_state(adev, 779a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 780282aae55SKen Wang return 0; 781227f7d58SKenneth Feng 782282aae55SKen Wang } 783282aae55SKen Wang 784282aae55SKen Wang static int vega10_ih_set_powergating_state(void *handle, 785282aae55SKen Wang enum amd_powergating_state state) 786282aae55SKen Wang { 787282aae55SKen Wang return 0; 788282aae55SKen Wang } 789282aae55SKen Wang 790282aae55SKen Wang const struct amd_ip_funcs vega10_ih_ip_funcs = { 791282aae55SKen Wang .name = "vega10_ih", 792282aae55SKen Wang .early_init = vega10_ih_early_init, 793282aae55SKen Wang .late_init = NULL, 794282aae55SKen Wang .sw_init = vega10_ih_sw_init, 795282aae55SKen Wang .sw_fini = vega10_ih_sw_fini, 796282aae55SKen Wang .hw_init = vega10_ih_hw_init, 797282aae55SKen Wang .hw_fini = vega10_ih_hw_fini, 798282aae55SKen Wang .suspend = vega10_ih_suspend, 799282aae55SKen Wang .resume = vega10_ih_resume, 800282aae55SKen Wang .is_idle = vega10_ih_is_idle, 801282aae55SKen Wang .wait_for_idle = vega10_ih_wait_for_idle, 802282aae55SKen Wang .soft_reset = vega10_ih_soft_reset, 803282aae55SKen Wang .set_clockgating_state = vega10_ih_set_clockgating_state, 804282aae55SKen Wang .set_powergating_state = vega10_ih_set_powergating_state, 805282aae55SKen Wang }; 806282aae55SKen Wang 807282aae55SKen Wang static const struct amdgpu_ih_funcs vega10_ih_funcs = { 808282aae55SKen Wang .get_wptr = vega10_ih_get_wptr, 809282aae55SKen Wang .decode_iv = vega10_ih_decode_iv, 810282aae55SKen Wang .set_rptr = vega10_ih_set_rptr 811282aae55SKen Wang }; 812282aae55SKen Wang 813282aae55SKen Wang static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 814282aae55SKen Wang { 815282aae55SKen Wang adev->irq.ih_funcs = &vega10_ih_funcs; 816282aae55SKen Wang } 817282aae55SKen Wang 818282aae55SKen Wang const struct amdgpu_ip_block_version vega10_ih_ip_block = 819282aae55SKen Wang { 820282aae55SKen Wang .type = AMD_IP_BLOCK_TYPE_IH, 821282aae55SKen Wang .major = 4, 822282aae55SKen Wang .minor = 0, 823282aae55SKen Wang .rev = 0, 824282aae55SKen Wang .funcs = &vega10_ih_ip_funcs, 825282aae55SKen Wang }; 826