1282aae55SKen Wang /* 2282aae55SKen Wang * Copyright 2016 Advanced Micro Devices, Inc. 3282aae55SKen Wang * 4282aae55SKen Wang * Permission is hereby granted, free of charge, to any person obtaining a 5282aae55SKen Wang * copy of this software and associated documentation files (the "Software"), 6282aae55SKen Wang * to deal in the Software without restriction, including without limitation 7282aae55SKen Wang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8282aae55SKen Wang * and/or sell copies of the Software, and to permit persons to whom the 9282aae55SKen Wang * Software is furnished to do so, subject to the following conditions: 10282aae55SKen Wang * 11282aae55SKen Wang * The above copyright notice and this permission notice shall be included in 12282aae55SKen Wang * all copies or substantial portions of the Software. 13282aae55SKen Wang * 14282aae55SKen Wang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15282aae55SKen Wang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16282aae55SKen Wang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17282aae55SKen Wang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18282aae55SKen Wang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19282aae55SKen Wang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20282aae55SKen Wang * OTHER DEALINGS IN THE SOFTWARE. 21282aae55SKen Wang * 22282aae55SKen Wang */ 2347b757fbSSam Ravnborg 2447b757fbSSam Ravnborg #include <linux/pci.h> 2547b757fbSSam Ravnborg 26282aae55SKen Wang #include "amdgpu.h" 27282aae55SKen Wang #include "amdgpu_ih.h" 28282aae55SKen Wang #include "soc15.h" 29282aae55SKen Wang 308af7454eSFeifei Xu #include "oss/osssys_4_0_offset.h" 318af7454eSFeifei Xu #include "oss/osssys_4_0_sh_mask.h" 32282aae55SKen Wang 33282aae55SKen Wang #include "soc15_common.h" 34282aae55SKen Wang #include "vega10_ih.h" 35282aae55SKen Wang 3674dcfe74STrigger Huang #define MAX_REARM_RETRY 10 37282aae55SKen Wang 38282aae55SKen Wang static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 39282aae55SKen Wang 40282aae55SKen Wang /** 41282aae55SKen Wang * vega10_ih_enable_interrupts - Enable the interrupt ring buffer 42282aae55SKen Wang * 43282aae55SKen Wang * @adev: amdgpu_device pointer 44282aae55SKen Wang * 45282aae55SKen Wang * Enable the interrupt ring buffer (VEGA10). 46282aae55SKen Wang */ 47282aae55SKen Wang static void vega10_ih_enable_interrupts(struct amdgpu_device *adev) 48282aae55SKen Wang { 49b2b7e457SHawking Zhang u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 50282aae55SKen Wang 51282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); 52282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); 53470b4250STrigger Huang if (amdgpu_virt_support_psp_prg_ih_reg(adev)) { 54470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 55470b4250STrigger Huang DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 56470b4250STrigger Huang return; 57470b4250STrigger Huang } 58470b4250STrigger Huang } else { 59b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 60470b4250STrigger Huang } 61282aae55SKen Wang adev->irq.ih.enabled = true; 62ad710812SChristian König 63ad710812SChristian König if (adev->irq.ih1.ring_size) { 64ad710812SChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 65ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 66ad710812SChristian König RB_ENABLE, 1); 67470b4250STrigger Huang if (amdgpu_virt_support_psp_prg_ih_reg(adev)) { 68470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 69470b4250STrigger Huang ih_rb_cntl)) { 70470b4250STrigger Huang DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 71470b4250STrigger Huang return; 72470b4250STrigger Huang } 73470b4250STrigger Huang } else { 74ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 75470b4250STrigger Huang } 76ad710812SChristian König adev->irq.ih1.enabled = true; 77ad710812SChristian König } 78ad710812SChristian König 79ad710812SChristian König if (adev->irq.ih2.ring_size) { 80ad710812SChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 81ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 82ad710812SChristian König RB_ENABLE, 1); 83470b4250STrigger Huang if (amdgpu_virt_support_psp_prg_ih_reg(adev)) { 84470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 85470b4250STrigger Huang ih_rb_cntl)) { 86470b4250STrigger Huang DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 87470b4250STrigger Huang return; 88470b4250STrigger Huang } 89470b4250STrigger Huang } else { 90ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 91470b4250STrigger Huang } 92ad710812SChristian König adev->irq.ih2.enabled = true; 93ad710812SChristian König } 94282aae55SKen Wang } 95282aae55SKen Wang 96282aae55SKen Wang /** 97282aae55SKen Wang * vega10_ih_disable_interrupts - Disable the interrupt ring buffer 98282aae55SKen Wang * 99282aae55SKen Wang * @adev: amdgpu_device pointer 100282aae55SKen Wang * 101282aae55SKen Wang * Disable the interrupt ring buffer (VEGA10). 102282aae55SKen Wang */ 103282aae55SKen Wang static void vega10_ih_disable_interrupts(struct amdgpu_device *adev) 104282aae55SKen Wang { 105b2b7e457SHawking Zhang u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 106282aae55SKen Wang 107282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); 108282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); 109470b4250STrigger Huang if (amdgpu_virt_support_psp_prg_ih_reg(adev)) { 110470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 111470b4250STrigger Huang DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 112470b4250STrigger Huang return; 113470b4250STrigger Huang } 114470b4250STrigger Huang } else { 115b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 116470b4250STrigger Huang } 117470b4250STrigger Huang 118282aae55SKen Wang /* set rptr, wptr to 0 */ 119b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 120b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 121282aae55SKen Wang adev->irq.ih.enabled = false; 122282aae55SKen Wang adev->irq.ih.rptr = 0; 123ad710812SChristian König 124ad710812SChristian König if (adev->irq.ih1.ring_size) { 125ad710812SChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 126ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 127ad710812SChristian König RB_ENABLE, 0); 128470b4250STrigger Huang if (amdgpu_virt_support_psp_prg_ih_reg(adev)) { 129470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 130470b4250STrigger Huang ih_rb_cntl)) { 131470b4250STrigger Huang DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 132470b4250STrigger Huang return; 133470b4250STrigger Huang } 134470b4250STrigger Huang } else { 135ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 136470b4250STrigger Huang } 137ad710812SChristian König /* set rptr, wptr to 0 */ 138ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 139ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 140ad710812SChristian König adev->irq.ih1.enabled = false; 141ad710812SChristian König adev->irq.ih1.rptr = 0; 142ad710812SChristian König } 143ad710812SChristian König 144ad710812SChristian König if (adev->irq.ih2.ring_size) { 145ad710812SChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 146ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 147ad710812SChristian König RB_ENABLE, 0); 148470b4250STrigger Huang if (amdgpu_virt_support_psp_prg_ih_reg(adev)) { 149470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 150470b4250STrigger Huang ih_rb_cntl)) { 151470b4250STrigger Huang DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 152470b4250STrigger Huang return; 153470b4250STrigger Huang } 154470b4250STrigger Huang } else { 155ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 156470b4250STrigger Huang } 157470b4250STrigger Huang 158ad710812SChristian König /* set rptr, wptr to 0 */ 159ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 160ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 161ad710812SChristian König adev->irq.ih2.enabled = false; 162ad710812SChristian König adev->irq.ih2.rptr = 0; 163ad710812SChristian König } 164ad710812SChristian König } 165ad710812SChristian König 166ad710812SChristian König static uint32_t vega10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 167ad710812SChristian König { 168ad710812SChristian König int rb_bufsz = order_base_2(ih->ring_size / 4); 169ad710812SChristian König 170ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 171ad710812SChristian König MC_SPACE, ih->use_bus_addr ? 1 : 4); 172ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 173ad710812SChristian König WPTR_OVERFLOW_CLEAR, 1); 174ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 175ad710812SChristian König WPTR_OVERFLOW_ENABLE, 1); 176ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 177ad710812SChristian König /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 178ad710812SChristian König * value is written to memory 179ad710812SChristian König */ 180ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 181ad710812SChristian König WPTR_WRITEBACK_ENABLE, 1); 182ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 183ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 184ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 185ad710812SChristian König 186ad710812SChristian König return ih_rb_cntl; 187282aae55SKen Wang } 188282aae55SKen Wang 1891ae64cecSChristian König static uint32_t vega10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 1901ae64cecSChristian König { 1911ae64cecSChristian König u32 ih_doorbell_rtpr = 0; 1921ae64cecSChristian König 1931ae64cecSChristian König if (ih->use_doorbell) { 1941ae64cecSChristian König ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 1951ae64cecSChristian König IH_DOORBELL_RPTR, OFFSET, 1961ae64cecSChristian König ih->doorbell_index); 1971ae64cecSChristian König ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 1981ae64cecSChristian König IH_DOORBELL_RPTR, 1991ae64cecSChristian König ENABLE, 1); 2001ae64cecSChristian König } else { 2011ae64cecSChristian König ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 2021ae64cecSChristian König IH_DOORBELL_RPTR, 2031ae64cecSChristian König ENABLE, 0); 2041ae64cecSChristian König } 2051ae64cecSChristian König return ih_doorbell_rtpr; 2061ae64cecSChristian König } 2071ae64cecSChristian König 208282aae55SKen Wang /** 209282aae55SKen Wang * vega10_ih_irq_init - init and enable the interrupt ring 210282aae55SKen Wang * 211282aae55SKen Wang * @adev: amdgpu_device pointer 212282aae55SKen Wang * 213282aae55SKen Wang * Allocate a ring buffer for the interrupt controller, 214282aae55SKen Wang * enable the RLC, disable interrupts, enable the IH 215282aae55SKen Wang * ring buffer and enable it (VI). 216282aae55SKen Wang * Called at device load and reume. 217282aae55SKen Wang * Returns 0 for success, errors for failure. 218282aae55SKen Wang */ 219282aae55SKen Wang static int vega10_ih_irq_init(struct amdgpu_device *adev) 220282aae55SKen Wang { 221ad710812SChristian König struct amdgpu_ih_ring *ih; 222f9c84ae5SLe Ma u32 ih_rb_cntl, ih_chicken; 223282aae55SKen Wang int ret = 0; 224282aae55SKen Wang u32 tmp; 225282aae55SKen Wang 226282aae55SKen Wang /* disable irqs */ 227282aae55SKen Wang vega10_ih_disable_interrupts(adev); 228282aae55SKen Wang 229bf383fb6SAlex Deucher adev->nbio_funcs->ih_control(adev); 230282aae55SKen Wang 231ad710812SChristian König ih = &adev->irq.ih; 232282aae55SKen Wang /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 233ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8); 234ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff); 235282aae55SKen Wang 236ad710812SChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 237ad710812SChristian König ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl); 238ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 239ad710812SChristian König !!adev->irq.msi_enabled); 240470b4250STrigger Huang 241470b4250STrigger Huang if (amdgpu_virt_support_psp_prg_ih_reg(adev)) { 242470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 243470b4250STrigger Huang DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 244470b4250STrigger Huang return -ETIMEDOUT; 245470b4250STrigger Huang } 246470b4250STrigger Huang } else { 247b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 248470b4250STrigger Huang } 249282aae55SKen Wang 250f9c84ae5SLe Ma if (adev->asic_type == CHIP_ARCTURUS && 251f9c84ae5SLe Ma adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 252f9c84ae5SLe Ma if (adev->irq.ih.use_bus_addr) { 253f9c84ae5SLe Ma ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 254f9c84ae5SLe Ma ih_chicken |= 0x00000010; 255f9c84ae5SLe Ma WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 256f9c84ae5SLe Ma } 257f9c84ae5SLe Ma } 258f9c84ae5SLe Ma 259282aae55SKen Wang /* set the writeback address whether it's enabled or not */ 260d81f78b4SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, 261d81f78b4SChristian König lower_32_bits(ih->wptr_addr)); 262d81f78b4SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, 263d81f78b4SChristian König upper_32_bits(ih->wptr_addr) & 0xFFFF); 264282aae55SKen Wang 265282aae55SKen Wang /* set rptr, wptr to 0 */ 266b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 2671ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 268282aae55SKen Wang 2691ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, 2701ae64cecSChristian König vega10_ih_doorbell_rptr(ih)); 271282aae55SKen Wang 272ad710812SChristian König ih = &adev->irq.ih1; 273ad710812SChristian König if (ih->ring_size) { 274ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING1, ih->gpu_addr >> 8); 275ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING1, 276ad710812SChristian König (ih->gpu_addr >> 40) & 0xff); 277ad710812SChristian König 278ad710812SChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 279ad710812SChristian König ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl); 2800133690eSChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 2810133690eSChristian König WPTR_OVERFLOW_ENABLE, 0); 2820133690eSChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 2830133690eSChristian König RB_FULL_DRAIN_ENABLE, 1); 284470b4250STrigger Huang if (amdgpu_virt_support_psp_prg_ih_reg(adev)) { 285470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 286470b4250STrigger Huang ih_rb_cntl)) { 287470b4250STrigger Huang DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 288470b4250STrigger Huang return -ETIMEDOUT; 289470b4250STrigger Huang } 290470b4250STrigger Huang } else { 291ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 292470b4250STrigger Huang } 293ad710812SChristian König 294ad710812SChristian König /* set rptr, wptr to 0 */ 295ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 2961ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 2971ae64cecSChristian König 2981ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1, 2991ae64cecSChristian König vega10_ih_doorbell_rptr(ih)); 300ad710812SChristian König } 301ad710812SChristian König 302ad710812SChristian König ih = &adev->irq.ih2; 303ad710812SChristian König if (ih->ring_size) { 304ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING2, ih->gpu_addr >> 8); 305ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING2, 306ad710812SChristian König (ih->gpu_addr >> 40) & 0xff); 307ad710812SChristian König 3081ae64cecSChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 309ad710812SChristian König ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl); 310470b4250STrigger Huang 311470b4250STrigger Huang if (amdgpu_virt_support_psp_prg_ih_reg(adev)) { 312470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 313470b4250STrigger Huang ih_rb_cntl)) { 314470b4250STrigger Huang DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 315470b4250STrigger Huang return -ETIMEDOUT; 316470b4250STrigger Huang } 317470b4250STrigger Huang } else { 318ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 319470b4250STrigger Huang } 320ad710812SChristian König 321ad710812SChristian König /* set rptr, wptr to 0 */ 322ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 3231ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 3241ae64cecSChristian König 3251ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2, 3261ae64cecSChristian König vega10_ih_doorbell_rptr(ih)); 327ad710812SChristian König } 328ad710812SChristian König 329b2b7e457SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 330282aae55SKen Wang tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 331282aae55SKen Wang CLIENT18_IS_STORM_CLIENT, 1); 332b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 333282aae55SKen Wang 334b2b7e457SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 335282aae55SKen Wang tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 336b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 337282aae55SKen Wang 338282aae55SKen Wang pci_set_master(adev->pdev); 339282aae55SKen Wang 340282aae55SKen Wang /* enable interrupts */ 341282aae55SKen Wang vega10_ih_enable_interrupts(adev); 342282aae55SKen Wang 343282aae55SKen Wang return ret; 344282aae55SKen Wang } 345282aae55SKen Wang 346282aae55SKen Wang /** 347282aae55SKen Wang * vega10_ih_irq_disable - disable interrupts 348282aae55SKen Wang * 349282aae55SKen Wang * @adev: amdgpu_device pointer 350282aae55SKen Wang * 351282aae55SKen Wang * Disable interrupts on the hw (VEGA10). 352282aae55SKen Wang */ 353282aae55SKen Wang static void vega10_ih_irq_disable(struct amdgpu_device *adev) 354282aae55SKen Wang { 355282aae55SKen Wang vega10_ih_disable_interrupts(adev); 356282aae55SKen Wang 357282aae55SKen Wang /* Wait and acknowledge irq */ 358282aae55SKen Wang mdelay(1); 359282aae55SKen Wang } 360282aae55SKen Wang 361282aae55SKen Wang /** 362282aae55SKen Wang * vega10_ih_get_wptr - get the IH ring buffer wptr 363282aae55SKen Wang * 364282aae55SKen Wang * @adev: amdgpu_device pointer 365282aae55SKen Wang * 366282aae55SKen Wang * Get the IH ring buffer wptr from either the register 367282aae55SKen Wang * or the writeback memory buffer (VEGA10). Also check for 368282aae55SKen Wang * ring buffer overflow and deal with it. 369282aae55SKen Wang * Returns the value of the wptr. 370282aae55SKen Wang */ 3718bb9eb48SChristian König static u32 vega10_ih_get_wptr(struct amdgpu_device *adev, 3728bb9eb48SChristian König struct amdgpu_ih_ring *ih) 373282aae55SKen Wang { 374cf67950eSChristian König u32 wptr, reg, tmp; 375282aae55SKen Wang 376d81f78b4SChristian König wptr = le32_to_cpu(*ih->wptr_cpu); 377282aae55SKen Wang 378b8217575SChristian König if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 379b8217575SChristian König goto out; 380b8217575SChristian König 381b8217575SChristian König /* Double check that the overflow wasn't already cleared. */ 382cf67950eSChristian König 383cf67950eSChristian König if (ih == &adev->irq.ih) 384cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 385cf67950eSChristian König else if (ih == &adev->irq.ih1) 386cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 387cf67950eSChristian König else if (ih == &adev->irq.ih2) 388cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 389cf67950eSChristian König else 390cf67950eSChristian König BUG(); 391cf67950eSChristian König 392cf67950eSChristian König wptr = RREG32_NO_KIQ(reg); 393b8217575SChristian König if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 394b8217575SChristian König goto out; 395b8217575SChristian König 396282aae55SKen Wang wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 397282aae55SKen Wang 398282aae55SKen Wang /* When a ring buffer overflow happen start parsing interrupt 399282aae55SKen Wang * from the last not overwritten vector (wptr + 32). Hopefully 400282aae55SKen Wang * this should allow us to catchup. 401282aae55SKen Wang */ 4028bb9eb48SChristian König tmp = (wptr + 32) & ih->ptr_mask; 403b8217575SChristian König dev_warn(adev->dev, "IH ring buffer overflow " 404b8217575SChristian König "(0x%08X, 0x%08X, 0x%08X)\n", 4058bb9eb48SChristian König wptr, ih->rptr, tmp); 4068bb9eb48SChristian König ih->rptr = tmp; 407282aae55SKen Wang 408cf67950eSChristian König if (ih == &adev->irq.ih) 409cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 410cf67950eSChristian König else if (ih == &adev->irq.ih1) 411cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 412cf67950eSChristian König else if (ih == &adev->irq.ih2) 413cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 414cf67950eSChristian König else 415cf67950eSChristian König BUG(); 416cf67950eSChristian König 417cf67950eSChristian König tmp = RREG32_NO_KIQ(reg); 418282aae55SKen Wang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 419cf67950eSChristian König WREG32_NO_KIQ(reg, tmp); 420b8217575SChristian König 421b8217575SChristian König out: 4228bb9eb48SChristian König return (wptr & ih->ptr_mask); 423282aae55SKen Wang } 424282aae55SKen Wang 425282aae55SKen Wang /** 426282aae55SKen Wang * vega10_ih_decode_iv - decode an interrupt vector 427282aae55SKen Wang * 428282aae55SKen Wang * @adev: amdgpu_device pointer 429282aae55SKen Wang * 430282aae55SKen Wang * Decodes the interrupt vector at the current rptr 431282aae55SKen Wang * position and also advance the position. 432282aae55SKen Wang */ 433282aae55SKen Wang static void vega10_ih_decode_iv(struct amdgpu_device *adev, 4348bb9eb48SChristian König struct amdgpu_ih_ring *ih, 435282aae55SKen Wang struct amdgpu_iv_entry *entry) 436282aae55SKen Wang { 437282aae55SKen Wang /* wptr/rptr are in bytes! */ 4388bb9eb48SChristian König u32 ring_index = ih->rptr >> 2; 439282aae55SKen Wang uint32_t dw[8]; 440282aae55SKen Wang 4418bb9eb48SChristian König dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 4428bb9eb48SChristian König dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 4438bb9eb48SChristian König dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 4448bb9eb48SChristian König dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 4458bb9eb48SChristian König dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); 4468bb9eb48SChristian König dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); 4478bb9eb48SChristian König dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); 4488bb9eb48SChristian König dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); 449282aae55SKen Wang 450282aae55SKen Wang entry->client_id = dw[0] & 0xff; 451282aae55SKen Wang entry->src_id = (dw[0] >> 8) & 0xff; 452282aae55SKen Wang entry->ring_id = (dw[0] >> 16) & 0xff; 453c4f46f22SChristian König entry->vmid = (dw[0] >> 24) & 0xf; 454c4f46f22SChristian König entry->vmid_src = (dw[0] >> 31); 455282aae55SKen Wang entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); 456282aae55SKen Wang entry->timestamp_src = dw[2] >> 31; 4573816e42fSChristian König entry->pasid = dw[3] & 0xffff; 458282aae55SKen Wang entry->pasid_src = dw[3] >> 31; 459282aae55SKen Wang entry->src_data[0] = dw[4]; 460282aae55SKen Wang entry->src_data[1] = dw[5]; 461282aae55SKen Wang entry->src_data[2] = dw[6]; 462282aae55SKen Wang entry->src_data[3] = dw[7]; 463282aae55SKen Wang 464282aae55SKen Wang /* wptr/rptr are in bytes! */ 4658bb9eb48SChristian König ih->rptr += 32; 466282aae55SKen Wang } 467282aae55SKen Wang 468282aae55SKen Wang /** 46974dcfe74STrigger Huang * vega10_ih_irq_rearm - rearm IRQ if lost 47074dcfe74STrigger Huang * 47174dcfe74STrigger Huang * @adev: amdgpu_device pointer 47274dcfe74STrigger Huang * 47374dcfe74STrigger Huang */ 47474dcfe74STrigger Huang static void vega10_ih_irq_rearm(struct amdgpu_device *adev, 47574dcfe74STrigger Huang struct amdgpu_ih_ring *ih) 47674dcfe74STrigger Huang { 47774dcfe74STrigger Huang uint32_t reg_rptr = 0; 47874dcfe74STrigger Huang uint32_t v = 0; 47974dcfe74STrigger Huang uint32_t i = 0; 48074dcfe74STrigger Huang 48174dcfe74STrigger Huang if (ih == &adev->irq.ih) 48274dcfe74STrigger Huang reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 48374dcfe74STrigger Huang else if (ih == &adev->irq.ih1) 48474dcfe74STrigger Huang reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 48574dcfe74STrigger Huang else if (ih == &adev->irq.ih2) 48674dcfe74STrigger Huang reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 48774dcfe74STrigger Huang else 48874dcfe74STrigger Huang return; 48974dcfe74STrigger Huang 49074dcfe74STrigger Huang /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */ 49174dcfe74STrigger Huang for (i = 0; i < MAX_REARM_RETRY; i++) { 49274dcfe74STrigger Huang v = RREG32_NO_KIQ(reg_rptr); 49374dcfe74STrigger Huang if ((v < ih->ring_size) && (v != ih->rptr)) 49474dcfe74STrigger Huang WDOORBELL32(ih->doorbell_index, ih->rptr); 49574dcfe74STrigger Huang else 49674dcfe74STrigger Huang break; 49774dcfe74STrigger Huang } 49874dcfe74STrigger Huang } 49974dcfe74STrigger Huang 50074dcfe74STrigger Huang /** 501282aae55SKen Wang * vega10_ih_set_rptr - set the IH ring buffer rptr 502282aae55SKen Wang * 503282aae55SKen Wang * @adev: amdgpu_device pointer 504282aae55SKen Wang * 505282aae55SKen Wang * Set the IH ring buffer rptr. 506282aae55SKen Wang */ 5078bb9eb48SChristian König static void vega10_ih_set_rptr(struct amdgpu_device *adev, 5088bb9eb48SChristian König struct amdgpu_ih_ring *ih) 509282aae55SKen Wang { 5108bb9eb48SChristian König if (ih->use_doorbell) { 511282aae55SKen Wang /* XXX check if swapping is necessary on BE */ 512d81f78b4SChristian König *ih->rptr_cpu = ih->rptr; 5138bb9eb48SChristian König WDOORBELL32(ih->doorbell_index, ih->rptr); 51474dcfe74STrigger Huang 51574dcfe74STrigger Huang if (amdgpu_sriov_vf(adev)) 51674dcfe74STrigger Huang vega10_ih_irq_rearm(adev, ih); 517cf67950eSChristian König } else if (ih == &adev->irq.ih) { 5188bb9eb48SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr); 519cf67950eSChristian König } else if (ih == &adev->irq.ih1) { 520cf67950eSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, ih->rptr); 521cf67950eSChristian König } else if (ih == &adev->irq.ih2) { 522cf67950eSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, ih->rptr); 523282aae55SKen Wang } 524282aae55SKen Wang } 525282aae55SKen Wang 526cf67950eSChristian König /** 527cf67950eSChristian König * vega10_ih_self_irq - dispatch work for ring 1 and 2 528cf67950eSChristian König * 529cf67950eSChristian König * @adev: amdgpu_device pointer 530cf67950eSChristian König * @source: irq source 531cf67950eSChristian König * @entry: IV with WPTR update 532cf67950eSChristian König * 533cf67950eSChristian König * Update the WPTR from the IV and schedule work to handle the entries. 534cf67950eSChristian König */ 535cf67950eSChristian König static int vega10_ih_self_irq(struct amdgpu_device *adev, 536cf67950eSChristian König struct amdgpu_irq_src *source, 537cf67950eSChristian König struct amdgpu_iv_entry *entry) 538cf67950eSChristian König { 539cf67950eSChristian König uint32_t wptr = cpu_to_le32(entry->src_data[0]); 540cf67950eSChristian König 541cf67950eSChristian König switch (entry->ring_id) { 542cf67950eSChristian König case 1: 543cf67950eSChristian König *adev->irq.ih1.wptr_cpu = wptr; 544cf67950eSChristian König schedule_work(&adev->irq.ih1_work); 545cf67950eSChristian König break; 546cf67950eSChristian König case 2: 547cf67950eSChristian König *adev->irq.ih2.wptr_cpu = wptr; 548cf67950eSChristian König schedule_work(&adev->irq.ih2_work); 549cf67950eSChristian König break; 550cf67950eSChristian König default: break; 551cf67950eSChristian König } 552cf67950eSChristian König return 0; 553cf67950eSChristian König } 554cf67950eSChristian König 555cf67950eSChristian König static const struct amdgpu_irq_src_funcs vega10_ih_self_irq_funcs = { 556cf67950eSChristian König .process = vega10_ih_self_irq, 557cf67950eSChristian König }; 558cf67950eSChristian König 559cf67950eSChristian König static void vega10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 560cf67950eSChristian König { 561cf67950eSChristian König adev->irq.self_irq.num_types = 0; 562cf67950eSChristian König adev->irq.self_irq.funcs = &vega10_ih_self_irq_funcs; 563cf67950eSChristian König } 564cf67950eSChristian König 565282aae55SKen Wang static int vega10_ih_early_init(void *handle) 566282aae55SKen Wang { 567282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 568282aae55SKen Wang 569282aae55SKen Wang vega10_ih_set_interrupt_funcs(adev); 570cf67950eSChristian König vega10_ih_set_self_irq_funcs(adev); 571282aae55SKen Wang return 0; 572282aae55SKen Wang } 573282aae55SKen Wang 574282aae55SKen Wang static int vega10_ih_sw_init(void *handle) 575282aae55SKen Wang { 576282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 577cf67950eSChristian König int r; 578cf67950eSChristian König 579cf67950eSChristian König r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 580cf67950eSChristian König &adev->irq.self_irq); 581cf67950eSChristian König if (r) 582cf67950eSChristian König return r; 583282aae55SKen Wang 584425c3143SChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true); 585282aae55SKen Wang if (r) 586282aae55SKen Wang return r; 587282aae55SKen Wang 5881ae64cecSChristian König adev->irq.ih.use_doorbell = true; 5891ae64cecSChristian König adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 5901ae64cecSChristian König 591ad710812SChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 592ad710812SChristian König if (r) 593ad710812SChristian König return r; 594ad710812SChristian König 5951ae64cecSChristian König adev->irq.ih1.use_doorbell = true; 596b51cd19eSChristian König adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; 5971ae64cecSChristian König 598ad710812SChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 599ad710812SChristian König if (r) 600ad710812SChristian König return r; 601ad710812SChristian König 6021ae64cecSChristian König adev->irq.ih2.use_doorbell = true; 603b51cd19eSChristian König adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1; 604282aae55SKen Wang 605282aae55SKen Wang r = amdgpu_irq_init(adev); 606282aae55SKen Wang 607282aae55SKen Wang return r; 608282aae55SKen Wang } 609282aae55SKen Wang 610282aae55SKen Wang static int vega10_ih_sw_fini(void *handle) 611282aae55SKen Wang { 612282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 613282aae55SKen Wang 614282aae55SKen Wang amdgpu_irq_fini(adev); 615ad710812SChristian König amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 616ad710812SChristian König amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 617425c3143SChristian König amdgpu_ih_ring_fini(adev, &adev->irq.ih); 618282aae55SKen Wang 619282aae55SKen Wang return 0; 620282aae55SKen Wang } 621282aae55SKen Wang 622282aae55SKen Wang static int vega10_ih_hw_init(void *handle) 623282aae55SKen Wang { 624282aae55SKen Wang int r; 625282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 626282aae55SKen Wang 627282aae55SKen Wang r = vega10_ih_irq_init(adev); 628282aae55SKen Wang if (r) 629282aae55SKen Wang return r; 630282aae55SKen Wang 631282aae55SKen Wang return 0; 632282aae55SKen Wang } 633282aae55SKen Wang 634282aae55SKen Wang static int vega10_ih_hw_fini(void *handle) 635282aae55SKen Wang { 636282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 637282aae55SKen Wang 638282aae55SKen Wang vega10_ih_irq_disable(adev); 639282aae55SKen Wang 640282aae55SKen Wang return 0; 641282aae55SKen Wang } 642282aae55SKen Wang 643282aae55SKen Wang static int vega10_ih_suspend(void *handle) 644282aae55SKen Wang { 645282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 646282aae55SKen Wang 647282aae55SKen Wang return vega10_ih_hw_fini(adev); 648282aae55SKen Wang } 649282aae55SKen Wang 650282aae55SKen Wang static int vega10_ih_resume(void *handle) 651282aae55SKen Wang { 652282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 653282aae55SKen Wang 654282aae55SKen Wang return vega10_ih_hw_init(adev); 655282aae55SKen Wang } 656282aae55SKen Wang 657282aae55SKen Wang static bool vega10_ih_is_idle(void *handle) 658282aae55SKen Wang { 659282aae55SKen Wang /* todo */ 660282aae55SKen Wang return true; 661282aae55SKen Wang } 662282aae55SKen Wang 663282aae55SKen Wang static int vega10_ih_wait_for_idle(void *handle) 664282aae55SKen Wang { 665282aae55SKen Wang /* todo */ 666282aae55SKen Wang return -ETIMEDOUT; 667282aae55SKen Wang } 668282aae55SKen Wang 669282aae55SKen Wang static int vega10_ih_soft_reset(void *handle) 670282aae55SKen Wang { 671282aae55SKen Wang /* todo */ 672282aae55SKen Wang 673282aae55SKen Wang return 0; 674282aae55SKen Wang } 675282aae55SKen Wang 676282aae55SKen Wang static int vega10_ih_set_clockgating_state(void *handle, 677282aae55SKen Wang enum amd_clockgating_state state) 678282aae55SKen Wang { 679282aae55SKen Wang return 0; 680282aae55SKen Wang } 681282aae55SKen Wang 682282aae55SKen Wang static int vega10_ih_set_powergating_state(void *handle, 683282aae55SKen Wang enum amd_powergating_state state) 684282aae55SKen Wang { 685282aae55SKen Wang return 0; 686282aae55SKen Wang } 687282aae55SKen Wang 688282aae55SKen Wang const struct amd_ip_funcs vega10_ih_ip_funcs = { 689282aae55SKen Wang .name = "vega10_ih", 690282aae55SKen Wang .early_init = vega10_ih_early_init, 691282aae55SKen Wang .late_init = NULL, 692282aae55SKen Wang .sw_init = vega10_ih_sw_init, 693282aae55SKen Wang .sw_fini = vega10_ih_sw_fini, 694282aae55SKen Wang .hw_init = vega10_ih_hw_init, 695282aae55SKen Wang .hw_fini = vega10_ih_hw_fini, 696282aae55SKen Wang .suspend = vega10_ih_suspend, 697282aae55SKen Wang .resume = vega10_ih_resume, 698282aae55SKen Wang .is_idle = vega10_ih_is_idle, 699282aae55SKen Wang .wait_for_idle = vega10_ih_wait_for_idle, 700282aae55SKen Wang .soft_reset = vega10_ih_soft_reset, 701282aae55SKen Wang .set_clockgating_state = vega10_ih_set_clockgating_state, 702282aae55SKen Wang .set_powergating_state = vega10_ih_set_powergating_state, 703282aae55SKen Wang }; 704282aae55SKen Wang 705282aae55SKen Wang static const struct amdgpu_ih_funcs vega10_ih_funcs = { 706282aae55SKen Wang .get_wptr = vega10_ih_get_wptr, 707282aae55SKen Wang .decode_iv = vega10_ih_decode_iv, 708282aae55SKen Wang .set_rptr = vega10_ih_set_rptr 709282aae55SKen Wang }; 710282aae55SKen Wang 711282aae55SKen Wang static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 712282aae55SKen Wang { 713282aae55SKen Wang adev->irq.ih_funcs = &vega10_ih_funcs; 714282aae55SKen Wang } 715282aae55SKen Wang 716282aae55SKen Wang const struct amdgpu_ip_block_version vega10_ih_ip_block = 717282aae55SKen Wang { 718282aae55SKen Wang .type = AMD_IP_BLOCK_TYPE_IH, 719282aae55SKen Wang .major = 4, 720282aae55SKen Wang .minor = 0, 721282aae55SKen Wang .rev = 0, 722282aae55SKen Wang .funcs = &vega10_ih_ip_funcs, 723282aae55SKen Wang }; 724