1282aae55SKen Wang /* 2282aae55SKen Wang * Copyright 2016 Advanced Micro Devices, Inc. 3282aae55SKen Wang * 4282aae55SKen Wang * Permission is hereby granted, free of charge, to any person obtaining a 5282aae55SKen Wang * copy of this software and associated documentation files (the "Software"), 6282aae55SKen Wang * to deal in the Software without restriction, including without limitation 7282aae55SKen Wang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8282aae55SKen Wang * and/or sell copies of the Software, and to permit persons to whom the 9282aae55SKen Wang * Software is furnished to do so, subject to the following conditions: 10282aae55SKen Wang * 11282aae55SKen Wang * The above copyright notice and this permission notice shall be included in 12282aae55SKen Wang * all copies or substantial portions of the Software. 13282aae55SKen Wang * 14282aae55SKen Wang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15282aae55SKen Wang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16282aae55SKen Wang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17282aae55SKen Wang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18282aae55SKen Wang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19282aae55SKen Wang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20282aae55SKen Wang * OTHER DEALINGS IN THE SOFTWARE. 21282aae55SKen Wang * 22282aae55SKen Wang */ 2347b757fbSSam Ravnborg 2447b757fbSSam Ravnborg #include <linux/pci.h> 2547b757fbSSam Ravnborg 26282aae55SKen Wang #include "amdgpu.h" 27282aae55SKen Wang #include "amdgpu_ih.h" 28282aae55SKen Wang #include "soc15.h" 29282aae55SKen Wang 308af7454eSFeifei Xu #include "oss/osssys_4_0_offset.h" 318af7454eSFeifei Xu #include "oss/osssys_4_0_sh_mask.h" 32282aae55SKen Wang 33282aae55SKen Wang #include "soc15_common.h" 34282aae55SKen Wang #include "vega10_ih.h" 35282aae55SKen Wang 3674dcfe74STrigger Huang #define MAX_REARM_RETRY 10 37282aae55SKen Wang 38282aae55SKen Wang static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 39282aae55SKen Wang 40282aae55SKen Wang /** 411ebb4841SHawking Zhang * vega10_ih_init_register_offset - Initialize register offset for ih rings 421ebb4841SHawking Zhang * 431ebb4841SHawking Zhang * @adev: amdgpu_device pointer 441ebb4841SHawking Zhang * 451ebb4841SHawking Zhang * Initialize register offset ih rings (VEGA10). 461ebb4841SHawking Zhang */ 471ebb4841SHawking Zhang static void vega10_ih_init_register_offset(struct amdgpu_device *adev) 481ebb4841SHawking Zhang { 491ebb4841SHawking Zhang struct amdgpu_ih_regs *ih_regs; 501ebb4841SHawking Zhang 511ebb4841SHawking Zhang if (adev->irq.ih.ring_size) { 521ebb4841SHawking Zhang ih_regs = &adev->irq.ih.ih_regs; 531ebb4841SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); 541ebb4841SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); 551ebb4841SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 561ebb4841SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 571ebb4841SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 581ebb4841SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); 591ebb4841SHawking Zhang ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); 601ebb4841SHawking Zhang ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); 611ebb4841SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; 621ebb4841SHawking Zhang } 631ebb4841SHawking Zhang 641ebb4841SHawking Zhang if (adev->irq.ih1.ring_size) { 651ebb4841SHawking Zhang ih_regs = &adev->irq.ih1.ih_regs; 661ebb4841SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); 671ebb4841SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); 681ebb4841SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 691ebb4841SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 701ebb4841SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 711ebb4841SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1); 721ebb4841SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; 731ebb4841SHawking Zhang } 741ebb4841SHawking Zhang 751ebb4841SHawking Zhang if (adev->irq.ih2.ring_size) { 761ebb4841SHawking Zhang ih_regs = &adev->irq.ih2.ih_regs; 771ebb4841SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); 781ebb4841SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2); 791ebb4841SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 801ebb4841SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 811ebb4841SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 821ebb4841SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2); 831ebb4841SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2; 841ebb4841SHawking Zhang } 851ebb4841SHawking Zhang } 861ebb4841SHawking Zhang 871ebb4841SHawking Zhang /** 88282aae55SKen Wang * vega10_ih_enable_interrupts - Enable the interrupt ring buffer 89282aae55SKen Wang * 90282aae55SKen Wang * @adev: amdgpu_device pointer 91282aae55SKen Wang * 92282aae55SKen Wang * Enable the interrupt ring buffer (VEGA10). 93282aae55SKen Wang */ 94282aae55SKen Wang static void vega10_ih_enable_interrupts(struct amdgpu_device *adev) 95282aae55SKen Wang { 96b2b7e457SHawking Zhang u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 97282aae55SKen Wang 98282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); 99282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); 1004cd4c5c0SMonk Liu if (amdgpu_sriov_vf(adev)) { 101470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 102470b4250STrigger Huang DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 103470b4250STrigger Huang return; 104470b4250STrigger Huang } 105470b4250STrigger Huang } else { 106b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 107470b4250STrigger Huang } 108282aae55SKen Wang adev->irq.ih.enabled = true; 109ad710812SChristian König 110ad710812SChristian König if (adev->irq.ih1.ring_size) { 111ad710812SChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 112ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 113ad710812SChristian König RB_ENABLE, 1); 1144cd4c5c0SMonk Liu if (amdgpu_sriov_vf(adev)) { 115470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 116470b4250STrigger Huang ih_rb_cntl)) { 117470b4250STrigger Huang DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 118470b4250STrigger Huang return; 119470b4250STrigger Huang } 120470b4250STrigger Huang } else { 121ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 122470b4250STrigger Huang } 123ad710812SChristian König adev->irq.ih1.enabled = true; 124ad710812SChristian König } 125ad710812SChristian König 126ad710812SChristian König if (adev->irq.ih2.ring_size) { 127ad710812SChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 128ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 129ad710812SChristian König RB_ENABLE, 1); 1304cd4c5c0SMonk Liu if (amdgpu_sriov_vf(adev)) { 131470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 132470b4250STrigger Huang ih_rb_cntl)) { 133470b4250STrigger Huang DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 134470b4250STrigger Huang return; 135470b4250STrigger Huang } 136470b4250STrigger Huang } else { 137ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 138470b4250STrigger Huang } 139ad710812SChristian König adev->irq.ih2.enabled = true; 140ad710812SChristian König } 14147509189SChristian König 14247509189SChristian König if (adev->irq.ih_soft.ring_size) 14347509189SChristian König adev->irq.ih_soft.enabled = true; 144282aae55SKen Wang } 145282aae55SKen Wang 146282aae55SKen Wang /** 147282aae55SKen Wang * vega10_ih_disable_interrupts - Disable the interrupt ring buffer 148282aae55SKen Wang * 149282aae55SKen Wang * @adev: amdgpu_device pointer 150282aae55SKen Wang * 151282aae55SKen Wang * Disable the interrupt ring buffer (VEGA10). 152282aae55SKen Wang */ 153282aae55SKen Wang static void vega10_ih_disable_interrupts(struct amdgpu_device *adev) 154282aae55SKen Wang { 155b2b7e457SHawking Zhang u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 156282aae55SKen Wang 157282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); 158282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); 1594cd4c5c0SMonk Liu if (amdgpu_sriov_vf(adev)) { 160470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 161470b4250STrigger Huang DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 162470b4250STrigger Huang return; 163470b4250STrigger Huang } 164470b4250STrigger Huang } else { 165b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 166470b4250STrigger Huang } 167470b4250STrigger Huang 168282aae55SKen Wang /* set rptr, wptr to 0 */ 169b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 170b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 171282aae55SKen Wang adev->irq.ih.enabled = false; 172282aae55SKen Wang adev->irq.ih.rptr = 0; 173ad710812SChristian König 174ad710812SChristian König if (adev->irq.ih1.ring_size) { 175ad710812SChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 176ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 177ad710812SChristian König RB_ENABLE, 0); 1784cd4c5c0SMonk Liu if (amdgpu_sriov_vf(adev)) { 179470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 180470b4250STrigger Huang ih_rb_cntl)) { 181470b4250STrigger Huang DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 182470b4250STrigger Huang return; 183470b4250STrigger Huang } 184470b4250STrigger Huang } else { 185ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 186470b4250STrigger Huang } 187ad710812SChristian König /* set rptr, wptr to 0 */ 188ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 189ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 190ad710812SChristian König adev->irq.ih1.enabled = false; 191ad710812SChristian König adev->irq.ih1.rptr = 0; 192ad710812SChristian König } 193ad710812SChristian König 194ad710812SChristian König if (adev->irq.ih2.ring_size) { 195ad710812SChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 196ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 197ad710812SChristian König RB_ENABLE, 0); 1984cd4c5c0SMonk Liu if (amdgpu_sriov_vf(adev)) { 199470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 200470b4250STrigger Huang ih_rb_cntl)) { 201470b4250STrigger Huang DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 202470b4250STrigger Huang return; 203470b4250STrigger Huang } 204470b4250STrigger Huang } else { 205ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 206470b4250STrigger Huang } 207470b4250STrigger Huang 208ad710812SChristian König /* set rptr, wptr to 0 */ 209ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 210ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 211ad710812SChristian König adev->irq.ih2.enabled = false; 212ad710812SChristian König adev->irq.ih2.rptr = 0; 213ad710812SChristian König } 214ad710812SChristian König } 215ad710812SChristian König 216c7375032SHawking Zhang /** 217c7375032SHawking Zhang * vega10_ih_toggle_ring_interrupts - toggle the interrupt ring buffer 218c7375032SHawking Zhang * 219c7375032SHawking Zhang * @adev: amdgpu_device pointer 220c7375032SHawking Zhang * @ih: amdgpu_ih_ring pointet 221c7375032SHawking Zhang * @enable: true - enable the interrupts, false - disable the interrupts 222c7375032SHawking Zhang * 223c7375032SHawking Zhang * Toggle the interrupt ring buffer (VEGA10) 224c7375032SHawking Zhang */ 225c7375032SHawking Zhang static int vega10_ih_toggle_ring_interrupts(struct amdgpu_device *adev, 226c7375032SHawking Zhang struct amdgpu_ih_ring *ih, 227c7375032SHawking Zhang bool enable) 228c7375032SHawking Zhang { 229c7375032SHawking Zhang struct amdgpu_ih_regs *ih_regs; 230c7375032SHawking Zhang uint32_t tmp; 231c7375032SHawking Zhang 232c7375032SHawking Zhang ih_regs = &ih->ih_regs; 233c7375032SHawking Zhang 234c7375032SHawking Zhang tmp = RREG32(ih_regs->ih_rb_cntl); 235c7375032SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); 236c7375032SHawking Zhang /* enable_intr field is only valid in ring0 */ 237c7375032SHawking Zhang if (ih == &adev->irq.ih) 238c7375032SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); 239c7375032SHawking Zhang if (amdgpu_sriov_vf(adev)) { 240c7375032SHawking Zhang if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 241c7375032SHawking Zhang dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 242c7375032SHawking Zhang return -ETIMEDOUT; 243c7375032SHawking Zhang } 244c7375032SHawking Zhang } else { 245c7375032SHawking Zhang WREG32(ih_regs->ih_rb_cntl, tmp); 246c7375032SHawking Zhang } 247c7375032SHawking Zhang 248c7375032SHawking Zhang if (enable) { 249c7375032SHawking Zhang ih->enabled = true; 250c7375032SHawking Zhang } else { 251c7375032SHawking Zhang /* set rptr, wptr to 0 */ 252c7375032SHawking Zhang WREG32(ih_regs->ih_rb_rptr, 0); 253c7375032SHawking Zhang WREG32(ih_regs->ih_rb_wptr, 0); 254c7375032SHawking Zhang ih->enabled = false; 255c7375032SHawking Zhang ih->rptr = 0; 256c7375032SHawking Zhang } 257c7375032SHawking Zhang 258c7375032SHawking Zhang return 0; 259c7375032SHawking Zhang } 260c7375032SHawking Zhang 261ad710812SChristian König static uint32_t vega10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 262ad710812SChristian König { 263ad710812SChristian König int rb_bufsz = order_base_2(ih->ring_size / 4); 264ad710812SChristian König 265ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 266ad710812SChristian König MC_SPACE, ih->use_bus_addr ? 1 : 4); 267ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 268ad710812SChristian König WPTR_OVERFLOW_CLEAR, 1); 269ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 270ad710812SChristian König WPTR_OVERFLOW_ENABLE, 1); 271ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 272ad710812SChristian König /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 273ad710812SChristian König * value is written to memory 274ad710812SChristian König */ 275ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 276ad710812SChristian König WPTR_WRITEBACK_ENABLE, 1); 277ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 278ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 279ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 280ad710812SChristian König 281ad710812SChristian König return ih_rb_cntl; 282282aae55SKen Wang } 283282aae55SKen Wang 2841ae64cecSChristian König static uint32_t vega10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 2851ae64cecSChristian König { 2861ae64cecSChristian König u32 ih_doorbell_rtpr = 0; 2871ae64cecSChristian König 2881ae64cecSChristian König if (ih->use_doorbell) { 2891ae64cecSChristian König ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 2901ae64cecSChristian König IH_DOORBELL_RPTR, OFFSET, 2911ae64cecSChristian König ih->doorbell_index); 2921ae64cecSChristian König ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 2931ae64cecSChristian König IH_DOORBELL_RPTR, 2941ae64cecSChristian König ENABLE, 1); 2951ae64cecSChristian König } else { 2961ae64cecSChristian König ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 2971ae64cecSChristian König IH_DOORBELL_RPTR, 2981ae64cecSChristian König ENABLE, 0); 2991ae64cecSChristian König } 3001ae64cecSChristian König return ih_doorbell_rtpr; 3011ae64cecSChristian König } 3021ae64cecSChristian König 303282aae55SKen Wang /** 304ffa02126SHawking Zhang * vega10_ih_enable_ring - enable an ih ring buffer 305ffa02126SHawking Zhang * 306ffa02126SHawking Zhang * @adev: amdgpu_device pointer 307ffa02126SHawking Zhang * @ih: amdgpu_ih_ring pointer 308ffa02126SHawking Zhang * 309ffa02126SHawking Zhang * Enable an ih ring buffer (VEGA10) 310ffa02126SHawking Zhang */ 311ffa02126SHawking Zhang static int vega10_ih_enable_ring(struct amdgpu_device *adev, 312ffa02126SHawking Zhang struct amdgpu_ih_ring *ih) 313ffa02126SHawking Zhang { 314ffa02126SHawking Zhang struct amdgpu_ih_regs *ih_regs; 315ffa02126SHawking Zhang uint32_t tmp; 316ffa02126SHawking Zhang 317ffa02126SHawking Zhang ih_regs = &ih->ih_regs; 318ffa02126SHawking Zhang 319ffa02126SHawking Zhang /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 320ffa02126SHawking Zhang WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); 321ffa02126SHawking Zhang WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); 322ffa02126SHawking Zhang 323ffa02126SHawking Zhang tmp = RREG32(ih_regs->ih_rb_cntl); 324ffa02126SHawking Zhang tmp = vega10_ih_rb_cntl(ih, tmp); 325ffa02126SHawking Zhang if (ih == &adev->irq.ih) 326ffa02126SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); 327ffa02126SHawking Zhang if (ih == &adev->irq.ih1) { 328ffa02126SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0); 329ffa02126SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); 330ffa02126SHawking Zhang } 331ffa02126SHawking Zhang if (amdgpu_sriov_vf(adev)) { 332ffa02126SHawking Zhang if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 333ffa02126SHawking Zhang dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 334ffa02126SHawking Zhang return -ETIMEDOUT; 335ffa02126SHawking Zhang } 336ffa02126SHawking Zhang } else { 337ffa02126SHawking Zhang WREG32(ih_regs->ih_rb_cntl, tmp); 338ffa02126SHawking Zhang } 339ffa02126SHawking Zhang 340ffa02126SHawking Zhang if (ih == &adev->irq.ih) { 341ffa02126SHawking Zhang /* set the ih ring 0 writeback address whether it's enabled or not */ 342ffa02126SHawking Zhang WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); 343ffa02126SHawking Zhang WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); 344ffa02126SHawking Zhang } 345ffa02126SHawking Zhang 346ffa02126SHawking Zhang /* set rptr, wptr to 0 */ 347ffa02126SHawking Zhang WREG32(ih_regs->ih_rb_wptr, 0); 348ffa02126SHawking Zhang WREG32(ih_regs->ih_rb_rptr, 0); 349ffa02126SHawking Zhang 350ffa02126SHawking Zhang WREG32(ih_regs->ih_doorbell_rptr, vega10_ih_doorbell_rptr(ih)); 351ffa02126SHawking Zhang 352ffa02126SHawking Zhang return 0; 353ffa02126SHawking Zhang } 354ffa02126SHawking Zhang 355ffa02126SHawking Zhang /** 356282aae55SKen Wang * vega10_ih_irq_init - init and enable the interrupt ring 357282aae55SKen Wang * 358282aae55SKen Wang * @adev: amdgpu_device pointer 359282aae55SKen Wang * 360282aae55SKen Wang * Allocate a ring buffer for the interrupt controller, 361282aae55SKen Wang * enable the RLC, disable interrupts, enable the IH 362282aae55SKen Wang * ring buffer and enable it (VI). 363282aae55SKen Wang * Called at device load and reume. 364282aae55SKen Wang * Returns 0 for success, errors for failure. 365282aae55SKen Wang */ 366282aae55SKen Wang static int vega10_ih_irq_init(struct amdgpu_device *adev) 367282aae55SKen Wang { 368ad710812SChristian König struct amdgpu_ih_ring *ih; 369f9c84ae5SLe Ma u32 ih_rb_cntl, ih_chicken; 370282aae55SKen Wang int ret = 0; 371282aae55SKen Wang u32 tmp; 372282aae55SKen Wang 373282aae55SKen Wang /* disable irqs */ 374282aae55SKen Wang vega10_ih_disable_interrupts(adev); 375282aae55SKen Wang 376bebc0762SHawking Zhang adev->nbio.funcs->ih_control(adev); 377282aae55SKen Wang 378ad710812SChristian König ih = &adev->irq.ih; 379282aae55SKen Wang /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 380ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8); 381ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff); 382282aae55SKen Wang 383ad710812SChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 384ad710812SChristian König ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl); 385ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 386ad710812SChristian König !!adev->irq.msi_enabled); 3874cd4c5c0SMonk Liu if (amdgpu_sriov_vf(adev)) { 388470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 389470b4250STrigger Huang DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 390470b4250STrigger Huang return -ETIMEDOUT; 391470b4250STrigger Huang } 392470b4250STrigger Huang } else { 393b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 394470b4250STrigger Huang } 395282aae55SKen Wang 39625344d7eSZhigang Luo if ((adev->asic_type == CHIP_ARCTURUS && 39725344d7eSZhigang Luo adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) || 39825344d7eSZhigang Luo adev->asic_type == CHIP_RENOIR) { 39925344d7eSZhigang Luo ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 40025344d7eSZhigang Luo if (adev->irq.ih.use_bus_addr) { 40125344d7eSZhigang Luo ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 40225344d7eSZhigang Luo MC_SPACE_GPA_ENABLE, 1); 40325344d7eSZhigang Luo } else { 40425344d7eSZhigang Luo ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 40525344d7eSZhigang Luo MC_SPACE_FBPA_ENABLE, 1); 40625344d7eSZhigang Luo } 407f9c84ae5SLe Ma WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 40825344d7eSZhigang Luo } 409f9c84ae5SLe Ma 410282aae55SKen Wang /* set the writeback address whether it's enabled or not */ 411d81f78b4SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, 412d81f78b4SChristian König lower_32_bits(ih->wptr_addr)); 413d81f78b4SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, 414d81f78b4SChristian König upper_32_bits(ih->wptr_addr) & 0xFFFF); 415282aae55SKen Wang 416282aae55SKen Wang /* set rptr, wptr to 0 */ 417b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 4181ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 419282aae55SKen Wang 4201ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, 4211ae64cecSChristian König vega10_ih_doorbell_rptr(ih)); 422282aae55SKen Wang 423ad710812SChristian König ih = &adev->irq.ih1; 424ad710812SChristian König if (ih->ring_size) { 425ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING1, ih->gpu_addr >> 8); 426ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING1, 427ad710812SChristian König (ih->gpu_addr >> 40) & 0xff); 428ad710812SChristian König 429ad710812SChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 430ad710812SChristian König ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl); 4310133690eSChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 4320133690eSChristian König WPTR_OVERFLOW_ENABLE, 0); 4330133690eSChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 4340133690eSChristian König RB_FULL_DRAIN_ENABLE, 1); 4354cd4c5c0SMonk Liu if (amdgpu_sriov_vf(adev)) { 436470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 437470b4250STrigger Huang ih_rb_cntl)) { 438470b4250STrigger Huang DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 439470b4250STrigger Huang return -ETIMEDOUT; 440470b4250STrigger Huang } 441470b4250STrigger Huang } else { 442ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 443470b4250STrigger Huang } 444ad710812SChristian König 445ad710812SChristian König /* set rptr, wptr to 0 */ 446ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 4471ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 4481ae64cecSChristian König 4491ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1, 4501ae64cecSChristian König vega10_ih_doorbell_rptr(ih)); 451ad710812SChristian König } 452ad710812SChristian König 453ad710812SChristian König ih = &adev->irq.ih2; 454ad710812SChristian König if (ih->ring_size) { 455ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING2, ih->gpu_addr >> 8); 456ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING2, 457ad710812SChristian König (ih->gpu_addr >> 40) & 0xff); 458ad710812SChristian König 4591ae64cecSChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 460ad710812SChristian König ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl); 461470b4250STrigger Huang 4624cd4c5c0SMonk Liu if (amdgpu_sriov_vf(adev)) { 463470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 464470b4250STrigger Huang ih_rb_cntl)) { 465470b4250STrigger Huang DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 466470b4250STrigger Huang return -ETIMEDOUT; 467470b4250STrigger Huang } 468470b4250STrigger Huang } else { 469ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 470470b4250STrigger Huang } 471ad710812SChristian König 472ad710812SChristian König /* set rptr, wptr to 0 */ 473ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 4741ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 4751ae64cecSChristian König 4761ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2, 4771ae64cecSChristian König vega10_ih_doorbell_rptr(ih)); 478ad710812SChristian König } 479ad710812SChristian König 480b2b7e457SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 481282aae55SKen Wang tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 482282aae55SKen Wang CLIENT18_IS_STORM_CLIENT, 1); 483b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 484282aae55SKen Wang 485b2b7e457SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 486282aae55SKen Wang tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 487b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 488282aae55SKen Wang 489282aae55SKen Wang pci_set_master(adev->pdev); 490282aae55SKen Wang 491282aae55SKen Wang /* enable interrupts */ 492282aae55SKen Wang vega10_ih_enable_interrupts(adev); 493282aae55SKen Wang 494282aae55SKen Wang return ret; 495282aae55SKen Wang } 496282aae55SKen Wang 497282aae55SKen Wang /** 498282aae55SKen Wang * vega10_ih_irq_disable - disable interrupts 499282aae55SKen Wang * 500282aae55SKen Wang * @adev: amdgpu_device pointer 501282aae55SKen Wang * 502282aae55SKen Wang * Disable interrupts on the hw (VEGA10). 503282aae55SKen Wang */ 504282aae55SKen Wang static void vega10_ih_irq_disable(struct amdgpu_device *adev) 505282aae55SKen Wang { 506282aae55SKen Wang vega10_ih_disable_interrupts(adev); 507282aae55SKen Wang 508282aae55SKen Wang /* Wait and acknowledge irq */ 509282aae55SKen Wang mdelay(1); 510282aae55SKen Wang } 511282aae55SKen Wang 512282aae55SKen Wang /** 513282aae55SKen Wang * vega10_ih_get_wptr - get the IH ring buffer wptr 514282aae55SKen Wang * 515282aae55SKen Wang * @adev: amdgpu_device pointer 5165162e40eSLee Jones * @ih: IH ring buffer to fetch wptr 517282aae55SKen Wang * 518282aae55SKen Wang * Get the IH ring buffer wptr from either the register 519282aae55SKen Wang * or the writeback memory buffer (VEGA10). Also check for 520282aae55SKen Wang * ring buffer overflow and deal with it. 521282aae55SKen Wang * Returns the value of the wptr. 522282aae55SKen Wang */ 5238bb9eb48SChristian König static u32 vega10_ih_get_wptr(struct amdgpu_device *adev, 5248bb9eb48SChristian König struct amdgpu_ih_ring *ih) 525282aae55SKen Wang { 526cf67950eSChristian König u32 wptr, reg, tmp; 527282aae55SKen Wang 528d81f78b4SChristian König wptr = le32_to_cpu(*ih->wptr_cpu); 529282aae55SKen Wang 530b8217575SChristian König if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 531b8217575SChristian König goto out; 532b8217575SChristian König 533b8217575SChristian König /* Double check that the overflow wasn't already cleared. */ 534cf67950eSChristian König 535cf67950eSChristian König if (ih == &adev->irq.ih) 536cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 537cf67950eSChristian König else if (ih == &adev->irq.ih1) 538cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 539cf67950eSChristian König else if (ih == &adev->irq.ih2) 540cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 541cf67950eSChristian König else 542cf67950eSChristian König BUG(); 543cf67950eSChristian König 544cf67950eSChristian König wptr = RREG32_NO_KIQ(reg); 545b8217575SChristian König if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 546b8217575SChristian König goto out; 547b8217575SChristian König 548282aae55SKen Wang wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 549282aae55SKen Wang 550282aae55SKen Wang /* When a ring buffer overflow happen start parsing interrupt 551282aae55SKen Wang * from the last not overwritten vector (wptr + 32). Hopefully 552282aae55SKen Wang * this should allow us to catchup. 553282aae55SKen Wang */ 5548bb9eb48SChristian König tmp = (wptr + 32) & ih->ptr_mask; 555b8217575SChristian König dev_warn(adev->dev, "IH ring buffer overflow " 556b8217575SChristian König "(0x%08X, 0x%08X, 0x%08X)\n", 5578bb9eb48SChristian König wptr, ih->rptr, tmp); 5588bb9eb48SChristian König ih->rptr = tmp; 559282aae55SKen Wang 560cf67950eSChristian König if (ih == &adev->irq.ih) 561cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 562cf67950eSChristian König else if (ih == &adev->irq.ih1) 563cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 564cf67950eSChristian König else if (ih == &adev->irq.ih2) 565cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 566cf67950eSChristian König else 567cf67950eSChristian König BUG(); 568cf67950eSChristian König 569cf67950eSChristian König tmp = RREG32_NO_KIQ(reg); 570282aae55SKen Wang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 571cf67950eSChristian König WREG32_NO_KIQ(reg, tmp); 572b8217575SChristian König 573b8217575SChristian König out: 5748bb9eb48SChristian König return (wptr & ih->ptr_mask); 575282aae55SKen Wang } 576282aae55SKen Wang 577282aae55SKen Wang /** 578282aae55SKen Wang * vega10_ih_decode_iv - decode an interrupt vector 579282aae55SKen Wang * 580282aae55SKen Wang * @adev: amdgpu_device pointer 5815162e40eSLee Jones * @ih: IH ring buffer to decode 5825162e40eSLee Jones * @entry: IV entry to place decoded information into 583282aae55SKen Wang * 584282aae55SKen Wang * Decodes the interrupt vector at the current rptr 585282aae55SKen Wang * position and also advance the position. 586282aae55SKen Wang */ 587282aae55SKen Wang static void vega10_ih_decode_iv(struct amdgpu_device *adev, 5888bb9eb48SChristian König struct amdgpu_ih_ring *ih, 589282aae55SKen Wang struct amdgpu_iv_entry *entry) 590282aae55SKen Wang { 591282aae55SKen Wang /* wptr/rptr are in bytes! */ 5928bb9eb48SChristian König u32 ring_index = ih->rptr >> 2; 593282aae55SKen Wang uint32_t dw[8]; 594282aae55SKen Wang 5958bb9eb48SChristian König dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 5968bb9eb48SChristian König dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 5978bb9eb48SChristian König dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 5988bb9eb48SChristian König dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 5998bb9eb48SChristian König dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); 6008bb9eb48SChristian König dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); 6018bb9eb48SChristian König dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); 6028bb9eb48SChristian König dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); 603282aae55SKen Wang 604282aae55SKen Wang entry->client_id = dw[0] & 0xff; 605282aae55SKen Wang entry->src_id = (dw[0] >> 8) & 0xff; 606282aae55SKen Wang entry->ring_id = (dw[0] >> 16) & 0xff; 607c4f46f22SChristian König entry->vmid = (dw[0] >> 24) & 0xf; 608c4f46f22SChristian König entry->vmid_src = (dw[0] >> 31); 609282aae55SKen Wang entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); 610282aae55SKen Wang entry->timestamp_src = dw[2] >> 31; 6113816e42fSChristian König entry->pasid = dw[3] & 0xffff; 612282aae55SKen Wang entry->pasid_src = dw[3] >> 31; 613282aae55SKen Wang entry->src_data[0] = dw[4]; 614282aae55SKen Wang entry->src_data[1] = dw[5]; 615282aae55SKen Wang entry->src_data[2] = dw[6]; 616282aae55SKen Wang entry->src_data[3] = dw[7]; 617282aae55SKen Wang 618282aae55SKen Wang /* wptr/rptr are in bytes! */ 6198bb9eb48SChristian König ih->rptr += 32; 620282aae55SKen Wang } 621282aae55SKen Wang 622282aae55SKen Wang /** 62374dcfe74STrigger Huang * vega10_ih_irq_rearm - rearm IRQ if lost 62474dcfe74STrigger Huang * 62574dcfe74STrigger Huang * @adev: amdgpu_device pointer 6265162e40eSLee Jones * @ih: IH ring to match 62774dcfe74STrigger Huang * 62874dcfe74STrigger Huang */ 62974dcfe74STrigger Huang static void vega10_ih_irq_rearm(struct amdgpu_device *adev, 63074dcfe74STrigger Huang struct amdgpu_ih_ring *ih) 63174dcfe74STrigger Huang { 63274dcfe74STrigger Huang uint32_t reg_rptr = 0; 63374dcfe74STrigger Huang uint32_t v = 0; 63474dcfe74STrigger Huang uint32_t i = 0; 63574dcfe74STrigger Huang 63674dcfe74STrigger Huang if (ih == &adev->irq.ih) 63774dcfe74STrigger Huang reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 63874dcfe74STrigger Huang else if (ih == &adev->irq.ih1) 63974dcfe74STrigger Huang reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 64074dcfe74STrigger Huang else if (ih == &adev->irq.ih2) 64174dcfe74STrigger Huang reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 64274dcfe74STrigger Huang else 64374dcfe74STrigger Huang return; 64474dcfe74STrigger Huang 64574dcfe74STrigger Huang /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */ 64674dcfe74STrigger Huang for (i = 0; i < MAX_REARM_RETRY; i++) { 64774dcfe74STrigger Huang v = RREG32_NO_KIQ(reg_rptr); 64874dcfe74STrigger Huang if ((v < ih->ring_size) && (v != ih->rptr)) 64974dcfe74STrigger Huang WDOORBELL32(ih->doorbell_index, ih->rptr); 65074dcfe74STrigger Huang else 65174dcfe74STrigger Huang break; 65274dcfe74STrigger Huang } 65374dcfe74STrigger Huang } 65474dcfe74STrigger Huang 65574dcfe74STrigger Huang /** 656282aae55SKen Wang * vega10_ih_set_rptr - set the IH ring buffer rptr 657282aae55SKen Wang * 658282aae55SKen Wang * @adev: amdgpu_device pointer 6595162e40eSLee Jones * @ih: IH ring buffer to set rptr 660282aae55SKen Wang * 661282aae55SKen Wang * Set the IH ring buffer rptr. 662282aae55SKen Wang */ 6638bb9eb48SChristian König static void vega10_ih_set_rptr(struct amdgpu_device *adev, 6648bb9eb48SChristian König struct amdgpu_ih_ring *ih) 665282aae55SKen Wang { 6668bb9eb48SChristian König if (ih->use_doorbell) { 667282aae55SKen Wang /* XXX check if swapping is necessary on BE */ 668d81f78b4SChristian König *ih->rptr_cpu = ih->rptr; 6698bb9eb48SChristian König WDOORBELL32(ih->doorbell_index, ih->rptr); 67074dcfe74STrigger Huang 67174dcfe74STrigger Huang if (amdgpu_sriov_vf(adev)) 67274dcfe74STrigger Huang vega10_ih_irq_rearm(adev, ih); 673cf67950eSChristian König } else if (ih == &adev->irq.ih) { 6748bb9eb48SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr); 675cf67950eSChristian König } else if (ih == &adev->irq.ih1) { 676cf67950eSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, ih->rptr); 677cf67950eSChristian König } else if (ih == &adev->irq.ih2) { 678cf67950eSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, ih->rptr); 679282aae55SKen Wang } 680282aae55SKen Wang } 681282aae55SKen Wang 682cf67950eSChristian König /** 683cf67950eSChristian König * vega10_ih_self_irq - dispatch work for ring 1 and 2 684cf67950eSChristian König * 685cf67950eSChristian König * @adev: amdgpu_device pointer 686cf67950eSChristian König * @source: irq source 687cf67950eSChristian König * @entry: IV with WPTR update 688cf67950eSChristian König * 689cf67950eSChristian König * Update the WPTR from the IV and schedule work to handle the entries. 690cf67950eSChristian König */ 691cf67950eSChristian König static int vega10_ih_self_irq(struct amdgpu_device *adev, 692cf67950eSChristian König struct amdgpu_irq_src *source, 693cf67950eSChristian König struct amdgpu_iv_entry *entry) 694cf67950eSChristian König { 695cf67950eSChristian König uint32_t wptr = cpu_to_le32(entry->src_data[0]); 696cf67950eSChristian König 697cf67950eSChristian König switch (entry->ring_id) { 698cf67950eSChristian König case 1: 699cf67950eSChristian König *adev->irq.ih1.wptr_cpu = wptr; 700cf67950eSChristian König schedule_work(&adev->irq.ih1_work); 701cf67950eSChristian König break; 702cf67950eSChristian König case 2: 703cf67950eSChristian König *adev->irq.ih2.wptr_cpu = wptr; 704cf67950eSChristian König schedule_work(&adev->irq.ih2_work); 705cf67950eSChristian König break; 706cf67950eSChristian König default: break; 707cf67950eSChristian König } 708cf67950eSChristian König return 0; 709cf67950eSChristian König } 710cf67950eSChristian König 711cf67950eSChristian König static const struct amdgpu_irq_src_funcs vega10_ih_self_irq_funcs = { 712cf67950eSChristian König .process = vega10_ih_self_irq, 713cf67950eSChristian König }; 714cf67950eSChristian König 715cf67950eSChristian König static void vega10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 716cf67950eSChristian König { 717cf67950eSChristian König adev->irq.self_irq.num_types = 0; 718cf67950eSChristian König adev->irq.self_irq.funcs = &vega10_ih_self_irq_funcs; 719cf67950eSChristian König } 720cf67950eSChristian König 721282aae55SKen Wang static int vega10_ih_early_init(void *handle) 722282aae55SKen Wang { 723282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 724282aae55SKen Wang 725282aae55SKen Wang vega10_ih_set_interrupt_funcs(adev); 726cf67950eSChristian König vega10_ih_set_self_irq_funcs(adev); 727282aae55SKen Wang return 0; 728282aae55SKen Wang } 729282aae55SKen Wang 730282aae55SKen Wang static int vega10_ih_sw_init(void *handle) 731282aae55SKen Wang { 732282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 733cf67950eSChristian König int r; 734cf67950eSChristian König 735cf67950eSChristian König r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 736cf67950eSChristian König &adev->irq.self_irq); 737cf67950eSChristian König if (r) 738cf67950eSChristian König return r; 739282aae55SKen Wang 740425c3143SChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true); 741282aae55SKen Wang if (r) 742282aae55SKen Wang return r; 743282aae55SKen Wang 7441ae64cecSChristian König adev->irq.ih.use_doorbell = true; 7451ae64cecSChristian König adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 7461ae64cecSChristian König 747ad710812SChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 748ad710812SChristian König if (r) 749ad710812SChristian König return r; 750ad710812SChristian König 7511ae64cecSChristian König adev->irq.ih1.use_doorbell = true; 752b51cd19eSChristian König adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; 7531ae64cecSChristian König 754ad710812SChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 755ad710812SChristian König if (r) 756ad710812SChristian König return r; 757ad710812SChristian König 7581ae64cecSChristian König adev->irq.ih2.use_doorbell = true; 759b51cd19eSChristian König adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1; 760282aae55SKen Wang 761*f0594717SHawking Zhang /* initialize ih control registers offset */ 762*f0594717SHawking Zhang vega10_ih_init_register_offset(adev); 763*f0594717SHawking Zhang 76447509189SChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); 76547509189SChristian König if (r) 76647509189SChristian König return r; 76747509189SChristian König 768282aae55SKen Wang r = amdgpu_irq_init(adev); 769282aae55SKen Wang 770282aae55SKen Wang return r; 771282aae55SKen Wang } 772282aae55SKen Wang 773282aae55SKen Wang static int vega10_ih_sw_fini(void *handle) 774282aae55SKen Wang { 775282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 776282aae55SKen Wang 777282aae55SKen Wang amdgpu_irq_fini(adev); 778ad710812SChristian König amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 779ad710812SChristian König amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 780425c3143SChristian König amdgpu_ih_ring_fini(adev, &adev->irq.ih); 781282aae55SKen Wang 782282aae55SKen Wang return 0; 783282aae55SKen Wang } 784282aae55SKen Wang 785282aae55SKen Wang static int vega10_ih_hw_init(void *handle) 786282aae55SKen Wang { 787282aae55SKen Wang int r; 788282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 789282aae55SKen Wang 790282aae55SKen Wang r = vega10_ih_irq_init(adev); 791282aae55SKen Wang if (r) 792282aae55SKen Wang return r; 793282aae55SKen Wang 794282aae55SKen Wang return 0; 795282aae55SKen Wang } 796282aae55SKen Wang 797282aae55SKen Wang static int vega10_ih_hw_fini(void *handle) 798282aae55SKen Wang { 799282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 800282aae55SKen Wang 801282aae55SKen Wang vega10_ih_irq_disable(adev); 802282aae55SKen Wang 803282aae55SKen Wang return 0; 804282aae55SKen Wang } 805282aae55SKen Wang 806282aae55SKen Wang static int vega10_ih_suspend(void *handle) 807282aae55SKen Wang { 808282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 809282aae55SKen Wang 810282aae55SKen Wang return vega10_ih_hw_fini(adev); 811282aae55SKen Wang } 812282aae55SKen Wang 813282aae55SKen Wang static int vega10_ih_resume(void *handle) 814282aae55SKen Wang { 815282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 816282aae55SKen Wang 817282aae55SKen Wang return vega10_ih_hw_init(adev); 818282aae55SKen Wang } 819282aae55SKen Wang 820282aae55SKen Wang static bool vega10_ih_is_idle(void *handle) 821282aae55SKen Wang { 822282aae55SKen Wang /* todo */ 823282aae55SKen Wang return true; 824282aae55SKen Wang } 825282aae55SKen Wang 826282aae55SKen Wang static int vega10_ih_wait_for_idle(void *handle) 827282aae55SKen Wang { 828282aae55SKen Wang /* todo */ 829282aae55SKen Wang return -ETIMEDOUT; 830282aae55SKen Wang } 831282aae55SKen Wang 832282aae55SKen Wang static int vega10_ih_soft_reset(void *handle) 833282aae55SKen Wang { 834282aae55SKen Wang /* todo */ 835282aae55SKen Wang 836282aae55SKen Wang return 0; 837282aae55SKen Wang } 838282aae55SKen Wang 839227f7d58SKenneth Feng static void vega10_ih_update_clockgating_state(struct amdgpu_device *adev, 840227f7d58SKenneth Feng bool enable) 841227f7d58SKenneth Feng { 842227f7d58SKenneth Feng uint32_t data, def, field_val; 843227f7d58SKenneth Feng 844227f7d58SKenneth Feng if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 845227f7d58SKenneth Feng def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 846227f7d58SKenneth Feng field_val = enable ? 0 : 1; 847227f7d58SKenneth Feng /** 848227f7d58SKenneth Feng * Vega10 does not have IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE 849227f7d58SKenneth Feng * and IH_BUFFER_MEM_CLK_SOFT_OVERRIDE field. 850227f7d58SKenneth Feng */ 851227f7d58SKenneth Feng if (adev->asic_type > CHIP_VEGA10) { 852227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 853227f7d58SKenneth Feng IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE, field_val); 854227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 855227f7d58SKenneth Feng IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val); 856227f7d58SKenneth Feng } 857227f7d58SKenneth Feng 858227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 859227f7d58SKenneth Feng DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 860227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 861227f7d58SKenneth Feng OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 862227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 863227f7d58SKenneth Feng LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 864227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 865227f7d58SKenneth Feng DYN_CLK_SOFT_OVERRIDE, field_val); 866227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 867227f7d58SKenneth Feng REG_CLK_SOFT_OVERRIDE, field_val); 868227f7d58SKenneth Feng if (def != data) 869227f7d58SKenneth Feng WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 870227f7d58SKenneth Feng } 871227f7d58SKenneth Feng } 872227f7d58SKenneth Feng 873282aae55SKen Wang static int vega10_ih_set_clockgating_state(void *handle, 874282aae55SKen Wang enum amd_clockgating_state state) 875282aae55SKen Wang { 876227f7d58SKenneth Feng struct amdgpu_device *adev = (struct amdgpu_device *)handle; 877227f7d58SKenneth Feng 878227f7d58SKenneth Feng vega10_ih_update_clockgating_state(adev, 879a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 880282aae55SKen Wang return 0; 881227f7d58SKenneth Feng 882282aae55SKen Wang } 883282aae55SKen Wang 884282aae55SKen Wang static int vega10_ih_set_powergating_state(void *handle, 885282aae55SKen Wang enum amd_powergating_state state) 886282aae55SKen Wang { 887282aae55SKen Wang return 0; 888282aae55SKen Wang } 889282aae55SKen Wang 890282aae55SKen Wang const struct amd_ip_funcs vega10_ih_ip_funcs = { 891282aae55SKen Wang .name = "vega10_ih", 892282aae55SKen Wang .early_init = vega10_ih_early_init, 893282aae55SKen Wang .late_init = NULL, 894282aae55SKen Wang .sw_init = vega10_ih_sw_init, 895282aae55SKen Wang .sw_fini = vega10_ih_sw_fini, 896282aae55SKen Wang .hw_init = vega10_ih_hw_init, 897282aae55SKen Wang .hw_fini = vega10_ih_hw_fini, 898282aae55SKen Wang .suspend = vega10_ih_suspend, 899282aae55SKen Wang .resume = vega10_ih_resume, 900282aae55SKen Wang .is_idle = vega10_ih_is_idle, 901282aae55SKen Wang .wait_for_idle = vega10_ih_wait_for_idle, 902282aae55SKen Wang .soft_reset = vega10_ih_soft_reset, 903282aae55SKen Wang .set_clockgating_state = vega10_ih_set_clockgating_state, 904282aae55SKen Wang .set_powergating_state = vega10_ih_set_powergating_state, 905282aae55SKen Wang }; 906282aae55SKen Wang 907282aae55SKen Wang static const struct amdgpu_ih_funcs vega10_ih_funcs = { 908282aae55SKen Wang .get_wptr = vega10_ih_get_wptr, 909282aae55SKen Wang .decode_iv = vega10_ih_decode_iv, 910282aae55SKen Wang .set_rptr = vega10_ih_set_rptr 911282aae55SKen Wang }; 912282aae55SKen Wang 913282aae55SKen Wang static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 914282aae55SKen Wang { 915282aae55SKen Wang adev->irq.ih_funcs = &vega10_ih_funcs; 916282aae55SKen Wang } 917282aae55SKen Wang 918282aae55SKen Wang const struct amdgpu_ip_block_version vega10_ih_ip_block = 919282aae55SKen Wang { 920282aae55SKen Wang .type = AMD_IP_BLOCK_TYPE_IH, 921282aae55SKen Wang .major = 4, 922282aae55SKen Wang .minor = 0, 923282aae55SKen Wang .rev = 0, 924282aae55SKen Wang .funcs = &vega10_ih_ip_funcs, 925282aae55SKen Wang }; 926