1282aae55SKen Wang /* 2282aae55SKen Wang * Copyright 2016 Advanced Micro Devices, Inc. 3282aae55SKen Wang * 4282aae55SKen Wang * Permission is hereby granted, free of charge, to any person obtaining a 5282aae55SKen Wang * copy of this software and associated documentation files (the "Software"), 6282aae55SKen Wang * to deal in the Software without restriction, including without limitation 7282aae55SKen Wang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8282aae55SKen Wang * and/or sell copies of the Software, and to permit persons to whom the 9282aae55SKen Wang * Software is furnished to do so, subject to the following conditions: 10282aae55SKen Wang * 11282aae55SKen Wang * The above copyright notice and this permission notice shall be included in 12282aae55SKen Wang * all copies or substantial portions of the Software. 13282aae55SKen Wang * 14282aae55SKen Wang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15282aae55SKen Wang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16282aae55SKen Wang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17282aae55SKen Wang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18282aae55SKen Wang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19282aae55SKen Wang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20282aae55SKen Wang * OTHER DEALINGS IN THE SOFTWARE. 21282aae55SKen Wang * 22282aae55SKen Wang */ 23248a1d6fSMasahiro Yamada #include <drm/drmP.h> 24282aae55SKen Wang #include "amdgpu.h" 25282aae55SKen Wang #include "amdgpu_ih.h" 26282aae55SKen Wang #include "soc15.h" 27282aae55SKen Wang 288af7454eSFeifei Xu #include "oss/osssys_4_0_offset.h" 298af7454eSFeifei Xu #include "oss/osssys_4_0_sh_mask.h" 30282aae55SKen Wang 31282aae55SKen Wang #include "soc15_common.h" 32282aae55SKen Wang #include "vega10_ih.h" 33282aae55SKen Wang 34282aae55SKen Wang 35282aae55SKen Wang 36282aae55SKen Wang static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 37282aae55SKen Wang 38282aae55SKen Wang /** 39282aae55SKen Wang * vega10_ih_enable_interrupts - Enable the interrupt ring buffer 40282aae55SKen Wang * 41282aae55SKen Wang * @adev: amdgpu_device pointer 42282aae55SKen Wang * 43282aae55SKen Wang * Enable the interrupt ring buffer (VEGA10). 44282aae55SKen Wang */ 45282aae55SKen Wang static void vega10_ih_enable_interrupts(struct amdgpu_device *adev) 46282aae55SKen Wang { 47b2b7e457SHawking Zhang u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 48282aae55SKen Wang 49282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); 50282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); 51b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 52282aae55SKen Wang adev->irq.ih.enabled = true; 53282aae55SKen Wang } 54282aae55SKen Wang 55282aae55SKen Wang /** 56282aae55SKen Wang * vega10_ih_disable_interrupts - Disable the interrupt ring buffer 57282aae55SKen Wang * 58282aae55SKen Wang * @adev: amdgpu_device pointer 59282aae55SKen Wang * 60282aae55SKen Wang * Disable the interrupt ring buffer (VEGA10). 61282aae55SKen Wang */ 62282aae55SKen Wang static void vega10_ih_disable_interrupts(struct amdgpu_device *adev) 63282aae55SKen Wang { 64b2b7e457SHawking Zhang u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 65282aae55SKen Wang 66282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); 67282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); 68b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 69282aae55SKen Wang /* set rptr, wptr to 0 */ 70b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 71b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 72282aae55SKen Wang adev->irq.ih.enabled = false; 73282aae55SKen Wang adev->irq.ih.rptr = 0; 74282aae55SKen Wang } 75282aae55SKen Wang 76282aae55SKen Wang /** 77282aae55SKen Wang * vega10_ih_irq_init - init and enable the interrupt ring 78282aae55SKen Wang * 79282aae55SKen Wang * @adev: amdgpu_device pointer 80282aae55SKen Wang * 81282aae55SKen Wang * Allocate a ring buffer for the interrupt controller, 82282aae55SKen Wang * enable the RLC, disable interrupts, enable the IH 83282aae55SKen Wang * ring buffer and enable it (VI). 84282aae55SKen Wang * Called at device load and reume. 85282aae55SKen Wang * Returns 0 for success, errors for failure. 86282aae55SKen Wang */ 87282aae55SKen Wang static int vega10_ih_irq_init(struct amdgpu_device *adev) 88282aae55SKen Wang { 89d81f78b4SChristian König struct amdgpu_ih_ring *ih = &adev->irq.ih; 90282aae55SKen Wang int ret = 0; 91282aae55SKen Wang int rb_bufsz; 92282aae55SKen Wang u32 ih_rb_cntl, ih_doorbell_rtpr; 93282aae55SKen Wang u32 tmp; 94282aae55SKen Wang 95282aae55SKen Wang /* disable irqs */ 96282aae55SKen Wang vega10_ih_disable_interrupts(adev); 97282aae55SKen Wang 98bf383fb6SAlex Deucher adev->nbio_funcs->ih_control(adev); 99282aae55SKen Wang 100b2b7e457SHawking Zhang ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 101282aae55SKen Wang /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 102b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); 103d81f78b4SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, 104d81f78b4SChristian König (adev->irq.ih.gpu_addr >> 40) & 0xff); 105d81f78b4SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 106d81f78b4SChristian König ih->use_bus_addr ? 1 : 4); 107282aae55SKen Wang rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); 108282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 109282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1); 110282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 111282aae55SKen Wang /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */ 112282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); 113282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 114282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 115282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 116282aae55SKen Wang 117282aae55SKen Wang if (adev->irq.msi_enabled) 118282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1); 119282aae55SKen Wang 120b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 121282aae55SKen Wang 122282aae55SKen Wang /* set the writeback address whether it's enabled or not */ 123d81f78b4SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, 124d81f78b4SChristian König lower_32_bits(ih->wptr_addr)); 125d81f78b4SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, 126d81f78b4SChristian König upper_32_bits(ih->wptr_addr) & 0xFFFF); 127282aae55SKen Wang 128282aae55SKen Wang /* set rptr, wptr to 0 */ 129b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 130b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 131282aae55SKen Wang 132b2b7e457SHawking Zhang ih_doorbell_rtpr = RREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR); 133282aae55SKen Wang if (adev->irq.ih.use_doorbell) { 134282aae55SKen Wang ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, 135282aae55SKen Wang OFFSET, adev->irq.ih.doorbell_index); 136282aae55SKen Wang ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, 137282aae55SKen Wang ENABLE, 1); 138282aae55SKen Wang } else { 139282aae55SKen Wang ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, 140282aae55SKen Wang ENABLE, 0); 141282aae55SKen Wang } 142b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, ih_doorbell_rtpr); 143bf383fb6SAlex Deucher adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, 144bf383fb6SAlex Deucher adev->irq.ih.doorbell_index); 145282aae55SKen Wang 146b2b7e457SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 147282aae55SKen Wang tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 148282aae55SKen Wang CLIENT18_IS_STORM_CLIENT, 1); 149b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 150282aae55SKen Wang 151b2b7e457SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 152282aae55SKen Wang tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 153b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 154282aae55SKen Wang 155282aae55SKen Wang pci_set_master(adev->pdev); 156282aae55SKen Wang 157282aae55SKen Wang /* enable interrupts */ 158282aae55SKen Wang vega10_ih_enable_interrupts(adev); 159282aae55SKen Wang 160282aae55SKen Wang return ret; 161282aae55SKen Wang } 162282aae55SKen Wang 163282aae55SKen Wang /** 164282aae55SKen Wang * vega10_ih_irq_disable - disable interrupts 165282aae55SKen Wang * 166282aae55SKen Wang * @adev: amdgpu_device pointer 167282aae55SKen Wang * 168282aae55SKen Wang * Disable interrupts on the hw (VEGA10). 169282aae55SKen Wang */ 170282aae55SKen Wang static void vega10_ih_irq_disable(struct amdgpu_device *adev) 171282aae55SKen Wang { 172282aae55SKen Wang vega10_ih_disable_interrupts(adev); 173282aae55SKen Wang 174282aae55SKen Wang /* Wait and acknowledge irq */ 175282aae55SKen Wang mdelay(1); 176282aae55SKen Wang } 177282aae55SKen Wang 178282aae55SKen Wang /** 179282aae55SKen Wang * vega10_ih_get_wptr - get the IH ring buffer wptr 180282aae55SKen Wang * 181282aae55SKen Wang * @adev: amdgpu_device pointer 182282aae55SKen Wang * 183282aae55SKen Wang * Get the IH ring buffer wptr from either the register 184282aae55SKen Wang * or the writeback memory buffer (VEGA10). Also check for 185282aae55SKen Wang * ring buffer overflow and deal with it. 186282aae55SKen Wang * Returns the value of the wptr. 187282aae55SKen Wang */ 1888bb9eb48SChristian König static u32 vega10_ih_get_wptr(struct amdgpu_device *adev, 1898bb9eb48SChristian König struct amdgpu_ih_ring *ih) 190282aae55SKen Wang { 191282aae55SKen Wang u32 wptr, tmp; 192282aae55SKen Wang 193d81f78b4SChristian König wptr = le32_to_cpu(*ih->wptr_cpu); 194282aae55SKen Wang 195b8217575SChristian König if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 196b8217575SChristian König goto out; 197b8217575SChristian König 198b8217575SChristian König /* Double check that the overflow wasn't already cleared. */ 199b8217575SChristian König wptr = RREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR)); 200b8217575SChristian König if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 201b8217575SChristian König goto out; 202b8217575SChristian König 203282aae55SKen Wang wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 204282aae55SKen Wang 205282aae55SKen Wang /* When a ring buffer overflow happen start parsing interrupt 206282aae55SKen Wang * from the last not overwritten vector (wptr + 32). Hopefully 207282aae55SKen Wang * this should allow us to catchup. 208282aae55SKen Wang */ 2098bb9eb48SChristian König tmp = (wptr + 32) & ih->ptr_mask; 210b8217575SChristian König dev_warn(adev->dev, "IH ring buffer overflow " 211b8217575SChristian König "(0x%08X, 0x%08X, 0x%08X)\n", 2128bb9eb48SChristian König wptr, ih->rptr, tmp); 2138bb9eb48SChristian König ih->rptr = tmp; 214282aae55SKen Wang 2157c3f2167SMonk Liu tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL)); 216282aae55SKen Wang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 2177c3f2167SMonk Liu WREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), tmp); 218b8217575SChristian König 219b8217575SChristian König out: 2208bb9eb48SChristian König return (wptr & ih->ptr_mask); 221282aae55SKen Wang } 222282aae55SKen Wang 223282aae55SKen Wang /** 224282aae55SKen Wang * vega10_ih_decode_iv - decode an interrupt vector 225282aae55SKen Wang * 226282aae55SKen Wang * @adev: amdgpu_device pointer 227282aae55SKen Wang * 228282aae55SKen Wang * Decodes the interrupt vector at the current rptr 229282aae55SKen Wang * position and also advance the position. 230282aae55SKen Wang */ 231282aae55SKen Wang static void vega10_ih_decode_iv(struct amdgpu_device *adev, 2328bb9eb48SChristian König struct amdgpu_ih_ring *ih, 233282aae55SKen Wang struct amdgpu_iv_entry *entry) 234282aae55SKen Wang { 235282aae55SKen Wang /* wptr/rptr are in bytes! */ 2368bb9eb48SChristian König u32 ring_index = ih->rptr >> 2; 237282aae55SKen Wang uint32_t dw[8]; 238282aae55SKen Wang 2398bb9eb48SChristian König dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 2408bb9eb48SChristian König dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 2418bb9eb48SChristian König dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 2428bb9eb48SChristian König dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 2438bb9eb48SChristian König dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); 2448bb9eb48SChristian König dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); 2458bb9eb48SChristian König dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); 2468bb9eb48SChristian König dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); 247282aae55SKen Wang 248282aae55SKen Wang entry->client_id = dw[0] & 0xff; 249282aae55SKen Wang entry->src_id = (dw[0] >> 8) & 0xff; 250282aae55SKen Wang entry->ring_id = (dw[0] >> 16) & 0xff; 251c4f46f22SChristian König entry->vmid = (dw[0] >> 24) & 0xf; 252c4f46f22SChristian König entry->vmid_src = (dw[0] >> 31); 253282aae55SKen Wang entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); 254282aae55SKen Wang entry->timestamp_src = dw[2] >> 31; 2553816e42fSChristian König entry->pasid = dw[3] & 0xffff; 256282aae55SKen Wang entry->pasid_src = dw[3] >> 31; 257282aae55SKen Wang entry->src_data[0] = dw[4]; 258282aae55SKen Wang entry->src_data[1] = dw[5]; 259282aae55SKen Wang entry->src_data[2] = dw[6]; 260282aae55SKen Wang entry->src_data[3] = dw[7]; 261282aae55SKen Wang 262282aae55SKen Wang /* wptr/rptr are in bytes! */ 2638bb9eb48SChristian König ih->rptr += 32; 264282aae55SKen Wang } 265282aae55SKen Wang 266282aae55SKen Wang /** 267282aae55SKen Wang * vega10_ih_set_rptr - set the IH ring buffer rptr 268282aae55SKen Wang * 269282aae55SKen Wang * @adev: amdgpu_device pointer 270282aae55SKen Wang * 271282aae55SKen Wang * Set the IH ring buffer rptr. 272282aae55SKen Wang */ 2738bb9eb48SChristian König static void vega10_ih_set_rptr(struct amdgpu_device *adev, 2748bb9eb48SChristian König struct amdgpu_ih_ring *ih) 275282aae55SKen Wang { 2768bb9eb48SChristian König if (ih->use_doorbell) { 277282aae55SKen Wang /* XXX check if swapping is necessary on BE */ 278d81f78b4SChristian König *ih->rptr_cpu = ih->rptr; 2798bb9eb48SChristian König WDOORBELL32(ih->doorbell_index, ih->rptr); 280282aae55SKen Wang } else { 2818bb9eb48SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr); 282282aae55SKen Wang } 283282aae55SKen Wang } 284282aae55SKen Wang 285282aae55SKen Wang static int vega10_ih_early_init(void *handle) 286282aae55SKen Wang { 287282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 288282aae55SKen Wang 289282aae55SKen Wang vega10_ih_set_interrupt_funcs(adev); 290282aae55SKen Wang return 0; 291282aae55SKen Wang } 292282aae55SKen Wang 293282aae55SKen Wang static int vega10_ih_sw_init(void *handle) 294282aae55SKen Wang { 295282aae55SKen Wang int r; 296282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 297282aae55SKen Wang 298425c3143SChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true); 299282aae55SKen Wang if (r) 300282aae55SKen Wang return r; 301282aae55SKen Wang 302282aae55SKen Wang adev->irq.ih.use_doorbell = true; 3039564f192SOak Zeng adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 304282aae55SKen Wang 305282aae55SKen Wang r = amdgpu_irq_init(adev); 306282aae55SKen Wang 307282aae55SKen Wang return r; 308282aae55SKen Wang } 309282aae55SKen Wang 310282aae55SKen Wang static int vega10_ih_sw_fini(void *handle) 311282aae55SKen Wang { 312282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 313282aae55SKen Wang 314282aae55SKen Wang amdgpu_irq_fini(adev); 315425c3143SChristian König amdgpu_ih_ring_fini(adev, &adev->irq.ih); 316282aae55SKen Wang 317282aae55SKen Wang return 0; 318282aae55SKen Wang } 319282aae55SKen Wang 320282aae55SKen Wang static int vega10_ih_hw_init(void *handle) 321282aae55SKen Wang { 322282aae55SKen Wang int r; 323282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 324282aae55SKen Wang 325282aae55SKen Wang r = vega10_ih_irq_init(adev); 326282aae55SKen Wang if (r) 327282aae55SKen Wang return r; 328282aae55SKen Wang 329282aae55SKen Wang return 0; 330282aae55SKen Wang } 331282aae55SKen Wang 332282aae55SKen Wang static int vega10_ih_hw_fini(void *handle) 333282aae55SKen Wang { 334282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 335282aae55SKen Wang 336282aae55SKen Wang vega10_ih_irq_disable(adev); 337282aae55SKen Wang 338282aae55SKen Wang return 0; 339282aae55SKen Wang } 340282aae55SKen Wang 341282aae55SKen Wang static int vega10_ih_suspend(void *handle) 342282aae55SKen Wang { 343282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 344282aae55SKen Wang 345282aae55SKen Wang return vega10_ih_hw_fini(adev); 346282aae55SKen Wang } 347282aae55SKen Wang 348282aae55SKen Wang static int vega10_ih_resume(void *handle) 349282aae55SKen Wang { 350282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 351282aae55SKen Wang 352282aae55SKen Wang return vega10_ih_hw_init(adev); 353282aae55SKen Wang } 354282aae55SKen Wang 355282aae55SKen Wang static bool vega10_ih_is_idle(void *handle) 356282aae55SKen Wang { 357282aae55SKen Wang /* todo */ 358282aae55SKen Wang return true; 359282aae55SKen Wang } 360282aae55SKen Wang 361282aae55SKen Wang static int vega10_ih_wait_for_idle(void *handle) 362282aae55SKen Wang { 363282aae55SKen Wang /* todo */ 364282aae55SKen Wang return -ETIMEDOUT; 365282aae55SKen Wang } 366282aae55SKen Wang 367282aae55SKen Wang static int vega10_ih_soft_reset(void *handle) 368282aae55SKen Wang { 369282aae55SKen Wang /* todo */ 370282aae55SKen Wang 371282aae55SKen Wang return 0; 372282aae55SKen Wang } 373282aae55SKen Wang 374282aae55SKen Wang static int vega10_ih_set_clockgating_state(void *handle, 375282aae55SKen Wang enum amd_clockgating_state state) 376282aae55SKen Wang { 377282aae55SKen Wang return 0; 378282aae55SKen Wang } 379282aae55SKen Wang 380282aae55SKen Wang static int vega10_ih_set_powergating_state(void *handle, 381282aae55SKen Wang enum amd_powergating_state state) 382282aae55SKen Wang { 383282aae55SKen Wang return 0; 384282aae55SKen Wang } 385282aae55SKen Wang 386282aae55SKen Wang const struct amd_ip_funcs vega10_ih_ip_funcs = { 387282aae55SKen Wang .name = "vega10_ih", 388282aae55SKen Wang .early_init = vega10_ih_early_init, 389282aae55SKen Wang .late_init = NULL, 390282aae55SKen Wang .sw_init = vega10_ih_sw_init, 391282aae55SKen Wang .sw_fini = vega10_ih_sw_fini, 392282aae55SKen Wang .hw_init = vega10_ih_hw_init, 393282aae55SKen Wang .hw_fini = vega10_ih_hw_fini, 394282aae55SKen Wang .suspend = vega10_ih_suspend, 395282aae55SKen Wang .resume = vega10_ih_resume, 396282aae55SKen Wang .is_idle = vega10_ih_is_idle, 397282aae55SKen Wang .wait_for_idle = vega10_ih_wait_for_idle, 398282aae55SKen Wang .soft_reset = vega10_ih_soft_reset, 399282aae55SKen Wang .set_clockgating_state = vega10_ih_set_clockgating_state, 400282aae55SKen Wang .set_powergating_state = vega10_ih_set_powergating_state, 401282aae55SKen Wang }; 402282aae55SKen Wang 403282aae55SKen Wang static const struct amdgpu_ih_funcs vega10_ih_funcs = { 404282aae55SKen Wang .get_wptr = vega10_ih_get_wptr, 405282aae55SKen Wang .decode_iv = vega10_ih_decode_iv, 406282aae55SKen Wang .set_rptr = vega10_ih_set_rptr 407282aae55SKen Wang }; 408282aae55SKen Wang 409282aae55SKen Wang static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 410282aae55SKen Wang { 411282aae55SKen Wang adev->irq.ih_funcs = &vega10_ih_funcs; 412282aae55SKen Wang } 413282aae55SKen Wang 414282aae55SKen Wang const struct amdgpu_ip_block_version vega10_ih_ip_block = 415282aae55SKen Wang { 416282aae55SKen Wang .type = AMD_IP_BLOCK_TYPE_IH, 417282aae55SKen Wang .major = 4, 418282aae55SKen Wang .minor = 0, 419282aae55SKen Wang .rev = 0, 420282aae55SKen Wang .funcs = &vega10_ih_ip_funcs, 421282aae55SKen Wang }; 422