1282aae55SKen Wang /* 2282aae55SKen Wang * Copyright 2016 Advanced Micro Devices, Inc. 3282aae55SKen Wang * 4282aae55SKen Wang * Permission is hereby granted, free of charge, to any person obtaining a 5282aae55SKen Wang * copy of this software and associated documentation files (the "Software"), 6282aae55SKen Wang * to deal in the Software without restriction, including without limitation 7282aae55SKen Wang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8282aae55SKen Wang * and/or sell copies of the Software, and to permit persons to whom the 9282aae55SKen Wang * Software is furnished to do so, subject to the following conditions: 10282aae55SKen Wang * 11282aae55SKen Wang * The above copyright notice and this permission notice shall be included in 12282aae55SKen Wang * all copies or substantial portions of the Software. 13282aae55SKen Wang * 14282aae55SKen Wang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15282aae55SKen Wang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16282aae55SKen Wang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17282aae55SKen Wang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18282aae55SKen Wang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19282aae55SKen Wang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20282aae55SKen Wang * OTHER DEALINGS IN THE SOFTWARE. 21282aae55SKen Wang * 22282aae55SKen Wang */ 2347b757fbSSam Ravnborg 2447b757fbSSam Ravnborg #include <linux/pci.h> 2547b757fbSSam Ravnborg 26282aae55SKen Wang #include "amdgpu.h" 27282aae55SKen Wang #include "amdgpu_ih.h" 28282aae55SKen Wang #include "soc15.h" 29282aae55SKen Wang 308af7454eSFeifei Xu #include "oss/osssys_4_0_offset.h" 318af7454eSFeifei Xu #include "oss/osssys_4_0_sh_mask.h" 32282aae55SKen Wang 33282aae55SKen Wang #include "soc15_common.h" 34282aae55SKen Wang #include "vega10_ih.h" 35282aae55SKen Wang 3674dcfe74STrigger Huang #define MAX_REARM_RETRY 10 37282aae55SKen Wang 38282aae55SKen Wang static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 39282aae55SKen Wang 40282aae55SKen Wang /** 41282aae55SKen Wang * vega10_ih_enable_interrupts - Enable the interrupt ring buffer 42282aae55SKen Wang * 43282aae55SKen Wang * @adev: amdgpu_device pointer 44282aae55SKen Wang * 45282aae55SKen Wang * Enable the interrupt ring buffer (VEGA10). 46282aae55SKen Wang */ 47282aae55SKen Wang static void vega10_ih_enable_interrupts(struct amdgpu_device *adev) 48282aae55SKen Wang { 49b2b7e457SHawking Zhang u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 50282aae55SKen Wang 51282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); 52282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); 534cd4c5c0SMonk Liu if (amdgpu_sriov_vf(adev)) { 54470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 55470b4250STrigger Huang DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 56470b4250STrigger Huang return; 57470b4250STrigger Huang } 58470b4250STrigger Huang } else { 59b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 60470b4250STrigger Huang } 61282aae55SKen Wang adev->irq.ih.enabled = true; 62ad710812SChristian König 63ad710812SChristian König if (adev->irq.ih1.ring_size) { 64ad710812SChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 65ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 66ad710812SChristian König RB_ENABLE, 1); 674cd4c5c0SMonk Liu if (amdgpu_sriov_vf(adev)) { 68470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 69470b4250STrigger Huang ih_rb_cntl)) { 70470b4250STrigger Huang DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 71470b4250STrigger Huang return; 72470b4250STrigger Huang } 73470b4250STrigger Huang } else { 74ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 75470b4250STrigger Huang } 76ad710812SChristian König adev->irq.ih1.enabled = true; 77ad710812SChristian König } 78ad710812SChristian König 79ad710812SChristian König if (adev->irq.ih2.ring_size) { 80ad710812SChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 81ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 82ad710812SChristian König RB_ENABLE, 1); 834cd4c5c0SMonk Liu if (amdgpu_sriov_vf(adev)) { 84470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 85470b4250STrigger Huang ih_rb_cntl)) { 86470b4250STrigger Huang DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 87470b4250STrigger Huang return; 88470b4250STrigger Huang } 89470b4250STrigger Huang } else { 90ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 91470b4250STrigger Huang } 92ad710812SChristian König adev->irq.ih2.enabled = true; 93ad710812SChristian König } 9447509189SChristian König 9547509189SChristian König if (adev->irq.ih_soft.ring_size) 9647509189SChristian König adev->irq.ih_soft.enabled = true; 97282aae55SKen Wang } 98282aae55SKen Wang 99282aae55SKen Wang /** 100282aae55SKen Wang * vega10_ih_disable_interrupts - Disable the interrupt ring buffer 101282aae55SKen Wang * 102282aae55SKen Wang * @adev: amdgpu_device pointer 103282aae55SKen Wang * 104282aae55SKen Wang * Disable the interrupt ring buffer (VEGA10). 105282aae55SKen Wang */ 106282aae55SKen Wang static void vega10_ih_disable_interrupts(struct amdgpu_device *adev) 107282aae55SKen Wang { 108b2b7e457SHawking Zhang u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 109282aae55SKen Wang 110282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); 111282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); 1124cd4c5c0SMonk Liu if (amdgpu_sriov_vf(adev)) { 113470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 114470b4250STrigger Huang DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 115470b4250STrigger Huang return; 116470b4250STrigger Huang } 117470b4250STrigger Huang } else { 118b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 119470b4250STrigger Huang } 120470b4250STrigger Huang 121282aae55SKen Wang /* set rptr, wptr to 0 */ 122b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 123b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 124282aae55SKen Wang adev->irq.ih.enabled = false; 125282aae55SKen Wang adev->irq.ih.rptr = 0; 126ad710812SChristian König 127ad710812SChristian König if (adev->irq.ih1.ring_size) { 128ad710812SChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 129ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 130ad710812SChristian König RB_ENABLE, 0); 1314cd4c5c0SMonk Liu if (amdgpu_sriov_vf(adev)) { 132470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 133470b4250STrigger Huang ih_rb_cntl)) { 134470b4250STrigger Huang DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 135470b4250STrigger Huang return; 136470b4250STrigger Huang } 137470b4250STrigger Huang } else { 138ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 139470b4250STrigger Huang } 140ad710812SChristian König /* set rptr, wptr to 0 */ 141ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 142ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 143ad710812SChristian König adev->irq.ih1.enabled = false; 144ad710812SChristian König adev->irq.ih1.rptr = 0; 145ad710812SChristian König } 146ad710812SChristian König 147ad710812SChristian König if (adev->irq.ih2.ring_size) { 148ad710812SChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 149ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 150ad710812SChristian König RB_ENABLE, 0); 1514cd4c5c0SMonk Liu if (amdgpu_sriov_vf(adev)) { 152470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 153470b4250STrigger Huang ih_rb_cntl)) { 154470b4250STrigger Huang DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 155470b4250STrigger Huang return; 156470b4250STrigger Huang } 157470b4250STrigger Huang } else { 158ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 159470b4250STrigger Huang } 160470b4250STrigger Huang 161ad710812SChristian König /* set rptr, wptr to 0 */ 162ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 163ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 164ad710812SChristian König adev->irq.ih2.enabled = false; 165ad710812SChristian König adev->irq.ih2.rptr = 0; 166ad710812SChristian König } 167ad710812SChristian König } 168ad710812SChristian König 169ad710812SChristian König static uint32_t vega10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 170ad710812SChristian König { 171ad710812SChristian König int rb_bufsz = order_base_2(ih->ring_size / 4); 172ad710812SChristian König 173ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 174ad710812SChristian König MC_SPACE, ih->use_bus_addr ? 1 : 4); 175ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 176ad710812SChristian König WPTR_OVERFLOW_CLEAR, 1); 177ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 178ad710812SChristian König WPTR_OVERFLOW_ENABLE, 1); 179ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 180ad710812SChristian König /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 181ad710812SChristian König * value is written to memory 182ad710812SChristian König */ 183ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 184ad710812SChristian König WPTR_WRITEBACK_ENABLE, 1); 185ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 186ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 187ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 188ad710812SChristian König 189ad710812SChristian König return ih_rb_cntl; 190282aae55SKen Wang } 191282aae55SKen Wang 1921ae64cecSChristian König static uint32_t vega10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 1931ae64cecSChristian König { 1941ae64cecSChristian König u32 ih_doorbell_rtpr = 0; 1951ae64cecSChristian König 1961ae64cecSChristian König if (ih->use_doorbell) { 1971ae64cecSChristian König ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 1981ae64cecSChristian König IH_DOORBELL_RPTR, OFFSET, 1991ae64cecSChristian König ih->doorbell_index); 2001ae64cecSChristian König ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 2011ae64cecSChristian König IH_DOORBELL_RPTR, 2021ae64cecSChristian König ENABLE, 1); 2031ae64cecSChristian König } else { 2041ae64cecSChristian König ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 2051ae64cecSChristian König IH_DOORBELL_RPTR, 2061ae64cecSChristian König ENABLE, 0); 2071ae64cecSChristian König } 2081ae64cecSChristian König return ih_doorbell_rtpr; 2091ae64cecSChristian König } 2101ae64cecSChristian König 211282aae55SKen Wang /** 212282aae55SKen Wang * vega10_ih_irq_init - init and enable the interrupt ring 213282aae55SKen Wang * 214282aae55SKen Wang * @adev: amdgpu_device pointer 215282aae55SKen Wang * 216282aae55SKen Wang * Allocate a ring buffer for the interrupt controller, 217282aae55SKen Wang * enable the RLC, disable interrupts, enable the IH 218282aae55SKen Wang * ring buffer and enable it (VI). 219282aae55SKen Wang * Called at device load and reume. 220282aae55SKen Wang * Returns 0 for success, errors for failure. 221282aae55SKen Wang */ 222282aae55SKen Wang static int vega10_ih_irq_init(struct amdgpu_device *adev) 223282aae55SKen Wang { 224ad710812SChristian König struct amdgpu_ih_ring *ih; 225f9c84ae5SLe Ma u32 ih_rb_cntl, ih_chicken; 226282aae55SKen Wang int ret = 0; 227282aae55SKen Wang u32 tmp; 228282aae55SKen Wang 229282aae55SKen Wang /* disable irqs */ 230282aae55SKen Wang vega10_ih_disable_interrupts(adev); 231282aae55SKen Wang 232bebc0762SHawking Zhang adev->nbio.funcs->ih_control(adev); 233282aae55SKen Wang 234ad710812SChristian König ih = &adev->irq.ih; 235282aae55SKen Wang /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 236ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8); 237ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff); 238282aae55SKen Wang 239ad710812SChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 240ad710812SChristian König ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl); 241ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 242ad710812SChristian König !!adev->irq.msi_enabled); 2434cd4c5c0SMonk Liu if (amdgpu_sriov_vf(adev)) { 244470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 245470b4250STrigger Huang DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 246470b4250STrigger Huang return -ETIMEDOUT; 247470b4250STrigger Huang } 248470b4250STrigger Huang } else { 249b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 250470b4250STrigger Huang } 251282aae55SKen Wang 25225344d7eSZhigang Luo if ((adev->asic_type == CHIP_ARCTURUS && 25325344d7eSZhigang Luo adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) || 25425344d7eSZhigang Luo adev->asic_type == CHIP_RENOIR) { 25525344d7eSZhigang Luo ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 25625344d7eSZhigang Luo if (adev->irq.ih.use_bus_addr) { 25725344d7eSZhigang Luo ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 25825344d7eSZhigang Luo MC_SPACE_GPA_ENABLE, 1); 25925344d7eSZhigang Luo } else { 26025344d7eSZhigang Luo ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 26125344d7eSZhigang Luo MC_SPACE_FBPA_ENABLE, 1); 26225344d7eSZhigang Luo } 263f9c84ae5SLe Ma WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 26425344d7eSZhigang Luo } 265f9c84ae5SLe Ma 266282aae55SKen Wang /* set the writeback address whether it's enabled or not */ 267d81f78b4SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, 268d81f78b4SChristian König lower_32_bits(ih->wptr_addr)); 269d81f78b4SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, 270d81f78b4SChristian König upper_32_bits(ih->wptr_addr) & 0xFFFF); 271282aae55SKen Wang 272282aae55SKen Wang /* set rptr, wptr to 0 */ 273b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 2741ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 275282aae55SKen Wang 2761ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, 2771ae64cecSChristian König vega10_ih_doorbell_rptr(ih)); 278282aae55SKen Wang 279ad710812SChristian König ih = &adev->irq.ih1; 280ad710812SChristian König if (ih->ring_size) { 281ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING1, ih->gpu_addr >> 8); 282ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING1, 283ad710812SChristian König (ih->gpu_addr >> 40) & 0xff); 284ad710812SChristian König 285ad710812SChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 286ad710812SChristian König ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl); 2870133690eSChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 2880133690eSChristian König WPTR_OVERFLOW_ENABLE, 0); 2890133690eSChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 2900133690eSChristian König RB_FULL_DRAIN_ENABLE, 1); 2914cd4c5c0SMonk Liu if (amdgpu_sriov_vf(adev)) { 292470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 293470b4250STrigger Huang ih_rb_cntl)) { 294470b4250STrigger Huang DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 295470b4250STrigger Huang return -ETIMEDOUT; 296470b4250STrigger Huang } 297470b4250STrigger Huang } else { 298ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 299470b4250STrigger Huang } 300ad710812SChristian König 301ad710812SChristian König /* set rptr, wptr to 0 */ 302ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 3031ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 3041ae64cecSChristian König 3051ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1, 3061ae64cecSChristian König vega10_ih_doorbell_rptr(ih)); 307ad710812SChristian König } 308ad710812SChristian König 309ad710812SChristian König ih = &adev->irq.ih2; 310ad710812SChristian König if (ih->ring_size) { 311ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING2, ih->gpu_addr >> 8); 312ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING2, 313ad710812SChristian König (ih->gpu_addr >> 40) & 0xff); 314ad710812SChristian König 3151ae64cecSChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 316ad710812SChristian König ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl); 317470b4250STrigger Huang 3184cd4c5c0SMonk Liu if (amdgpu_sriov_vf(adev)) { 319470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 320470b4250STrigger Huang ih_rb_cntl)) { 321470b4250STrigger Huang DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 322470b4250STrigger Huang return -ETIMEDOUT; 323470b4250STrigger Huang } 324470b4250STrigger Huang } else { 325ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 326470b4250STrigger Huang } 327ad710812SChristian König 328ad710812SChristian König /* set rptr, wptr to 0 */ 329ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 3301ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 3311ae64cecSChristian König 3321ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2, 3331ae64cecSChristian König vega10_ih_doorbell_rptr(ih)); 334ad710812SChristian König } 335ad710812SChristian König 336b2b7e457SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 337282aae55SKen Wang tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 338282aae55SKen Wang CLIENT18_IS_STORM_CLIENT, 1); 339b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 340282aae55SKen Wang 341b2b7e457SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 342282aae55SKen Wang tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 343b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 344282aae55SKen Wang 345282aae55SKen Wang pci_set_master(adev->pdev); 346282aae55SKen Wang 347282aae55SKen Wang /* enable interrupts */ 348282aae55SKen Wang vega10_ih_enable_interrupts(adev); 349282aae55SKen Wang 350282aae55SKen Wang return ret; 351282aae55SKen Wang } 352282aae55SKen Wang 353282aae55SKen Wang /** 354282aae55SKen Wang * vega10_ih_irq_disable - disable interrupts 355282aae55SKen Wang * 356282aae55SKen Wang * @adev: amdgpu_device pointer 357282aae55SKen Wang * 358282aae55SKen Wang * Disable interrupts on the hw (VEGA10). 359282aae55SKen Wang */ 360282aae55SKen Wang static void vega10_ih_irq_disable(struct amdgpu_device *adev) 361282aae55SKen Wang { 362282aae55SKen Wang vega10_ih_disable_interrupts(adev); 363282aae55SKen Wang 364282aae55SKen Wang /* Wait and acknowledge irq */ 365282aae55SKen Wang mdelay(1); 366282aae55SKen Wang } 367282aae55SKen Wang 368282aae55SKen Wang /** 369282aae55SKen Wang * vega10_ih_get_wptr - get the IH ring buffer wptr 370282aae55SKen Wang * 371282aae55SKen Wang * @adev: amdgpu_device pointer 372*5162e40eSLee Jones * @ih: IH ring buffer to fetch wptr 373282aae55SKen Wang * 374282aae55SKen Wang * Get the IH ring buffer wptr from either the register 375282aae55SKen Wang * or the writeback memory buffer (VEGA10). Also check for 376282aae55SKen Wang * ring buffer overflow and deal with it. 377282aae55SKen Wang * Returns the value of the wptr. 378282aae55SKen Wang */ 3798bb9eb48SChristian König static u32 vega10_ih_get_wptr(struct amdgpu_device *adev, 3808bb9eb48SChristian König struct amdgpu_ih_ring *ih) 381282aae55SKen Wang { 382cf67950eSChristian König u32 wptr, reg, tmp; 383282aae55SKen Wang 384d81f78b4SChristian König wptr = le32_to_cpu(*ih->wptr_cpu); 385282aae55SKen Wang 386b8217575SChristian König if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 387b8217575SChristian König goto out; 388b8217575SChristian König 389b8217575SChristian König /* Double check that the overflow wasn't already cleared. */ 390cf67950eSChristian König 391cf67950eSChristian König if (ih == &adev->irq.ih) 392cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 393cf67950eSChristian König else if (ih == &adev->irq.ih1) 394cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 395cf67950eSChristian König else if (ih == &adev->irq.ih2) 396cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 397cf67950eSChristian König else 398cf67950eSChristian König BUG(); 399cf67950eSChristian König 400cf67950eSChristian König wptr = RREG32_NO_KIQ(reg); 401b8217575SChristian König if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 402b8217575SChristian König goto out; 403b8217575SChristian König 404282aae55SKen Wang wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 405282aae55SKen Wang 406282aae55SKen Wang /* When a ring buffer overflow happen start parsing interrupt 407282aae55SKen Wang * from the last not overwritten vector (wptr + 32). Hopefully 408282aae55SKen Wang * this should allow us to catchup. 409282aae55SKen Wang */ 4108bb9eb48SChristian König tmp = (wptr + 32) & ih->ptr_mask; 411b8217575SChristian König dev_warn(adev->dev, "IH ring buffer overflow " 412b8217575SChristian König "(0x%08X, 0x%08X, 0x%08X)\n", 4138bb9eb48SChristian König wptr, ih->rptr, tmp); 4148bb9eb48SChristian König ih->rptr = tmp; 415282aae55SKen Wang 416cf67950eSChristian König if (ih == &adev->irq.ih) 417cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 418cf67950eSChristian König else if (ih == &adev->irq.ih1) 419cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 420cf67950eSChristian König else if (ih == &adev->irq.ih2) 421cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 422cf67950eSChristian König else 423cf67950eSChristian König BUG(); 424cf67950eSChristian König 425cf67950eSChristian König tmp = RREG32_NO_KIQ(reg); 426282aae55SKen Wang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 427cf67950eSChristian König WREG32_NO_KIQ(reg, tmp); 428b8217575SChristian König 429b8217575SChristian König out: 4308bb9eb48SChristian König return (wptr & ih->ptr_mask); 431282aae55SKen Wang } 432282aae55SKen Wang 433282aae55SKen Wang /** 434282aae55SKen Wang * vega10_ih_decode_iv - decode an interrupt vector 435282aae55SKen Wang * 436282aae55SKen Wang * @adev: amdgpu_device pointer 437*5162e40eSLee Jones * @ih: IH ring buffer to decode 438*5162e40eSLee Jones * @entry: IV entry to place decoded information into 439282aae55SKen Wang * 440282aae55SKen Wang * Decodes the interrupt vector at the current rptr 441282aae55SKen Wang * position and also advance the position. 442282aae55SKen Wang */ 443282aae55SKen Wang static void vega10_ih_decode_iv(struct amdgpu_device *adev, 4448bb9eb48SChristian König struct amdgpu_ih_ring *ih, 445282aae55SKen Wang struct amdgpu_iv_entry *entry) 446282aae55SKen Wang { 447282aae55SKen Wang /* wptr/rptr are in bytes! */ 4488bb9eb48SChristian König u32 ring_index = ih->rptr >> 2; 449282aae55SKen Wang uint32_t dw[8]; 450282aae55SKen Wang 4518bb9eb48SChristian König dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 4528bb9eb48SChristian König dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 4538bb9eb48SChristian König dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 4548bb9eb48SChristian König dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 4558bb9eb48SChristian König dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); 4568bb9eb48SChristian König dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); 4578bb9eb48SChristian König dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); 4588bb9eb48SChristian König dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); 459282aae55SKen Wang 460282aae55SKen Wang entry->client_id = dw[0] & 0xff; 461282aae55SKen Wang entry->src_id = (dw[0] >> 8) & 0xff; 462282aae55SKen Wang entry->ring_id = (dw[0] >> 16) & 0xff; 463c4f46f22SChristian König entry->vmid = (dw[0] >> 24) & 0xf; 464c4f46f22SChristian König entry->vmid_src = (dw[0] >> 31); 465282aae55SKen Wang entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); 466282aae55SKen Wang entry->timestamp_src = dw[2] >> 31; 4673816e42fSChristian König entry->pasid = dw[3] & 0xffff; 468282aae55SKen Wang entry->pasid_src = dw[3] >> 31; 469282aae55SKen Wang entry->src_data[0] = dw[4]; 470282aae55SKen Wang entry->src_data[1] = dw[5]; 471282aae55SKen Wang entry->src_data[2] = dw[6]; 472282aae55SKen Wang entry->src_data[3] = dw[7]; 473282aae55SKen Wang 474282aae55SKen Wang /* wptr/rptr are in bytes! */ 4758bb9eb48SChristian König ih->rptr += 32; 476282aae55SKen Wang } 477282aae55SKen Wang 478282aae55SKen Wang /** 47974dcfe74STrigger Huang * vega10_ih_irq_rearm - rearm IRQ if lost 48074dcfe74STrigger Huang * 48174dcfe74STrigger Huang * @adev: amdgpu_device pointer 482*5162e40eSLee Jones * @ih: IH ring to match 48374dcfe74STrigger Huang * 48474dcfe74STrigger Huang */ 48574dcfe74STrigger Huang static void vega10_ih_irq_rearm(struct amdgpu_device *adev, 48674dcfe74STrigger Huang struct amdgpu_ih_ring *ih) 48774dcfe74STrigger Huang { 48874dcfe74STrigger Huang uint32_t reg_rptr = 0; 48974dcfe74STrigger Huang uint32_t v = 0; 49074dcfe74STrigger Huang uint32_t i = 0; 49174dcfe74STrigger Huang 49274dcfe74STrigger Huang if (ih == &adev->irq.ih) 49374dcfe74STrigger Huang reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 49474dcfe74STrigger Huang else if (ih == &adev->irq.ih1) 49574dcfe74STrigger Huang reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 49674dcfe74STrigger Huang else if (ih == &adev->irq.ih2) 49774dcfe74STrigger Huang reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 49874dcfe74STrigger Huang else 49974dcfe74STrigger Huang return; 50074dcfe74STrigger Huang 50174dcfe74STrigger Huang /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */ 50274dcfe74STrigger Huang for (i = 0; i < MAX_REARM_RETRY; i++) { 50374dcfe74STrigger Huang v = RREG32_NO_KIQ(reg_rptr); 50474dcfe74STrigger Huang if ((v < ih->ring_size) && (v != ih->rptr)) 50574dcfe74STrigger Huang WDOORBELL32(ih->doorbell_index, ih->rptr); 50674dcfe74STrigger Huang else 50774dcfe74STrigger Huang break; 50874dcfe74STrigger Huang } 50974dcfe74STrigger Huang } 51074dcfe74STrigger Huang 51174dcfe74STrigger Huang /** 512282aae55SKen Wang * vega10_ih_set_rptr - set the IH ring buffer rptr 513282aae55SKen Wang * 514282aae55SKen Wang * @adev: amdgpu_device pointer 515*5162e40eSLee Jones * @ih: IH ring buffer to set rptr 516282aae55SKen Wang * 517282aae55SKen Wang * Set the IH ring buffer rptr. 518282aae55SKen Wang */ 5198bb9eb48SChristian König static void vega10_ih_set_rptr(struct amdgpu_device *adev, 5208bb9eb48SChristian König struct amdgpu_ih_ring *ih) 521282aae55SKen Wang { 5228bb9eb48SChristian König if (ih->use_doorbell) { 523282aae55SKen Wang /* XXX check if swapping is necessary on BE */ 524d81f78b4SChristian König *ih->rptr_cpu = ih->rptr; 5258bb9eb48SChristian König WDOORBELL32(ih->doorbell_index, ih->rptr); 52674dcfe74STrigger Huang 52774dcfe74STrigger Huang if (amdgpu_sriov_vf(adev)) 52874dcfe74STrigger Huang vega10_ih_irq_rearm(adev, ih); 529cf67950eSChristian König } else if (ih == &adev->irq.ih) { 5308bb9eb48SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr); 531cf67950eSChristian König } else if (ih == &adev->irq.ih1) { 532cf67950eSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, ih->rptr); 533cf67950eSChristian König } else if (ih == &adev->irq.ih2) { 534cf67950eSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, ih->rptr); 535282aae55SKen Wang } 536282aae55SKen Wang } 537282aae55SKen Wang 538cf67950eSChristian König /** 539cf67950eSChristian König * vega10_ih_self_irq - dispatch work for ring 1 and 2 540cf67950eSChristian König * 541cf67950eSChristian König * @adev: amdgpu_device pointer 542cf67950eSChristian König * @source: irq source 543cf67950eSChristian König * @entry: IV with WPTR update 544cf67950eSChristian König * 545cf67950eSChristian König * Update the WPTR from the IV and schedule work to handle the entries. 546cf67950eSChristian König */ 547cf67950eSChristian König static int vega10_ih_self_irq(struct amdgpu_device *adev, 548cf67950eSChristian König struct amdgpu_irq_src *source, 549cf67950eSChristian König struct amdgpu_iv_entry *entry) 550cf67950eSChristian König { 551cf67950eSChristian König uint32_t wptr = cpu_to_le32(entry->src_data[0]); 552cf67950eSChristian König 553cf67950eSChristian König switch (entry->ring_id) { 554cf67950eSChristian König case 1: 555cf67950eSChristian König *adev->irq.ih1.wptr_cpu = wptr; 556cf67950eSChristian König schedule_work(&adev->irq.ih1_work); 557cf67950eSChristian König break; 558cf67950eSChristian König case 2: 559cf67950eSChristian König *adev->irq.ih2.wptr_cpu = wptr; 560cf67950eSChristian König schedule_work(&adev->irq.ih2_work); 561cf67950eSChristian König break; 562cf67950eSChristian König default: break; 563cf67950eSChristian König } 564cf67950eSChristian König return 0; 565cf67950eSChristian König } 566cf67950eSChristian König 567cf67950eSChristian König static const struct amdgpu_irq_src_funcs vega10_ih_self_irq_funcs = { 568cf67950eSChristian König .process = vega10_ih_self_irq, 569cf67950eSChristian König }; 570cf67950eSChristian König 571cf67950eSChristian König static void vega10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 572cf67950eSChristian König { 573cf67950eSChristian König adev->irq.self_irq.num_types = 0; 574cf67950eSChristian König adev->irq.self_irq.funcs = &vega10_ih_self_irq_funcs; 575cf67950eSChristian König } 576cf67950eSChristian König 577282aae55SKen Wang static int vega10_ih_early_init(void *handle) 578282aae55SKen Wang { 579282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 580282aae55SKen Wang 581282aae55SKen Wang vega10_ih_set_interrupt_funcs(adev); 582cf67950eSChristian König vega10_ih_set_self_irq_funcs(adev); 583282aae55SKen Wang return 0; 584282aae55SKen Wang } 585282aae55SKen Wang 586282aae55SKen Wang static int vega10_ih_sw_init(void *handle) 587282aae55SKen Wang { 588282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 589cf67950eSChristian König int r; 590cf67950eSChristian König 591cf67950eSChristian König r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 592cf67950eSChristian König &adev->irq.self_irq); 593cf67950eSChristian König if (r) 594cf67950eSChristian König return r; 595282aae55SKen Wang 596425c3143SChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true); 597282aae55SKen Wang if (r) 598282aae55SKen Wang return r; 599282aae55SKen Wang 6001ae64cecSChristian König adev->irq.ih.use_doorbell = true; 6011ae64cecSChristian König adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 6021ae64cecSChristian König 603ad710812SChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 604ad710812SChristian König if (r) 605ad710812SChristian König return r; 606ad710812SChristian König 6071ae64cecSChristian König adev->irq.ih1.use_doorbell = true; 608b51cd19eSChristian König adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; 6091ae64cecSChristian König 610ad710812SChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 611ad710812SChristian König if (r) 612ad710812SChristian König return r; 613ad710812SChristian König 6141ae64cecSChristian König adev->irq.ih2.use_doorbell = true; 615b51cd19eSChristian König adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1; 616282aae55SKen Wang 61747509189SChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); 61847509189SChristian König if (r) 61947509189SChristian König return r; 62047509189SChristian König 621282aae55SKen Wang r = amdgpu_irq_init(adev); 622282aae55SKen Wang 623282aae55SKen Wang return r; 624282aae55SKen Wang } 625282aae55SKen Wang 626282aae55SKen Wang static int vega10_ih_sw_fini(void *handle) 627282aae55SKen Wang { 628282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 629282aae55SKen Wang 630282aae55SKen Wang amdgpu_irq_fini(adev); 631ad710812SChristian König amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 632ad710812SChristian König amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 633425c3143SChristian König amdgpu_ih_ring_fini(adev, &adev->irq.ih); 634282aae55SKen Wang 635282aae55SKen Wang return 0; 636282aae55SKen Wang } 637282aae55SKen Wang 638282aae55SKen Wang static int vega10_ih_hw_init(void *handle) 639282aae55SKen Wang { 640282aae55SKen Wang int r; 641282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 642282aae55SKen Wang 643282aae55SKen Wang r = vega10_ih_irq_init(adev); 644282aae55SKen Wang if (r) 645282aae55SKen Wang return r; 646282aae55SKen Wang 647282aae55SKen Wang return 0; 648282aae55SKen Wang } 649282aae55SKen Wang 650282aae55SKen Wang static int vega10_ih_hw_fini(void *handle) 651282aae55SKen Wang { 652282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 653282aae55SKen Wang 654282aae55SKen Wang vega10_ih_irq_disable(adev); 655282aae55SKen Wang 656282aae55SKen Wang return 0; 657282aae55SKen Wang } 658282aae55SKen Wang 659282aae55SKen Wang static int vega10_ih_suspend(void *handle) 660282aae55SKen Wang { 661282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 662282aae55SKen Wang 663282aae55SKen Wang return vega10_ih_hw_fini(adev); 664282aae55SKen Wang } 665282aae55SKen Wang 666282aae55SKen Wang static int vega10_ih_resume(void *handle) 667282aae55SKen Wang { 668282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 669282aae55SKen Wang 670282aae55SKen Wang return vega10_ih_hw_init(adev); 671282aae55SKen Wang } 672282aae55SKen Wang 673282aae55SKen Wang static bool vega10_ih_is_idle(void *handle) 674282aae55SKen Wang { 675282aae55SKen Wang /* todo */ 676282aae55SKen Wang return true; 677282aae55SKen Wang } 678282aae55SKen Wang 679282aae55SKen Wang static int vega10_ih_wait_for_idle(void *handle) 680282aae55SKen Wang { 681282aae55SKen Wang /* todo */ 682282aae55SKen Wang return -ETIMEDOUT; 683282aae55SKen Wang } 684282aae55SKen Wang 685282aae55SKen Wang static int vega10_ih_soft_reset(void *handle) 686282aae55SKen Wang { 687282aae55SKen Wang /* todo */ 688282aae55SKen Wang 689282aae55SKen Wang return 0; 690282aae55SKen Wang } 691282aae55SKen Wang 692227f7d58SKenneth Feng static void vega10_ih_update_clockgating_state(struct amdgpu_device *adev, 693227f7d58SKenneth Feng bool enable) 694227f7d58SKenneth Feng { 695227f7d58SKenneth Feng uint32_t data, def, field_val; 696227f7d58SKenneth Feng 697227f7d58SKenneth Feng if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 698227f7d58SKenneth Feng def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 699227f7d58SKenneth Feng field_val = enable ? 0 : 1; 700227f7d58SKenneth Feng /** 701227f7d58SKenneth Feng * Vega10 does not have IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE 702227f7d58SKenneth Feng * and IH_BUFFER_MEM_CLK_SOFT_OVERRIDE field. 703227f7d58SKenneth Feng */ 704227f7d58SKenneth Feng if (adev->asic_type > CHIP_VEGA10) { 705227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 706227f7d58SKenneth Feng IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE, field_val); 707227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 708227f7d58SKenneth Feng IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val); 709227f7d58SKenneth Feng } 710227f7d58SKenneth Feng 711227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 712227f7d58SKenneth Feng DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 713227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 714227f7d58SKenneth Feng OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 715227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 716227f7d58SKenneth Feng LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 717227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 718227f7d58SKenneth Feng DYN_CLK_SOFT_OVERRIDE, field_val); 719227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 720227f7d58SKenneth Feng REG_CLK_SOFT_OVERRIDE, field_val); 721227f7d58SKenneth Feng if (def != data) 722227f7d58SKenneth Feng WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 723227f7d58SKenneth Feng } 724227f7d58SKenneth Feng } 725227f7d58SKenneth Feng 726282aae55SKen Wang static int vega10_ih_set_clockgating_state(void *handle, 727282aae55SKen Wang enum amd_clockgating_state state) 728282aae55SKen Wang { 729227f7d58SKenneth Feng struct amdgpu_device *adev = (struct amdgpu_device *)handle; 730227f7d58SKenneth Feng 731227f7d58SKenneth Feng vega10_ih_update_clockgating_state(adev, 732a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 733282aae55SKen Wang return 0; 734227f7d58SKenneth Feng 735282aae55SKen Wang } 736282aae55SKen Wang 737282aae55SKen Wang static int vega10_ih_set_powergating_state(void *handle, 738282aae55SKen Wang enum amd_powergating_state state) 739282aae55SKen Wang { 740282aae55SKen Wang return 0; 741282aae55SKen Wang } 742282aae55SKen Wang 743282aae55SKen Wang const struct amd_ip_funcs vega10_ih_ip_funcs = { 744282aae55SKen Wang .name = "vega10_ih", 745282aae55SKen Wang .early_init = vega10_ih_early_init, 746282aae55SKen Wang .late_init = NULL, 747282aae55SKen Wang .sw_init = vega10_ih_sw_init, 748282aae55SKen Wang .sw_fini = vega10_ih_sw_fini, 749282aae55SKen Wang .hw_init = vega10_ih_hw_init, 750282aae55SKen Wang .hw_fini = vega10_ih_hw_fini, 751282aae55SKen Wang .suspend = vega10_ih_suspend, 752282aae55SKen Wang .resume = vega10_ih_resume, 753282aae55SKen Wang .is_idle = vega10_ih_is_idle, 754282aae55SKen Wang .wait_for_idle = vega10_ih_wait_for_idle, 755282aae55SKen Wang .soft_reset = vega10_ih_soft_reset, 756282aae55SKen Wang .set_clockgating_state = vega10_ih_set_clockgating_state, 757282aae55SKen Wang .set_powergating_state = vega10_ih_set_powergating_state, 758282aae55SKen Wang }; 759282aae55SKen Wang 760282aae55SKen Wang static const struct amdgpu_ih_funcs vega10_ih_funcs = { 761282aae55SKen Wang .get_wptr = vega10_ih_get_wptr, 762282aae55SKen Wang .decode_iv = vega10_ih_decode_iv, 763282aae55SKen Wang .set_rptr = vega10_ih_set_rptr 764282aae55SKen Wang }; 765282aae55SKen Wang 766282aae55SKen Wang static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 767282aae55SKen Wang { 768282aae55SKen Wang adev->irq.ih_funcs = &vega10_ih_funcs; 769282aae55SKen Wang } 770282aae55SKen Wang 771282aae55SKen Wang const struct amdgpu_ip_block_version vega10_ih_ip_block = 772282aae55SKen Wang { 773282aae55SKen Wang .type = AMD_IP_BLOCK_TYPE_IH, 774282aae55SKen Wang .major = 4, 775282aae55SKen Wang .minor = 0, 776282aae55SKen Wang .rev = 0, 777282aae55SKen Wang .funcs = &vega10_ih_ip_funcs, 778282aae55SKen Wang }; 779