1282aae55SKen Wang /* 2282aae55SKen Wang * Copyright 2016 Advanced Micro Devices, Inc. 3282aae55SKen Wang * 4282aae55SKen Wang * Permission is hereby granted, free of charge, to any person obtaining a 5282aae55SKen Wang * copy of this software and associated documentation files (the "Software"), 6282aae55SKen Wang * to deal in the Software without restriction, including without limitation 7282aae55SKen Wang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8282aae55SKen Wang * and/or sell copies of the Software, and to permit persons to whom the 9282aae55SKen Wang * Software is furnished to do so, subject to the following conditions: 10282aae55SKen Wang * 11282aae55SKen Wang * The above copyright notice and this permission notice shall be included in 12282aae55SKen Wang * all copies or substantial portions of the Software. 13282aae55SKen Wang * 14282aae55SKen Wang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15282aae55SKen Wang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16282aae55SKen Wang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17282aae55SKen Wang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18282aae55SKen Wang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19282aae55SKen Wang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20282aae55SKen Wang * OTHER DEALINGS IN THE SOFTWARE. 21282aae55SKen Wang * 22282aae55SKen Wang */ 23248a1d6fSMasahiro Yamada #include <drm/drmP.h> 24282aae55SKen Wang #include "amdgpu.h" 25282aae55SKen Wang #include "amdgpu_ih.h" 26282aae55SKen Wang #include "soc15.h" 27282aae55SKen Wang 288af7454eSFeifei Xu #include "oss/osssys_4_0_offset.h" 298af7454eSFeifei Xu #include "oss/osssys_4_0_sh_mask.h" 30282aae55SKen Wang 31282aae55SKen Wang #include "soc15_common.h" 32282aae55SKen Wang #include "vega10_ih.h" 33282aae55SKen Wang 3474dcfe74STrigger Huang #define MAX_REARM_RETRY 10 35282aae55SKen Wang 36282aae55SKen Wang static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 37282aae55SKen Wang 38282aae55SKen Wang /** 39282aae55SKen Wang * vega10_ih_enable_interrupts - Enable the interrupt ring buffer 40282aae55SKen Wang * 41282aae55SKen Wang * @adev: amdgpu_device pointer 42282aae55SKen Wang * 43282aae55SKen Wang * Enable the interrupt ring buffer (VEGA10). 44282aae55SKen Wang */ 45282aae55SKen Wang static void vega10_ih_enable_interrupts(struct amdgpu_device *adev) 46282aae55SKen Wang { 47b2b7e457SHawking Zhang u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 48282aae55SKen Wang 49282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); 50282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); 51470b4250STrigger Huang if (amdgpu_virt_support_psp_prg_ih_reg(adev)) { 52470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 53470b4250STrigger Huang DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 54470b4250STrigger Huang return; 55470b4250STrigger Huang } 56470b4250STrigger Huang } else { 57b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 58470b4250STrigger Huang } 59282aae55SKen Wang adev->irq.ih.enabled = true; 60ad710812SChristian König 61ad710812SChristian König if (adev->irq.ih1.ring_size) { 62ad710812SChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 63ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 64ad710812SChristian König RB_ENABLE, 1); 65470b4250STrigger Huang if (amdgpu_virt_support_psp_prg_ih_reg(adev)) { 66470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 67470b4250STrigger Huang ih_rb_cntl)) { 68470b4250STrigger Huang DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 69470b4250STrigger Huang return; 70470b4250STrigger Huang } 71470b4250STrigger Huang } else { 72ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 73470b4250STrigger Huang } 74ad710812SChristian König adev->irq.ih1.enabled = true; 75ad710812SChristian König } 76ad710812SChristian König 77ad710812SChristian König if (adev->irq.ih2.ring_size) { 78ad710812SChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 79ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 80ad710812SChristian König RB_ENABLE, 1); 81470b4250STrigger Huang if (amdgpu_virt_support_psp_prg_ih_reg(adev)) { 82470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 83470b4250STrigger Huang ih_rb_cntl)) { 84470b4250STrigger Huang DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 85470b4250STrigger Huang return; 86470b4250STrigger Huang } 87470b4250STrigger Huang } else { 88ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 89470b4250STrigger Huang } 90ad710812SChristian König adev->irq.ih2.enabled = true; 91ad710812SChristian König } 92282aae55SKen Wang } 93282aae55SKen Wang 94282aae55SKen Wang /** 95282aae55SKen Wang * vega10_ih_disable_interrupts - Disable the interrupt ring buffer 96282aae55SKen Wang * 97282aae55SKen Wang * @adev: amdgpu_device pointer 98282aae55SKen Wang * 99282aae55SKen Wang * Disable the interrupt ring buffer (VEGA10). 100282aae55SKen Wang */ 101282aae55SKen Wang static void vega10_ih_disable_interrupts(struct amdgpu_device *adev) 102282aae55SKen Wang { 103b2b7e457SHawking Zhang u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 104282aae55SKen Wang 105282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); 106282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); 107470b4250STrigger Huang if (amdgpu_virt_support_psp_prg_ih_reg(adev)) { 108470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 109470b4250STrigger Huang DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 110470b4250STrigger Huang return; 111470b4250STrigger Huang } 112470b4250STrigger Huang } else { 113b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 114470b4250STrigger Huang } 115470b4250STrigger Huang 116282aae55SKen Wang /* set rptr, wptr to 0 */ 117b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 118b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 119282aae55SKen Wang adev->irq.ih.enabled = false; 120282aae55SKen Wang adev->irq.ih.rptr = 0; 121ad710812SChristian König 122ad710812SChristian König if (adev->irq.ih1.ring_size) { 123ad710812SChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 124ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 125ad710812SChristian König RB_ENABLE, 0); 126470b4250STrigger Huang if (amdgpu_virt_support_psp_prg_ih_reg(adev)) { 127470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 128470b4250STrigger Huang ih_rb_cntl)) { 129470b4250STrigger Huang DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 130470b4250STrigger Huang return; 131470b4250STrigger Huang } 132470b4250STrigger Huang } else { 133ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 134470b4250STrigger Huang } 135ad710812SChristian König /* set rptr, wptr to 0 */ 136ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 137ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 138ad710812SChristian König adev->irq.ih1.enabled = false; 139ad710812SChristian König adev->irq.ih1.rptr = 0; 140ad710812SChristian König } 141ad710812SChristian König 142ad710812SChristian König if (adev->irq.ih2.ring_size) { 143ad710812SChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 144ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 145ad710812SChristian König RB_ENABLE, 0); 146470b4250STrigger Huang if (amdgpu_virt_support_psp_prg_ih_reg(adev)) { 147470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 148470b4250STrigger Huang ih_rb_cntl)) { 149470b4250STrigger Huang DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 150470b4250STrigger Huang return; 151470b4250STrigger Huang } 152470b4250STrigger Huang } else { 153ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 154470b4250STrigger Huang } 155470b4250STrigger Huang 156ad710812SChristian König /* set rptr, wptr to 0 */ 157ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 158ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 159ad710812SChristian König adev->irq.ih2.enabled = false; 160ad710812SChristian König adev->irq.ih2.rptr = 0; 161ad710812SChristian König } 162ad710812SChristian König } 163ad710812SChristian König 164ad710812SChristian König static uint32_t vega10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 165ad710812SChristian König { 166ad710812SChristian König int rb_bufsz = order_base_2(ih->ring_size / 4); 167ad710812SChristian König 168ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 169ad710812SChristian König MC_SPACE, ih->use_bus_addr ? 1 : 4); 170ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 171ad710812SChristian König WPTR_OVERFLOW_CLEAR, 1); 172ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 173ad710812SChristian König WPTR_OVERFLOW_ENABLE, 1); 174ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 175ad710812SChristian König /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 176ad710812SChristian König * value is written to memory 177ad710812SChristian König */ 178ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 179ad710812SChristian König WPTR_WRITEBACK_ENABLE, 1); 180ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 181ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 182ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 183ad710812SChristian König 184ad710812SChristian König return ih_rb_cntl; 185282aae55SKen Wang } 186282aae55SKen Wang 1871ae64cecSChristian König static uint32_t vega10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 1881ae64cecSChristian König { 1891ae64cecSChristian König u32 ih_doorbell_rtpr = 0; 1901ae64cecSChristian König 1911ae64cecSChristian König if (ih->use_doorbell) { 1921ae64cecSChristian König ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 1931ae64cecSChristian König IH_DOORBELL_RPTR, OFFSET, 1941ae64cecSChristian König ih->doorbell_index); 1951ae64cecSChristian König ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 1961ae64cecSChristian König IH_DOORBELL_RPTR, 1971ae64cecSChristian König ENABLE, 1); 1981ae64cecSChristian König } else { 1991ae64cecSChristian König ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 2001ae64cecSChristian König IH_DOORBELL_RPTR, 2011ae64cecSChristian König ENABLE, 0); 2021ae64cecSChristian König } 2031ae64cecSChristian König return ih_doorbell_rtpr; 2041ae64cecSChristian König } 2051ae64cecSChristian König 206282aae55SKen Wang /** 207282aae55SKen Wang * vega10_ih_irq_init - init and enable the interrupt ring 208282aae55SKen Wang * 209282aae55SKen Wang * @adev: amdgpu_device pointer 210282aae55SKen Wang * 211282aae55SKen Wang * Allocate a ring buffer for the interrupt controller, 212282aae55SKen Wang * enable the RLC, disable interrupts, enable the IH 213282aae55SKen Wang * ring buffer and enable it (VI). 214282aae55SKen Wang * Called at device load and reume. 215282aae55SKen Wang * Returns 0 for success, errors for failure. 216282aae55SKen Wang */ 217282aae55SKen Wang static int vega10_ih_irq_init(struct amdgpu_device *adev) 218282aae55SKen Wang { 219ad710812SChristian König struct amdgpu_ih_ring *ih; 2201ae64cecSChristian König u32 ih_rb_cntl; 221282aae55SKen Wang int ret = 0; 222282aae55SKen Wang u32 tmp; 223282aae55SKen Wang 224282aae55SKen Wang /* disable irqs */ 225282aae55SKen Wang vega10_ih_disable_interrupts(adev); 226282aae55SKen Wang 227bf383fb6SAlex Deucher adev->nbio_funcs->ih_control(adev); 228282aae55SKen Wang 229ad710812SChristian König ih = &adev->irq.ih; 230282aae55SKen Wang /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 231ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8); 232ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff); 233282aae55SKen Wang 234ad710812SChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 235ad710812SChristian König ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl); 236ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 237ad710812SChristian König !!adev->irq.msi_enabled); 238470b4250STrigger Huang 239470b4250STrigger Huang if (amdgpu_virt_support_psp_prg_ih_reg(adev)) { 240470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 241470b4250STrigger Huang DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 242470b4250STrigger Huang return -ETIMEDOUT; 243470b4250STrigger Huang } 244470b4250STrigger Huang } else { 245b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 246470b4250STrigger Huang } 247282aae55SKen Wang 248282aae55SKen Wang /* set the writeback address whether it's enabled or not */ 249d81f78b4SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, 250d81f78b4SChristian König lower_32_bits(ih->wptr_addr)); 251d81f78b4SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, 252d81f78b4SChristian König upper_32_bits(ih->wptr_addr) & 0xFFFF); 253282aae55SKen Wang 254282aae55SKen Wang /* set rptr, wptr to 0 */ 255b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 2561ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 257282aae55SKen Wang 2581ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, 2591ae64cecSChristian König vega10_ih_doorbell_rptr(ih)); 260282aae55SKen Wang 261ad710812SChristian König ih = &adev->irq.ih1; 262ad710812SChristian König if (ih->ring_size) { 263ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING1, ih->gpu_addr >> 8); 264ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING1, 265ad710812SChristian König (ih->gpu_addr >> 40) & 0xff); 266ad710812SChristian König 267ad710812SChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 268ad710812SChristian König ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl); 2690133690eSChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 2700133690eSChristian König WPTR_OVERFLOW_ENABLE, 0); 2710133690eSChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 2720133690eSChristian König RB_FULL_DRAIN_ENABLE, 1); 273470b4250STrigger Huang if (amdgpu_virt_support_psp_prg_ih_reg(adev)) { 274470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 275470b4250STrigger Huang ih_rb_cntl)) { 276470b4250STrigger Huang DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 277470b4250STrigger Huang return -ETIMEDOUT; 278470b4250STrigger Huang } 279470b4250STrigger Huang } else { 280ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 281470b4250STrigger Huang } 282ad710812SChristian König 283ad710812SChristian König /* set rptr, wptr to 0 */ 284ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 2851ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 2861ae64cecSChristian König 2871ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1, 2881ae64cecSChristian König vega10_ih_doorbell_rptr(ih)); 289ad710812SChristian König } 290ad710812SChristian König 291ad710812SChristian König ih = &adev->irq.ih2; 292ad710812SChristian König if (ih->ring_size) { 293ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING2, ih->gpu_addr >> 8); 294ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING2, 295ad710812SChristian König (ih->gpu_addr >> 40) & 0xff); 296ad710812SChristian König 2971ae64cecSChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 298ad710812SChristian König ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl); 299470b4250STrigger Huang 300470b4250STrigger Huang if (amdgpu_virt_support_psp_prg_ih_reg(adev)) { 301470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 302470b4250STrigger Huang ih_rb_cntl)) { 303470b4250STrigger Huang DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 304470b4250STrigger Huang return -ETIMEDOUT; 305470b4250STrigger Huang } 306470b4250STrigger Huang } else { 307ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 308470b4250STrigger Huang } 309ad710812SChristian König 310ad710812SChristian König /* set rptr, wptr to 0 */ 311ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 3121ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 3131ae64cecSChristian König 3141ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2, 3151ae64cecSChristian König vega10_ih_doorbell_rptr(ih)); 316ad710812SChristian König } 317ad710812SChristian König 318b2b7e457SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 319282aae55SKen Wang tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 320282aae55SKen Wang CLIENT18_IS_STORM_CLIENT, 1); 321b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 322282aae55SKen Wang 323b2b7e457SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 324282aae55SKen Wang tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 325b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 326282aae55SKen Wang 327282aae55SKen Wang pci_set_master(adev->pdev); 328282aae55SKen Wang 329282aae55SKen Wang /* enable interrupts */ 330282aae55SKen Wang vega10_ih_enable_interrupts(adev); 331282aae55SKen Wang 332282aae55SKen Wang return ret; 333282aae55SKen Wang } 334282aae55SKen Wang 335282aae55SKen Wang /** 336282aae55SKen Wang * vega10_ih_irq_disable - disable interrupts 337282aae55SKen Wang * 338282aae55SKen Wang * @adev: amdgpu_device pointer 339282aae55SKen Wang * 340282aae55SKen Wang * Disable interrupts on the hw (VEGA10). 341282aae55SKen Wang */ 342282aae55SKen Wang static void vega10_ih_irq_disable(struct amdgpu_device *adev) 343282aae55SKen Wang { 344282aae55SKen Wang vega10_ih_disable_interrupts(adev); 345282aae55SKen Wang 346282aae55SKen Wang /* Wait and acknowledge irq */ 347282aae55SKen Wang mdelay(1); 348282aae55SKen Wang } 349282aae55SKen Wang 350282aae55SKen Wang /** 351282aae55SKen Wang * vega10_ih_get_wptr - get the IH ring buffer wptr 352282aae55SKen Wang * 353282aae55SKen Wang * @adev: amdgpu_device pointer 354282aae55SKen Wang * 355282aae55SKen Wang * Get the IH ring buffer wptr from either the register 356282aae55SKen Wang * or the writeback memory buffer (VEGA10). Also check for 357282aae55SKen Wang * ring buffer overflow and deal with it. 358282aae55SKen Wang * Returns the value of the wptr. 359282aae55SKen Wang */ 3608bb9eb48SChristian König static u32 vega10_ih_get_wptr(struct amdgpu_device *adev, 3618bb9eb48SChristian König struct amdgpu_ih_ring *ih) 362282aae55SKen Wang { 363cf67950eSChristian König u32 wptr, reg, tmp; 364282aae55SKen Wang 365d81f78b4SChristian König wptr = le32_to_cpu(*ih->wptr_cpu); 366282aae55SKen Wang 367b8217575SChristian König if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 368b8217575SChristian König goto out; 369b8217575SChristian König 370b8217575SChristian König /* Double check that the overflow wasn't already cleared. */ 371cf67950eSChristian König 372cf67950eSChristian König if (ih == &adev->irq.ih) 373cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 374cf67950eSChristian König else if (ih == &adev->irq.ih1) 375cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 376cf67950eSChristian König else if (ih == &adev->irq.ih2) 377cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 378cf67950eSChristian König else 379cf67950eSChristian König BUG(); 380cf67950eSChristian König 381cf67950eSChristian König wptr = RREG32_NO_KIQ(reg); 382b8217575SChristian König if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 383b8217575SChristian König goto out; 384b8217575SChristian König 385282aae55SKen Wang wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 386282aae55SKen Wang 387282aae55SKen Wang /* When a ring buffer overflow happen start parsing interrupt 388282aae55SKen Wang * from the last not overwritten vector (wptr + 32). Hopefully 389282aae55SKen Wang * this should allow us to catchup. 390282aae55SKen Wang */ 3918bb9eb48SChristian König tmp = (wptr + 32) & ih->ptr_mask; 392b8217575SChristian König dev_warn(adev->dev, "IH ring buffer overflow " 393b8217575SChristian König "(0x%08X, 0x%08X, 0x%08X)\n", 3948bb9eb48SChristian König wptr, ih->rptr, tmp); 3958bb9eb48SChristian König ih->rptr = tmp; 396282aae55SKen Wang 397cf67950eSChristian König if (ih == &adev->irq.ih) 398cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 399cf67950eSChristian König else if (ih == &adev->irq.ih1) 400cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 401cf67950eSChristian König else if (ih == &adev->irq.ih2) 402cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 403cf67950eSChristian König else 404cf67950eSChristian König BUG(); 405cf67950eSChristian König 406cf67950eSChristian König tmp = RREG32_NO_KIQ(reg); 407282aae55SKen Wang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 408cf67950eSChristian König WREG32_NO_KIQ(reg, tmp); 409b8217575SChristian König 410b8217575SChristian König out: 4118bb9eb48SChristian König return (wptr & ih->ptr_mask); 412282aae55SKen Wang } 413282aae55SKen Wang 414282aae55SKen Wang /** 415282aae55SKen Wang * vega10_ih_decode_iv - decode an interrupt vector 416282aae55SKen Wang * 417282aae55SKen Wang * @adev: amdgpu_device pointer 418282aae55SKen Wang * 419282aae55SKen Wang * Decodes the interrupt vector at the current rptr 420282aae55SKen Wang * position and also advance the position. 421282aae55SKen Wang */ 422282aae55SKen Wang static void vega10_ih_decode_iv(struct amdgpu_device *adev, 4238bb9eb48SChristian König struct amdgpu_ih_ring *ih, 424282aae55SKen Wang struct amdgpu_iv_entry *entry) 425282aae55SKen Wang { 426282aae55SKen Wang /* wptr/rptr are in bytes! */ 4278bb9eb48SChristian König u32 ring_index = ih->rptr >> 2; 428282aae55SKen Wang uint32_t dw[8]; 429282aae55SKen Wang 4308bb9eb48SChristian König dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 4318bb9eb48SChristian König dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 4328bb9eb48SChristian König dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 4338bb9eb48SChristian König dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 4348bb9eb48SChristian König dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); 4358bb9eb48SChristian König dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); 4368bb9eb48SChristian König dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); 4378bb9eb48SChristian König dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); 438282aae55SKen Wang 439282aae55SKen Wang entry->client_id = dw[0] & 0xff; 440282aae55SKen Wang entry->src_id = (dw[0] >> 8) & 0xff; 441282aae55SKen Wang entry->ring_id = (dw[0] >> 16) & 0xff; 442c4f46f22SChristian König entry->vmid = (dw[0] >> 24) & 0xf; 443c4f46f22SChristian König entry->vmid_src = (dw[0] >> 31); 444282aae55SKen Wang entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); 445282aae55SKen Wang entry->timestamp_src = dw[2] >> 31; 4463816e42fSChristian König entry->pasid = dw[3] & 0xffff; 447282aae55SKen Wang entry->pasid_src = dw[3] >> 31; 448282aae55SKen Wang entry->src_data[0] = dw[4]; 449282aae55SKen Wang entry->src_data[1] = dw[5]; 450282aae55SKen Wang entry->src_data[2] = dw[6]; 451282aae55SKen Wang entry->src_data[3] = dw[7]; 452282aae55SKen Wang 453282aae55SKen Wang /* wptr/rptr are in bytes! */ 4548bb9eb48SChristian König ih->rptr += 32; 455282aae55SKen Wang } 456282aae55SKen Wang 457282aae55SKen Wang /** 45874dcfe74STrigger Huang * vega10_ih_irq_rearm - rearm IRQ if lost 45974dcfe74STrigger Huang * 46074dcfe74STrigger Huang * @adev: amdgpu_device pointer 46174dcfe74STrigger Huang * 46274dcfe74STrigger Huang */ 46374dcfe74STrigger Huang static void vega10_ih_irq_rearm(struct amdgpu_device *adev, 46474dcfe74STrigger Huang struct amdgpu_ih_ring *ih) 46574dcfe74STrigger Huang { 46674dcfe74STrigger Huang uint32_t reg_rptr = 0; 46774dcfe74STrigger Huang uint32_t v = 0; 46874dcfe74STrigger Huang uint32_t i = 0; 46974dcfe74STrigger Huang 47074dcfe74STrigger Huang if (ih == &adev->irq.ih) 47174dcfe74STrigger Huang reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 47274dcfe74STrigger Huang else if (ih == &adev->irq.ih1) 47374dcfe74STrigger Huang reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 47474dcfe74STrigger Huang else if (ih == &adev->irq.ih2) 47574dcfe74STrigger Huang reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 47674dcfe74STrigger Huang else 47774dcfe74STrigger Huang return; 47874dcfe74STrigger Huang 47974dcfe74STrigger Huang /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */ 48074dcfe74STrigger Huang for (i = 0; i < MAX_REARM_RETRY; i++) { 48174dcfe74STrigger Huang v = RREG32_NO_KIQ(reg_rptr); 48274dcfe74STrigger Huang if ((v < ih->ring_size) && (v != ih->rptr)) 48374dcfe74STrigger Huang WDOORBELL32(ih->doorbell_index, ih->rptr); 48474dcfe74STrigger Huang else 48574dcfe74STrigger Huang break; 48674dcfe74STrigger Huang } 48774dcfe74STrigger Huang } 48874dcfe74STrigger Huang 48974dcfe74STrigger Huang /** 490282aae55SKen Wang * vega10_ih_set_rptr - set the IH ring buffer rptr 491282aae55SKen Wang * 492282aae55SKen Wang * @adev: amdgpu_device pointer 493282aae55SKen Wang * 494282aae55SKen Wang * Set the IH ring buffer rptr. 495282aae55SKen Wang */ 4968bb9eb48SChristian König static void vega10_ih_set_rptr(struct amdgpu_device *adev, 4978bb9eb48SChristian König struct amdgpu_ih_ring *ih) 498282aae55SKen Wang { 4998bb9eb48SChristian König if (ih->use_doorbell) { 500282aae55SKen Wang /* XXX check if swapping is necessary on BE */ 501d81f78b4SChristian König *ih->rptr_cpu = ih->rptr; 5028bb9eb48SChristian König WDOORBELL32(ih->doorbell_index, ih->rptr); 50374dcfe74STrigger Huang 50474dcfe74STrigger Huang if (amdgpu_sriov_vf(adev)) 50574dcfe74STrigger Huang vega10_ih_irq_rearm(adev, ih); 506cf67950eSChristian König } else if (ih == &adev->irq.ih) { 5078bb9eb48SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr); 508cf67950eSChristian König } else if (ih == &adev->irq.ih1) { 509cf67950eSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, ih->rptr); 510cf67950eSChristian König } else if (ih == &adev->irq.ih2) { 511cf67950eSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, ih->rptr); 512282aae55SKen Wang } 513282aae55SKen Wang } 514282aae55SKen Wang 515cf67950eSChristian König /** 516cf67950eSChristian König * vega10_ih_self_irq - dispatch work for ring 1 and 2 517cf67950eSChristian König * 518cf67950eSChristian König * @adev: amdgpu_device pointer 519cf67950eSChristian König * @source: irq source 520cf67950eSChristian König * @entry: IV with WPTR update 521cf67950eSChristian König * 522cf67950eSChristian König * Update the WPTR from the IV and schedule work to handle the entries. 523cf67950eSChristian König */ 524cf67950eSChristian König static int vega10_ih_self_irq(struct amdgpu_device *adev, 525cf67950eSChristian König struct amdgpu_irq_src *source, 526cf67950eSChristian König struct amdgpu_iv_entry *entry) 527cf67950eSChristian König { 528cf67950eSChristian König uint32_t wptr = cpu_to_le32(entry->src_data[0]); 529cf67950eSChristian König 530cf67950eSChristian König switch (entry->ring_id) { 531cf67950eSChristian König case 1: 532cf67950eSChristian König *adev->irq.ih1.wptr_cpu = wptr; 533cf67950eSChristian König schedule_work(&adev->irq.ih1_work); 534cf67950eSChristian König break; 535cf67950eSChristian König case 2: 536cf67950eSChristian König *adev->irq.ih2.wptr_cpu = wptr; 537cf67950eSChristian König schedule_work(&adev->irq.ih2_work); 538cf67950eSChristian König break; 539cf67950eSChristian König default: break; 540cf67950eSChristian König } 541cf67950eSChristian König return 0; 542cf67950eSChristian König } 543cf67950eSChristian König 544cf67950eSChristian König static const struct amdgpu_irq_src_funcs vega10_ih_self_irq_funcs = { 545cf67950eSChristian König .process = vega10_ih_self_irq, 546cf67950eSChristian König }; 547cf67950eSChristian König 548cf67950eSChristian König static void vega10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 549cf67950eSChristian König { 550cf67950eSChristian König adev->irq.self_irq.num_types = 0; 551cf67950eSChristian König adev->irq.self_irq.funcs = &vega10_ih_self_irq_funcs; 552cf67950eSChristian König } 553cf67950eSChristian König 554282aae55SKen Wang static int vega10_ih_early_init(void *handle) 555282aae55SKen Wang { 556282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 557282aae55SKen Wang 558282aae55SKen Wang vega10_ih_set_interrupt_funcs(adev); 559cf67950eSChristian König vega10_ih_set_self_irq_funcs(adev); 560282aae55SKen Wang return 0; 561282aae55SKen Wang } 562282aae55SKen Wang 563282aae55SKen Wang static int vega10_ih_sw_init(void *handle) 564282aae55SKen Wang { 565282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 566cf67950eSChristian König int r; 567cf67950eSChristian König 568cf67950eSChristian König r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 569cf67950eSChristian König &adev->irq.self_irq); 570cf67950eSChristian König if (r) 571cf67950eSChristian König return r; 572282aae55SKen Wang 573425c3143SChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true); 574282aae55SKen Wang if (r) 575282aae55SKen Wang return r; 576282aae55SKen Wang 5771ae64cecSChristian König adev->irq.ih.use_doorbell = true; 5781ae64cecSChristian König adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 5791ae64cecSChristian König 580ad710812SChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 581ad710812SChristian König if (r) 582ad710812SChristian König return r; 583ad710812SChristian König 5841ae64cecSChristian König adev->irq.ih1.use_doorbell = true; 585b51cd19eSChristian König adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; 5861ae64cecSChristian König 587ad710812SChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 588ad710812SChristian König if (r) 589ad710812SChristian König return r; 590ad710812SChristian König 5911ae64cecSChristian König adev->irq.ih2.use_doorbell = true; 592b51cd19eSChristian König adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1; 593282aae55SKen Wang 594282aae55SKen Wang r = amdgpu_irq_init(adev); 595282aae55SKen Wang 596282aae55SKen Wang return r; 597282aae55SKen Wang } 598282aae55SKen Wang 599282aae55SKen Wang static int vega10_ih_sw_fini(void *handle) 600282aae55SKen Wang { 601282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 602282aae55SKen Wang 603282aae55SKen Wang amdgpu_irq_fini(adev); 604ad710812SChristian König amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 605ad710812SChristian König amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 606425c3143SChristian König amdgpu_ih_ring_fini(adev, &adev->irq.ih); 607282aae55SKen Wang 608282aae55SKen Wang return 0; 609282aae55SKen Wang } 610282aae55SKen Wang 611282aae55SKen Wang static int vega10_ih_hw_init(void *handle) 612282aae55SKen Wang { 613282aae55SKen Wang int r; 614282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 615282aae55SKen Wang 616282aae55SKen Wang r = vega10_ih_irq_init(adev); 617282aae55SKen Wang if (r) 618282aae55SKen Wang return r; 619282aae55SKen Wang 620282aae55SKen Wang return 0; 621282aae55SKen Wang } 622282aae55SKen Wang 623282aae55SKen Wang static int vega10_ih_hw_fini(void *handle) 624282aae55SKen Wang { 625282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 626282aae55SKen Wang 627282aae55SKen Wang vega10_ih_irq_disable(adev); 628282aae55SKen Wang 629282aae55SKen Wang return 0; 630282aae55SKen Wang } 631282aae55SKen Wang 632282aae55SKen Wang static int vega10_ih_suspend(void *handle) 633282aae55SKen Wang { 634282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 635282aae55SKen Wang 636282aae55SKen Wang return vega10_ih_hw_fini(adev); 637282aae55SKen Wang } 638282aae55SKen Wang 639282aae55SKen Wang static int vega10_ih_resume(void *handle) 640282aae55SKen Wang { 641282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 642282aae55SKen Wang 643282aae55SKen Wang return vega10_ih_hw_init(adev); 644282aae55SKen Wang } 645282aae55SKen Wang 646282aae55SKen Wang static bool vega10_ih_is_idle(void *handle) 647282aae55SKen Wang { 648282aae55SKen Wang /* todo */ 649282aae55SKen Wang return true; 650282aae55SKen Wang } 651282aae55SKen Wang 652282aae55SKen Wang static int vega10_ih_wait_for_idle(void *handle) 653282aae55SKen Wang { 654282aae55SKen Wang /* todo */ 655282aae55SKen Wang return -ETIMEDOUT; 656282aae55SKen Wang } 657282aae55SKen Wang 658282aae55SKen Wang static int vega10_ih_soft_reset(void *handle) 659282aae55SKen Wang { 660282aae55SKen Wang /* todo */ 661282aae55SKen Wang 662282aae55SKen Wang return 0; 663282aae55SKen Wang } 664282aae55SKen Wang 665282aae55SKen Wang static int vega10_ih_set_clockgating_state(void *handle, 666282aae55SKen Wang enum amd_clockgating_state state) 667282aae55SKen Wang { 668282aae55SKen Wang return 0; 669282aae55SKen Wang } 670282aae55SKen Wang 671282aae55SKen Wang static int vega10_ih_set_powergating_state(void *handle, 672282aae55SKen Wang enum amd_powergating_state state) 673282aae55SKen Wang { 674282aae55SKen Wang return 0; 675282aae55SKen Wang } 676282aae55SKen Wang 677282aae55SKen Wang const struct amd_ip_funcs vega10_ih_ip_funcs = { 678282aae55SKen Wang .name = "vega10_ih", 679282aae55SKen Wang .early_init = vega10_ih_early_init, 680282aae55SKen Wang .late_init = NULL, 681282aae55SKen Wang .sw_init = vega10_ih_sw_init, 682282aae55SKen Wang .sw_fini = vega10_ih_sw_fini, 683282aae55SKen Wang .hw_init = vega10_ih_hw_init, 684282aae55SKen Wang .hw_fini = vega10_ih_hw_fini, 685282aae55SKen Wang .suspend = vega10_ih_suspend, 686282aae55SKen Wang .resume = vega10_ih_resume, 687282aae55SKen Wang .is_idle = vega10_ih_is_idle, 688282aae55SKen Wang .wait_for_idle = vega10_ih_wait_for_idle, 689282aae55SKen Wang .soft_reset = vega10_ih_soft_reset, 690282aae55SKen Wang .set_clockgating_state = vega10_ih_set_clockgating_state, 691282aae55SKen Wang .set_powergating_state = vega10_ih_set_powergating_state, 692282aae55SKen Wang }; 693282aae55SKen Wang 694282aae55SKen Wang static const struct amdgpu_ih_funcs vega10_ih_funcs = { 695282aae55SKen Wang .get_wptr = vega10_ih_get_wptr, 696282aae55SKen Wang .decode_iv = vega10_ih_decode_iv, 697282aae55SKen Wang .set_rptr = vega10_ih_set_rptr 698282aae55SKen Wang }; 699282aae55SKen Wang 700282aae55SKen Wang static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 701282aae55SKen Wang { 702282aae55SKen Wang adev->irq.ih_funcs = &vega10_ih_funcs; 703282aae55SKen Wang } 704282aae55SKen Wang 705282aae55SKen Wang const struct amdgpu_ip_block_version vega10_ih_ip_block = 706282aae55SKen Wang { 707282aae55SKen Wang .type = AMD_IP_BLOCK_TYPE_IH, 708282aae55SKen Wang .major = 4, 709282aae55SKen Wang .minor = 0, 710282aae55SKen Wang .rev = 0, 711282aae55SKen Wang .funcs = &vega10_ih_ip_funcs, 712282aae55SKen Wang }; 713