1282aae55SKen Wang /* 2282aae55SKen Wang * Copyright 2016 Advanced Micro Devices, Inc. 3282aae55SKen Wang * 4282aae55SKen Wang * Permission is hereby granted, free of charge, to any person obtaining a 5282aae55SKen Wang * copy of this software and associated documentation files (the "Software"), 6282aae55SKen Wang * to deal in the Software without restriction, including without limitation 7282aae55SKen Wang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8282aae55SKen Wang * and/or sell copies of the Software, and to permit persons to whom the 9282aae55SKen Wang * Software is furnished to do so, subject to the following conditions: 10282aae55SKen Wang * 11282aae55SKen Wang * The above copyright notice and this permission notice shall be included in 12282aae55SKen Wang * all copies or substantial portions of the Software. 13282aae55SKen Wang * 14282aae55SKen Wang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15282aae55SKen Wang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16282aae55SKen Wang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17282aae55SKen Wang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18282aae55SKen Wang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19282aae55SKen Wang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20282aae55SKen Wang * OTHER DEALINGS IN THE SOFTWARE. 21282aae55SKen Wang * 22282aae55SKen Wang */ 2347b757fbSSam Ravnborg 2447b757fbSSam Ravnborg #include <linux/pci.h> 2547b757fbSSam Ravnborg 26282aae55SKen Wang #include "amdgpu.h" 27282aae55SKen Wang #include "amdgpu_ih.h" 28282aae55SKen Wang #include "soc15.h" 29282aae55SKen Wang 308af7454eSFeifei Xu #include "oss/osssys_4_0_offset.h" 318af7454eSFeifei Xu #include "oss/osssys_4_0_sh_mask.h" 32282aae55SKen Wang 33282aae55SKen Wang #include "soc15_common.h" 34282aae55SKen Wang #include "vega10_ih.h" 35282aae55SKen Wang 3674dcfe74STrigger Huang #define MAX_REARM_RETRY 10 37282aae55SKen Wang 38282aae55SKen Wang static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 39282aae55SKen Wang 40282aae55SKen Wang /** 411ebb4841SHawking Zhang * vega10_ih_init_register_offset - Initialize register offset for ih rings 421ebb4841SHawking Zhang * 431ebb4841SHawking Zhang * @adev: amdgpu_device pointer 441ebb4841SHawking Zhang * 451ebb4841SHawking Zhang * Initialize register offset ih rings (VEGA10). 461ebb4841SHawking Zhang */ 471ebb4841SHawking Zhang static void vega10_ih_init_register_offset(struct amdgpu_device *adev) 481ebb4841SHawking Zhang { 491ebb4841SHawking Zhang struct amdgpu_ih_regs *ih_regs; 501ebb4841SHawking Zhang 511ebb4841SHawking Zhang if (adev->irq.ih.ring_size) { 521ebb4841SHawking Zhang ih_regs = &adev->irq.ih.ih_regs; 531ebb4841SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); 541ebb4841SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); 551ebb4841SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 561ebb4841SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 571ebb4841SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 581ebb4841SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); 591ebb4841SHawking Zhang ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); 601ebb4841SHawking Zhang ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); 611ebb4841SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; 621ebb4841SHawking Zhang } 631ebb4841SHawking Zhang 641ebb4841SHawking Zhang if (adev->irq.ih1.ring_size) { 651ebb4841SHawking Zhang ih_regs = &adev->irq.ih1.ih_regs; 661ebb4841SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); 671ebb4841SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); 681ebb4841SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 691ebb4841SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 701ebb4841SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 711ebb4841SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1); 721ebb4841SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; 731ebb4841SHawking Zhang } 741ebb4841SHawking Zhang 751ebb4841SHawking Zhang if (adev->irq.ih2.ring_size) { 761ebb4841SHawking Zhang ih_regs = &adev->irq.ih2.ih_regs; 771ebb4841SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); 781ebb4841SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2); 791ebb4841SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 801ebb4841SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 811ebb4841SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 821ebb4841SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2); 831ebb4841SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2; 841ebb4841SHawking Zhang } 851ebb4841SHawking Zhang } 861ebb4841SHawking Zhang 871ebb4841SHawking Zhang /** 88c7375032SHawking Zhang * vega10_ih_toggle_ring_interrupts - toggle the interrupt ring buffer 89c7375032SHawking Zhang * 90c7375032SHawking Zhang * @adev: amdgpu_device pointer 91c7375032SHawking Zhang * @ih: amdgpu_ih_ring pointet 92c7375032SHawking Zhang * @enable: true - enable the interrupts, false - disable the interrupts 93c7375032SHawking Zhang * 94c7375032SHawking Zhang * Toggle the interrupt ring buffer (VEGA10) 95c7375032SHawking Zhang */ 96c7375032SHawking Zhang static int vega10_ih_toggle_ring_interrupts(struct amdgpu_device *adev, 97c7375032SHawking Zhang struct amdgpu_ih_ring *ih, 98c7375032SHawking Zhang bool enable) 99c7375032SHawking Zhang { 100c7375032SHawking Zhang struct amdgpu_ih_regs *ih_regs; 101c7375032SHawking Zhang uint32_t tmp; 102c7375032SHawking Zhang 103c7375032SHawking Zhang ih_regs = &ih->ih_regs; 104c7375032SHawking Zhang 105c7375032SHawking Zhang tmp = RREG32(ih_regs->ih_rb_cntl); 106c7375032SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); 107c7375032SHawking Zhang /* enable_intr field is only valid in ring0 */ 108c7375032SHawking Zhang if (ih == &adev->irq.ih) 109c7375032SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); 110c7375032SHawking Zhang if (amdgpu_sriov_vf(adev)) { 111c7375032SHawking Zhang if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 112c7375032SHawking Zhang dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 113c7375032SHawking Zhang return -ETIMEDOUT; 114c7375032SHawking Zhang } 115c7375032SHawking Zhang } else { 116c7375032SHawking Zhang WREG32(ih_regs->ih_rb_cntl, tmp); 117c7375032SHawking Zhang } 118c7375032SHawking Zhang 119c7375032SHawking Zhang if (enable) { 120c7375032SHawking Zhang ih->enabled = true; 121c7375032SHawking Zhang } else { 122c7375032SHawking Zhang /* set rptr, wptr to 0 */ 123c7375032SHawking Zhang WREG32(ih_regs->ih_rb_rptr, 0); 124c7375032SHawking Zhang WREG32(ih_regs->ih_rb_wptr, 0); 125c7375032SHawking Zhang ih->enabled = false; 126c7375032SHawking Zhang ih->rptr = 0; 127c7375032SHawking Zhang } 128c7375032SHawking Zhang 129c7375032SHawking Zhang return 0; 130c7375032SHawking Zhang } 131c7375032SHawking Zhang 132fd95e1b1SHawking Zhang /** 133fd95e1b1SHawking Zhang * vega10_ih_toggle_interrupts - Toggle all the available interrupt ring buffers 134fd95e1b1SHawking Zhang * 135fd95e1b1SHawking Zhang * @adev: amdgpu_device pointer 136fd95e1b1SHawking Zhang * @enable: enable or disable interrupt ring buffers 137fd95e1b1SHawking Zhang * 138fd95e1b1SHawking Zhang * Toggle all the available interrupt ring buffers (VEGA10). 139fd95e1b1SHawking Zhang */ 140fd95e1b1SHawking Zhang static int vega10_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable) 141fd95e1b1SHawking Zhang { 142fd95e1b1SHawking Zhang struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 143fd95e1b1SHawking Zhang int i; 144fd95e1b1SHawking Zhang int r; 145fd95e1b1SHawking Zhang 146fd95e1b1SHawking Zhang for (i = 0; i < ARRAY_SIZE(ih); i++) { 147fd95e1b1SHawking Zhang if (ih[i]->ring_size) { 148fd95e1b1SHawking Zhang r = vega10_ih_toggle_ring_interrupts(adev, ih[i], enable); 149fd95e1b1SHawking Zhang if (r) 150fd95e1b1SHawking Zhang return r; 151fd95e1b1SHawking Zhang } 152fd95e1b1SHawking Zhang } 153fd95e1b1SHawking Zhang 154fd95e1b1SHawking Zhang return 0; 155fd95e1b1SHawking Zhang } 156fd95e1b1SHawking Zhang 157ad710812SChristian König static uint32_t vega10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 158ad710812SChristian König { 159ad710812SChristian König int rb_bufsz = order_base_2(ih->ring_size / 4); 160ad710812SChristian König 161ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 162ad710812SChristian König MC_SPACE, ih->use_bus_addr ? 1 : 4); 163ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 164ad710812SChristian König WPTR_OVERFLOW_CLEAR, 1); 165ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 166ad710812SChristian König WPTR_OVERFLOW_ENABLE, 1); 167ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 168ad710812SChristian König /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 169ad710812SChristian König * value is written to memory 170ad710812SChristian König */ 171ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 172ad710812SChristian König WPTR_WRITEBACK_ENABLE, 1); 173ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 174ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 175ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 176ad710812SChristian König 177ad710812SChristian König return ih_rb_cntl; 178282aae55SKen Wang } 179282aae55SKen Wang 1801ae64cecSChristian König static uint32_t vega10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 1811ae64cecSChristian König { 1821ae64cecSChristian König u32 ih_doorbell_rtpr = 0; 1831ae64cecSChristian König 1841ae64cecSChristian König if (ih->use_doorbell) { 1851ae64cecSChristian König ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 1861ae64cecSChristian König IH_DOORBELL_RPTR, OFFSET, 1871ae64cecSChristian König ih->doorbell_index); 1881ae64cecSChristian König ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 1891ae64cecSChristian König IH_DOORBELL_RPTR, 1901ae64cecSChristian König ENABLE, 1); 1911ae64cecSChristian König } else { 1921ae64cecSChristian König ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 1931ae64cecSChristian König IH_DOORBELL_RPTR, 1941ae64cecSChristian König ENABLE, 0); 1951ae64cecSChristian König } 1961ae64cecSChristian König return ih_doorbell_rtpr; 1971ae64cecSChristian König } 1981ae64cecSChristian König 199282aae55SKen Wang /** 200ffa02126SHawking Zhang * vega10_ih_enable_ring - enable an ih ring buffer 201ffa02126SHawking Zhang * 202ffa02126SHawking Zhang * @adev: amdgpu_device pointer 203ffa02126SHawking Zhang * @ih: amdgpu_ih_ring pointer 204ffa02126SHawking Zhang * 205ffa02126SHawking Zhang * Enable an ih ring buffer (VEGA10) 206ffa02126SHawking Zhang */ 207ffa02126SHawking Zhang static int vega10_ih_enable_ring(struct amdgpu_device *adev, 208ffa02126SHawking Zhang struct amdgpu_ih_ring *ih) 209ffa02126SHawking Zhang { 210ffa02126SHawking Zhang struct amdgpu_ih_regs *ih_regs; 211ffa02126SHawking Zhang uint32_t tmp; 212ffa02126SHawking Zhang 213ffa02126SHawking Zhang ih_regs = &ih->ih_regs; 214ffa02126SHawking Zhang 215ffa02126SHawking Zhang /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 216ffa02126SHawking Zhang WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); 217ffa02126SHawking Zhang WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); 218ffa02126SHawking Zhang 219ffa02126SHawking Zhang tmp = RREG32(ih_regs->ih_rb_cntl); 220ffa02126SHawking Zhang tmp = vega10_ih_rb_cntl(ih, tmp); 221ffa02126SHawking Zhang if (ih == &adev->irq.ih) 222ffa02126SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); 223ffa02126SHawking Zhang if (ih == &adev->irq.ih1) { 224ffa02126SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0); 225ffa02126SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); 226ffa02126SHawking Zhang } 227ffa02126SHawking Zhang if (amdgpu_sriov_vf(adev)) { 228ffa02126SHawking Zhang if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 229ffa02126SHawking Zhang dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 230ffa02126SHawking Zhang return -ETIMEDOUT; 231ffa02126SHawking Zhang } 232ffa02126SHawking Zhang } else { 233ffa02126SHawking Zhang WREG32(ih_regs->ih_rb_cntl, tmp); 234ffa02126SHawking Zhang } 235ffa02126SHawking Zhang 236ffa02126SHawking Zhang if (ih == &adev->irq.ih) { 237ffa02126SHawking Zhang /* set the ih ring 0 writeback address whether it's enabled or not */ 238ffa02126SHawking Zhang WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); 239ffa02126SHawking Zhang WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); 240ffa02126SHawking Zhang } 241ffa02126SHawking Zhang 242ffa02126SHawking Zhang /* set rptr, wptr to 0 */ 243ffa02126SHawking Zhang WREG32(ih_regs->ih_rb_wptr, 0); 244ffa02126SHawking Zhang WREG32(ih_regs->ih_rb_rptr, 0); 245ffa02126SHawking Zhang 246ffa02126SHawking Zhang WREG32(ih_regs->ih_doorbell_rptr, vega10_ih_doorbell_rptr(ih)); 247ffa02126SHawking Zhang 248ffa02126SHawking Zhang return 0; 249ffa02126SHawking Zhang } 250ffa02126SHawking Zhang 251ffa02126SHawking Zhang /** 252282aae55SKen Wang * vega10_ih_irq_init - init and enable the interrupt ring 253282aae55SKen Wang * 254282aae55SKen Wang * @adev: amdgpu_device pointer 255282aae55SKen Wang * 256282aae55SKen Wang * Allocate a ring buffer for the interrupt controller, 257282aae55SKen Wang * enable the RLC, disable interrupts, enable the IH 258282aae55SKen Wang * ring buffer and enable it (VI). 259282aae55SKen Wang * Called at device load and reume. 260282aae55SKen Wang * Returns 0 for success, errors for failure. 261282aae55SKen Wang */ 262282aae55SKen Wang static int vega10_ih_irq_init(struct amdgpu_device *adev) 263282aae55SKen Wang { 26421822b6aSHawking Zhang struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 26521822b6aSHawking Zhang u32 ih_chicken; 266fd95e1b1SHawking Zhang int ret; 26721822b6aSHawking Zhang int i; 268282aae55SKen Wang u32 tmp; 269282aae55SKen Wang 270282aae55SKen Wang /* disable irqs */ 271fd95e1b1SHawking Zhang ret = vega10_ih_toggle_interrupts(adev, false); 272fd95e1b1SHawking Zhang if (ret) 273fd95e1b1SHawking Zhang return ret; 274282aae55SKen Wang 275bebc0762SHawking Zhang adev->nbio.funcs->ih_control(adev); 276282aae55SKen Wang 27725344d7eSZhigang Luo if ((adev->asic_type == CHIP_ARCTURUS && 27825344d7eSZhigang Luo adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) || 27925344d7eSZhigang Luo adev->asic_type == CHIP_RENOIR) { 28025344d7eSZhigang Luo ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 28125344d7eSZhigang Luo if (adev->irq.ih.use_bus_addr) { 28225344d7eSZhigang Luo ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 28325344d7eSZhigang Luo MC_SPACE_GPA_ENABLE, 1); 28425344d7eSZhigang Luo } else { 28525344d7eSZhigang Luo ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 28625344d7eSZhigang Luo MC_SPACE_FBPA_ENABLE, 1); 28725344d7eSZhigang Luo } 288f9c84ae5SLe Ma WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 28925344d7eSZhigang Luo } 290f9c84ae5SLe Ma 29121822b6aSHawking Zhang for (i = 0; i < ARRAY_SIZE(ih); i++) { 29221822b6aSHawking Zhang if (ih[i]->ring_size) { 29321822b6aSHawking Zhang ret = vega10_ih_enable_ring(adev, ih[i]); 29421822b6aSHawking Zhang if (ret) 29521822b6aSHawking Zhang return ret; 296470b4250STrigger Huang } 297ad710812SChristian König } 298ad710812SChristian König 299b2b7e457SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 300282aae55SKen Wang tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 301282aae55SKen Wang CLIENT18_IS_STORM_CLIENT, 1); 302b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 303282aae55SKen Wang 304b2b7e457SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 305282aae55SKen Wang tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 306b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 307282aae55SKen Wang 308282aae55SKen Wang pci_set_master(adev->pdev); 309282aae55SKen Wang 310282aae55SKen Wang /* enable interrupts */ 311fd95e1b1SHawking Zhang ret = vega10_ih_toggle_interrupts(adev, true); 312fd95e1b1SHawking Zhang if (ret) 313282aae55SKen Wang return ret; 314fd95e1b1SHawking Zhang 315fd95e1b1SHawking Zhang return 0; 316282aae55SKen Wang } 317282aae55SKen Wang 318282aae55SKen Wang /** 319282aae55SKen Wang * vega10_ih_irq_disable - disable interrupts 320282aae55SKen Wang * 321282aae55SKen Wang * @adev: amdgpu_device pointer 322282aae55SKen Wang * 323282aae55SKen Wang * Disable interrupts on the hw (VEGA10). 324282aae55SKen Wang */ 325282aae55SKen Wang static void vega10_ih_irq_disable(struct amdgpu_device *adev) 326282aae55SKen Wang { 327fd95e1b1SHawking Zhang vega10_ih_toggle_interrupts(adev, false); 328282aae55SKen Wang 329282aae55SKen Wang /* Wait and acknowledge irq */ 330282aae55SKen Wang mdelay(1); 331282aae55SKen Wang } 332282aae55SKen Wang 333282aae55SKen Wang /** 334282aae55SKen Wang * vega10_ih_get_wptr - get the IH ring buffer wptr 335282aae55SKen Wang * 336282aae55SKen Wang * @adev: amdgpu_device pointer 3375162e40eSLee Jones * @ih: IH ring buffer to fetch wptr 338282aae55SKen Wang * 339282aae55SKen Wang * Get the IH ring buffer wptr from either the register 340282aae55SKen Wang * or the writeback memory buffer (VEGA10). Also check for 341282aae55SKen Wang * ring buffer overflow and deal with it. 342282aae55SKen Wang * Returns the value of the wptr. 343282aae55SKen Wang */ 3448bb9eb48SChristian König static u32 vega10_ih_get_wptr(struct amdgpu_device *adev, 3458bb9eb48SChristian König struct amdgpu_ih_ring *ih) 346282aae55SKen Wang { 347554bdbf6SHawking Zhang u32 wptr, tmp; 348554bdbf6SHawking Zhang struct amdgpu_ih_regs *ih_regs; 349282aae55SKen Wang 350d81f78b4SChristian König wptr = le32_to_cpu(*ih->wptr_cpu); 351554bdbf6SHawking Zhang ih_regs = &ih->ih_regs; 352282aae55SKen Wang 353b8217575SChristian König if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 354b8217575SChristian König goto out; 355b8217575SChristian König 356b8217575SChristian König /* Double check that the overflow wasn't already cleared. */ 357554bdbf6SHawking Zhang wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); 358b8217575SChristian König if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 359b8217575SChristian König goto out; 360b8217575SChristian König 361282aae55SKen Wang wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 362282aae55SKen Wang 363282aae55SKen Wang /* When a ring buffer overflow happen start parsing interrupt 364282aae55SKen Wang * from the last not overwritten vector (wptr + 32). Hopefully 365282aae55SKen Wang * this should allow us to catchup. 366282aae55SKen Wang */ 3678bb9eb48SChristian König tmp = (wptr + 32) & ih->ptr_mask; 368b8217575SChristian König dev_warn(adev->dev, "IH ring buffer overflow " 369b8217575SChristian König "(0x%08X, 0x%08X, 0x%08X)\n", 3708bb9eb48SChristian König wptr, ih->rptr, tmp); 3718bb9eb48SChristian König ih->rptr = tmp; 372282aae55SKen Wang 373554bdbf6SHawking Zhang tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); 374282aae55SKen Wang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 375554bdbf6SHawking Zhang WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 376b8217575SChristian König 377b8217575SChristian König out: 3788bb9eb48SChristian König return (wptr & ih->ptr_mask); 379282aae55SKen Wang } 380282aae55SKen Wang 381282aae55SKen Wang /** 38274dcfe74STrigger Huang * vega10_ih_irq_rearm - rearm IRQ if lost 38374dcfe74STrigger Huang * 38474dcfe74STrigger Huang * @adev: amdgpu_device pointer 3855162e40eSLee Jones * @ih: IH ring to match 38674dcfe74STrigger Huang * 38774dcfe74STrigger Huang */ 38874dcfe74STrigger Huang static void vega10_ih_irq_rearm(struct amdgpu_device *adev, 38974dcfe74STrigger Huang struct amdgpu_ih_ring *ih) 39074dcfe74STrigger Huang { 39174dcfe74STrigger Huang uint32_t v = 0; 39274dcfe74STrigger Huang uint32_t i = 0; 393554bdbf6SHawking Zhang struct amdgpu_ih_regs *ih_regs; 39474dcfe74STrigger Huang 395554bdbf6SHawking Zhang ih_regs = &ih->ih_regs; 39674dcfe74STrigger Huang /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */ 39774dcfe74STrigger Huang for (i = 0; i < MAX_REARM_RETRY; i++) { 398554bdbf6SHawking Zhang v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); 39974dcfe74STrigger Huang if ((v < ih->ring_size) && (v != ih->rptr)) 40074dcfe74STrigger Huang WDOORBELL32(ih->doorbell_index, ih->rptr); 40174dcfe74STrigger Huang else 40274dcfe74STrigger Huang break; 40374dcfe74STrigger Huang } 40474dcfe74STrigger Huang } 40574dcfe74STrigger Huang 40674dcfe74STrigger Huang /** 407282aae55SKen Wang * vega10_ih_set_rptr - set the IH ring buffer rptr 408282aae55SKen Wang * 409282aae55SKen Wang * @adev: amdgpu_device pointer 4105162e40eSLee Jones * @ih: IH ring buffer to set rptr 411282aae55SKen Wang * 412282aae55SKen Wang * Set the IH ring buffer rptr. 413282aae55SKen Wang */ 4148bb9eb48SChristian König static void vega10_ih_set_rptr(struct amdgpu_device *adev, 4158bb9eb48SChristian König struct amdgpu_ih_ring *ih) 416282aae55SKen Wang { 417554bdbf6SHawking Zhang struct amdgpu_ih_regs *ih_regs; 418554bdbf6SHawking Zhang 4198bb9eb48SChristian König if (ih->use_doorbell) { 420282aae55SKen Wang /* XXX check if swapping is necessary on BE */ 421d81f78b4SChristian König *ih->rptr_cpu = ih->rptr; 4228bb9eb48SChristian König WDOORBELL32(ih->doorbell_index, ih->rptr); 42374dcfe74STrigger Huang 42474dcfe74STrigger Huang if (amdgpu_sriov_vf(adev)) 42574dcfe74STrigger Huang vega10_ih_irq_rearm(adev, ih); 426554bdbf6SHawking Zhang } else { 427554bdbf6SHawking Zhang ih_regs = &ih->ih_regs; 428554bdbf6SHawking Zhang WREG32(ih_regs->ih_rb_rptr, ih->rptr); 429282aae55SKen Wang } 430282aae55SKen Wang } 431282aae55SKen Wang 432cf67950eSChristian König /** 433cf67950eSChristian König * vega10_ih_self_irq - dispatch work for ring 1 and 2 434cf67950eSChristian König * 435cf67950eSChristian König * @adev: amdgpu_device pointer 436cf67950eSChristian König * @source: irq source 437cf67950eSChristian König * @entry: IV with WPTR update 438cf67950eSChristian König * 439cf67950eSChristian König * Update the WPTR from the IV and schedule work to handle the entries. 440cf67950eSChristian König */ 441cf67950eSChristian König static int vega10_ih_self_irq(struct amdgpu_device *adev, 442cf67950eSChristian König struct amdgpu_irq_src *source, 443cf67950eSChristian König struct amdgpu_iv_entry *entry) 444cf67950eSChristian König { 445cf67950eSChristian König uint32_t wptr = cpu_to_le32(entry->src_data[0]); 446cf67950eSChristian König 447cf67950eSChristian König switch (entry->ring_id) { 448cf67950eSChristian König case 1: 449cf67950eSChristian König *adev->irq.ih1.wptr_cpu = wptr; 450cf67950eSChristian König schedule_work(&adev->irq.ih1_work); 451cf67950eSChristian König break; 452cf67950eSChristian König case 2: 453cf67950eSChristian König *adev->irq.ih2.wptr_cpu = wptr; 454cf67950eSChristian König schedule_work(&adev->irq.ih2_work); 455cf67950eSChristian König break; 456cf67950eSChristian König default: break; 457cf67950eSChristian König } 458cf67950eSChristian König return 0; 459cf67950eSChristian König } 460cf67950eSChristian König 461cf67950eSChristian König static const struct amdgpu_irq_src_funcs vega10_ih_self_irq_funcs = { 462cf67950eSChristian König .process = vega10_ih_self_irq, 463cf67950eSChristian König }; 464cf67950eSChristian König 465cf67950eSChristian König static void vega10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 466cf67950eSChristian König { 467cf67950eSChristian König adev->irq.self_irq.num_types = 0; 468cf67950eSChristian König adev->irq.self_irq.funcs = &vega10_ih_self_irq_funcs; 469cf67950eSChristian König } 470cf67950eSChristian König 471282aae55SKen Wang static int vega10_ih_early_init(void *handle) 472282aae55SKen Wang { 473282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 474282aae55SKen Wang 475282aae55SKen Wang vega10_ih_set_interrupt_funcs(adev); 476cf67950eSChristian König vega10_ih_set_self_irq_funcs(adev); 477282aae55SKen Wang return 0; 478282aae55SKen Wang } 479282aae55SKen Wang 480282aae55SKen Wang static int vega10_ih_sw_init(void *handle) 481282aae55SKen Wang { 482282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 483cf67950eSChristian König int r; 484cf67950eSChristian König 485cf67950eSChristian König r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 486cf67950eSChristian König &adev->irq.self_irq); 487cf67950eSChristian König if (r) 488cf67950eSChristian König return r; 489282aae55SKen Wang 490425c3143SChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true); 491282aae55SKen Wang if (r) 492282aae55SKen Wang return r; 493282aae55SKen Wang 4941ae64cecSChristian König adev->irq.ih.use_doorbell = true; 4951ae64cecSChristian König adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 4961ae64cecSChristian König 497ad710812SChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 498ad710812SChristian König if (r) 499ad710812SChristian König return r; 500ad710812SChristian König 5011ae64cecSChristian König adev->irq.ih1.use_doorbell = true; 502b51cd19eSChristian König adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; 5031ae64cecSChristian König 504ad710812SChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 505ad710812SChristian König if (r) 506ad710812SChristian König return r; 507ad710812SChristian König 5081ae64cecSChristian König adev->irq.ih2.use_doorbell = true; 509b51cd19eSChristian König adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1; 510282aae55SKen Wang 511f0594717SHawking Zhang /* initialize ih control registers offset */ 512f0594717SHawking Zhang vega10_ih_init_register_offset(adev); 513f0594717SHawking Zhang 51447509189SChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); 51547509189SChristian König if (r) 51647509189SChristian König return r; 51747509189SChristian König 518282aae55SKen Wang r = amdgpu_irq_init(adev); 519282aae55SKen Wang 520282aae55SKen Wang return r; 521282aae55SKen Wang } 522282aae55SKen Wang 523282aae55SKen Wang static int vega10_ih_sw_fini(void *handle) 524282aae55SKen Wang { 525282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 526282aae55SKen Wang 527282aae55SKen Wang amdgpu_irq_fini(adev); 528ad710812SChristian König amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 529ad710812SChristian König amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 530425c3143SChristian König amdgpu_ih_ring_fini(adev, &adev->irq.ih); 531282aae55SKen Wang 532282aae55SKen Wang return 0; 533282aae55SKen Wang } 534282aae55SKen Wang 535282aae55SKen Wang static int vega10_ih_hw_init(void *handle) 536282aae55SKen Wang { 537282aae55SKen Wang int r; 538282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 539282aae55SKen Wang 540282aae55SKen Wang r = vega10_ih_irq_init(adev); 541282aae55SKen Wang if (r) 542282aae55SKen Wang return r; 543282aae55SKen Wang 544282aae55SKen Wang return 0; 545282aae55SKen Wang } 546282aae55SKen Wang 547282aae55SKen Wang static int vega10_ih_hw_fini(void *handle) 548282aae55SKen Wang { 549282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 550282aae55SKen Wang 551282aae55SKen Wang vega10_ih_irq_disable(adev); 552282aae55SKen Wang 553282aae55SKen Wang return 0; 554282aae55SKen Wang } 555282aae55SKen Wang 556282aae55SKen Wang static int vega10_ih_suspend(void *handle) 557282aae55SKen Wang { 558282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 559282aae55SKen Wang 560282aae55SKen Wang return vega10_ih_hw_fini(adev); 561282aae55SKen Wang } 562282aae55SKen Wang 563282aae55SKen Wang static int vega10_ih_resume(void *handle) 564282aae55SKen Wang { 565282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 566282aae55SKen Wang 567282aae55SKen Wang return vega10_ih_hw_init(adev); 568282aae55SKen Wang } 569282aae55SKen Wang 570282aae55SKen Wang static bool vega10_ih_is_idle(void *handle) 571282aae55SKen Wang { 572282aae55SKen Wang /* todo */ 573282aae55SKen Wang return true; 574282aae55SKen Wang } 575282aae55SKen Wang 576282aae55SKen Wang static int vega10_ih_wait_for_idle(void *handle) 577282aae55SKen Wang { 578282aae55SKen Wang /* todo */ 579282aae55SKen Wang return -ETIMEDOUT; 580282aae55SKen Wang } 581282aae55SKen Wang 582282aae55SKen Wang static int vega10_ih_soft_reset(void *handle) 583282aae55SKen Wang { 584282aae55SKen Wang /* todo */ 585282aae55SKen Wang 586282aae55SKen Wang return 0; 587282aae55SKen Wang } 588282aae55SKen Wang 589227f7d58SKenneth Feng static void vega10_ih_update_clockgating_state(struct amdgpu_device *adev, 590227f7d58SKenneth Feng bool enable) 591227f7d58SKenneth Feng { 592227f7d58SKenneth Feng uint32_t data, def, field_val; 593227f7d58SKenneth Feng 594227f7d58SKenneth Feng if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 595227f7d58SKenneth Feng def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 596227f7d58SKenneth Feng field_val = enable ? 0 : 1; 597227f7d58SKenneth Feng /** 5982601fa64SHawking Zhang * Vega10/12 and RAVEN don't have IH_BUFFER_MEM_CLK_SOFT_OVERRIDE field. 599227f7d58SKenneth Feng */ 6002601fa64SHawking Zhang if (adev->asic_type == CHIP_RENOIR) 601227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 602227f7d58SKenneth Feng IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val); 603227f7d58SKenneth Feng 604227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 605227f7d58SKenneth Feng DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 606227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 607227f7d58SKenneth Feng OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 608227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 609227f7d58SKenneth Feng LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 610227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 611227f7d58SKenneth Feng DYN_CLK_SOFT_OVERRIDE, field_val); 612227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 613227f7d58SKenneth Feng REG_CLK_SOFT_OVERRIDE, field_val); 614227f7d58SKenneth Feng if (def != data) 615227f7d58SKenneth Feng WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 616227f7d58SKenneth Feng } 617227f7d58SKenneth Feng } 618227f7d58SKenneth Feng 619282aae55SKen Wang static int vega10_ih_set_clockgating_state(void *handle, 620282aae55SKen Wang enum amd_clockgating_state state) 621282aae55SKen Wang { 622227f7d58SKenneth Feng struct amdgpu_device *adev = (struct amdgpu_device *)handle; 623227f7d58SKenneth Feng 624227f7d58SKenneth Feng vega10_ih_update_clockgating_state(adev, 625a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 626282aae55SKen Wang return 0; 627227f7d58SKenneth Feng 628282aae55SKen Wang } 629282aae55SKen Wang 630282aae55SKen Wang static int vega10_ih_set_powergating_state(void *handle, 631282aae55SKen Wang enum amd_powergating_state state) 632282aae55SKen Wang { 633282aae55SKen Wang return 0; 634282aae55SKen Wang } 635282aae55SKen Wang 636282aae55SKen Wang const struct amd_ip_funcs vega10_ih_ip_funcs = { 637282aae55SKen Wang .name = "vega10_ih", 638282aae55SKen Wang .early_init = vega10_ih_early_init, 639282aae55SKen Wang .late_init = NULL, 640282aae55SKen Wang .sw_init = vega10_ih_sw_init, 641282aae55SKen Wang .sw_fini = vega10_ih_sw_fini, 642282aae55SKen Wang .hw_init = vega10_ih_hw_init, 643282aae55SKen Wang .hw_fini = vega10_ih_hw_fini, 644282aae55SKen Wang .suspend = vega10_ih_suspend, 645282aae55SKen Wang .resume = vega10_ih_resume, 646282aae55SKen Wang .is_idle = vega10_ih_is_idle, 647282aae55SKen Wang .wait_for_idle = vega10_ih_wait_for_idle, 648282aae55SKen Wang .soft_reset = vega10_ih_soft_reset, 649282aae55SKen Wang .set_clockgating_state = vega10_ih_set_clockgating_state, 650282aae55SKen Wang .set_powergating_state = vega10_ih_set_powergating_state, 651282aae55SKen Wang }; 652282aae55SKen Wang 653282aae55SKen Wang static const struct amdgpu_ih_funcs vega10_ih_funcs = { 654282aae55SKen Wang .get_wptr = vega10_ih_get_wptr, 655*40838281SHawking Zhang .decode_iv = amdgpu_ih_decode_iv_helper, 656282aae55SKen Wang .set_rptr = vega10_ih_set_rptr 657282aae55SKen Wang }; 658282aae55SKen Wang 659282aae55SKen Wang static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 660282aae55SKen Wang { 661282aae55SKen Wang adev->irq.ih_funcs = &vega10_ih_funcs; 662282aae55SKen Wang } 663282aae55SKen Wang 664282aae55SKen Wang const struct amdgpu_ip_block_version vega10_ih_ip_block = 665282aae55SKen Wang { 666282aae55SKen Wang .type = AMD_IP_BLOCK_TYPE_IH, 667282aae55SKen Wang .major = 4, 668282aae55SKen Wang .minor = 0, 669282aae55SKen Wang .rev = 0, 670282aae55SKen Wang .funcs = &vega10_ih_ip_funcs, 671282aae55SKen Wang }; 672