1282aae55SKen Wang /* 2282aae55SKen Wang * Copyright 2016 Advanced Micro Devices, Inc. 3282aae55SKen Wang * 4282aae55SKen Wang * Permission is hereby granted, free of charge, to any person obtaining a 5282aae55SKen Wang * copy of this software and associated documentation files (the "Software"), 6282aae55SKen Wang * to deal in the Software without restriction, including without limitation 7282aae55SKen Wang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8282aae55SKen Wang * and/or sell copies of the Software, and to permit persons to whom the 9282aae55SKen Wang * Software is furnished to do so, subject to the following conditions: 10282aae55SKen Wang * 11282aae55SKen Wang * The above copyright notice and this permission notice shall be included in 12282aae55SKen Wang * all copies or substantial portions of the Software. 13282aae55SKen Wang * 14282aae55SKen Wang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15282aae55SKen Wang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16282aae55SKen Wang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17282aae55SKen Wang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18282aae55SKen Wang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19282aae55SKen Wang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20282aae55SKen Wang * OTHER DEALINGS IN THE SOFTWARE. 21282aae55SKen Wang * 22282aae55SKen Wang */ 2347b757fbSSam Ravnborg 2447b757fbSSam Ravnborg #include <linux/pci.h> 2547b757fbSSam Ravnborg 26282aae55SKen Wang #include "amdgpu.h" 27282aae55SKen Wang #include "amdgpu_ih.h" 28282aae55SKen Wang #include "soc15.h" 29282aae55SKen Wang 308af7454eSFeifei Xu #include "oss/osssys_4_0_offset.h" 318af7454eSFeifei Xu #include "oss/osssys_4_0_sh_mask.h" 32282aae55SKen Wang 33282aae55SKen Wang #include "soc15_common.h" 34282aae55SKen Wang #include "vega10_ih.h" 35282aae55SKen Wang 3674dcfe74STrigger Huang #define MAX_REARM_RETRY 10 37282aae55SKen Wang 38282aae55SKen Wang static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 39282aae55SKen Wang 40282aae55SKen Wang /** 411ebb4841SHawking Zhang * vega10_ih_init_register_offset - Initialize register offset for ih rings 421ebb4841SHawking Zhang * 431ebb4841SHawking Zhang * @adev: amdgpu_device pointer 441ebb4841SHawking Zhang * 451ebb4841SHawking Zhang * Initialize register offset ih rings (VEGA10). 461ebb4841SHawking Zhang */ 471ebb4841SHawking Zhang static void vega10_ih_init_register_offset(struct amdgpu_device *adev) 481ebb4841SHawking Zhang { 491ebb4841SHawking Zhang struct amdgpu_ih_regs *ih_regs; 501ebb4841SHawking Zhang 511ebb4841SHawking Zhang if (adev->irq.ih.ring_size) { 521ebb4841SHawking Zhang ih_regs = &adev->irq.ih.ih_regs; 531ebb4841SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); 541ebb4841SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); 551ebb4841SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 561ebb4841SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 571ebb4841SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 581ebb4841SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); 591ebb4841SHawking Zhang ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); 601ebb4841SHawking Zhang ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); 611ebb4841SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; 621ebb4841SHawking Zhang } 631ebb4841SHawking Zhang 641ebb4841SHawking Zhang if (adev->irq.ih1.ring_size) { 651ebb4841SHawking Zhang ih_regs = &adev->irq.ih1.ih_regs; 661ebb4841SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); 671ebb4841SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); 681ebb4841SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 691ebb4841SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 701ebb4841SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 711ebb4841SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1); 721ebb4841SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; 731ebb4841SHawking Zhang } 741ebb4841SHawking Zhang 751ebb4841SHawking Zhang if (adev->irq.ih2.ring_size) { 761ebb4841SHawking Zhang ih_regs = &adev->irq.ih2.ih_regs; 771ebb4841SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); 781ebb4841SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2); 791ebb4841SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 801ebb4841SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 811ebb4841SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 821ebb4841SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2); 831ebb4841SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2; 841ebb4841SHawking Zhang } 851ebb4841SHawking Zhang } 861ebb4841SHawking Zhang 871ebb4841SHawking Zhang /** 88c7375032SHawking Zhang * vega10_ih_toggle_ring_interrupts - toggle the interrupt ring buffer 89c7375032SHawking Zhang * 90c7375032SHawking Zhang * @adev: amdgpu_device pointer 91c7375032SHawking Zhang * @ih: amdgpu_ih_ring pointet 92c7375032SHawking Zhang * @enable: true - enable the interrupts, false - disable the interrupts 93c7375032SHawking Zhang * 94c7375032SHawking Zhang * Toggle the interrupt ring buffer (VEGA10) 95c7375032SHawking Zhang */ 96c7375032SHawking Zhang static int vega10_ih_toggle_ring_interrupts(struct amdgpu_device *adev, 97c7375032SHawking Zhang struct amdgpu_ih_ring *ih, 98c7375032SHawking Zhang bool enable) 99c7375032SHawking Zhang { 100c7375032SHawking Zhang struct amdgpu_ih_regs *ih_regs; 101c7375032SHawking Zhang uint32_t tmp; 102c7375032SHawking Zhang 103c7375032SHawking Zhang ih_regs = &ih->ih_regs; 104c7375032SHawking Zhang 105c7375032SHawking Zhang tmp = RREG32(ih_regs->ih_rb_cntl); 106c7375032SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); 1079dd9cc2fSAlex Sierra tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1); 108c7375032SHawking Zhang /* enable_intr field is only valid in ring0 */ 109c7375032SHawking Zhang if (ih == &adev->irq.ih) 110c7375032SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); 111c7375032SHawking Zhang if (amdgpu_sriov_vf(adev)) { 112c7375032SHawking Zhang if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 113c7375032SHawking Zhang dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 114c7375032SHawking Zhang return -ETIMEDOUT; 115c7375032SHawking Zhang } 116c7375032SHawking Zhang } else { 117c7375032SHawking Zhang WREG32(ih_regs->ih_rb_cntl, tmp); 118c7375032SHawking Zhang } 119c7375032SHawking Zhang 120c7375032SHawking Zhang if (enable) { 121c7375032SHawking Zhang ih->enabled = true; 122c7375032SHawking Zhang } else { 123c7375032SHawking Zhang /* set rptr, wptr to 0 */ 124c7375032SHawking Zhang WREG32(ih_regs->ih_rb_rptr, 0); 125c7375032SHawking Zhang WREG32(ih_regs->ih_rb_wptr, 0); 126c7375032SHawking Zhang ih->enabled = false; 127c7375032SHawking Zhang ih->rptr = 0; 128c7375032SHawking Zhang } 129c7375032SHawking Zhang 130c7375032SHawking Zhang return 0; 131c7375032SHawking Zhang } 132c7375032SHawking Zhang 133fd95e1b1SHawking Zhang /** 134fd95e1b1SHawking Zhang * vega10_ih_toggle_interrupts - Toggle all the available interrupt ring buffers 135fd95e1b1SHawking Zhang * 136fd95e1b1SHawking Zhang * @adev: amdgpu_device pointer 137fd95e1b1SHawking Zhang * @enable: enable or disable interrupt ring buffers 138fd95e1b1SHawking Zhang * 139fd95e1b1SHawking Zhang * Toggle all the available interrupt ring buffers (VEGA10). 140fd95e1b1SHawking Zhang */ 141fd95e1b1SHawking Zhang static int vega10_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable) 142fd95e1b1SHawking Zhang { 143fd95e1b1SHawking Zhang struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 144fd95e1b1SHawking Zhang int i; 145fd95e1b1SHawking Zhang int r; 146fd95e1b1SHawking Zhang 147fd95e1b1SHawking Zhang for (i = 0; i < ARRAY_SIZE(ih); i++) { 148fd95e1b1SHawking Zhang if (ih[i]->ring_size) { 149fd95e1b1SHawking Zhang r = vega10_ih_toggle_ring_interrupts(adev, ih[i], enable); 150fd95e1b1SHawking Zhang if (r) 151fd95e1b1SHawking Zhang return r; 152fd95e1b1SHawking Zhang } 153fd95e1b1SHawking Zhang } 154fd95e1b1SHawking Zhang 155fd95e1b1SHawking Zhang return 0; 156fd95e1b1SHawking Zhang } 157fd95e1b1SHawking Zhang 158ad710812SChristian König static uint32_t vega10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 159ad710812SChristian König { 160ad710812SChristian König int rb_bufsz = order_base_2(ih->ring_size / 4); 161ad710812SChristian König 162ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 163ad710812SChristian König MC_SPACE, ih->use_bus_addr ? 1 : 4); 164ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 165ad710812SChristian König WPTR_OVERFLOW_CLEAR, 1); 166ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 167ad710812SChristian König WPTR_OVERFLOW_ENABLE, 1); 168ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 169ad710812SChristian König /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 170ad710812SChristian König * value is written to memory 171ad710812SChristian König */ 172ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 173ad710812SChristian König WPTR_WRITEBACK_ENABLE, 1); 174ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 175ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 176ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 177ad710812SChristian König 178ad710812SChristian König return ih_rb_cntl; 179282aae55SKen Wang } 180282aae55SKen Wang 1811ae64cecSChristian König static uint32_t vega10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 1821ae64cecSChristian König { 1831ae64cecSChristian König u32 ih_doorbell_rtpr = 0; 1841ae64cecSChristian König 1851ae64cecSChristian König if (ih->use_doorbell) { 1861ae64cecSChristian König ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 1871ae64cecSChristian König IH_DOORBELL_RPTR, OFFSET, 1881ae64cecSChristian König ih->doorbell_index); 1891ae64cecSChristian König ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 1901ae64cecSChristian König IH_DOORBELL_RPTR, 1911ae64cecSChristian König ENABLE, 1); 1921ae64cecSChristian König } else { 1931ae64cecSChristian König ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 1941ae64cecSChristian König IH_DOORBELL_RPTR, 1951ae64cecSChristian König ENABLE, 0); 1961ae64cecSChristian König } 1971ae64cecSChristian König return ih_doorbell_rtpr; 1981ae64cecSChristian König } 1991ae64cecSChristian König 200282aae55SKen Wang /** 201ffa02126SHawking Zhang * vega10_ih_enable_ring - enable an ih ring buffer 202ffa02126SHawking Zhang * 203ffa02126SHawking Zhang * @adev: amdgpu_device pointer 204ffa02126SHawking Zhang * @ih: amdgpu_ih_ring pointer 205ffa02126SHawking Zhang * 206ffa02126SHawking Zhang * Enable an ih ring buffer (VEGA10) 207ffa02126SHawking Zhang */ 208ffa02126SHawking Zhang static int vega10_ih_enable_ring(struct amdgpu_device *adev, 209ffa02126SHawking Zhang struct amdgpu_ih_ring *ih) 210ffa02126SHawking Zhang { 211ffa02126SHawking Zhang struct amdgpu_ih_regs *ih_regs; 212ffa02126SHawking Zhang uint32_t tmp; 213ffa02126SHawking Zhang 214ffa02126SHawking Zhang ih_regs = &ih->ih_regs; 215ffa02126SHawking Zhang 216ffa02126SHawking Zhang /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 217ffa02126SHawking Zhang WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); 218ffa02126SHawking Zhang WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); 219ffa02126SHawking Zhang 220ffa02126SHawking Zhang tmp = RREG32(ih_regs->ih_rb_cntl); 221ffa02126SHawking Zhang tmp = vega10_ih_rb_cntl(ih, tmp); 222ffa02126SHawking Zhang if (ih == &adev->irq.ih) 223ffa02126SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); 224b672cb1eSPhilip Yang if (ih == &adev->irq.ih1) 225ffa02126SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); 226ffa02126SHawking Zhang if (amdgpu_sriov_vf(adev)) { 227ffa02126SHawking Zhang if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 228ffa02126SHawking Zhang dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 229ffa02126SHawking Zhang return -ETIMEDOUT; 230ffa02126SHawking Zhang } 231ffa02126SHawking Zhang } else { 232ffa02126SHawking Zhang WREG32(ih_regs->ih_rb_cntl, tmp); 233ffa02126SHawking Zhang } 234ffa02126SHawking Zhang 235ffa02126SHawking Zhang if (ih == &adev->irq.ih) { 236ffa02126SHawking Zhang /* set the ih ring 0 writeback address whether it's enabled or not */ 237ffa02126SHawking Zhang WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); 238ffa02126SHawking Zhang WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); 239ffa02126SHawking Zhang } 240ffa02126SHawking Zhang 241ffa02126SHawking Zhang /* set rptr, wptr to 0 */ 242ffa02126SHawking Zhang WREG32(ih_regs->ih_rb_wptr, 0); 243ffa02126SHawking Zhang WREG32(ih_regs->ih_rb_rptr, 0); 244ffa02126SHawking Zhang 245ffa02126SHawking Zhang WREG32(ih_regs->ih_doorbell_rptr, vega10_ih_doorbell_rptr(ih)); 246ffa02126SHawking Zhang 247ffa02126SHawking Zhang return 0; 248ffa02126SHawking Zhang } 249ffa02126SHawking Zhang 250ffa02126SHawking Zhang /** 251282aae55SKen Wang * vega10_ih_irq_init - init and enable the interrupt ring 252282aae55SKen Wang * 253282aae55SKen Wang * @adev: amdgpu_device pointer 254282aae55SKen Wang * 255282aae55SKen Wang * Allocate a ring buffer for the interrupt controller, 256282aae55SKen Wang * enable the RLC, disable interrupts, enable the IH 257282aae55SKen Wang * ring buffer and enable it (VI). 258282aae55SKen Wang * Called at device load and reume. 259282aae55SKen Wang * Returns 0 for success, errors for failure. 260282aae55SKen Wang */ 261282aae55SKen Wang static int vega10_ih_irq_init(struct amdgpu_device *adev) 262282aae55SKen Wang { 26321822b6aSHawking Zhang struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 26421822b6aSHawking Zhang u32 ih_chicken; 265fd95e1b1SHawking Zhang int ret; 26621822b6aSHawking Zhang int i; 267282aae55SKen Wang 268282aae55SKen Wang /* disable irqs */ 269fd95e1b1SHawking Zhang ret = vega10_ih_toggle_interrupts(adev, false); 270fd95e1b1SHawking Zhang if (ret) 271fd95e1b1SHawking Zhang return ret; 272282aae55SKen Wang 273bebc0762SHawking Zhang adev->nbio.funcs->ih_control(adev); 274282aae55SKen Wang 27595c0c257SHawking Zhang if (adev->asic_type == CHIP_RENOIR) { 27625344d7eSZhigang Luo ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 27725344d7eSZhigang Luo if (adev->irq.ih.use_bus_addr) { 27825344d7eSZhigang Luo ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 27925344d7eSZhigang Luo MC_SPACE_GPA_ENABLE, 1); 28025344d7eSZhigang Luo } 281f9c84ae5SLe Ma WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 28225344d7eSZhigang Luo } 283f9c84ae5SLe Ma 28421822b6aSHawking Zhang for (i = 0; i < ARRAY_SIZE(ih); i++) { 28521822b6aSHawking Zhang if (ih[i]->ring_size) { 28621822b6aSHawking Zhang ret = vega10_ih_enable_ring(adev, ih[i]); 28721822b6aSHawking Zhang if (ret) 28821822b6aSHawking Zhang return ret; 289470b4250STrigger Huang } 290ad710812SChristian König } 291ad710812SChristian König 292282aae55SKen Wang pci_set_master(adev->pdev); 293282aae55SKen Wang 294282aae55SKen Wang /* enable interrupts */ 295fd95e1b1SHawking Zhang ret = vega10_ih_toggle_interrupts(adev, true); 296fd95e1b1SHawking Zhang if (ret) 297282aae55SKen Wang return ret; 298fd95e1b1SHawking Zhang 2997f03b148SHawking Zhang if (adev->irq.ih_soft.ring_size) 3007f03b148SHawking Zhang adev->irq.ih_soft.enabled = true; 3017f03b148SHawking Zhang 302fd95e1b1SHawking Zhang return 0; 303282aae55SKen Wang } 304282aae55SKen Wang 305282aae55SKen Wang /** 306282aae55SKen Wang * vega10_ih_irq_disable - disable interrupts 307282aae55SKen Wang * 308282aae55SKen Wang * @adev: amdgpu_device pointer 309282aae55SKen Wang * 310282aae55SKen Wang * Disable interrupts on the hw (VEGA10). 311282aae55SKen Wang */ 312282aae55SKen Wang static void vega10_ih_irq_disable(struct amdgpu_device *adev) 313282aae55SKen Wang { 314fd95e1b1SHawking Zhang vega10_ih_toggle_interrupts(adev, false); 315282aae55SKen Wang 316282aae55SKen Wang /* Wait and acknowledge irq */ 317282aae55SKen Wang mdelay(1); 318282aae55SKen Wang } 319282aae55SKen Wang 320282aae55SKen Wang /** 321282aae55SKen Wang * vega10_ih_get_wptr - get the IH ring buffer wptr 322282aae55SKen Wang * 323282aae55SKen Wang * @adev: amdgpu_device pointer 3245162e40eSLee Jones * @ih: IH ring buffer to fetch wptr 325282aae55SKen Wang * 326282aae55SKen Wang * Get the IH ring buffer wptr from either the register 327282aae55SKen Wang * or the writeback memory buffer (VEGA10). Also check for 328282aae55SKen Wang * ring buffer overflow and deal with it. 329282aae55SKen Wang * Returns the value of the wptr. 330282aae55SKen Wang */ 3318bb9eb48SChristian König static u32 vega10_ih_get_wptr(struct amdgpu_device *adev, 3328bb9eb48SChristian König struct amdgpu_ih_ring *ih) 333282aae55SKen Wang { 334554bdbf6SHawking Zhang u32 wptr, tmp; 335554bdbf6SHawking Zhang struct amdgpu_ih_regs *ih_regs; 336282aae55SKen Wang 337b672cb1eSPhilip Yang if (ih == &adev->irq.ih) { 338b672cb1eSPhilip Yang /* Only ring0 supports writeback. On other rings fall back 339b672cb1eSPhilip Yang * to register-based code with overflow checking below. 340b672cb1eSPhilip Yang */ 341d81f78b4SChristian König wptr = le32_to_cpu(*ih->wptr_cpu); 342282aae55SKen Wang 343b8217575SChristian König if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 344b8217575SChristian König goto out; 345b672cb1eSPhilip Yang } 346b672cb1eSPhilip Yang 347b672cb1eSPhilip Yang ih_regs = &ih->ih_regs; 348b8217575SChristian König 349b8217575SChristian König /* Double check that the overflow wasn't already cleared. */ 350554bdbf6SHawking Zhang wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); 351b8217575SChristian König if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 352b8217575SChristian König goto out; 353b8217575SChristian König 354282aae55SKen Wang wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 355282aae55SKen Wang 356282aae55SKen Wang /* When a ring buffer overflow happen start parsing interrupt 357282aae55SKen Wang * from the last not overwritten vector (wptr + 32). Hopefully 358282aae55SKen Wang * this should allow us to catchup. 359282aae55SKen Wang */ 3608bb9eb48SChristian König tmp = (wptr + 32) & ih->ptr_mask; 361b8217575SChristian König dev_warn(adev->dev, "IH ring buffer overflow " 362b8217575SChristian König "(0x%08X, 0x%08X, 0x%08X)\n", 3638bb9eb48SChristian König wptr, ih->rptr, tmp); 3648bb9eb48SChristian König ih->rptr = tmp; 365282aae55SKen Wang 366554bdbf6SHawking Zhang tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); 367282aae55SKen Wang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 368554bdbf6SHawking Zhang WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 369b8217575SChristian König 370b8217575SChristian König out: 3718bb9eb48SChristian König return (wptr & ih->ptr_mask); 372282aae55SKen Wang } 373282aae55SKen Wang 374282aae55SKen Wang /** 37574dcfe74STrigger Huang * vega10_ih_irq_rearm - rearm IRQ if lost 37674dcfe74STrigger Huang * 37774dcfe74STrigger Huang * @adev: amdgpu_device pointer 3785162e40eSLee Jones * @ih: IH ring to match 37974dcfe74STrigger Huang * 38074dcfe74STrigger Huang */ 38174dcfe74STrigger Huang static void vega10_ih_irq_rearm(struct amdgpu_device *adev, 38274dcfe74STrigger Huang struct amdgpu_ih_ring *ih) 38374dcfe74STrigger Huang { 38474dcfe74STrigger Huang uint32_t v = 0; 38574dcfe74STrigger Huang uint32_t i = 0; 386554bdbf6SHawking Zhang struct amdgpu_ih_regs *ih_regs; 38774dcfe74STrigger Huang 388554bdbf6SHawking Zhang ih_regs = &ih->ih_regs; 38974dcfe74STrigger Huang /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */ 39074dcfe74STrigger Huang for (i = 0; i < MAX_REARM_RETRY; i++) { 391554bdbf6SHawking Zhang v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); 39274dcfe74STrigger Huang if ((v < ih->ring_size) && (v != ih->rptr)) 39374dcfe74STrigger Huang WDOORBELL32(ih->doorbell_index, ih->rptr); 39474dcfe74STrigger Huang else 39574dcfe74STrigger Huang break; 39674dcfe74STrigger Huang } 39774dcfe74STrigger Huang } 39874dcfe74STrigger Huang 39974dcfe74STrigger Huang /** 400282aae55SKen Wang * vega10_ih_set_rptr - set the IH ring buffer rptr 401282aae55SKen Wang * 402282aae55SKen Wang * @adev: amdgpu_device pointer 4035162e40eSLee Jones * @ih: IH ring buffer to set rptr 404282aae55SKen Wang * 405282aae55SKen Wang * Set the IH ring buffer rptr. 406282aae55SKen Wang */ 4078bb9eb48SChristian König static void vega10_ih_set_rptr(struct amdgpu_device *adev, 4088bb9eb48SChristian König struct amdgpu_ih_ring *ih) 409282aae55SKen Wang { 410554bdbf6SHawking Zhang struct amdgpu_ih_regs *ih_regs; 411554bdbf6SHawking Zhang 4128bb9eb48SChristian König if (ih->use_doorbell) { 413282aae55SKen Wang /* XXX check if swapping is necessary on BE */ 414d81f78b4SChristian König *ih->rptr_cpu = ih->rptr; 4158bb9eb48SChristian König WDOORBELL32(ih->doorbell_index, ih->rptr); 41674dcfe74STrigger Huang 41774dcfe74STrigger Huang if (amdgpu_sriov_vf(adev)) 41874dcfe74STrigger Huang vega10_ih_irq_rearm(adev, ih); 419554bdbf6SHawking Zhang } else { 420554bdbf6SHawking Zhang ih_regs = &ih->ih_regs; 421554bdbf6SHawking Zhang WREG32(ih_regs->ih_rb_rptr, ih->rptr); 422282aae55SKen Wang } 423282aae55SKen Wang } 424282aae55SKen Wang 425cf67950eSChristian König /** 426cf67950eSChristian König * vega10_ih_self_irq - dispatch work for ring 1 and 2 427cf67950eSChristian König * 428cf67950eSChristian König * @adev: amdgpu_device pointer 429cf67950eSChristian König * @source: irq source 430cf67950eSChristian König * @entry: IV with WPTR update 431cf67950eSChristian König * 432cf67950eSChristian König * Update the WPTR from the IV and schedule work to handle the entries. 433cf67950eSChristian König */ 434cf67950eSChristian König static int vega10_ih_self_irq(struct amdgpu_device *adev, 435cf67950eSChristian König struct amdgpu_irq_src *source, 436cf67950eSChristian König struct amdgpu_iv_entry *entry) 437cf67950eSChristian König { 438cf67950eSChristian König switch (entry->ring_id) { 439cf67950eSChristian König case 1: 440cf67950eSChristian König schedule_work(&adev->irq.ih1_work); 441cf67950eSChristian König break; 442cf67950eSChristian König case 2: 443cf67950eSChristian König schedule_work(&adev->irq.ih2_work); 444cf67950eSChristian König break; 445cf67950eSChristian König default: break; 446cf67950eSChristian König } 447cf67950eSChristian König return 0; 448cf67950eSChristian König } 449cf67950eSChristian König 450cf67950eSChristian König static const struct amdgpu_irq_src_funcs vega10_ih_self_irq_funcs = { 451cf67950eSChristian König .process = vega10_ih_self_irq, 452cf67950eSChristian König }; 453cf67950eSChristian König 454cf67950eSChristian König static void vega10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 455cf67950eSChristian König { 456cf67950eSChristian König adev->irq.self_irq.num_types = 0; 457cf67950eSChristian König adev->irq.self_irq.funcs = &vega10_ih_self_irq_funcs; 458cf67950eSChristian König } 459cf67950eSChristian König 460282aae55SKen Wang static int vega10_ih_early_init(void *handle) 461282aae55SKen Wang { 462282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 463282aae55SKen Wang 464282aae55SKen Wang vega10_ih_set_interrupt_funcs(adev); 465cf67950eSChristian König vega10_ih_set_self_irq_funcs(adev); 466282aae55SKen Wang return 0; 467282aae55SKen Wang } 468282aae55SKen Wang 469282aae55SKen Wang static int vega10_ih_sw_init(void *handle) 470282aae55SKen Wang { 471282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 472cf67950eSChristian König int r; 473cf67950eSChristian König 474cf67950eSChristian König r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 475cf67950eSChristian König &adev->irq.self_irq); 476cf67950eSChristian König if (r) 477cf67950eSChristian König return r; 478282aae55SKen Wang 479425c3143SChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true); 480282aae55SKen Wang if (r) 481282aae55SKen Wang return r; 482282aae55SKen Wang 4831ae64cecSChristian König adev->irq.ih.use_doorbell = true; 4841ae64cecSChristian König adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 4851ae64cecSChristian König 4869f18985dSHawking Zhang if (!(adev->flags & AMD_IS_APU)) { 487ad710812SChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 488ad710812SChristian König if (r) 489ad710812SChristian König return r; 490ad710812SChristian König 4911ae64cecSChristian König adev->irq.ih1.use_doorbell = true; 492b51cd19eSChristian König adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; 4931ae64cecSChristian König 494ad710812SChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 495ad710812SChristian König if (r) 496ad710812SChristian König return r; 497ad710812SChristian König 4981ae64cecSChristian König adev->irq.ih2.use_doorbell = true; 499b51cd19eSChristian König adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1; 5009f18985dSHawking Zhang } 501f0594717SHawking Zhang /* initialize ih control registers offset */ 502f0594717SHawking Zhang vega10_ih_init_register_offset(adev); 503f0594717SHawking Zhang 50447509189SChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); 50547509189SChristian König if (r) 50647509189SChristian König return r; 50747509189SChristian König 508282aae55SKen Wang r = amdgpu_irq_init(adev); 509282aae55SKen Wang 510282aae55SKen Wang return r; 511282aae55SKen Wang } 512282aae55SKen Wang 513282aae55SKen Wang static int vega10_ih_sw_fini(void *handle) 514282aae55SKen Wang { 515282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 516282aae55SKen Wang 51772c8c97bSAndrey Grodzovsky amdgpu_irq_fini_sw(adev); 518282aae55SKen Wang 519282aae55SKen Wang return 0; 520282aae55SKen Wang } 521282aae55SKen Wang 522282aae55SKen Wang static int vega10_ih_hw_init(void *handle) 523282aae55SKen Wang { 524282aae55SKen Wang int r; 525282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 526282aae55SKen Wang 527282aae55SKen Wang r = vega10_ih_irq_init(adev); 528282aae55SKen Wang if (r) 529282aae55SKen Wang return r; 530282aae55SKen Wang 531282aae55SKen Wang return 0; 532282aae55SKen Wang } 533282aae55SKen Wang 534282aae55SKen Wang static int vega10_ih_hw_fini(void *handle) 535282aae55SKen Wang { 536282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 537282aae55SKen Wang 538282aae55SKen Wang vega10_ih_irq_disable(adev); 539282aae55SKen Wang 540282aae55SKen Wang return 0; 541282aae55SKen Wang } 542282aae55SKen Wang 543282aae55SKen Wang static int vega10_ih_suspend(void *handle) 544282aae55SKen Wang { 545282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 546282aae55SKen Wang 547282aae55SKen Wang return vega10_ih_hw_fini(adev); 548282aae55SKen Wang } 549282aae55SKen Wang 550282aae55SKen Wang static int vega10_ih_resume(void *handle) 551282aae55SKen Wang { 552282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 553282aae55SKen Wang 554282aae55SKen Wang return vega10_ih_hw_init(adev); 555282aae55SKen Wang } 556282aae55SKen Wang 557282aae55SKen Wang static bool vega10_ih_is_idle(void *handle) 558282aae55SKen Wang { 559282aae55SKen Wang /* todo */ 560282aae55SKen Wang return true; 561282aae55SKen Wang } 562282aae55SKen Wang 563282aae55SKen Wang static int vega10_ih_wait_for_idle(void *handle) 564282aae55SKen Wang { 565282aae55SKen Wang /* todo */ 566282aae55SKen Wang return -ETIMEDOUT; 567282aae55SKen Wang } 568282aae55SKen Wang 569282aae55SKen Wang static int vega10_ih_soft_reset(void *handle) 570282aae55SKen Wang { 571282aae55SKen Wang /* todo */ 572282aae55SKen Wang 573282aae55SKen Wang return 0; 574282aae55SKen Wang } 575282aae55SKen Wang 576227f7d58SKenneth Feng static void vega10_ih_update_clockgating_state(struct amdgpu_device *adev, 577227f7d58SKenneth Feng bool enable) 578227f7d58SKenneth Feng { 579227f7d58SKenneth Feng uint32_t data, def, field_val; 580227f7d58SKenneth Feng 581227f7d58SKenneth Feng if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 582227f7d58SKenneth Feng def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 583227f7d58SKenneth Feng field_val = enable ? 0 : 1; 584227f7d58SKenneth Feng /** 5852601fa64SHawking Zhang * Vega10/12 and RAVEN don't have IH_BUFFER_MEM_CLK_SOFT_OVERRIDE field. 586227f7d58SKenneth Feng */ 5872601fa64SHawking Zhang if (adev->asic_type == CHIP_RENOIR) 588227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 589227f7d58SKenneth Feng IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val); 590227f7d58SKenneth Feng 591227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 592227f7d58SKenneth Feng DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 593227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 594227f7d58SKenneth Feng OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 595227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 596227f7d58SKenneth Feng LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 597227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 598227f7d58SKenneth Feng DYN_CLK_SOFT_OVERRIDE, field_val); 599227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 600227f7d58SKenneth Feng REG_CLK_SOFT_OVERRIDE, field_val); 601227f7d58SKenneth Feng if (def != data) 602227f7d58SKenneth Feng WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 603227f7d58SKenneth Feng } 604227f7d58SKenneth Feng } 605227f7d58SKenneth Feng 606282aae55SKen Wang static int vega10_ih_set_clockgating_state(void *handle, 607282aae55SKen Wang enum amd_clockgating_state state) 608282aae55SKen Wang { 609227f7d58SKenneth Feng struct amdgpu_device *adev = (struct amdgpu_device *)handle; 610227f7d58SKenneth Feng 611227f7d58SKenneth Feng vega10_ih_update_clockgating_state(adev, 612a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 613282aae55SKen Wang return 0; 614227f7d58SKenneth Feng 615282aae55SKen Wang } 616282aae55SKen Wang 617282aae55SKen Wang static int vega10_ih_set_powergating_state(void *handle, 618282aae55SKen Wang enum amd_powergating_state state) 619282aae55SKen Wang { 620282aae55SKen Wang return 0; 621282aae55SKen Wang } 622282aae55SKen Wang 623282aae55SKen Wang const struct amd_ip_funcs vega10_ih_ip_funcs = { 624282aae55SKen Wang .name = "vega10_ih", 625282aae55SKen Wang .early_init = vega10_ih_early_init, 626282aae55SKen Wang .late_init = NULL, 627282aae55SKen Wang .sw_init = vega10_ih_sw_init, 628282aae55SKen Wang .sw_fini = vega10_ih_sw_fini, 629282aae55SKen Wang .hw_init = vega10_ih_hw_init, 630282aae55SKen Wang .hw_fini = vega10_ih_hw_fini, 631282aae55SKen Wang .suspend = vega10_ih_suspend, 632282aae55SKen Wang .resume = vega10_ih_resume, 633282aae55SKen Wang .is_idle = vega10_ih_is_idle, 634282aae55SKen Wang .wait_for_idle = vega10_ih_wait_for_idle, 635282aae55SKen Wang .soft_reset = vega10_ih_soft_reset, 636282aae55SKen Wang .set_clockgating_state = vega10_ih_set_clockgating_state, 637282aae55SKen Wang .set_powergating_state = vega10_ih_set_powergating_state, 638282aae55SKen Wang }; 639282aae55SKen Wang 640282aae55SKen Wang static const struct amdgpu_ih_funcs vega10_ih_funcs = { 641282aae55SKen Wang .get_wptr = vega10_ih_get_wptr, 64240838281SHawking Zhang .decode_iv = amdgpu_ih_decode_iv_helper, 643*3c2d6ea2SPhilip Yang .decode_iv_ts = amdgpu_ih_decode_iv_ts_helper, 644282aae55SKen Wang .set_rptr = vega10_ih_set_rptr 645282aae55SKen Wang }; 646282aae55SKen Wang 647282aae55SKen Wang static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 648282aae55SKen Wang { 649282aae55SKen Wang adev->irq.ih_funcs = &vega10_ih_funcs; 650282aae55SKen Wang } 651282aae55SKen Wang 652282aae55SKen Wang const struct amdgpu_ip_block_version vega10_ih_ip_block = 653282aae55SKen Wang { 654282aae55SKen Wang .type = AMD_IP_BLOCK_TYPE_IH, 655282aae55SKen Wang .major = 4, 656282aae55SKen Wang .minor = 0, 657282aae55SKen Wang .rev = 0, 658282aae55SKen Wang .funcs = &vega10_ih_ip_funcs, 659282aae55SKen Wang }; 660