1282aae55SKen Wang /* 2282aae55SKen Wang * Copyright 2016 Advanced Micro Devices, Inc. 3282aae55SKen Wang * 4282aae55SKen Wang * Permission is hereby granted, free of charge, to any person obtaining a 5282aae55SKen Wang * copy of this software and associated documentation files (the "Software"), 6282aae55SKen Wang * to deal in the Software without restriction, including without limitation 7282aae55SKen Wang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8282aae55SKen Wang * and/or sell copies of the Software, and to permit persons to whom the 9282aae55SKen Wang * Software is furnished to do so, subject to the following conditions: 10282aae55SKen Wang * 11282aae55SKen Wang * The above copyright notice and this permission notice shall be included in 12282aae55SKen Wang * all copies or substantial portions of the Software. 13282aae55SKen Wang * 14282aae55SKen Wang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15282aae55SKen Wang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16282aae55SKen Wang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17282aae55SKen Wang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18282aae55SKen Wang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19282aae55SKen Wang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20282aae55SKen Wang * OTHER DEALINGS IN THE SOFTWARE. 21282aae55SKen Wang * 22282aae55SKen Wang */ 2347b757fbSSam Ravnborg 2447b757fbSSam Ravnborg #include <linux/pci.h> 2547b757fbSSam Ravnborg 26282aae55SKen Wang #include "amdgpu.h" 27282aae55SKen Wang #include "amdgpu_ih.h" 28282aae55SKen Wang #include "soc15.h" 29282aae55SKen Wang 308af7454eSFeifei Xu #include "oss/osssys_4_0_offset.h" 318af7454eSFeifei Xu #include "oss/osssys_4_0_sh_mask.h" 32282aae55SKen Wang 33282aae55SKen Wang #include "soc15_common.h" 34282aae55SKen Wang #include "vega10_ih.h" 35282aae55SKen Wang 3674dcfe74STrigger Huang #define MAX_REARM_RETRY 10 37282aae55SKen Wang 38282aae55SKen Wang static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 39282aae55SKen Wang 40282aae55SKen Wang /** 41282aae55SKen Wang * vega10_ih_enable_interrupts - Enable the interrupt ring buffer 42282aae55SKen Wang * 43282aae55SKen Wang * @adev: amdgpu_device pointer 44282aae55SKen Wang * 45282aae55SKen Wang * Enable the interrupt ring buffer (VEGA10). 46282aae55SKen Wang */ 47282aae55SKen Wang static void vega10_ih_enable_interrupts(struct amdgpu_device *adev) 48282aae55SKen Wang { 49b2b7e457SHawking Zhang u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 50282aae55SKen Wang 51282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); 52282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); 534cd4c5c0SMonk Liu if (amdgpu_sriov_vf(adev)) { 54470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 55470b4250STrigger Huang DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 56470b4250STrigger Huang return; 57470b4250STrigger Huang } 58470b4250STrigger Huang } else { 59b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 60470b4250STrigger Huang } 61282aae55SKen Wang adev->irq.ih.enabled = true; 62ad710812SChristian König 63ad710812SChristian König if (adev->irq.ih1.ring_size) { 64ad710812SChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 65ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 66ad710812SChristian König RB_ENABLE, 1); 674cd4c5c0SMonk Liu if (amdgpu_sriov_vf(adev)) { 68470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 69470b4250STrigger Huang ih_rb_cntl)) { 70470b4250STrigger Huang DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 71470b4250STrigger Huang return; 72470b4250STrigger Huang } 73470b4250STrigger Huang } else { 74ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 75470b4250STrigger Huang } 76ad710812SChristian König adev->irq.ih1.enabled = true; 77ad710812SChristian König } 78ad710812SChristian König 79ad710812SChristian König if (adev->irq.ih2.ring_size) { 80ad710812SChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 81ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 82ad710812SChristian König RB_ENABLE, 1); 834cd4c5c0SMonk Liu if (amdgpu_sriov_vf(adev)) { 84470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 85470b4250STrigger Huang ih_rb_cntl)) { 86470b4250STrigger Huang DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 87470b4250STrigger Huang return; 88470b4250STrigger Huang } 89470b4250STrigger Huang } else { 90ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 91470b4250STrigger Huang } 92ad710812SChristian König adev->irq.ih2.enabled = true; 93ad710812SChristian König } 94282aae55SKen Wang } 95282aae55SKen Wang 96282aae55SKen Wang /** 97282aae55SKen Wang * vega10_ih_disable_interrupts - Disable the interrupt ring buffer 98282aae55SKen Wang * 99282aae55SKen Wang * @adev: amdgpu_device pointer 100282aae55SKen Wang * 101282aae55SKen Wang * Disable the interrupt ring buffer (VEGA10). 102282aae55SKen Wang */ 103282aae55SKen Wang static void vega10_ih_disable_interrupts(struct amdgpu_device *adev) 104282aae55SKen Wang { 105b2b7e457SHawking Zhang u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 106282aae55SKen Wang 107282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); 108282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); 1094cd4c5c0SMonk Liu if (amdgpu_sriov_vf(adev)) { 110470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 111470b4250STrigger Huang DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 112470b4250STrigger Huang return; 113470b4250STrigger Huang } 114470b4250STrigger Huang } else { 115b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 116470b4250STrigger Huang } 117470b4250STrigger Huang 118282aae55SKen Wang /* set rptr, wptr to 0 */ 119b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 120b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 121282aae55SKen Wang adev->irq.ih.enabled = false; 122282aae55SKen Wang adev->irq.ih.rptr = 0; 123ad710812SChristian König 124ad710812SChristian König if (adev->irq.ih1.ring_size) { 125ad710812SChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 126ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 127ad710812SChristian König RB_ENABLE, 0); 1284cd4c5c0SMonk Liu if (amdgpu_sriov_vf(adev)) { 129470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 130470b4250STrigger Huang ih_rb_cntl)) { 131470b4250STrigger Huang DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 132470b4250STrigger Huang return; 133470b4250STrigger Huang } 134470b4250STrigger Huang } else { 135ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 136470b4250STrigger Huang } 137ad710812SChristian König /* set rptr, wptr to 0 */ 138ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 139ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 140ad710812SChristian König adev->irq.ih1.enabled = false; 141ad710812SChristian König adev->irq.ih1.rptr = 0; 142ad710812SChristian König } 143ad710812SChristian König 144ad710812SChristian König if (adev->irq.ih2.ring_size) { 145ad710812SChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 146ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 147ad710812SChristian König RB_ENABLE, 0); 1484cd4c5c0SMonk Liu if (amdgpu_sriov_vf(adev)) { 149470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 150470b4250STrigger Huang ih_rb_cntl)) { 151470b4250STrigger Huang DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 152470b4250STrigger Huang return; 153470b4250STrigger Huang } 154470b4250STrigger Huang } else { 155ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 156470b4250STrigger Huang } 157470b4250STrigger Huang 158ad710812SChristian König /* set rptr, wptr to 0 */ 159ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 160ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 161ad710812SChristian König adev->irq.ih2.enabled = false; 162ad710812SChristian König adev->irq.ih2.rptr = 0; 163ad710812SChristian König } 164ad710812SChristian König } 165ad710812SChristian König 166ad710812SChristian König static uint32_t vega10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 167ad710812SChristian König { 168ad710812SChristian König int rb_bufsz = order_base_2(ih->ring_size / 4); 169ad710812SChristian König 170ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 171ad710812SChristian König MC_SPACE, ih->use_bus_addr ? 1 : 4); 172ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 173ad710812SChristian König WPTR_OVERFLOW_CLEAR, 1); 174ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 175ad710812SChristian König WPTR_OVERFLOW_ENABLE, 1); 176ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 177ad710812SChristian König /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 178ad710812SChristian König * value is written to memory 179ad710812SChristian König */ 180ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 181ad710812SChristian König WPTR_WRITEBACK_ENABLE, 1); 182ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 183ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 184ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 185ad710812SChristian König 186ad710812SChristian König return ih_rb_cntl; 187282aae55SKen Wang } 188282aae55SKen Wang 1891ae64cecSChristian König static uint32_t vega10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 1901ae64cecSChristian König { 1911ae64cecSChristian König u32 ih_doorbell_rtpr = 0; 1921ae64cecSChristian König 1931ae64cecSChristian König if (ih->use_doorbell) { 1941ae64cecSChristian König ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 1951ae64cecSChristian König IH_DOORBELL_RPTR, OFFSET, 1961ae64cecSChristian König ih->doorbell_index); 1971ae64cecSChristian König ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 1981ae64cecSChristian König IH_DOORBELL_RPTR, 1991ae64cecSChristian König ENABLE, 1); 2001ae64cecSChristian König } else { 2011ae64cecSChristian König ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 2021ae64cecSChristian König IH_DOORBELL_RPTR, 2031ae64cecSChristian König ENABLE, 0); 2041ae64cecSChristian König } 2051ae64cecSChristian König return ih_doorbell_rtpr; 2061ae64cecSChristian König } 2071ae64cecSChristian König 208282aae55SKen Wang /** 209282aae55SKen Wang * vega10_ih_irq_init - init and enable the interrupt ring 210282aae55SKen Wang * 211282aae55SKen Wang * @adev: amdgpu_device pointer 212282aae55SKen Wang * 213282aae55SKen Wang * Allocate a ring buffer for the interrupt controller, 214282aae55SKen Wang * enable the RLC, disable interrupts, enable the IH 215282aae55SKen Wang * ring buffer and enable it (VI). 216282aae55SKen Wang * Called at device load and reume. 217282aae55SKen Wang * Returns 0 for success, errors for failure. 218282aae55SKen Wang */ 219282aae55SKen Wang static int vega10_ih_irq_init(struct amdgpu_device *adev) 220282aae55SKen Wang { 221ad710812SChristian König struct amdgpu_ih_ring *ih; 222f9c84ae5SLe Ma u32 ih_rb_cntl, ih_chicken; 223282aae55SKen Wang int ret = 0; 224282aae55SKen Wang u32 tmp; 225282aae55SKen Wang 226282aae55SKen Wang /* disable irqs */ 227282aae55SKen Wang vega10_ih_disable_interrupts(adev); 228282aae55SKen Wang 229bebc0762SHawking Zhang adev->nbio.funcs->ih_control(adev); 230282aae55SKen Wang 231ad710812SChristian König ih = &adev->irq.ih; 232282aae55SKen Wang /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 233ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8); 234ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff); 235282aae55SKen Wang 236ad710812SChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 237537e3bbfSAaron Liu ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 238ad710812SChristian König ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl); 239537e3bbfSAaron Liu if (adev->irq.ih.use_bus_addr) { 240537e3bbfSAaron Liu ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 241537e3bbfSAaron Liu } else { 242537e3bbfSAaron Liu ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, MC_SPACE_FBPA_ENABLE, 1); 243537e3bbfSAaron Liu } 244ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 245ad710812SChristian König !!adev->irq.msi_enabled); 246470b4250STrigger Huang 2474cd4c5c0SMonk Liu if (amdgpu_sriov_vf(adev)) { 248470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 249470b4250STrigger Huang DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 250470b4250STrigger Huang return -ETIMEDOUT; 251470b4250STrigger Huang } 252470b4250STrigger Huang } else { 253b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 254470b4250STrigger Huang } 255282aae55SKen Wang 256537e3bbfSAaron Liu if ((adev->asic_type == CHIP_ARCTURUS 257537e3bbfSAaron Liu && adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) 258537e3bbfSAaron Liu || adev->asic_type == CHIP_RENOIR) 259f9c84ae5SLe Ma WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 260f9c84ae5SLe Ma 261282aae55SKen Wang /* set the writeback address whether it's enabled or not */ 262d81f78b4SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, 263d81f78b4SChristian König lower_32_bits(ih->wptr_addr)); 264d81f78b4SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, 265d81f78b4SChristian König upper_32_bits(ih->wptr_addr) & 0xFFFF); 266282aae55SKen Wang 267282aae55SKen Wang /* set rptr, wptr to 0 */ 268b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 2691ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 270282aae55SKen Wang 2711ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, 2721ae64cecSChristian König vega10_ih_doorbell_rptr(ih)); 273282aae55SKen Wang 274ad710812SChristian König ih = &adev->irq.ih1; 275ad710812SChristian König if (ih->ring_size) { 276ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING1, ih->gpu_addr >> 8); 277ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING1, 278ad710812SChristian König (ih->gpu_addr >> 40) & 0xff); 279ad710812SChristian König 280ad710812SChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 281ad710812SChristian König ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl); 2820133690eSChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 2830133690eSChristian König WPTR_OVERFLOW_ENABLE, 0); 2840133690eSChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 2850133690eSChristian König RB_FULL_DRAIN_ENABLE, 1); 2864cd4c5c0SMonk Liu if (amdgpu_sriov_vf(adev)) { 287470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 288470b4250STrigger Huang ih_rb_cntl)) { 289470b4250STrigger Huang DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 290470b4250STrigger Huang return -ETIMEDOUT; 291470b4250STrigger Huang } 292470b4250STrigger Huang } else { 293ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 294470b4250STrigger Huang } 295ad710812SChristian König 296ad710812SChristian König /* set rptr, wptr to 0 */ 297ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 2981ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 2991ae64cecSChristian König 3001ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1, 3011ae64cecSChristian König vega10_ih_doorbell_rptr(ih)); 302ad710812SChristian König } 303ad710812SChristian König 304ad710812SChristian König ih = &adev->irq.ih2; 305ad710812SChristian König if (ih->ring_size) { 306ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING2, ih->gpu_addr >> 8); 307ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING2, 308ad710812SChristian König (ih->gpu_addr >> 40) & 0xff); 309ad710812SChristian König 3101ae64cecSChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 311ad710812SChristian König ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl); 312470b4250STrigger Huang 3134cd4c5c0SMonk Liu if (amdgpu_sriov_vf(adev)) { 314470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 315470b4250STrigger Huang ih_rb_cntl)) { 316470b4250STrigger Huang DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 317470b4250STrigger Huang return -ETIMEDOUT; 318470b4250STrigger Huang } 319470b4250STrigger Huang } else { 320ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 321470b4250STrigger Huang } 322ad710812SChristian König 323ad710812SChristian König /* set rptr, wptr to 0 */ 324ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 3251ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 3261ae64cecSChristian König 3271ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2, 3281ae64cecSChristian König vega10_ih_doorbell_rptr(ih)); 329ad710812SChristian König } 330ad710812SChristian König 331b2b7e457SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 332282aae55SKen Wang tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 333282aae55SKen Wang CLIENT18_IS_STORM_CLIENT, 1); 334b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 335282aae55SKen Wang 336b2b7e457SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 337282aae55SKen Wang tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 338b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 339282aae55SKen Wang 340282aae55SKen Wang pci_set_master(adev->pdev); 341282aae55SKen Wang 342282aae55SKen Wang /* enable interrupts */ 343282aae55SKen Wang vega10_ih_enable_interrupts(adev); 344282aae55SKen Wang 345282aae55SKen Wang return ret; 346282aae55SKen Wang } 347282aae55SKen Wang 348282aae55SKen Wang /** 349282aae55SKen Wang * vega10_ih_irq_disable - disable interrupts 350282aae55SKen Wang * 351282aae55SKen Wang * @adev: amdgpu_device pointer 352282aae55SKen Wang * 353282aae55SKen Wang * Disable interrupts on the hw (VEGA10). 354282aae55SKen Wang */ 355282aae55SKen Wang static void vega10_ih_irq_disable(struct amdgpu_device *adev) 356282aae55SKen Wang { 357282aae55SKen Wang vega10_ih_disable_interrupts(adev); 358282aae55SKen Wang 359282aae55SKen Wang /* Wait and acknowledge irq */ 360282aae55SKen Wang mdelay(1); 361282aae55SKen Wang } 362282aae55SKen Wang 363282aae55SKen Wang /** 364282aae55SKen Wang * vega10_ih_get_wptr - get the IH ring buffer wptr 365282aae55SKen Wang * 366282aae55SKen Wang * @adev: amdgpu_device pointer 367282aae55SKen Wang * 368282aae55SKen Wang * Get the IH ring buffer wptr from either the register 369282aae55SKen Wang * or the writeback memory buffer (VEGA10). Also check for 370282aae55SKen Wang * ring buffer overflow and deal with it. 371282aae55SKen Wang * Returns the value of the wptr. 372282aae55SKen Wang */ 3738bb9eb48SChristian König static u32 vega10_ih_get_wptr(struct amdgpu_device *adev, 3748bb9eb48SChristian König struct amdgpu_ih_ring *ih) 375282aae55SKen Wang { 376cf67950eSChristian König u32 wptr, reg, tmp; 377282aae55SKen Wang 378d81f78b4SChristian König wptr = le32_to_cpu(*ih->wptr_cpu); 379282aae55SKen Wang 380b8217575SChristian König if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 381b8217575SChristian König goto out; 382b8217575SChristian König 383b8217575SChristian König /* Double check that the overflow wasn't already cleared. */ 384cf67950eSChristian König 385cf67950eSChristian König if (ih == &adev->irq.ih) 386cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 387cf67950eSChristian König else if (ih == &adev->irq.ih1) 388cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 389cf67950eSChristian König else if (ih == &adev->irq.ih2) 390cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 391cf67950eSChristian König else 392cf67950eSChristian König BUG(); 393cf67950eSChristian König 394cf67950eSChristian König wptr = RREG32_NO_KIQ(reg); 395b8217575SChristian König if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 396b8217575SChristian König goto out; 397b8217575SChristian König 398282aae55SKen Wang wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 399282aae55SKen Wang 400282aae55SKen Wang /* When a ring buffer overflow happen start parsing interrupt 401282aae55SKen Wang * from the last not overwritten vector (wptr + 32). Hopefully 402282aae55SKen Wang * this should allow us to catchup. 403282aae55SKen Wang */ 4048bb9eb48SChristian König tmp = (wptr + 32) & ih->ptr_mask; 405b8217575SChristian König dev_warn(adev->dev, "IH ring buffer overflow " 406b8217575SChristian König "(0x%08X, 0x%08X, 0x%08X)\n", 4078bb9eb48SChristian König wptr, ih->rptr, tmp); 4088bb9eb48SChristian König ih->rptr = tmp; 409282aae55SKen Wang 410cf67950eSChristian König if (ih == &adev->irq.ih) 411cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 412cf67950eSChristian König else if (ih == &adev->irq.ih1) 413cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 414cf67950eSChristian König else if (ih == &adev->irq.ih2) 415cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 416cf67950eSChristian König else 417cf67950eSChristian König BUG(); 418cf67950eSChristian König 419cf67950eSChristian König tmp = RREG32_NO_KIQ(reg); 420282aae55SKen Wang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 421cf67950eSChristian König WREG32_NO_KIQ(reg, tmp); 422b8217575SChristian König 423b8217575SChristian König out: 4248bb9eb48SChristian König return (wptr & ih->ptr_mask); 425282aae55SKen Wang } 426282aae55SKen Wang 427282aae55SKen Wang /** 428282aae55SKen Wang * vega10_ih_decode_iv - decode an interrupt vector 429282aae55SKen Wang * 430282aae55SKen Wang * @adev: amdgpu_device pointer 431282aae55SKen Wang * 432282aae55SKen Wang * Decodes the interrupt vector at the current rptr 433282aae55SKen Wang * position and also advance the position. 434282aae55SKen Wang */ 435282aae55SKen Wang static void vega10_ih_decode_iv(struct amdgpu_device *adev, 4368bb9eb48SChristian König struct amdgpu_ih_ring *ih, 437282aae55SKen Wang struct amdgpu_iv_entry *entry) 438282aae55SKen Wang { 439282aae55SKen Wang /* wptr/rptr are in bytes! */ 4408bb9eb48SChristian König u32 ring_index = ih->rptr >> 2; 441282aae55SKen Wang uint32_t dw[8]; 442282aae55SKen Wang 4438bb9eb48SChristian König dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 4448bb9eb48SChristian König dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 4458bb9eb48SChristian König dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 4468bb9eb48SChristian König dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 4478bb9eb48SChristian König dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); 4488bb9eb48SChristian König dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); 4498bb9eb48SChristian König dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); 4508bb9eb48SChristian König dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); 451282aae55SKen Wang 452282aae55SKen Wang entry->client_id = dw[0] & 0xff; 453282aae55SKen Wang entry->src_id = (dw[0] >> 8) & 0xff; 454282aae55SKen Wang entry->ring_id = (dw[0] >> 16) & 0xff; 455c4f46f22SChristian König entry->vmid = (dw[0] >> 24) & 0xf; 456c4f46f22SChristian König entry->vmid_src = (dw[0] >> 31); 457282aae55SKen Wang entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); 458282aae55SKen Wang entry->timestamp_src = dw[2] >> 31; 4593816e42fSChristian König entry->pasid = dw[3] & 0xffff; 460282aae55SKen Wang entry->pasid_src = dw[3] >> 31; 461282aae55SKen Wang entry->src_data[0] = dw[4]; 462282aae55SKen Wang entry->src_data[1] = dw[5]; 463282aae55SKen Wang entry->src_data[2] = dw[6]; 464282aae55SKen Wang entry->src_data[3] = dw[7]; 465282aae55SKen Wang 466282aae55SKen Wang /* wptr/rptr are in bytes! */ 4678bb9eb48SChristian König ih->rptr += 32; 468282aae55SKen Wang } 469282aae55SKen Wang 470282aae55SKen Wang /** 47174dcfe74STrigger Huang * vega10_ih_irq_rearm - rearm IRQ if lost 47274dcfe74STrigger Huang * 47374dcfe74STrigger Huang * @adev: amdgpu_device pointer 47474dcfe74STrigger Huang * 47574dcfe74STrigger Huang */ 47674dcfe74STrigger Huang static void vega10_ih_irq_rearm(struct amdgpu_device *adev, 47774dcfe74STrigger Huang struct amdgpu_ih_ring *ih) 47874dcfe74STrigger Huang { 47974dcfe74STrigger Huang uint32_t reg_rptr = 0; 48074dcfe74STrigger Huang uint32_t v = 0; 48174dcfe74STrigger Huang uint32_t i = 0; 48274dcfe74STrigger Huang 48374dcfe74STrigger Huang if (ih == &adev->irq.ih) 48474dcfe74STrigger Huang reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 48574dcfe74STrigger Huang else if (ih == &adev->irq.ih1) 48674dcfe74STrigger Huang reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 48774dcfe74STrigger Huang else if (ih == &adev->irq.ih2) 48874dcfe74STrigger Huang reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 48974dcfe74STrigger Huang else 49074dcfe74STrigger Huang return; 49174dcfe74STrigger Huang 49274dcfe74STrigger Huang /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */ 49374dcfe74STrigger Huang for (i = 0; i < MAX_REARM_RETRY; i++) { 49474dcfe74STrigger Huang v = RREG32_NO_KIQ(reg_rptr); 49574dcfe74STrigger Huang if ((v < ih->ring_size) && (v != ih->rptr)) 49674dcfe74STrigger Huang WDOORBELL32(ih->doorbell_index, ih->rptr); 49774dcfe74STrigger Huang else 49874dcfe74STrigger Huang break; 49974dcfe74STrigger Huang } 50074dcfe74STrigger Huang } 50174dcfe74STrigger Huang 50274dcfe74STrigger Huang /** 503282aae55SKen Wang * vega10_ih_set_rptr - set the IH ring buffer rptr 504282aae55SKen Wang * 505282aae55SKen Wang * @adev: amdgpu_device pointer 506282aae55SKen Wang * 507282aae55SKen Wang * Set the IH ring buffer rptr. 508282aae55SKen Wang */ 5098bb9eb48SChristian König static void vega10_ih_set_rptr(struct amdgpu_device *adev, 5108bb9eb48SChristian König struct amdgpu_ih_ring *ih) 511282aae55SKen Wang { 5128bb9eb48SChristian König if (ih->use_doorbell) { 513282aae55SKen Wang /* XXX check if swapping is necessary on BE */ 514d81f78b4SChristian König *ih->rptr_cpu = ih->rptr; 5158bb9eb48SChristian König WDOORBELL32(ih->doorbell_index, ih->rptr); 51674dcfe74STrigger Huang 51774dcfe74STrigger Huang if (amdgpu_sriov_vf(adev)) 51874dcfe74STrigger Huang vega10_ih_irq_rearm(adev, ih); 519cf67950eSChristian König } else if (ih == &adev->irq.ih) { 5208bb9eb48SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr); 521cf67950eSChristian König } else if (ih == &adev->irq.ih1) { 522cf67950eSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, ih->rptr); 523cf67950eSChristian König } else if (ih == &adev->irq.ih2) { 524cf67950eSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, ih->rptr); 525282aae55SKen Wang } 526282aae55SKen Wang } 527282aae55SKen Wang 528cf67950eSChristian König /** 529cf67950eSChristian König * vega10_ih_self_irq - dispatch work for ring 1 and 2 530cf67950eSChristian König * 531cf67950eSChristian König * @adev: amdgpu_device pointer 532cf67950eSChristian König * @source: irq source 533cf67950eSChristian König * @entry: IV with WPTR update 534cf67950eSChristian König * 535cf67950eSChristian König * Update the WPTR from the IV and schedule work to handle the entries. 536cf67950eSChristian König */ 537cf67950eSChristian König static int vega10_ih_self_irq(struct amdgpu_device *adev, 538cf67950eSChristian König struct amdgpu_irq_src *source, 539cf67950eSChristian König struct amdgpu_iv_entry *entry) 540cf67950eSChristian König { 541cf67950eSChristian König uint32_t wptr = cpu_to_le32(entry->src_data[0]); 542cf67950eSChristian König 543cf67950eSChristian König switch (entry->ring_id) { 544cf67950eSChristian König case 1: 545cf67950eSChristian König *adev->irq.ih1.wptr_cpu = wptr; 546cf67950eSChristian König schedule_work(&adev->irq.ih1_work); 547cf67950eSChristian König break; 548cf67950eSChristian König case 2: 549cf67950eSChristian König *adev->irq.ih2.wptr_cpu = wptr; 550cf67950eSChristian König schedule_work(&adev->irq.ih2_work); 551cf67950eSChristian König break; 552cf67950eSChristian König default: break; 553cf67950eSChristian König } 554cf67950eSChristian König return 0; 555cf67950eSChristian König } 556cf67950eSChristian König 557cf67950eSChristian König static const struct amdgpu_irq_src_funcs vega10_ih_self_irq_funcs = { 558cf67950eSChristian König .process = vega10_ih_self_irq, 559cf67950eSChristian König }; 560cf67950eSChristian König 561cf67950eSChristian König static void vega10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 562cf67950eSChristian König { 563cf67950eSChristian König adev->irq.self_irq.num_types = 0; 564cf67950eSChristian König adev->irq.self_irq.funcs = &vega10_ih_self_irq_funcs; 565cf67950eSChristian König } 566cf67950eSChristian König 567282aae55SKen Wang static int vega10_ih_early_init(void *handle) 568282aae55SKen Wang { 569282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 570282aae55SKen Wang 571282aae55SKen Wang vega10_ih_set_interrupt_funcs(adev); 572cf67950eSChristian König vega10_ih_set_self_irq_funcs(adev); 573282aae55SKen Wang return 0; 574282aae55SKen Wang } 575282aae55SKen Wang 576282aae55SKen Wang static int vega10_ih_sw_init(void *handle) 577282aae55SKen Wang { 578282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 579cf67950eSChristian König int r; 580cf67950eSChristian König 581cf67950eSChristian König r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 582cf67950eSChristian König &adev->irq.self_irq); 583cf67950eSChristian König if (r) 584cf67950eSChristian König return r; 585282aae55SKen Wang 586425c3143SChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true); 587282aae55SKen Wang if (r) 588282aae55SKen Wang return r; 589282aae55SKen Wang 5901ae64cecSChristian König adev->irq.ih.use_doorbell = true; 5911ae64cecSChristian König adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 5921ae64cecSChristian König 593ad710812SChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 594ad710812SChristian König if (r) 595ad710812SChristian König return r; 596ad710812SChristian König 5971ae64cecSChristian König adev->irq.ih1.use_doorbell = true; 598b51cd19eSChristian König adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; 5991ae64cecSChristian König 600ad710812SChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 601ad710812SChristian König if (r) 602ad710812SChristian König return r; 603ad710812SChristian König 6041ae64cecSChristian König adev->irq.ih2.use_doorbell = true; 605b51cd19eSChristian König adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1; 606282aae55SKen Wang 607282aae55SKen Wang r = amdgpu_irq_init(adev); 608282aae55SKen Wang 609282aae55SKen Wang return r; 610282aae55SKen Wang } 611282aae55SKen Wang 612282aae55SKen Wang static int vega10_ih_sw_fini(void *handle) 613282aae55SKen Wang { 614282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 615282aae55SKen Wang 616282aae55SKen Wang amdgpu_irq_fini(adev); 617ad710812SChristian König amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 618ad710812SChristian König amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 619425c3143SChristian König amdgpu_ih_ring_fini(adev, &adev->irq.ih); 620282aae55SKen Wang 621282aae55SKen Wang return 0; 622282aae55SKen Wang } 623282aae55SKen Wang 624282aae55SKen Wang static int vega10_ih_hw_init(void *handle) 625282aae55SKen Wang { 626282aae55SKen Wang int r; 627282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 628282aae55SKen Wang 629282aae55SKen Wang r = vega10_ih_irq_init(adev); 630282aae55SKen Wang if (r) 631282aae55SKen Wang return r; 632282aae55SKen Wang 633282aae55SKen Wang return 0; 634282aae55SKen Wang } 635282aae55SKen Wang 636282aae55SKen Wang static int vega10_ih_hw_fini(void *handle) 637282aae55SKen Wang { 638282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 639282aae55SKen Wang 640282aae55SKen Wang vega10_ih_irq_disable(adev); 641282aae55SKen Wang 642282aae55SKen Wang return 0; 643282aae55SKen Wang } 644282aae55SKen Wang 645282aae55SKen Wang static int vega10_ih_suspend(void *handle) 646282aae55SKen Wang { 647282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 648282aae55SKen Wang 649282aae55SKen Wang return vega10_ih_hw_fini(adev); 650282aae55SKen Wang } 651282aae55SKen Wang 652282aae55SKen Wang static int vega10_ih_resume(void *handle) 653282aae55SKen Wang { 654282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 655282aae55SKen Wang 656282aae55SKen Wang return vega10_ih_hw_init(adev); 657282aae55SKen Wang } 658282aae55SKen Wang 659282aae55SKen Wang static bool vega10_ih_is_idle(void *handle) 660282aae55SKen Wang { 661282aae55SKen Wang /* todo */ 662282aae55SKen Wang return true; 663282aae55SKen Wang } 664282aae55SKen Wang 665282aae55SKen Wang static int vega10_ih_wait_for_idle(void *handle) 666282aae55SKen Wang { 667282aae55SKen Wang /* todo */ 668282aae55SKen Wang return -ETIMEDOUT; 669282aae55SKen Wang } 670282aae55SKen Wang 671282aae55SKen Wang static int vega10_ih_soft_reset(void *handle) 672282aae55SKen Wang { 673282aae55SKen Wang /* todo */ 674282aae55SKen Wang 675282aae55SKen Wang return 0; 676282aae55SKen Wang } 677282aae55SKen Wang 678227f7d58SKenneth Feng static void vega10_ih_update_clockgating_state(struct amdgpu_device *adev, 679227f7d58SKenneth Feng bool enable) 680227f7d58SKenneth Feng { 681227f7d58SKenneth Feng uint32_t data, def, field_val; 682227f7d58SKenneth Feng 683227f7d58SKenneth Feng if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 684227f7d58SKenneth Feng def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 685227f7d58SKenneth Feng field_val = enable ? 0 : 1; 686227f7d58SKenneth Feng /** 687227f7d58SKenneth Feng * Vega10 does not have IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE 688227f7d58SKenneth Feng * and IH_BUFFER_MEM_CLK_SOFT_OVERRIDE field. 689227f7d58SKenneth Feng */ 690227f7d58SKenneth Feng if (adev->asic_type > CHIP_VEGA10) { 691227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 692227f7d58SKenneth Feng IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE, field_val); 693227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 694227f7d58SKenneth Feng IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val); 695227f7d58SKenneth Feng } 696227f7d58SKenneth Feng 697227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 698227f7d58SKenneth Feng DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 699227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 700227f7d58SKenneth Feng OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 701227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 702227f7d58SKenneth Feng LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 703227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 704227f7d58SKenneth Feng DYN_CLK_SOFT_OVERRIDE, field_val); 705227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 706227f7d58SKenneth Feng REG_CLK_SOFT_OVERRIDE, field_val); 707227f7d58SKenneth Feng if (def != data) 708227f7d58SKenneth Feng WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 709227f7d58SKenneth Feng } 710227f7d58SKenneth Feng } 711227f7d58SKenneth Feng 712282aae55SKen Wang static int vega10_ih_set_clockgating_state(void *handle, 713282aae55SKen Wang enum amd_clockgating_state state) 714282aae55SKen Wang { 715227f7d58SKenneth Feng struct amdgpu_device *adev = (struct amdgpu_device *)handle; 716227f7d58SKenneth Feng 717227f7d58SKenneth Feng vega10_ih_update_clockgating_state(adev, 718227f7d58SKenneth Feng state == AMD_CG_STATE_GATE ? true : false); 719282aae55SKen Wang return 0; 720227f7d58SKenneth Feng 721282aae55SKen Wang } 722282aae55SKen Wang 723282aae55SKen Wang static int vega10_ih_set_powergating_state(void *handle, 724282aae55SKen Wang enum amd_powergating_state state) 725282aae55SKen Wang { 726282aae55SKen Wang return 0; 727282aae55SKen Wang } 728282aae55SKen Wang 729282aae55SKen Wang const struct amd_ip_funcs vega10_ih_ip_funcs = { 730282aae55SKen Wang .name = "vega10_ih", 731282aae55SKen Wang .early_init = vega10_ih_early_init, 732282aae55SKen Wang .late_init = NULL, 733282aae55SKen Wang .sw_init = vega10_ih_sw_init, 734282aae55SKen Wang .sw_fini = vega10_ih_sw_fini, 735282aae55SKen Wang .hw_init = vega10_ih_hw_init, 736282aae55SKen Wang .hw_fini = vega10_ih_hw_fini, 737282aae55SKen Wang .suspend = vega10_ih_suspend, 738282aae55SKen Wang .resume = vega10_ih_resume, 739282aae55SKen Wang .is_idle = vega10_ih_is_idle, 740282aae55SKen Wang .wait_for_idle = vega10_ih_wait_for_idle, 741282aae55SKen Wang .soft_reset = vega10_ih_soft_reset, 742282aae55SKen Wang .set_clockgating_state = vega10_ih_set_clockgating_state, 743282aae55SKen Wang .set_powergating_state = vega10_ih_set_powergating_state, 744282aae55SKen Wang }; 745282aae55SKen Wang 746282aae55SKen Wang static const struct amdgpu_ih_funcs vega10_ih_funcs = { 747282aae55SKen Wang .get_wptr = vega10_ih_get_wptr, 748282aae55SKen Wang .decode_iv = vega10_ih_decode_iv, 749282aae55SKen Wang .set_rptr = vega10_ih_set_rptr 750282aae55SKen Wang }; 751282aae55SKen Wang 752282aae55SKen Wang static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 753282aae55SKen Wang { 754282aae55SKen Wang adev->irq.ih_funcs = &vega10_ih_funcs; 755282aae55SKen Wang } 756282aae55SKen Wang 757282aae55SKen Wang const struct amdgpu_ip_block_version vega10_ih_ip_block = 758282aae55SKen Wang { 759282aae55SKen Wang .type = AMD_IP_BLOCK_TYPE_IH, 760282aae55SKen Wang .major = 4, 761282aae55SKen Wang .minor = 0, 762282aae55SKen Wang .rev = 0, 763282aae55SKen Wang .funcs = &vega10_ih_ip_funcs, 764282aae55SKen Wang }; 765