1282aae55SKen Wang /* 2282aae55SKen Wang * Copyright 2016 Advanced Micro Devices, Inc. 3282aae55SKen Wang * 4282aae55SKen Wang * Permission is hereby granted, free of charge, to any person obtaining a 5282aae55SKen Wang * copy of this software and associated documentation files (the "Software"), 6282aae55SKen Wang * to deal in the Software without restriction, including without limitation 7282aae55SKen Wang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8282aae55SKen Wang * and/or sell copies of the Software, and to permit persons to whom the 9282aae55SKen Wang * Software is furnished to do so, subject to the following conditions: 10282aae55SKen Wang * 11282aae55SKen Wang * The above copyright notice and this permission notice shall be included in 12282aae55SKen Wang * all copies or substantial portions of the Software. 13282aae55SKen Wang * 14282aae55SKen Wang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15282aae55SKen Wang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16282aae55SKen Wang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17282aae55SKen Wang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18282aae55SKen Wang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19282aae55SKen Wang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20282aae55SKen Wang * OTHER DEALINGS IN THE SOFTWARE. 21282aae55SKen Wang * 22282aae55SKen Wang */ 2347b757fbSSam Ravnborg 2447b757fbSSam Ravnborg #include <linux/pci.h> 2547b757fbSSam Ravnborg 26282aae55SKen Wang #include "amdgpu.h" 27282aae55SKen Wang #include "amdgpu_ih.h" 28282aae55SKen Wang #include "soc15.h" 29282aae55SKen Wang 308af7454eSFeifei Xu #include "oss/osssys_4_0_offset.h" 318af7454eSFeifei Xu #include "oss/osssys_4_0_sh_mask.h" 32282aae55SKen Wang 33282aae55SKen Wang #include "soc15_common.h" 34282aae55SKen Wang #include "vega10_ih.h" 35282aae55SKen Wang 3674dcfe74STrigger Huang #define MAX_REARM_RETRY 10 37282aae55SKen Wang 38282aae55SKen Wang static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 39282aae55SKen Wang 40282aae55SKen Wang /** 41*1ebb4841SHawking Zhang * vega10_ih_init_register_offset - Initialize register offset for ih rings 42*1ebb4841SHawking Zhang * 43*1ebb4841SHawking Zhang * @adev: amdgpu_device pointer 44*1ebb4841SHawking Zhang * 45*1ebb4841SHawking Zhang * Initialize register offset ih rings (VEGA10). 46*1ebb4841SHawking Zhang */ 47*1ebb4841SHawking Zhang static void vega10_ih_init_register_offset(struct amdgpu_device *adev) 48*1ebb4841SHawking Zhang { 49*1ebb4841SHawking Zhang struct amdgpu_ih_regs *ih_regs; 50*1ebb4841SHawking Zhang 51*1ebb4841SHawking Zhang if (adev->irq.ih.ring_size) { 52*1ebb4841SHawking Zhang ih_regs = &adev->irq.ih.ih_regs; 53*1ebb4841SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); 54*1ebb4841SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); 55*1ebb4841SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 56*1ebb4841SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 57*1ebb4841SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 58*1ebb4841SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); 59*1ebb4841SHawking Zhang ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); 60*1ebb4841SHawking Zhang ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); 61*1ebb4841SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; 62*1ebb4841SHawking Zhang } 63*1ebb4841SHawking Zhang 64*1ebb4841SHawking Zhang if (adev->irq.ih1.ring_size) { 65*1ebb4841SHawking Zhang ih_regs = &adev->irq.ih1.ih_regs; 66*1ebb4841SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); 67*1ebb4841SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); 68*1ebb4841SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 69*1ebb4841SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 70*1ebb4841SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 71*1ebb4841SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1); 72*1ebb4841SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; 73*1ebb4841SHawking Zhang } 74*1ebb4841SHawking Zhang 75*1ebb4841SHawking Zhang if (adev->irq.ih2.ring_size) { 76*1ebb4841SHawking Zhang ih_regs = &adev->irq.ih2.ih_regs; 77*1ebb4841SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); 78*1ebb4841SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2); 79*1ebb4841SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 80*1ebb4841SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 81*1ebb4841SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 82*1ebb4841SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2); 83*1ebb4841SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2; 84*1ebb4841SHawking Zhang } 85*1ebb4841SHawking Zhang } 86*1ebb4841SHawking Zhang 87*1ebb4841SHawking Zhang /** 88282aae55SKen Wang * vega10_ih_enable_interrupts - Enable the interrupt ring buffer 89282aae55SKen Wang * 90282aae55SKen Wang * @adev: amdgpu_device pointer 91282aae55SKen Wang * 92282aae55SKen Wang * Enable the interrupt ring buffer (VEGA10). 93282aae55SKen Wang */ 94282aae55SKen Wang static void vega10_ih_enable_interrupts(struct amdgpu_device *adev) 95282aae55SKen Wang { 96b2b7e457SHawking Zhang u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 97282aae55SKen Wang 98282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); 99282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); 1004cd4c5c0SMonk Liu if (amdgpu_sriov_vf(adev)) { 101470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 102470b4250STrigger Huang DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 103470b4250STrigger Huang return; 104470b4250STrigger Huang } 105470b4250STrigger Huang } else { 106b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 107470b4250STrigger Huang } 108282aae55SKen Wang adev->irq.ih.enabled = true; 109ad710812SChristian König 110ad710812SChristian König if (adev->irq.ih1.ring_size) { 111ad710812SChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 112ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 113ad710812SChristian König RB_ENABLE, 1); 1144cd4c5c0SMonk Liu if (amdgpu_sriov_vf(adev)) { 115470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 116470b4250STrigger Huang ih_rb_cntl)) { 117470b4250STrigger Huang DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 118470b4250STrigger Huang return; 119470b4250STrigger Huang } 120470b4250STrigger Huang } else { 121ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 122470b4250STrigger Huang } 123ad710812SChristian König adev->irq.ih1.enabled = true; 124ad710812SChristian König } 125ad710812SChristian König 126ad710812SChristian König if (adev->irq.ih2.ring_size) { 127ad710812SChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 128ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 129ad710812SChristian König RB_ENABLE, 1); 1304cd4c5c0SMonk Liu if (amdgpu_sriov_vf(adev)) { 131470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 132470b4250STrigger Huang ih_rb_cntl)) { 133470b4250STrigger Huang DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 134470b4250STrigger Huang return; 135470b4250STrigger Huang } 136470b4250STrigger Huang } else { 137ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 138470b4250STrigger Huang } 139ad710812SChristian König adev->irq.ih2.enabled = true; 140ad710812SChristian König } 14147509189SChristian König 14247509189SChristian König if (adev->irq.ih_soft.ring_size) 14347509189SChristian König adev->irq.ih_soft.enabled = true; 144282aae55SKen Wang } 145282aae55SKen Wang 146282aae55SKen Wang /** 147282aae55SKen Wang * vega10_ih_disable_interrupts - Disable the interrupt ring buffer 148282aae55SKen Wang * 149282aae55SKen Wang * @adev: amdgpu_device pointer 150282aae55SKen Wang * 151282aae55SKen Wang * Disable the interrupt ring buffer (VEGA10). 152282aae55SKen Wang */ 153282aae55SKen Wang static void vega10_ih_disable_interrupts(struct amdgpu_device *adev) 154282aae55SKen Wang { 155b2b7e457SHawking Zhang u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 156282aae55SKen Wang 157282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); 158282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); 1594cd4c5c0SMonk Liu if (amdgpu_sriov_vf(adev)) { 160470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 161470b4250STrigger Huang DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 162470b4250STrigger Huang return; 163470b4250STrigger Huang } 164470b4250STrigger Huang } else { 165b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 166470b4250STrigger Huang } 167470b4250STrigger Huang 168282aae55SKen Wang /* set rptr, wptr to 0 */ 169b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 170b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 171282aae55SKen Wang adev->irq.ih.enabled = false; 172282aae55SKen Wang adev->irq.ih.rptr = 0; 173ad710812SChristian König 174ad710812SChristian König if (adev->irq.ih1.ring_size) { 175ad710812SChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 176ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 177ad710812SChristian König RB_ENABLE, 0); 1784cd4c5c0SMonk Liu if (amdgpu_sriov_vf(adev)) { 179470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 180470b4250STrigger Huang ih_rb_cntl)) { 181470b4250STrigger Huang DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 182470b4250STrigger Huang return; 183470b4250STrigger Huang } 184470b4250STrigger Huang } else { 185ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 186470b4250STrigger Huang } 187ad710812SChristian König /* set rptr, wptr to 0 */ 188ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 189ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 190ad710812SChristian König adev->irq.ih1.enabled = false; 191ad710812SChristian König adev->irq.ih1.rptr = 0; 192ad710812SChristian König } 193ad710812SChristian König 194ad710812SChristian König if (adev->irq.ih2.ring_size) { 195ad710812SChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 196ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 197ad710812SChristian König RB_ENABLE, 0); 1984cd4c5c0SMonk Liu if (amdgpu_sriov_vf(adev)) { 199470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 200470b4250STrigger Huang ih_rb_cntl)) { 201470b4250STrigger Huang DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 202470b4250STrigger Huang return; 203470b4250STrigger Huang } 204470b4250STrigger Huang } else { 205ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 206470b4250STrigger Huang } 207470b4250STrigger Huang 208ad710812SChristian König /* set rptr, wptr to 0 */ 209ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 210ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 211ad710812SChristian König adev->irq.ih2.enabled = false; 212ad710812SChristian König adev->irq.ih2.rptr = 0; 213ad710812SChristian König } 214ad710812SChristian König } 215ad710812SChristian König 216ad710812SChristian König static uint32_t vega10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 217ad710812SChristian König { 218ad710812SChristian König int rb_bufsz = order_base_2(ih->ring_size / 4); 219ad710812SChristian König 220ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 221ad710812SChristian König MC_SPACE, ih->use_bus_addr ? 1 : 4); 222ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 223ad710812SChristian König WPTR_OVERFLOW_CLEAR, 1); 224ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 225ad710812SChristian König WPTR_OVERFLOW_ENABLE, 1); 226ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 227ad710812SChristian König /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 228ad710812SChristian König * value is written to memory 229ad710812SChristian König */ 230ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 231ad710812SChristian König WPTR_WRITEBACK_ENABLE, 1); 232ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 233ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 234ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 235ad710812SChristian König 236ad710812SChristian König return ih_rb_cntl; 237282aae55SKen Wang } 238282aae55SKen Wang 2391ae64cecSChristian König static uint32_t vega10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 2401ae64cecSChristian König { 2411ae64cecSChristian König u32 ih_doorbell_rtpr = 0; 2421ae64cecSChristian König 2431ae64cecSChristian König if (ih->use_doorbell) { 2441ae64cecSChristian König ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 2451ae64cecSChristian König IH_DOORBELL_RPTR, OFFSET, 2461ae64cecSChristian König ih->doorbell_index); 2471ae64cecSChristian König ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 2481ae64cecSChristian König IH_DOORBELL_RPTR, 2491ae64cecSChristian König ENABLE, 1); 2501ae64cecSChristian König } else { 2511ae64cecSChristian König ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 2521ae64cecSChristian König IH_DOORBELL_RPTR, 2531ae64cecSChristian König ENABLE, 0); 2541ae64cecSChristian König } 2551ae64cecSChristian König return ih_doorbell_rtpr; 2561ae64cecSChristian König } 2571ae64cecSChristian König 258282aae55SKen Wang /** 259282aae55SKen Wang * vega10_ih_irq_init - init and enable the interrupt ring 260282aae55SKen Wang * 261282aae55SKen Wang * @adev: amdgpu_device pointer 262282aae55SKen Wang * 263282aae55SKen Wang * Allocate a ring buffer for the interrupt controller, 264282aae55SKen Wang * enable the RLC, disable interrupts, enable the IH 265282aae55SKen Wang * ring buffer and enable it (VI). 266282aae55SKen Wang * Called at device load and reume. 267282aae55SKen Wang * Returns 0 for success, errors for failure. 268282aae55SKen Wang */ 269282aae55SKen Wang static int vega10_ih_irq_init(struct amdgpu_device *adev) 270282aae55SKen Wang { 271ad710812SChristian König struct amdgpu_ih_ring *ih; 272f9c84ae5SLe Ma u32 ih_rb_cntl, ih_chicken; 273282aae55SKen Wang int ret = 0; 274282aae55SKen Wang u32 tmp; 275282aae55SKen Wang 276282aae55SKen Wang /* disable irqs */ 277282aae55SKen Wang vega10_ih_disable_interrupts(adev); 278282aae55SKen Wang 279bebc0762SHawking Zhang adev->nbio.funcs->ih_control(adev); 280282aae55SKen Wang 281ad710812SChristian König ih = &adev->irq.ih; 282282aae55SKen Wang /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 283ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8); 284ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff); 285282aae55SKen Wang 286ad710812SChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 287ad710812SChristian König ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl); 288ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 289ad710812SChristian König !!adev->irq.msi_enabled); 2904cd4c5c0SMonk Liu if (amdgpu_sriov_vf(adev)) { 291470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 292470b4250STrigger Huang DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 293470b4250STrigger Huang return -ETIMEDOUT; 294470b4250STrigger Huang } 295470b4250STrigger Huang } else { 296b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 297470b4250STrigger Huang } 298282aae55SKen Wang 29925344d7eSZhigang Luo if ((adev->asic_type == CHIP_ARCTURUS && 30025344d7eSZhigang Luo adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) || 30125344d7eSZhigang Luo adev->asic_type == CHIP_RENOIR) { 30225344d7eSZhigang Luo ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 30325344d7eSZhigang Luo if (adev->irq.ih.use_bus_addr) { 30425344d7eSZhigang Luo ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 30525344d7eSZhigang Luo MC_SPACE_GPA_ENABLE, 1); 30625344d7eSZhigang Luo } else { 30725344d7eSZhigang Luo ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 30825344d7eSZhigang Luo MC_SPACE_FBPA_ENABLE, 1); 30925344d7eSZhigang Luo } 310f9c84ae5SLe Ma WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 31125344d7eSZhigang Luo } 312f9c84ae5SLe Ma 313282aae55SKen Wang /* set the writeback address whether it's enabled or not */ 314d81f78b4SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, 315d81f78b4SChristian König lower_32_bits(ih->wptr_addr)); 316d81f78b4SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, 317d81f78b4SChristian König upper_32_bits(ih->wptr_addr) & 0xFFFF); 318282aae55SKen Wang 319282aae55SKen Wang /* set rptr, wptr to 0 */ 320b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 3211ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 322282aae55SKen Wang 3231ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, 3241ae64cecSChristian König vega10_ih_doorbell_rptr(ih)); 325282aae55SKen Wang 326ad710812SChristian König ih = &adev->irq.ih1; 327ad710812SChristian König if (ih->ring_size) { 328ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING1, ih->gpu_addr >> 8); 329ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING1, 330ad710812SChristian König (ih->gpu_addr >> 40) & 0xff); 331ad710812SChristian König 332ad710812SChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 333ad710812SChristian König ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl); 3340133690eSChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 3350133690eSChristian König WPTR_OVERFLOW_ENABLE, 0); 3360133690eSChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 3370133690eSChristian König RB_FULL_DRAIN_ENABLE, 1); 3384cd4c5c0SMonk Liu if (amdgpu_sriov_vf(adev)) { 339470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 340470b4250STrigger Huang ih_rb_cntl)) { 341470b4250STrigger Huang DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 342470b4250STrigger Huang return -ETIMEDOUT; 343470b4250STrigger Huang } 344470b4250STrigger Huang } else { 345ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 346470b4250STrigger Huang } 347ad710812SChristian König 348ad710812SChristian König /* set rptr, wptr to 0 */ 349ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 3501ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 3511ae64cecSChristian König 3521ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1, 3531ae64cecSChristian König vega10_ih_doorbell_rptr(ih)); 354ad710812SChristian König } 355ad710812SChristian König 356ad710812SChristian König ih = &adev->irq.ih2; 357ad710812SChristian König if (ih->ring_size) { 358ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING2, ih->gpu_addr >> 8); 359ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING2, 360ad710812SChristian König (ih->gpu_addr >> 40) & 0xff); 361ad710812SChristian König 3621ae64cecSChristian König ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 363ad710812SChristian König ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl); 364470b4250STrigger Huang 3654cd4c5c0SMonk Liu if (amdgpu_sriov_vf(adev)) { 366470b4250STrigger Huang if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 367470b4250STrigger Huang ih_rb_cntl)) { 368470b4250STrigger Huang DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 369470b4250STrigger Huang return -ETIMEDOUT; 370470b4250STrigger Huang } 371470b4250STrigger Huang } else { 372ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 373470b4250STrigger Huang } 374ad710812SChristian König 375ad710812SChristian König /* set rptr, wptr to 0 */ 376ad710812SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 3771ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 3781ae64cecSChristian König 3791ae64cecSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2, 3801ae64cecSChristian König vega10_ih_doorbell_rptr(ih)); 381ad710812SChristian König } 382ad710812SChristian König 383b2b7e457SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 384282aae55SKen Wang tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 385282aae55SKen Wang CLIENT18_IS_STORM_CLIENT, 1); 386b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 387282aae55SKen Wang 388b2b7e457SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 389282aae55SKen Wang tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 390b2b7e457SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 391282aae55SKen Wang 392282aae55SKen Wang pci_set_master(adev->pdev); 393282aae55SKen Wang 394282aae55SKen Wang /* enable interrupts */ 395282aae55SKen Wang vega10_ih_enable_interrupts(adev); 396282aae55SKen Wang 397282aae55SKen Wang return ret; 398282aae55SKen Wang } 399282aae55SKen Wang 400282aae55SKen Wang /** 401282aae55SKen Wang * vega10_ih_irq_disable - disable interrupts 402282aae55SKen Wang * 403282aae55SKen Wang * @adev: amdgpu_device pointer 404282aae55SKen Wang * 405282aae55SKen Wang * Disable interrupts on the hw (VEGA10). 406282aae55SKen Wang */ 407282aae55SKen Wang static void vega10_ih_irq_disable(struct amdgpu_device *adev) 408282aae55SKen Wang { 409282aae55SKen Wang vega10_ih_disable_interrupts(adev); 410282aae55SKen Wang 411282aae55SKen Wang /* Wait and acknowledge irq */ 412282aae55SKen Wang mdelay(1); 413282aae55SKen Wang } 414282aae55SKen Wang 415282aae55SKen Wang /** 416282aae55SKen Wang * vega10_ih_get_wptr - get the IH ring buffer wptr 417282aae55SKen Wang * 418282aae55SKen Wang * @adev: amdgpu_device pointer 4195162e40eSLee Jones * @ih: IH ring buffer to fetch wptr 420282aae55SKen Wang * 421282aae55SKen Wang * Get the IH ring buffer wptr from either the register 422282aae55SKen Wang * or the writeback memory buffer (VEGA10). Also check for 423282aae55SKen Wang * ring buffer overflow and deal with it. 424282aae55SKen Wang * Returns the value of the wptr. 425282aae55SKen Wang */ 4268bb9eb48SChristian König static u32 vega10_ih_get_wptr(struct amdgpu_device *adev, 4278bb9eb48SChristian König struct amdgpu_ih_ring *ih) 428282aae55SKen Wang { 429cf67950eSChristian König u32 wptr, reg, tmp; 430282aae55SKen Wang 431d81f78b4SChristian König wptr = le32_to_cpu(*ih->wptr_cpu); 432282aae55SKen Wang 433b8217575SChristian König if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 434b8217575SChristian König goto out; 435b8217575SChristian König 436b8217575SChristian König /* Double check that the overflow wasn't already cleared. */ 437cf67950eSChristian König 438cf67950eSChristian König if (ih == &adev->irq.ih) 439cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 440cf67950eSChristian König else if (ih == &adev->irq.ih1) 441cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 442cf67950eSChristian König else if (ih == &adev->irq.ih2) 443cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 444cf67950eSChristian König else 445cf67950eSChristian König BUG(); 446cf67950eSChristian König 447cf67950eSChristian König wptr = RREG32_NO_KIQ(reg); 448b8217575SChristian König if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 449b8217575SChristian König goto out; 450b8217575SChristian König 451282aae55SKen Wang wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 452282aae55SKen Wang 453282aae55SKen Wang /* When a ring buffer overflow happen start parsing interrupt 454282aae55SKen Wang * from the last not overwritten vector (wptr + 32). Hopefully 455282aae55SKen Wang * this should allow us to catchup. 456282aae55SKen Wang */ 4578bb9eb48SChristian König tmp = (wptr + 32) & ih->ptr_mask; 458b8217575SChristian König dev_warn(adev->dev, "IH ring buffer overflow " 459b8217575SChristian König "(0x%08X, 0x%08X, 0x%08X)\n", 4608bb9eb48SChristian König wptr, ih->rptr, tmp); 4618bb9eb48SChristian König ih->rptr = tmp; 462282aae55SKen Wang 463cf67950eSChristian König if (ih == &adev->irq.ih) 464cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 465cf67950eSChristian König else if (ih == &adev->irq.ih1) 466cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 467cf67950eSChristian König else if (ih == &adev->irq.ih2) 468cf67950eSChristian König reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 469cf67950eSChristian König else 470cf67950eSChristian König BUG(); 471cf67950eSChristian König 472cf67950eSChristian König tmp = RREG32_NO_KIQ(reg); 473282aae55SKen Wang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 474cf67950eSChristian König WREG32_NO_KIQ(reg, tmp); 475b8217575SChristian König 476b8217575SChristian König out: 4778bb9eb48SChristian König return (wptr & ih->ptr_mask); 478282aae55SKen Wang } 479282aae55SKen Wang 480282aae55SKen Wang /** 481282aae55SKen Wang * vega10_ih_decode_iv - decode an interrupt vector 482282aae55SKen Wang * 483282aae55SKen Wang * @adev: amdgpu_device pointer 4845162e40eSLee Jones * @ih: IH ring buffer to decode 4855162e40eSLee Jones * @entry: IV entry to place decoded information into 486282aae55SKen Wang * 487282aae55SKen Wang * Decodes the interrupt vector at the current rptr 488282aae55SKen Wang * position and also advance the position. 489282aae55SKen Wang */ 490282aae55SKen Wang static void vega10_ih_decode_iv(struct amdgpu_device *adev, 4918bb9eb48SChristian König struct amdgpu_ih_ring *ih, 492282aae55SKen Wang struct amdgpu_iv_entry *entry) 493282aae55SKen Wang { 494282aae55SKen Wang /* wptr/rptr are in bytes! */ 4958bb9eb48SChristian König u32 ring_index = ih->rptr >> 2; 496282aae55SKen Wang uint32_t dw[8]; 497282aae55SKen Wang 4988bb9eb48SChristian König dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 4998bb9eb48SChristian König dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 5008bb9eb48SChristian König dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 5018bb9eb48SChristian König dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 5028bb9eb48SChristian König dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); 5038bb9eb48SChristian König dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); 5048bb9eb48SChristian König dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); 5058bb9eb48SChristian König dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); 506282aae55SKen Wang 507282aae55SKen Wang entry->client_id = dw[0] & 0xff; 508282aae55SKen Wang entry->src_id = (dw[0] >> 8) & 0xff; 509282aae55SKen Wang entry->ring_id = (dw[0] >> 16) & 0xff; 510c4f46f22SChristian König entry->vmid = (dw[0] >> 24) & 0xf; 511c4f46f22SChristian König entry->vmid_src = (dw[0] >> 31); 512282aae55SKen Wang entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); 513282aae55SKen Wang entry->timestamp_src = dw[2] >> 31; 5143816e42fSChristian König entry->pasid = dw[3] & 0xffff; 515282aae55SKen Wang entry->pasid_src = dw[3] >> 31; 516282aae55SKen Wang entry->src_data[0] = dw[4]; 517282aae55SKen Wang entry->src_data[1] = dw[5]; 518282aae55SKen Wang entry->src_data[2] = dw[6]; 519282aae55SKen Wang entry->src_data[3] = dw[7]; 520282aae55SKen Wang 521282aae55SKen Wang /* wptr/rptr are in bytes! */ 5228bb9eb48SChristian König ih->rptr += 32; 523282aae55SKen Wang } 524282aae55SKen Wang 525282aae55SKen Wang /** 52674dcfe74STrigger Huang * vega10_ih_irq_rearm - rearm IRQ if lost 52774dcfe74STrigger Huang * 52874dcfe74STrigger Huang * @adev: amdgpu_device pointer 5295162e40eSLee Jones * @ih: IH ring to match 53074dcfe74STrigger Huang * 53174dcfe74STrigger Huang */ 53274dcfe74STrigger Huang static void vega10_ih_irq_rearm(struct amdgpu_device *adev, 53374dcfe74STrigger Huang struct amdgpu_ih_ring *ih) 53474dcfe74STrigger Huang { 53574dcfe74STrigger Huang uint32_t reg_rptr = 0; 53674dcfe74STrigger Huang uint32_t v = 0; 53774dcfe74STrigger Huang uint32_t i = 0; 53874dcfe74STrigger Huang 53974dcfe74STrigger Huang if (ih == &adev->irq.ih) 54074dcfe74STrigger Huang reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 54174dcfe74STrigger Huang else if (ih == &adev->irq.ih1) 54274dcfe74STrigger Huang reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 54374dcfe74STrigger Huang else if (ih == &adev->irq.ih2) 54474dcfe74STrigger Huang reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 54574dcfe74STrigger Huang else 54674dcfe74STrigger Huang return; 54774dcfe74STrigger Huang 54874dcfe74STrigger Huang /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */ 54974dcfe74STrigger Huang for (i = 0; i < MAX_REARM_RETRY; i++) { 55074dcfe74STrigger Huang v = RREG32_NO_KIQ(reg_rptr); 55174dcfe74STrigger Huang if ((v < ih->ring_size) && (v != ih->rptr)) 55274dcfe74STrigger Huang WDOORBELL32(ih->doorbell_index, ih->rptr); 55374dcfe74STrigger Huang else 55474dcfe74STrigger Huang break; 55574dcfe74STrigger Huang } 55674dcfe74STrigger Huang } 55774dcfe74STrigger Huang 55874dcfe74STrigger Huang /** 559282aae55SKen Wang * vega10_ih_set_rptr - set the IH ring buffer rptr 560282aae55SKen Wang * 561282aae55SKen Wang * @adev: amdgpu_device pointer 5625162e40eSLee Jones * @ih: IH ring buffer to set rptr 563282aae55SKen Wang * 564282aae55SKen Wang * Set the IH ring buffer rptr. 565282aae55SKen Wang */ 5668bb9eb48SChristian König static void vega10_ih_set_rptr(struct amdgpu_device *adev, 5678bb9eb48SChristian König struct amdgpu_ih_ring *ih) 568282aae55SKen Wang { 5698bb9eb48SChristian König if (ih->use_doorbell) { 570282aae55SKen Wang /* XXX check if swapping is necessary on BE */ 571d81f78b4SChristian König *ih->rptr_cpu = ih->rptr; 5728bb9eb48SChristian König WDOORBELL32(ih->doorbell_index, ih->rptr); 57374dcfe74STrigger Huang 57474dcfe74STrigger Huang if (amdgpu_sriov_vf(adev)) 57574dcfe74STrigger Huang vega10_ih_irq_rearm(adev, ih); 576cf67950eSChristian König } else if (ih == &adev->irq.ih) { 5778bb9eb48SChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr); 578cf67950eSChristian König } else if (ih == &adev->irq.ih1) { 579cf67950eSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, ih->rptr); 580cf67950eSChristian König } else if (ih == &adev->irq.ih2) { 581cf67950eSChristian König WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, ih->rptr); 582282aae55SKen Wang } 583282aae55SKen Wang } 584282aae55SKen Wang 585cf67950eSChristian König /** 586cf67950eSChristian König * vega10_ih_self_irq - dispatch work for ring 1 and 2 587cf67950eSChristian König * 588cf67950eSChristian König * @adev: amdgpu_device pointer 589cf67950eSChristian König * @source: irq source 590cf67950eSChristian König * @entry: IV with WPTR update 591cf67950eSChristian König * 592cf67950eSChristian König * Update the WPTR from the IV and schedule work to handle the entries. 593cf67950eSChristian König */ 594cf67950eSChristian König static int vega10_ih_self_irq(struct amdgpu_device *adev, 595cf67950eSChristian König struct amdgpu_irq_src *source, 596cf67950eSChristian König struct amdgpu_iv_entry *entry) 597cf67950eSChristian König { 598cf67950eSChristian König uint32_t wptr = cpu_to_le32(entry->src_data[0]); 599cf67950eSChristian König 600cf67950eSChristian König switch (entry->ring_id) { 601cf67950eSChristian König case 1: 602cf67950eSChristian König *adev->irq.ih1.wptr_cpu = wptr; 603cf67950eSChristian König schedule_work(&adev->irq.ih1_work); 604cf67950eSChristian König break; 605cf67950eSChristian König case 2: 606cf67950eSChristian König *adev->irq.ih2.wptr_cpu = wptr; 607cf67950eSChristian König schedule_work(&adev->irq.ih2_work); 608cf67950eSChristian König break; 609cf67950eSChristian König default: break; 610cf67950eSChristian König } 611cf67950eSChristian König return 0; 612cf67950eSChristian König } 613cf67950eSChristian König 614cf67950eSChristian König static const struct amdgpu_irq_src_funcs vega10_ih_self_irq_funcs = { 615cf67950eSChristian König .process = vega10_ih_self_irq, 616cf67950eSChristian König }; 617cf67950eSChristian König 618cf67950eSChristian König static void vega10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 619cf67950eSChristian König { 620cf67950eSChristian König adev->irq.self_irq.num_types = 0; 621cf67950eSChristian König adev->irq.self_irq.funcs = &vega10_ih_self_irq_funcs; 622cf67950eSChristian König } 623cf67950eSChristian König 624282aae55SKen Wang static int vega10_ih_early_init(void *handle) 625282aae55SKen Wang { 626282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 627282aae55SKen Wang 628282aae55SKen Wang vega10_ih_set_interrupt_funcs(adev); 629cf67950eSChristian König vega10_ih_set_self_irq_funcs(adev); 630282aae55SKen Wang return 0; 631282aae55SKen Wang } 632282aae55SKen Wang 633282aae55SKen Wang static int vega10_ih_sw_init(void *handle) 634282aae55SKen Wang { 635282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 636cf67950eSChristian König int r; 637cf67950eSChristian König 638cf67950eSChristian König r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 639cf67950eSChristian König &adev->irq.self_irq); 640cf67950eSChristian König if (r) 641cf67950eSChristian König return r; 642282aae55SKen Wang 643425c3143SChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true); 644282aae55SKen Wang if (r) 645282aae55SKen Wang return r; 646282aae55SKen Wang 6471ae64cecSChristian König adev->irq.ih.use_doorbell = true; 6481ae64cecSChristian König adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 6491ae64cecSChristian König 650ad710812SChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 651ad710812SChristian König if (r) 652ad710812SChristian König return r; 653ad710812SChristian König 6541ae64cecSChristian König adev->irq.ih1.use_doorbell = true; 655b51cd19eSChristian König adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; 6561ae64cecSChristian König 657ad710812SChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 658ad710812SChristian König if (r) 659ad710812SChristian König return r; 660ad710812SChristian König 6611ae64cecSChristian König adev->irq.ih2.use_doorbell = true; 662b51cd19eSChristian König adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1; 663282aae55SKen Wang 66447509189SChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); 66547509189SChristian König if (r) 66647509189SChristian König return r; 66747509189SChristian König 668282aae55SKen Wang r = amdgpu_irq_init(adev); 669282aae55SKen Wang 670282aae55SKen Wang return r; 671282aae55SKen Wang } 672282aae55SKen Wang 673282aae55SKen Wang static int vega10_ih_sw_fini(void *handle) 674282aae55SKen Wang { 675282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 676282aae55SKen Wang 677282aae55SKen Wang amdgpu_irq_fini(adev); 678ad710812SChristian König amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 679ad710812SChristian König amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 680425c3143SChristian König amdgpu_ih_ring_fini(adev, &adev->irq.ih); 681282aae55SKen Wang 682282aae55SKen Wang return 0; 683282aae55SKen Wang } 684282aae55SKen Wang 685282aae55SKen Wang static int vega10_ih_hw_init(void *handle) 686282aae55SKen Wang { 687282aae55SKen Wang int r; 688282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 689282aae55SKen Wang 690282aae55SKen Wang r = vega10_ih_irq_init(adev); 691282aae55SKen Wang if (r) 692282aae55SKen Wang return r; 693282aae55SKen Wang 694282aae55SKen Wang return 0; 695282aae55SKen Wang } 696282aae55SKen Wang 697282aae55SKen Wang static int vega10_ih_hw_fini(void *handle) 698282aae55SKen Wang { 699282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 700282aae55SKen Wang 701282aae55SKen Wang vega10_ih_irq_disable(adev); 702282aae55SKen Wang 703282aae55SKen Wang return 0; 704282aae55SKen Wang } 705282aae55SKen Wang 706282aae55SKen Wang static int vega10_ih_suspend(void *handle) 707282aae55SKen Wang { 708282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 709282aae55SKen Wang 710282aae55SKen Wang return vega10_ih_hw_fini(adev); 711282aae55SKen Wang } 712282aae55SKen Wang 713282aae55SKen Wang static int vega10_ih_resume(void *handle) 714282aae55SKen Wang { 715282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 716282aae55SKen Wang 717282aae55SKen Wang return vega10_ih_hw_init(adev); 718282aae55SKen Wang } 719282aae55SKen Wang 720282aae55SKen Wang static bool vega10_ih_is_idle(void *handle) 721282aae55SKen Wang { 722282aae55SKen Wang /* todo */ 723282aae55SKen Wang return true; 724282aae55SKen Wang } 725282aae55SKen Wang 726282aae55SKen Wang static int vega10_ih_wait_for_idle(void *handle) 727282aae55SKen Wang { 728282aae55SKen Wang /* todo */ 729282aae55SKen Wang return -ETIMEDOUT; 730282aae55SKen Wang } 731282aae55SKen Wang 732282aae55SKen Wang static int vega10_ih_soft_reset(void *handle) 733282aae55SKen Wang { 734282aae55SKen Wang /* todo */ 735282aae55SKen Wang 736282aae55SKen Wang return 0; 737282aae55SKen Wang } 738282aae55SKen Wang 739227f7d58SKenneth Feng static void vega10_ih_update_clockgating_state(struct amdgpu_device *adev, 740227f7d58SKenneth Feng bool enable) 741227f7d58SKenneth Feng { 742227f7d58SKenneth Feng uint32_t data, def, field_val; 743227f7d58SKenneth Feng 744227f7d58SKenneth Feng if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 745227f7d58SKenneth Feng def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 746227f7d58SKenneth Feng field_val = enable ? 0 : 1; 747227f7d58SKenneth Feng /** 748227f7d58SKenneth Feng * Vega10 does not have IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE 749227f7d58SKenneth Feng * and IH_BUFFER_MEM_CLK_SOFT_OVERRIDE field. 750227f7d58SKenneth Feng */ 751227f7d58SKenneth Feng if (adev->asic_type > CHIP_VEGA10) { 752227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 753227f7d58SKenneth Feng IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE, field_val); 754227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 755227f7d58SKenneth Feng IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val); 756227f7d58SKenneth Feng } 757227f7d58SKenneth Feng 758227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 759227f7d58SKenneth Feng DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 760227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 761227f7d58SKenneth Feng OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 762227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 763227f7d58SKenneth Feng LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 764227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 765227f7d58SKenneth Feng DYN_CLK_SOFT_OVERRIDE, field_val); 766227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL, 767227f7d58SKenneth Feng REG_CLK_SOFT_OVERRIDE, field_val); 768227f7d58SKenneth Feng if (def != data) 769227f7d58SKenneth Feng WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 770227f7d58SKenneth Feng } 771227f7d58SKenneth Feng } 772227f7d58SKenneth Feng 773282aae55SKen Wang static int vega10_ih_set_clockgating_state(void *handle, 774282aae55SKen Wang enum amd_clockgating_state state) 775282aae55SKen Wang { 776227f7d58SKenneth Feng struct amdgpu_device *adev = (struct amdgpu_device *)handle; 777227f7d58SKenneth Feng 778227f7d58SKenneth Feng vega10_ih_update_clockgating_state(adev, 779a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 780282aae55SKen Wang return 0; 781227f7d58SKenneth Feng 782282aae55SKen Wang } 783282aae55SKen Wang 784282aae55SKen Wang static int vega10_ih_set_powergating_state(void *handle, 785282aae55SKen Wang enum amd_powergating_state state) 786282aae55SKen Wang { 787282aae55SKen Wang return 0; 788282aae55SKen Wang } 789282aae55SKen Wang 790282aae55SKen Wang const struct amd_ip_funcs vega10_ih_ip_funcs = { 791282aae55SKen Wang .name = "vega10_ih", 792282aae55SKen Wang .early_init = vega10_ih_early_init, 793282aae55SKen Wang .late_init = NULL, 794282aae55SKen Wang .sw_init = vega10_ih_sw_init, 795282aae55SKen Wang .sw_fini = vega10_ih_sw_fini, 796282aae55SKen Wang .hw_init = vega10_ih_hw_init, 797282aae55SKen Wang .hw_fini = vega10_ih_hw_fini, 798282aae55SKen Wang .suspend = vega10_ih_suspend, 799282aae55SKen Wang .resume = vega10_ih_resume, 800282aae55SKen Wang .is_idle = vega10_ih_is_idle, 801282aae55SKen Wang .wait_for_idle = vega10_ih_wait_for_idle, 802282aae55SKen Wang .soft_reset = vega10_ih_soft_reset, 803282aae55SKen Wang .set_clockgating_state = vega10_ih_set_clockgating_state, 804282aae55SKen Wang .set_powergating_state = vega10_ih_set_powergating_state, 805282aae55SKen Wang }; 806282aae55SKen Wang 807282aae55SKen Wang static const struct amdgpu_ih_funcs vega10_ih_funcs = { 808282aae55SKen Wang .get_wptr = vega10_ih_get_wptr, 809282aae55SKen Wang .decode_iv = vega10_ih_decode_iv, 810282aae55SKen Wang .set_rptr = vega10_ih_set_rptr 811282aae55SKen Wang }; 812282aae55SKen Wang 813282aae55SKen Wang static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 814282aae55SKen Wang { 815282aae55SKen Wang adev->irq.ih_funcs = &vega10_ih_funcs; 816282aae55SKen Wang } 817282aae55SKen Wang 818282aae55SKen Wang const struct amdgpu_ip_block_version vega10_ih_ip_block = 819282aae55SKen Wang { 820282aae55SKen Wang .type = AMD_IP_BLOCK_TYPE_IH, 821282aae55SKen Wang .major = 4, 822282aae55SKen Wang .minor = 0, 823282aae55SKen Wang .rev = 0, 824282aae55SKen Wang .funcs = &vega10_ih_ip_funcs, 825282aae55SKen Wang }; 826