1282aae55SKen Wang /* 2282aae55SKen Wang * Copyright 2016 Advanced Micro Devices, Inc. 3282aae55SKen Wang * 4282aae55SKen Wang * Permission is hereby granted, free of charge, to any person obtaining a 5282aae55SKen Wang * copy of this software and associated documentation files (the "Software"), 6282aae55SKen Wang * to deal in the Software without restriction, including without limitation 7282aae55SKen Wang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8282aae55SKen Wang * and/or sell copies of the Software, and to permit persons to whom the 9282aae55SKen Wang * Software is furnished to do so, subject to the following conditions: 10282aae55SKen Wang * 11282aae55SKen Wang * The above copyright notice and this permission notice shall be included in 12282aae55SKen Wang * all copies or substantial portions of the Software. 13282aae55SKen Wang * 14282aae55SKen Wang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15282aae55SKen Wang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16282aae55SKen Wang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17282aae55SKen Wang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18282aae55SKen Wang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19282aae55SKen Wang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20282aae55SKen Wang * OTHER DEALINGS IN THE SOFTWARE. 21282aae55SKen Wang * 22282aae55SKen Wang */ 23248a1d6fSMasahiro Yamada #include <drm/drmP.h> 24282aae55SKen Wang #include "amdgpu.h" 25282aae55SKen Wang #include "amdgpu_ih.h" 26282aae55SKen Wang #include "soc15.h" 27282aae55SKen Wang 28282aae55SKen Wang 29282aae55SKen Wang #include "vega10/soc15ip.h" 30282aae55SKen Wang #include "vega10/OSSSYS/osssys_4_0_offset.h" 31282aae55SKen Wang #include "vega10/OSSSYS/osssys_4_0_sh_mask.h" 32282aae55SKen Wang 33282aae55SKen Wang #include "soc15_common.h" 34282aae55SKen Wang #include "vega10_ih.h" 35282aae55SKen Wang 36282aae55SKen Wang 37282aae55SKen Wang 38282aae55SKen Wang static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 39282aae55SKen Wang 40282aae55SKen Wang /** 41282aae55SKen Wang * vega10_ih_enable_interrupts - Enable the interrupt ring buffer 42282aae55SKen Wang * 43282aae55SKen Wang * @adev: amdgpu_device pointer 44282aae55SKen Wang * 45282aae55SKen Wang * Enable the interrupt ring buffer (VEGA10). 46282aae55SKen Wang */ 47282aae55SKen Wang static void vega10_ih_enable_interrupts(struct amdgpu_device *adev) 48282aae55SKen Wang { 49282aae55SKen Wang u32 ih_rb_cntl = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL)); 50282aae55SKen Wang 51282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); 52282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); 53282aae55SKen Wang WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), ih_rb_cntl); 54282aae55SKen Wang adev->irq.ih.enabled = true; 55282aae55SKen Wang } 56282aae55SKen Wang 57282aae55SKen Wang /** 58282aae55SKen Wang * vega10_ih_disable_interrupts - Disable the interrupt ring buffer 59282aae55SKen Wang * 60282aae55SKen Wang * @adev: amdgpu_device pointer 61282aae55SKen Wang * 62282aae55SKen Wang * Disable the interrupt ring buffer (VEGA10). 63282aae55SKen Wang */ 64282aae55SKen Wang static void vega10_ih_disable_interrupts(struct amdgpu_device *adev) 65282aae55SKen Wang { 66282aae55SKen Wang u32 ih_rb_cntl = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL)); 67282aae55SKen Wang 68282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); 69282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); 70282aae55SKen Wang WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), ih_rb_cntl); 71282aae55SKen Wang /* set rptr, wptr to 0 */ 72282aae55SKen Wang WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR), 0); 73282aae55SKen Wang WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR), 0); 74282aae55SKen Wang adev->irq.ih.enabled = false; 75282aae55SKen Wang adev->irq.ih.rptr = 0; 76282aae55SKen Wang } 77282aae55SKen Wang 78282aae55SKen Wang /** 79282aae55SKen Wang * vega10_ih_irq_init - init and enable the interrupt ring 80282aae55SKen Wang * 81282aae55SKen Wang * @adev: amdgpu_device pointer 82282aae55SKen Wang * 83282aae55SKen Wang * Allocate a ring buffer for the interrupt controller, 84282aae55SKen Wang * enable the RLC, disable interrupts, enable the IH 85282aae55SKen Wang * ring buffer and enable it (VI). 86282aae55SKen Wang * Called at device load and reume. 87282aae55SKen Wang * Returns 0 for success, errors for failure. 88282aae55SKen Wang */ 89282aae55SKen Wang static int vega10_ih_irq_init(struct amdgpu_device *adev) 90282aae55SKen Wang { 91282aae55SKen Wang int ret = 0; 92282aae55SKen Wang int rb_bufsz; 93282aae55SKen Wang u32 ih_rb_cntl, ih_doorbell_rtpr; 94282aae55SKen Wang u32 tmp; 95282aae55SKen Wang u64 wptr_off; 96282aae55SKen Wang 97282aae55SKen Wang /* disable irqs */ 98282aae55SKen Wang vega10_ih_disable_interrupts(adev); 99282aae55SKen Wang 100aecbe64fSChunming Zhou if (adev->flags & AMD_IS_APU) 101aecbe64fSChunming Zhou nbio_v7_0_ih_control(adev); 102aecbe64fSChunming Zhou else 103282aae55SKen Wang nbio_v6_1_ih_control(adev); 104282aae55SKen Wang 105282aae55SKen Wang ih_rb_cntl = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL)); 106282aae55SKen Wang /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 107282aae55SKen Wang if (adev->irq.ih.use_bus_addr) { 108282aae55SKen Wang WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE), adev->irq.ih.rb_dma_addr >> 8); 10960508d3dSAlex Xie WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI), ((u64)adev->irq.ih.rb_dma_addr >> 40) & 0xff); 110282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 1); 111282aae55SKen Wang } else { 112282aae55SKen Wang WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE), adev->irq.ih.gpu_addr >> 8); 113282aae55SKen Wang WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI), (adev->irq.ih.gpu_addr >> 40) & 0xff); 114282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 4); 115282aae55SKen Wang } 116282aae55SKen Wang rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); 117282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 118282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1); 119282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 120282aae55SKen Wang /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */ 121282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); 122282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 123282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 124282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 125282aae55SKen Wang 126282aae55SKen Wang if (adev->irq.msi_enabled) 127282aae55SKen Wang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1); 128282aae55SKen Wang 129282aae55SKen Wang WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), ih_rb_cntl); 130282aae55SKen Wang 131282aae55SKen Wang /* set the writeback address whether it's enabled or not */ 132282aae55SKen Wang if (adev->irq.ih.use_bus_addr) 133282aae55SKen Wang wptr_off = adev->irq.ih.rb_dma_addr + (adev->irq.ih.wptr_offs * 4); 134282aae55SKen Wang else 135282aae55SKen Wang wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); 136282aae55SKen Wang WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO), lower_32_bits(wptr_off)); 137282aae55SKen Wang WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI), upper_32_bits(wptr_off) & 0xFF); 138282aae55SKen Wang 139282aae55SKen Wang /* set rptr, wptr to 0 */ 140282aae55SKen Wang WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR), 0); 141282aae55SKen Wang WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR), 0); 142282aae55SKen Wang 143282aae55SKen Wang ih_doorbell_rtpr = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR)); 144282aae55SKen Wang if (adev->irq.ih.use_doorbell) { 145282aae55SKen Wang ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, 146282aae55SKen Wang OFFSET, adev->irq.ih.doorbell_index); 147282aae55SKen Wang ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, 148282aae55SKen Wang ENABLE, 1); 149282aae55SKen Wang } else { 150282aae55SKen Wang ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, 151282aae55SKen Wang ENABLE, 0); 152282aae55SKen Wang } 153282aae55SKen Wang WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR), ih_doorbell_rtpr); 154aecbe64fSChunming Zhou if (adev->flags & AMD_IS_APU) 155aecbe64fSChunming Zhou nbio_v7_0_ih_doorbell_range(adev, adev->irq.ih.use_doorbell, adev->irq.ih.doorbell_index); 156aecbe64fSChunming Zhou else 157282aae55SKen Wang nbio_v6_1_ih_doorbell_range(adev, adev->irq.ih.use_doorbell, adev->irq.ih.doorbell_index); 158282aae55SKen Wang 159282aae55SKen Wang tmp = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL)); 160282aae55SKen Wang tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 161282aae55SKen Wang CLIENT18_IS_STORM_CLIENT, 1); 162282aae55SKen Wang WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL), tmp); 163282aae55SKen Wang 164282aae55SKen Wang tmp = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_INT_FLOOD_CNTL)); 165282aae55SKen Wang tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 166282aae55SKen Wang WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_INT_FLOOD_CNTL), tmp); 167282aae55SKen Wang 168282aae55SKen Wang pci_set_master(adev->pdev); 169282aae55SKen Wang 170282aae55SKen Wang /* enable interrupts */ 171282aae55SKen Wang vega10_ih_enable_interrupts(adev); 172282aae55SKen Wang 173282aae55SKen Wang return ret; 174282aae55SKen Wang } 175282aae55SKen Wang 176282aae55SKen Wang /** 177282aae55SKen Wang * vega10_ih_irq_disable - disable interrupts 178282aae55SKen Wang * 179282aae55SKen Wang * @adev: amdgpu_device pointer 180282aae55SKen Wang * 181282aae55SKen Wang * Disable interrupts on the hw (VEGA10). 182282aae55SKen Wang */ 183282aae55SKen Wang static void vega10_ih_irq_disable(struct amdgpu_device *adev) 184282aae55SKen Wang { 185282aae55SKen Wang vega10_ih_disable_interrupts(adev); 186282aae55SKen Wang 187282aae55SKen Wang /* Wait and acknowledge irq */ 188282aae55SKen Wang mdelay(1); 189282aae55SKen Wang } 190282aae55SKen Wang 191282aae55SKen Wang /** 192282aae55SKen Wang * vega10_ih_get_wptr - get the IH ring buffer wptr 193282aae55SKen Wang * 194282aae55SKen Wang * @adev: amdgpu_device pointer 195282aae55SKen Wang * 196282aae55SKen Wang * Get the IH ring buffer wptr from either the register 197282aae55SKen Wang * or the writeback memory buffer (VEGA10). Also check for 198282aae55SKen Wang * ring buffer overflow and deal with it. 199282aae55SKen Wang * Returns the value of the wptr. 200282aae55SKen Wang */ 201282aae55SKen Wang static u32 vega10_ih_get_wptr(struct amdgpu_device *adev) 202282aae55SKen Wang { 203282aae55SKen Wang u32 wptr, tmp; 204282aae55SKen Wang 205282aae55SKen Wang if (adev->irq.ih.use_bus_addr) 206282aae55SKen Wang wptr = le32_to_cpu(adev->irq.ih.ring[adev->irq.ih.wptr_offs]); 207282aae55SKen Wang else 208282aae55SKen Wang wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); 209282aae55SKen Wang 210282aae55SKen Wang if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { 211282aae55SKen Wang wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 212282aae55SKen Wang 213282aae55SKen Wang /* When a ring buffer overflow happen start parsing interrupt 214282aae55SKen Wang * from the last not overwritten vector (wptr + 32). Hopefully 215282aae55SKen Wang * this should allow us to catchup. 216282aae55SKen Wang */ 217282aae55SKen Wang tmp = (wptr + 32) & adev->irq.ih.ptr_mask; 218282aae55SKen Wang dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", 219282aae55SKen Wang wptr, adev->irq.ih.rptr, tmp); 220282aae55SKen Wang adev->irq.ih.rptr = tmp; 221282aae55SKen Wang 222282aae55SKen Wang tmp = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL)); 223282aae55SKen Wang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 224282aae55SKen Wang WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), tmp); 225282aae55SKen Wang } 226282aae55SKen Wang return (wptr & adev->irq.ih.ptr_mask); 227282aae55SKen Wang } 228282aae55SKen Wang 229282aae55SKen Wang /** 23000ecd8a2SFelix Kuehling * vega10_ih_prescreen_iv - prescreen an interrupt vector 23100ecd8a2SFelix Kuehling * 23200ecd8a2SFelix Kuehling * @adev: amdgpu_device pointer 23300ecd8a2SFelix Kuehling * 23400ecd8a2SFelix Kuehling * Returns true if the interrupt vector should be further processed. 23500ecd8a2SFelix Kuehling */ 23600ecd8a2SFelix Kuehling static bool vega10_ih_prescreen_iv(struct amdgpu_device *adev) 23700ecd8a2SFelix Kuehling { 23800ecd8a2SFelix Kuehling /* TODO: Filter known pending page faults */ 23900ecd8a2SFelix Kuehling return true; 24000ecd8a2SFelix Kuehling } 24100ecd8a2SFelix Kuehling 24200ecd8a2SFelix Kuehling /** 243282aae55SKen Wang * vega10_ih_decode_iv - decode an interrupt vector 244282aae55SKen Wang * 245282aae55SKen Wang * @adev: amdgpu_device pointer 246282aae55SKen Wang * 247282aae55SKen Wang * Decodes the interrupt vector at the current rptr 248282aae55SKen Wang * position and also advance the position. 249282aae55SKen Wang */ 250282aae55SKen Wang static void vega10_ih_decode_iv(struct amdgpu_device *adev, 251282aae55SKen Wang struct amdgpu_iv_entry *entry) 252282aae55SKen Wang { 253282aae55SKen Wang /* wptr/rptr are in bytes! */ 254282aae55SKen Wang u32 ring_index = adev->irq.ih.rptr >> 2; 255282aae55SKen Wang uint32_t dw[8]; 256282aae55SKen Wang 257282aae55SKen Wang dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]); 258282aae55SKen Wang dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]); 259282aae55SKen Wang dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]); 260282aae55SKen Wang dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]); 261282aae55SKen Wang dw[4] = le32_to_cpu(adev->irq.ih.ring[ring_index + 4]); 262282aae55SKen Wang dw[5] = le32_to_cpu(adev->irq.ih.ring[ring_index + 5]); 263282aae55SKen Wang dw[6] = le32_to_cpu(adev->irq.ih.ring[ring_index + 6]); 264282aae55SKen Wang dw[7] = le32_to_cpu(adev->irq.ih.ring[ring_index + 7]); 265282aae55SKen Wang 266282aae55SKen Wang entry->client_id = dw[0] & 0xff; 267282aae55SKen Wang entry->src_id = (dw[0] >> 8) & 0xff; 268282aae55SKen Wang entry->ring_id = (dw[0] >> 16) & 0xff; 269282aae55SKen Wang entry->vm_id = (dw[0] >> 24) & 0xf; 270282aae55SKen Wang entry->vm_id_src = (dw[0] >> 31); 271282aae55SKen Wang entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); 272282aae55SKen Wang entry->timestamp_src = dw[2] >> 31; 273282aae55SKen Wang entry->pas_id = dw[3] & 0xffff; 274282aae55SKen Wang entry->pasid_src = dw[3] >> 31; 275282aae55SKen Wang entry->src_data[0] = dw[4]; 276282aae55SKen Wang entry->src_data[1] = dw[5]; 277282aae55SKen Wang entry->src_data[2] = dw[6]; 278282aae55SKen Wang entry->src_data[3] = dw[7]; 279282aae55SKen Wang 280282aae55SKen Wang 281282aae55SKen Wang /* wptr/rptr are in bytes! */ 282282aae55SKen Wang adev->irq.ih.rptr += 32; 283282aae55SKen Wang } 284282aae55SKen Wang 285282aae55SKen Wang /** 286282aae55SKen Wang * vega10_ih_set_rptr - set the IH ring buffer rptr 287282aae55SKen Wang * 288282aae55SKen Wang * @adev: amdgpu_device pointer 289282aae55SKen Wang * 290282aae55SKen Wang * Set the IH ring buffer rptr. 291282aae55SKen Wang */ 292282aae55SKen Wang static void vega10_ih_set_rptr(struct amdgpu_device *adev) 293282aae55SKen Wang { 294282aae55SKen Wang if (adev->irq.ih.use_doorbell) { 295282aae55SKen Wang /* XXX check if swapping is necessary on BE */ 296282aae55SKen Wang if (adev->irq.ih.use_bus_addr) 297282aae55SKen Wang adev->irq.ih.ring[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr; 298282aae55SKen Wang else 299282aae55SKen Wang adev->wb.wb[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr; 300282aae55SKen Wang WDOORBELL32(adev->irq.ih.doorbell_index, adev->irq.ih.rptr); 301282aae55SKen Wang } else { 302282aae55SKen Wang WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR), adev->irq.ih.rptr); 303282aae55SKen Wang } 304282aae55SKen Wang } 305282aae55SKen Wang 306282aae55SKen Wang static int vega10_ih_early_init(void *handle) 307282aae55SKen Wang { 308282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 309282aae55SKen Wang 310282aae55SKen Wang vega10_ih_set_interrupt_funcs(adev); 311282aae55SKen Wang return 0; 312282aae55SKen Wang } 313282aae55SKen Wang 314282aae55SKen Wang static int vega10_ih_sw_init(void *handle) 315282aae55SKen Wang { 316282aae55SKen Wang int r; 317282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 318282aae55SKen Wang 319282aae55SKen Wang r = amdgpu_ih_ring_init(adev, 256 * 1024, true); 320282aae55SKen Wang if (r) 321282aae55SKen Wang return r; 322282aae55SKen Wang 323282aae55SKen Wang adev->irq.ih.use_doorbell = true; 324282aae55SKen Wang adev->irq.ih.doorbell_index = AMDGPU_DOORBELL64_IH << 1; 325282aae55SKen Wang 326282aae55SKen Wang r = amdgpu_irq_init(adev); 327282aae55SKen Wang 328282aae55SKen Wang return r; 329282aae55SKen Wang } 330282aae55SKen Wang 331282aae55SKen Wang static int vega10_ih_sw_fini(void *handle) 332282aae55SKen Wang { 333282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 334282aae55SKen Wang 335282aae55SKen Wang amdgpu_irq_fini(adev); 336282aae55SKen Wang amdgpu_ih_ring_fini(adev); 337282aae55SKen Wang 338282aae55SKen Wang return 0; 339282aae55SKen Wang } 340282aae55SKen Wang 341282aae55SKen Wang static int vega10_ih_hw_init(void *handle) 342282aae55SKen Wang { 343282aae55SKen Wang int r; 344282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 345282aae55SKen Wang 346282aae55SKen Wang r = vega10_ih_irq_init(adev); 347282aae55SKen Wang if (r) 348282aae55SKen Wang return r; 349282aae55SKen Wang 350282aae55SKen Wang return 0; 351282aae55SKen Wang } 352282aae55SKen Wang 353282aae55SKen Wang static int vega10_ih_hw_fini(void *handle) 354282aae55SKen Wang { 355282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 356282aae55SKen Wang 357282aae55SKen Wang vega10_ih_irq_disable(adev); 358282aae55SKen Wang 359282aae55SKen Wang return 0; 360282aae55SKen Wang } 361282aae55SKen Wang 362282aae55SKen Wang static int vega10_ih_suspend(void *handle) 363282aae55SKen Wang { 364282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 365282aae55SKen Wang 366282aae55SKen Wang return vega10_ih_hw_fini(adev); 367282aae55SKen Wang } 368282aae55SKen Wang 369282aae55SKen Wang static int vega10_ih_resume(void *handle) 370282aae55SKen Wang { 371282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 372282aae55SKen Wang 373282aae55SKen Wang return vega10_ih_hw_init(adev); 374282aae55SKen Wang } 375282aae55SKen Wang 376282aae55SKen Wang static bool vega10_ih_is_idle(void *handle) 377282aae55SKen Wang { 378282aae55SKen Wang /* todo */ 379282aae55SKen Wang return true; 380282aae55SKen Wang } 381282aae55SKen Wang 382282aae55SKen Wang static int vega10_ih_wait_for_idle(void *handle) 383282aae55SKen Wang { 384282aae55SKen Wang /* todo */ 385282aae55SKen Wang return -ETIMEDOUT; 386282aae55SKen Wang } 387282aae55SKen Wang 388282aae55SKen Wang static int vega10_ih_soft_reset(void *handle) 389282aae55SKen Wang { 390282aae55SKen Wang /* todo */ 391282aae55SKen Wang 392282aae55SKen Wang return 0; 393282aae55SKen Wang } 394282aae55SKen Wang 395282aae55SKen Wang static int vega10_ih_set_clockgating_state(void *handle, 396282aae55SKen Wang enum amd_clockgating_state state) 397282aae55SKen Wang { 398282aae55SKen Wang return 0; 399282aae55SKen Wang } 400282aae55SKen Wang 401282aae55SKen Wang static int vega10_ih_set_powergating_state(void *handle, 402282aae55SKen Wang enum amd_powergating_state state) 403282aae55SKen Wang { 404282aae55SKen Wang return 0; 405282aae55SKen Wang } 406282aae55SKen Wang 407282aae55SKen Wang const struct amd_ip_funcs vega10_ih_ip_funcs = { 408282aae55SKen Wang .name = "vega10_ih", 409282aae55SKen Wang .early_init = vega10_ih_early_init, 410282aae55SKen Wang .late_init = NULL, 411282aae55SKen Wang .sw_init = vega10_ih_sw_init, 412282aae55SKen Wang .sw_fini = vega10_ih_sw_fini, 413282aae55SKen Wang .hw_init = vega10_ih_hw_init, 414282aae55SKen Wang .hw_fini = vega10_ih_hw_fini, 415282aae55SKen Wang .suspend = vega10_ih_suspend, 416282aae55SKen Wang .resume = vega10_ih_resume, 417282aae55SKen Wang .is_idle = vega10_ih_is_idle, 418282aae55SKen Wang .wait_for_idle = vega10_ih_wait_for_idle, 419282aae55SKen Wang .soft_reset = vega10_ih_soft_reset, 420282aae55SKen Wang .set_clockgating_state = vega10_ih_set_clockgating_state, 421282aae55SKen Wang .set_powergating_state = vega10_ih_set_powergating_state, 422282aae55SKen Wang }; 423282aae55SKen Wang 424282aae55SKen Wang static const struct amdgpu_ih_funcs vega10_ih_funcs = { 425282aae55SKen Wang .get_wptr = vega10_ih_get_wptr, 42600ecd8a2SFelix Kuehling .prescreen_iv = vega10_ih_prescreen_iv, 427282aae55SKen Wang .decode_iv = vega10_ih_decode_iv, 428282aae55SKen Wang .set_rptr = vega10_ih_set_rptr 429282aae55SKen Wang }; 430282aae55SKen Wang 431282aae55SKen Wang static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 432282aae55SKen Wang { 433282aae55SKen Wang if (adev->irq.ih_funcs == NULL) 434282aae55SKen Wang adev->irq.ih_funcs = &vega10_ih_funcs; 435282aae55SKen Wang } 436282aae55SKen Wang 437282aae55SKen Wang const struct amdgpu_ip_block_version vega10_ih_ip_block = 438282aae55SKen Wang { 439282aae55SKen Wang .type = AMD_IP_BLOCK_TYPE_IH, 440282aae55SKen Wang .major = 4, 441282aae55SKen Wang .minor = 0, 442282aae55SKen Wang .rev = 0, 443282aae55SKen Wang .funcs = &vega10_ih_ip_funcs, 444282aae55SKen Wang }; 445