1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drm_drv.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_vcn.h" 29 #include "amdgpu_pm.h" 30 #include "soc15.h" 31 #include "soc15d.h" 32 #include "soc15_hw_ip.h" 33 #include "vcn_v2_0.h" 34 35 #include "vcn/vcn_4_0_3_offset.h" 36 #include "vcn/vcn_4_0_3_sh_mask.h" 37 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 38 39 #define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL 40 #define mmUVD_DPG_LMA_CTL_BASE_IDX regUVD_DPG_LMA_CTL_BASE_IDX 41 #define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA 42 #define mmUVD_DPG_LMA_DATA_BASE_IDX regUVD_DPG_LMA_DATA_BASE_IDX 43 44 #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00 45 #define VCN1_VID_SOC_ADDRESS_3_0 0x48300 46 47 static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev); 48 static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev); 49 static int vcn_v4_0_3_set_powergating_state(void *handle, 50 enum amd_powergating_state state); 51 static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_device *adev, 52 int inst_idx, struct dpg_pause_state *new_state); 53 static void vcn_v4_0_3_unified_ring_set_wptr(struct amdgpu_ring *ring); 54 static void vcn_v4_0_3_set_ras_funcs(struct amdgpu_device *adev); 55 static void vcn_v4_0_3_enable_ras(struct amdgpu_device *adev, 56 int inst_idx, bool indirect); 57 /** 58 * vcn_v4_0_3_early_init - set function pointers 59 * 60 * @handle: amdgpu_device pointer 61 * 62 * Set ring and irq function pointers 63 */ 64 static int vcn_v4_0_3_early_init(void *handle) 65 { 66 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 67 68 /* re-use enc ring as unified ring */ 69 adev->vcn.num_enc_rings = 1; 70 71 vcn_v4_0_3_set_unified_ring_funcs(adev); 72 vcn_v4_0_3_set_irq_funcs(adev); 73 vcn_v4_0_3_set_ras_funcs(adev); 74 75 return amdgpu_vcn_early_init(adev); 76 } 77 78 /** 79 * vcn_v4_0_3_sw_init - sw init for VCN block 80 * 81 * @handle: amdgpu_device pointer 82 * 83 * Load firmware and sw initialization 84 */ 85 static int vcn_v4_0_3_sw_init(void *handle) 86 { 87 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 88 struct amdgpu_ring *ring; 89 int i, r, vcn_inst; 90 91 r = amdgpu_vcn_sw_init(adev); 92 if (r) 93 return r; 94 95 amdgpu_vcn_setup_ucode(adev); 96 97 r = amdgpu_vcn_resume(adev); 98 if (r) 99 return r; 100 101 /* VCN DEC TRAP */ 102 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 103 VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst->irq); 104 if (r) 105 return r; 106 107 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 108 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 109 110 vcn_inst = GET_INST(VCN, i); 111 112 ring = &adev->vcn.inst[i].ring_enc[0]; 113 ring->use_doorbell = true; 114 115 if (!amdgpu_sriov_vf(adev)) 116 ring->doorbell_index = 117 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 118 9 * vcn_inst; 119 else 120 ring->doorbell_index = 121 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 122 32 * vcn_inst; 123 124 ring->vm_hub = AMDGPU_MMHUB0(adev->vcn.inst[i].aid_id); 125 sprintf(ring->name, "vcn_unified_%d", adev->vcn.inst[i].aid_id); 126 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, 127 AMDGPU_RING_PRIO_DEFAULT, 128 &adev->vcn.inst[i].sched_score); 129 if (r) 130 return r; 131 132 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 133 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); 134 fw_shared->sq.is_enabled = true; 135 136 if (amdgpu_vcnfw_log) 137 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]); 138 } 139 140 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 141 adev->vcn.pause_dpg_mode = vcn_v4_0_3_pause_dpg_mode; 142 143 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) { 144 r = amdgpu_vcn_ras_sw_init(adev); 145 if (r) { 146 dev_err(adev->dev, "Failed to initialize vcn ras block!\n"); 147 return r; 148 } 149 } 150 151 return 0; 152 } 153 154 /** 155 * vcn_v4_0_3_sw_fini - sw fini for VCN block 156 * 157 * @handle: amdgpu_device pointer 158 * 159 * VCN suspend and free up sw allocation 160 */ 161 static int vcn_v4_0_3_sw_fini(void *handle) 162 { 163 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 164 int i, r, idx; 165 166 if (drm_dev_enter(&adev->ddev, &idx)) { 167 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 168 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 169 170 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 171 fw_shared->present_flag_0 = 0; 172 fw_shared->sq.is_enabled = cpu_to_le32(false); 173 } 174 drm_dev_exit(idx); 175 } 176 177 r = amdgpu_vcn_suspend(adev); 178 if (r) 179 return r; 180 181 r = amdgpu_vcn_sw_fini(adev); 182 183 return r; 184 } 185 186 /** 187 * vcn_v4_0_3_hw_init - start and test VCN block 188 * 189 * @handle: amdgpu_device pointer 190 * 191 * Initialize the hardware, boot up the VCPU and do some testing 192 */ 193 static int vcn_v4_0_3_hw_init(void *handle) 194 { 195 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 196 struct amdgpu_ring *ring; 197 int i, r, vcn_inst; 198 199 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 200 vcn_inst = GET_INST(VCN, i); 201 ring = &adev->vcn.inst[i].ring_enc[0]; 202 203 if (ring->use_doorbell) { 204 adev->nbio.funcs->vcn_doorbell_range( 205 adev, ring->use_doorbell, 206 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 207 9 * vcn_inst, 208 adev->vcn.inst[i].aid_id); 209 210 WREG32_SOC15( 211 VCN, GET_INST(VCN, ring->me), 212 regVCN_RB1_DB_CTRL, 213 ring->doorbell_index 214 << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 215 VCN_RB1_DB_CTRL__EN_MASK); 216 217 /* Read DB_CTRL to flush the write DB_CTRL command. */ 218 RREG32_SOC15( 219 VCN, GET_INST(VCN, ring->me), 220 regVCN_RB1_DB_CTRL); 221 } 222 223 r = amdgpu_ring_test_helper(ring); 224 if (r) 225 goto done; 226 } 227 228 done: 229 if (!r) 230 DRM_DEV_INFO(adev->dev, "VCN decode initialized successfully(under %s).\n", 231 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 232 233 return r; 234 } 235 236 /** 237 * vcn_v4_0_3_hw_fini - stop the hardware block 238 * 239 * @handle: amdgpu_device pointer 240 * 241 * Stop the VCN block, mark ring as not ready any more 242 */ 243 static int vcn_v4_0_3_hw_fini(void *handle) 244 { 245 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 246 247 cancel_delayed_work_sync(&adev->vcn.idle_work); 248 249 if (adev->vcn.cur_state != AMD_PG_STATE_GATE) 250 vcn_v4_0_3_set_powergating_state(adev, AMD_PG_STATE_GATE); 251 252 return 0; 253 } 254 255 /** 256 * vcn_v4_0_3_suspend - suspend VCN block 257 * 258 * @handle: amdgpu_device pointer 259 * 260 * HW fini and suspend VCN block 261 */ 262 static int vcn_v4_0_3_suspend(void *handle) 263 { 264 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 265 int r; 266 267 r = vcn_v4_0_3_hw_fini(adev); 268 if (r) 269 return r; 270 271 r = amdgpu_vcn_suspend(adev); 272 273 return r; 274 } 275 276 /** 277 * vcn_v4_0_3_resume - resume VCN block 278 * 279 * @handle: amdgpu_device pointer 280 * 281 * Resume firmware and hw init VCN block 282 */ 283 static int vcn_v4_0_3_resume(void *handle) 284 { 285 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 286 int r; 287 288 r = amdgpu_vcn_resume(adev); 289 if (r) 290 return r; 291 292 r = vcn_v4_0_3_hw_init(adev); 293 294 return r; 295 } 296 297 /** 298 * vcn_v4_0_3_mc_resume - memory controller programming 299 * 300 * @adev: amdgpu_device pointer 301 * @inst_idx: instance number 302 * 303 * Let the VCN memory controller know it's offsets 304 */ 305 static void vcn_v4_0_3_mc_resume(struct amdgpu_device *adev, int inst_idx) 306 { 307 uint32_t offset, size, vcn_inst; 308 const struct common_firmware_header *hdr; 309 310 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 311 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 312 313 vcn_inst = GET_INST(VCN, inst_idx); 314 /* cache window 0: fw */ 315 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 316 WREG32_SOC15( 317 VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 318 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx] 319 .tmr_mc_addr_lo)); 320 WREG32_SOC15( 321 VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 322 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx] 323 .tmr_mc_addr_hi)); 324 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0, 0); 325 offset = 0; 326 } else { 327 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 328 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr)); 329 WREG32_SOC15(VCN, vcn_inst, 330 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 331 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr)); 332 offset = size; 333 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0, 334 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 335 } 336 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE0, size); 337 338 /* cache window 1: stack */ 339 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 340 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset)); 341 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 342 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset)); 343 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET1, 0); 344 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE1, 345 AMDGPU_VCN_STACK_SIZE); 346 347 /* cache window 2: context */ 348 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 349 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 350 AMDGPU_VCN_STACK_SIZE)); 351 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 352 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 353 AMDGPU_VCN_STACK_SIZE)); 354 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET2, 0); 355 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE2, 356 AMDGPU_VCN_CONTEXT_SIZE); 357 358 /* non-cache window */ 359 WREG32_SOC15( 360 VCN, vcn_inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 361 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr)); 362 WREG32_SOC15( 363 VCN, vcn_inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 364 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr)); 365 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); 366 WREG32_SOC15( 367 VCN, vcn_inst, regUVD_VCPU_NONCACHE_SIZE0, 368 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 369 } 370 371 /** 372 * vcn_v4_0_3_mc_resume_dpg_mode - memory controller programming for dpg mode 373 * 374 * @adev: amdgpu_device pointer 375 * @inst_idx: instance number index 376 * @indirect: indirectly write sram 377 * 378 * Let the VCN memory controller know it's offsets with dpg mode 379 */ 380 static void vcn_v4_0_3_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 381 { 382 uint32_t offset, size; 383 const struct common_firmware_header *hdr; 384 385 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 386 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 387 388 /* cache window 0: fw */ 389 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 390 if (!indirect) { 391 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 392 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 393 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + 394 inst_idx].tmr_mc_addr_lo), 0, indirect); 395 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 396 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 397 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + 398 inst_idx].tmr_mc_addr_hi), 0, indirect); 399 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 400 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 401 } else { 402 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 403 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 404 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 405 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 406 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 407 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 408 } 409 offset = 0; 410 } else { 411 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 412 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 413 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 414 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 415 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 416 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 417 offset = size; 418 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 419 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 420 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 421 } 422 423 if (!indirect) 424 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 425 VCN, 0, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 426 else 427 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 428 VCN, 0, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 429 430 /* cache window 1: stack */ 431 if (!indirect) { 432 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 433 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 434 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 435 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 436 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 437 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 438 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 439 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 440 } else { 441 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 442 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 443 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 444 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 445 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 446 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 447 } 448 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 449 VCN, 0, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 450 451 /* cache window 2: context */ 452 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 453 VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 454 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 455 AMDGPU_VCN_STACK_SIZE), 0, indirect); 456 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 457 VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 458 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 459 AMDGPU_VCN_STACK_SIZE), 0, indirect); 460 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 461 VCN, 0, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 462 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 463 VCN, 0, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 464 465 /* non-cache window */ 466 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 467 VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 468 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 469 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 470 VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 471 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 472 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 473 VCN, 0, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 474 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 475 VCN, 0, regUVD_VCPU_NONCACHE_SIZE0), 476 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); 477 478 /* VCN global tiling registers */ 479 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 480 VCN, 0, regUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 481 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 482 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 483 } 484 485 /** 486 * vcn_v4_0_3_disable_clock_gating - disable VCN clock gating 487 * 488 * @adev: amdgpu_device pointer 489 * @inst_idx: instance number 490 * 491 * Disable clock gating for VCN block 492 */ 493 static void vcn_v4_0_3_disable_clock_gating(struct amdgpu_device *adev, int inst_idx) 494 { 495 uint32_t data; 496 int vcn_inst; 497 498 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 499 return; 500 501 vcn_inst = GET_INST(VCN, inst_idx); 502 503 /* VCN disable CGC */ 504 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); 505 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 506 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 507 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 508 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); 509 510 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_GATE); 511 data &= ~(UVD_CGC_GATE__SYS_MASK 512 | UVD_CGC_GATE__MPEG2_MASK 513 | UVD_CGC_GATE__REGS_MASK 514 | UVD_CGC_GATE__RBC_MASK 515 | UVD_CGC_GATE__LMI_MC_MASK 516 | UVD_CGC_GATE__LMI_UMC_MASK 517 | UVD_CGC_GATE__MPC_MASK 518 | UVD_CGC_GATE__LBSI_MASK 519 | UVD_CGC_GATE__LRBBM_MASK 520 | UVD_CGC_GATE__WCB_MASK 521 | UVD_CGC_GATE__VCPU_MASK 522 | UVD_CGC_GATE__MMSCH_MASK); 523 524 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_GATE, data); 525 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF); 526 527 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); 528 data &= ~(UVD_CGC_CTRL__SYS_MODE_MASK 529 | UVD_CGC_CTRL__MPEG2_MODE_MASK 530 | UVD_CGC_CTRL__REGS_MODE_MASK 531 | UVD_CGC_CTRL__RBC_MODE_MASK 532 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 533 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 534 | UVD_CGC_CTRL__MPC_MODE_MASK 535 | UVD_CGC_CTRL__LBSI_MODE_MASK 536 | UVD_CGC_CTRL__LRBBM_MODE_MASK 537 | UVD_CGC_CTRL__WCB_MODE_MASK 538 | UVD_CGC_CTRL__VCPU_MODE_MASK 539 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 540 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); 541 542 data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_GATE); 543 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 544 | UVD_SUVD_CGC_GATE__SIT_MASK 545 | UVD_SUVD_CGC_GATE__SMP_MASK 546 | UVD_SUVD_CGC_GATE__SCM_MASK 547 | UVD_SUVD_CGC_GATE__SDB_MASK 548 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 549 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 550 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 551 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 552 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 553 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 554 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 555 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 556 | UVD_SUVD_CGC_GATE__ENT_MASK 557 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 558 | UVD_SUVD_CGC_GATE__SITE_MASK 559 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 560 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 561 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 562 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 563 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 564 WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_GATE, data); 565 566 data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL); 567 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 568 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 569 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 570 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 571 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 572 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 573 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 574 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 575 WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL, data); 576 } 577 578 /** 579 * vcn_v4_0_3_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode 580 * 581 * @adev: amdgpu_device pointer 582 * @sram_sel: sram select 583 * @inst_idx: instance number index 584 * @indirect: indirectly write sram 585 * 586 * Disable clock gating for VCN block with dpg mode 587 */ 588 static void vcn_v4_0_3_disable_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel, 589 int inst_idx, uint8_t indirect) 590 { 591 uint32_t reg_data = 0; 592 593 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 594 return; 595 596 /* enable sw clock gating control */ 597 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 598 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 599 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 600 reg_data &= ~(UVD_CGC_CTRL__SYS_MODE_MASK | 601 UVD_CGC_CTRL__MPEG2_MODE_MASK | 602 UVD_CGC_CTRL__REGS_MODE_MASK | 603 UVD_CGC_CTRL__RBC_MODE_MASK | 604 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 605 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 606 UVD_CGC_CTRL__IDCT_MODE_MASK | 607 UVD_CGC_CTRL__MPRD_MODE_MASK | 608 UVD_CGC_CTRL__MPC_MODE_MASK | 609 UVD_CGC_CTRL__LBSI_MODE_MASK | 610 UVD_CGC_CTRL__LRBBM_MODE_MASK | 611 UVD_CGC_CTRL__WCB_MODE_MASK | 612 UVD_CGC_CTRL__VCPU_MODE_MASK); 613 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 614 VCN, 0, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); 615 616 /* turn off clock gating */ 617 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 618 VCN, 0, regUVD_CGC_GATE), 0, sram_sel, indirect); 619 620 /* turn on SUVD clock gating */ 621 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 622 VCN, 0, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 623 624 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 625 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 626 VCN, 0, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 627 } 628 629 /** 630 * vcn_v4_0_3_enable_clock_gating - enable VCN clock gating 631 * 632 * @adev: amdgpu_device pointer 633 * @inst_idx: instance number 634 * 635 * Enable clock gating for VCN block 636 */ 637 static void vcn_v4_0_3_enable_clock_gating(struct amdgpu_device *adev, int inst_idx) 638 { 639 uint32_t data; 640 int vcn_inst; 641 642 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 643 return; 644 645 vcn_inst = GET_INST(VCN, inst_idx); 646 647 /* enable VCN CGC */ 648 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); 649 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 650 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 651 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 652 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); 653 654 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); 655 data |= (UVD_CGC_CTRL__SYS_MODE_MASK 656 | UVD_CGC_CTRL__MPEG2_MODE_MASK 657 | UVD_CGC_CTRL__REGS_MODE_MASK 658 | UVD_CGC_CTRL__RBC_MODE_MASK 659 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 660 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 661 | UVD_CGC_CTRL__MPC_MODE_MASK 662 | UVD_CGC_CTRL__LBSI_MODE_MASK 663 | UVD_CGC_CTRL__LRBBM_MODE_MASK 664 | UVD_CGC_CTRL__WCB_MODE_MASK 665 | UVD_CGC_CTRL__VCPU_MODE_MASK); 666 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); 667 668 data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL); 669 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 670 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 671 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 672 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 673 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 674 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 675 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 676 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 677 WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL, data); 678 } 679 680 /** 681 * vcn_v4_0_3_start_dpg_mode - VCN start with dpg mode 682 * 683 * @adev: amdgpu_device pointer 684 * @inst_idx: instance number index 685 * @indirect: indirectly write sram 686 * 687 * Start VCN block with dpg mode 688 */ 689 static int vcn_v4_0_3_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 690 { 691 volatile struct amdgpu_vcn4_fw_shared *fw_shared = 692 adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 693 struct amdgpu_ring *ring; 694 int vcn_inst; 695 uint32_t tmp; 696 697 vcn_inst = GET_INST(VCN, inst_idx); 698 /* disable register anti-hang mechanism */ 699 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 1, 700 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 701 /* enable dynamic power gating mode */ 702 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS); 703 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 704 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 705 WREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS, tmp); 706 707 if (indirect) { 708 DRM_DEV_DEBUG(adev->dev, "VCN %d start: on AID %d", 709 inst_idx, adev->vcn.inst[inst_idx].aid_id); 710 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = 711 (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 712 /* Use dummy register 0xDEADBEEF passing AID selection to PSP FW */ 713 WREG32_SOC15_DPG_MODE(inst_idx, 0xDEADBEEF, 714 adev->vcn.inst[inst_idx].aid_id, 0, true); 715 } 716 717 /* enable clock gating */ 718 vcn_v4_0_3_disable_clock_gating_dpg_mode(adev, 0, inst_idx, indirect); 719 720 /* enable VCPU clock */ 721 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 722 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 723 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK; 724 725 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 726 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect); 727 728 /* disable master interrupt */ 729 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 730 VCN, 0, regUVD_MASTINT_EN), 0, 0, indirect); 731 732 /* setup regUVD_LMI_CTRL */ 733 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 734 UVD_LMI_CTRL__REQ_MODE_MASK | 735 UVD_LMI_CTRL__CRC_RESET_MASK | 736 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 737 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 738 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 739 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 740 0x00100000L); 741 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 742 VCN, 0, regUVD_LMI_CTRL), tmp, 0, indirect); 743 744 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 745 VCN, 0, regUVD_MPC_CNTL), 746 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 747 748 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 749 VCN, 0, regUVD_MPC_SET_MUXA0), 750 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 751 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 752 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 753 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 754 755 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 756 VCN, 0, regUVD_MPC_SET_MUXB0), 757 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 758 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 759 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 760 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 761 762 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 763 VCN, 0, regUVD_MPC_SET_MUX), 764 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 765 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 766 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 767 768 vcn_v4_0_3_mc_resume_dpg_mode(adev, inst_idx, indirect); 769 770 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 771 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 772 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 773 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect); 774 775 /* enable LMI MC and UMC channels */ 776 tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT; 777 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 778 VCN, 0, regUVD_LMI_CTRL2), tmp, 0, indirect); 779 780 vcn_v4_0_3_enable_ras(adev, inst_idx, indirect); 781 782 /* enable master interrupt */ 783 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 784 VCN, 0, regUVD_MASTINT_EN), 785 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 786 787 if (indirect) 788 amdgpu_vcn_psp_update_sram(adev, inst_idx, AMDGPU_UCODE_ID_VCN0_RAM); 789 790 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 791 792 /* program the RB_BASE for ring buffer */ 793 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, 794 lower_32_bits(ring->gpu_addr)); 795 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, 796 upper_32_bits(ring->gpu_addr)); 797 798 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, 799 ring->ring_size / sizeof(uint32_t)); 800 801 /* resetting ring, fw should not check RB ring */ 802 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 803 tmp &= ~(VCN_RB_ENABLE__RB_EN_MASK); 804 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 805 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 806 807 /* Initialize the ring buffer's read and write pointers */ 808 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0); 809 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0); 810 ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 811 812 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 813 tmp |= VCN_RB_ENABLE__RB_EN_MASK; 814 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 815 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 816 817 /*resetting done, fw can check RB ring */ 818 fw_shared->sq.queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 819 820 return 0; 821 } 822 823 /** 824 * vcn_v4_0_3_start - VCN start 825 * 826 * @adev: amdgpu_device pointer 827 * 828 * Start VCN block 829 */ 830 static int vcn_v4_0_3_start(struct amdgpu_device *adev) 831 { 832 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 833 struct amdgpu_ring *ring; 834 int i, j, k, r, vcn_inst; 835 uint32_t tmp; 836 837 if (adev->pm.dpm_enabled) 838 amdgpu_dpm_enable_uvd(adev, true); 839 840 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 841 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 842 r = vcn_v4_0_3_start_dpg_mode(adev, i, adev->vcn.indirect_sram); 843 continue; 844 } 845 846 vcn_inst = GET_INST(VCN, i); 847 /* set VCN status busy */ 848 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) | 849 UVD_STATUS__UVD_BUSY; 850 WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, tmp); 851 852 /*SW clock gating */ 853 vcn_v4_0_3_disable_clock_gating(adev, i); 854 855 /* enable VCPU clock */ 856 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 857 UVD_VCPU_CNTL__CLK_EN_MASK, 858 ~UVD_VCPU_CNTL__CLK_EN_MASK); 859 860 /* disable master interrupt */ 861 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0, 862 ~UVD_MASTINT_EN__VCPU_EN_MASK); 863 864 /* enable LMI MC and UMC channels */ 865 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_LMI_CTRL2), 0, 866 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 867 868 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 869 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 870 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 871 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 872 873 /* setup regUVD_LMI_CTRL */ 874 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL); 875 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL, 876 tmp | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 877 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 878 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 879 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 880 881 /* setup regUVD_MPC_CNTL */ 882 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL); 883 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 884 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 885 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL, tmp); 886 887 /* setup UVD_MPC_SET_MUXA0 */ 888 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXA0, 889 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 890 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 891 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 892 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 893 894 /* setup UVD_MPC_SET_MUXB0 */ 895 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXB0, 896 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 897 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 898 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 899 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 900 901 /* setup UVD_MPC_SET_MUX */ 902 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUX, 903 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 904 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 905 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 906 907 vcn_v4_0_3_mc_resume(adev, i); 908 909 /* VCN global tiling registers */ 910 WREG32_SOC15(VCN, vcn_inst, regUVD_GFX8_ADDR_CONFIG, 911 adev->gfx.config.gb_addr_config); 912 WREG32_SOC15(VCN, vcn_inst, regUVD_GFX10_ADDR_CONFIG, 913 adev->gfx.config.gb_addr_config); 914 915 /* unblock VCPU register access */ 916 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 0, 917 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 918 919 /* release VCPU reset to boot */ 920 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, 921 ~UVD_VCPU_CNTL__BLK_RST_MASK); 922 923 for (j = 0; j < 10; ++j) { 924 uint32_t status; 925 926 for (k = 0; k < 100; ++k) { 927 status = RREG32_SOC15(VCN, vcn_inst, 928 regUVD_STATUS); 929 if (status & 2) 930 break; 931 mdelay(10); 932 } 933 r = 0; 934 if (status & 2) 935 break; 936 937 DRM_DEV_ERROR(adev->dev, 938 "VCN decode not responding, trying to reset the VCPU!!!\n"); 939 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, 940 regUVD_VCPU_CNTL), 941 UVD_VCPU_CNTL__BLK_RST_MASK, 942 ~UVD_VCPU_CNTL__BLK_RST_MASK); 943 mdelay(10); 944 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, 945 regUVD_VCPU_CNTL), 946 0, ~UVD_VCPU_CNTL__BLK_RST_MASK); 947 948 mdelay(10); 949 r = -1; 950 } 951 952 if (r) { 953 DRM_DEV_ERROR(adev->dev, "VCN decode not responding, giving up!!!\n"); 954 return r; 955 } 956 957 /* enable master interrupt */ 958 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 959 UVD_MASTINT_EN__VCPU_EN_MASK, 960 ~UVD_MASTINT_EN__VCPU_EN_MASK); 961 962 /* clear the busy bit of VCN_STATUS */ 963 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0, 964 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 965 966 ring = &adev->vcn.inst[i].ring_enc[0]; 967 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 968 969 /* program the RB_BASE for ring buffer */ 970 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, 971 lower_32_bits(ring->gpu_addr)); 972 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, 973 upper_32_bits(ring->gpu_addr)); 974 975 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, 976 ring->ring_size / sizeof(uint32_t)); 977 978 /* resetting ring, fw should not check RB ring */ 979 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 980 tmp &= ~(VCN_RB_ENABLE__RB_EN_MASK); 981 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 982 983 /* Initialize the ring buffer's read and write pointers */ 984 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0); 985 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0); 986 987 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 988 tmp |= VCN_RB_ENABLE__RB_EN_MASK; 989 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 990 991 ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 992 fw_shared->sq.queue_mode &= 993 cpu_to_le32(~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF)); 994 995 } 996 return 0; 997 } 998 999 /** 1000 * vcn_v4_0_3_stop_dpg_mode - VCN stop with dpg mode 1001 * 1002 * @adev: amdgpu_device pointer 1003 * @inst_idx: instance number index 1004 * 1005 * Stop VCN block with dpg mode 1006 */ 1007 static int vcn_v4_0_3_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) 1008 { 1009 uint32_t tmp; 1010 int vcn_inst; 1011 1012 vcn_inst = GET_INST(VCN, inst_idx); 1013 1014 /* Wait for power status to be 1 */ 1015 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1, 1016 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1017 1018 /* wait for read ptr to be equal to write ptr */ 1019 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 1020 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1021 1022 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1, 1023 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1024 1025 /* disable dynamic power gating mode */ 1026 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 0, 1027 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1028 return 0; 1029 } 1030 1031 /** 1032 * vcn_v4_0_3_stop - VCN stop 1033 * 1034 * @adev: amdgpu_device pointer 1035 * 1036 * Stop VCN block 1037 */ 1038 static int vcn_v4_0_3_stop(struct amdgpu_device *adev) 1039 { 1040 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1041 int i, r = 0, vcn_inst; 1042 uint32_t tmp; 1043 1044 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1045 vcn_inst = GET_INST(VCN, i); 1046 1047 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1048 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; 1049 1050 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1051 vcn_v4_0_3_stop_dpg_mode(adev, i); 1052 continue; 1053 } 1054 1055 /* wait for vcn idle */ 1056 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS, 1057 UVD_STATUS__IDLE, 0x7); 1058 if (r) 1059 goto Done; 1060 1061 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1062 UVD_LMI_STATUS__READ_CLEAN_MASK | 1063 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1064 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1065 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, 1066 tmp); 1067 if (r) 1068 goto Done; 1069 1070 /* stall UMC channel */ 1071 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2); 1072 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1073 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2, tmp); 1074 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1075 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1076 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, 1077 tmp); 1078 if (r) 1079 goto Done; 1080 1081 /* Unblock VCPU Register access */ 1082 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 1083 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1084 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1085 1086 /* release VCPU reset to boot */ 1087 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 1088 UVD_VCPU_CNTL__BLK_RST_MASK, 1089 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1090 1091 /* disable VCPU clock */ 1092 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, 1093 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1094 1095 /* reset LMI UMC/LMI/VCPU */ 1096 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 1097 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1098 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 1099 1100 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 1101 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1102 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 1103 1104 /* clear VCN status */ 1105 WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, 0); 1106 1107 /* apply HW clock gating */ 1108 vcn_v4_0_3_enable_clock_gating(adev, i); 1109 } 1110 Done: 1111 if (adev->pm.dpm_enabled) 1112 amdgpu_dpm_enable_uvd(adev, false); 1113 1114 return 0; 1115 } 1116 1117 /** 1118 * vcn_v4_0_3_pause_dpg_mode - VCN pause with dpg mode 1119 * 1120 * @adev: amdgpu_device pointer 1121 * @inst_idx: instance number index 1122 * @new_state: pause state 1123 * 1124 * Pause dpg mode for VCN block 1125 */ 1126 static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx, 1127 struct dpg_pause_state *new_state) 1128 { 1129 1130 return 0; 1131 } 1132 1133 /** 1134 * vcn_v4_0_3_unified_ring_get_rptr - get unified read pointer 1135 * 1136 * @ring: amdgpu_ring pointer 1137 * 1138 * Returns the current hardware unified read pointer 1139 */ 1140 static uint64_t vcn_v4_0_3_unified_ring_get_rptr(struct amdgpu_ring *ring) 1141 { 1142 struct amdgpu_device *adev = ring->adev; 1143 1144 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1145 DRM_ERROR("wrong ring id is identified in %s", __func__); 1146 1147 return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_RPTR); 1148 } 1149 1150 /** 1151 * vcn_v4_0_3_unified_ring_get_wptr - get unified write pointer 1152 * 1153 * @ring: amdgpu_ring pointer 1154 * 1155 * Returns the current hardware unified write pointer 1156 */ 1157 static uint64_t vcn_v4_0_3_unified_ring_get_wptr(struct amdgpu_ring *ring) 1158 { 1159 struct amdgpu_device *adev = ring->adev; 1160 1161 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1162 DRM_ERROR("wrong ring id is identified in %s", __func__); 1163 1164 if (ring->use_doorbell) 1165 return *ring->wptr_cpu_addr; 1166 else 1167 return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), 1168 regUVD_RB_WPTR); 1169 } 1170 1171 /** 1172 * vcn_v4_0_3_unified_ring_set_wptr - set enc write pointer 1173 * 1174 * @ring: amdgpu_ring pointer 1175 * 1176 * Commits the enc write pointer to the hardware 1177 */ 1178 static void vcn_v4_0_3_unified_ring_set_wptr(struct amdgpu_ring *ring) 1179 { 1180 struct amdgpu_device *adev = ring->adev; 1181 1182 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1183 DRM_ERROR("wrong ring id is identified in %s", __func__); 1184 1185 if (ring->use_doorbell) { 1186 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1187 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1188 } else { 1189 WREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR, 1190 lower_32_bits(ring->wptr)); 1191 } 1192 } 1193 1194 static const struct amdgpu_ring_funcs vcn_v4_0_3_unified_ring_vm_funcs = { 1195 .type = AMDGPU_RING_TYPE_VCN_ENC, 1196 .align_mask = 0x3f, 1197 .nop = VCN_ENC_CMD_NO_OP, 1198 .get_rptr = vcn_v4_0_3_unified_ring_get_rptr, 1199 .get_wptr = vcn_v4_0_3_unified_ring_get_wptr, 1200 .set_wptr = vcn_v4_0_3_unified_ring_set_wptr, 1201 .emit_frame_size = 1202 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1203 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1204 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1205 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1206 1, /* vcn_v2_0_enc_ring_insert_end */ 1207 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1208 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1209 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1210 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 1211 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1212 .test_ib = amdgpu_vcn_unified_ring_test_ib, 1213 .insert_nop = amdgpu_ring_insert_nop, 1214 .insert_end = vcn_v2_0_enc_ring_insert_end, 1215 .pad_ib = amdgpu_ring_generic_pad_ib, 1216 .begin_use = amdgpu_vcn_ring_begin_use, 1217 .end_use = amdgpu_vcn_ring_end_use, 1218 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 1219 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 1220 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1221 }; 1222 1223 /** 1224 * vcn_v4_0_3_set_unified_ring_funcs - set unified ring functions 1225 * 1226 * @adev: amdgpu_device pointer 1227 * 1228 * Set unified ring functions 1229 */ 1230 static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev) 1231 { 1232 int i, vcn_inst; 1233 1234 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1235 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_3_unified_ring_vm_funcs; 1236 adev->vcn.inst[i].ring_enc[0].me = i; 1237 vcn_inst = GET_INST(VCN, i); 1238 adev->vcn.inst[i].aid_id = 1239 vcn_inst / adev->vcn.num_inst_per_aid; 1240 } 1241 DRM_DEV_INFO(adev->dev, "VCN decode is enabled in VM mode\n"); 1242 } 1243 1244 /** 1245 * vcn_v4_0_3_is_idle - check VCN block is idle 1246 * 1247 * @handle: amdgpu_device pointer 1248 * 1249 * Check whether VCN block is idle 1250 */ 1251 static bool vcn_v4_0_3_is_idle(void *handle) 1252 { 1253 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1254 int i, ret = 1; 1255 1256 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1257 ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) == 1258 UVD_STATUS__IDLE); 1259 } 1260 1261 return ret; 1262 } 1263 1264 /** 1265 * vcn_v4_0_3_wait_for_idle - wait for VCN block idle 1266 * 1267 * @handle: amdgpu_device pointer 1268 * 1269 * Wait for VCN block idle 1270 */ 1271 static int vcn_v4_0_3_wait_for_idle(void *handle) 1272 { 1273 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1274 int i, ret = 0; 1275 1276 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1277 ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS, 1278 UVD_STATUS__IDLE, UVD_STATUS__IDLE); 1279 if (ret) 1280 return ret; 1281 } 1282 1283 return ret; 1284 } 1285 1286 /* vcn_v4_0_3_set_clockgating_state - set VCN block clockgating state 1287 * 1288 * @handle: amdgpu_device pointer 1289 * @state: clock gating state 1290 * 1291 * Set VCN block clockgating state 1292 */ 1293 static int vcn_v4_0_3_set_clockgating_state(void *handle, 1294 enum amd_clockgating_state state) 1295 { 1296 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1297 bool enable = state == AMD_CG_STATE_GATE; 1298 int i; 1299 1300 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1301 if (enable) { 1302 if (RREG32_SOC15(VCN, GET_INST(VCN, i), 1303 regUVD_STATUS) != UVD_STATUS__IDLE) 1304 return -EBUSY; 1305 vcn_v4_0_3_enable_clock_gating(adev, i); 1306 } else { 1307 vcn_v4_0_3_disable_clock_gating(adev, i); 1308 } 1309 } 1310 return 0; 1311 } 1312 1313 /** 1314 * vcn_v4_0_3_set_powergating_state - set VCN block powergating state 1315 * 1316 * @handle: amdgpu_device pointer 1317 * @state: power gating state 1318 * 1319 * Set VCN block powergating state 1320 */ 1321 static int vcn_v4_0_3_set_powergating_state(void *handle, 1322 enum amd_powergating_state state) 1323 { 1324 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1325 int ret; 1326 1327 if (state == adev->vcn.cur_state) 1328 return 0; 1329 1330 if (state == AMD_PG_STATE_GATE) 1331 ret = vcn_v4_0_3_stop(adev); 1332 else 1333 ret = vcn_v4_0_3_start(adev); 1334 1335 if (!ret) 1336 adev->vcn.cur_state = state; 1337 1338 return ret; 1339 } 1340 1341 /** 1342 * vcn_v4_0_3_set_interrupt_state - set VCN block interrupt state 1343 * 1344 * @adev: amdgpu_device pointer 1345 * @source: interrupt sources 1346 * @type: interrupt types 1347 * @state: interrupt states 1348 * 1349 * Set VCN block interrupt state 1350 */ 1351 static int vcn_v4_0_3_set_interrupt_state(struct amdgpu_device *adev, 1352 struct amdgpu_irq_src *source, 1353 unsigned int type, 1354 enum amdgpu_interrupt_state state) 1355 { 1356 return 0; 1357 } 1358 1359 /** 1360 * vcn_v4_0_3_process_interrupt - process VCN block interrupt 1361 * 1362 * @adev: amdgpu_device pointer 1363 * @source: interrupt sources 1364 * @entry: interrupt entry from clients and sources 1365 * 1366 * Process VCN block interrupt 1367 */ 1368 static int vcn_v4_0_3_process_interrupt(struct amdgpu_device *adev, 1369 struct amdgpu_irq_src *source, 1370 struct amdgpu_iv_entry *entry) 1371 { 1372 uint32_t i, inst; 1373 1374 i = node_id_to_phys_map[entry->node_id]; 1375 1376 DRM_DEV_DEBUG(adev->dev, "IH: VCN TRAP\n"); 1377 1378 for (inst = 0; inst < adev->vcn.num_vcn_inst; ++inst) 1379 if (adev->vcn.inst[inst].aid_id == i) 1380 break; 1381 1382 if (inst >= adev->vcn.num_vcn_inst) { 1383 dev_WARN_ONCE(adev->dev, 1, 1384 "Interrupt received for unknown VCN instance %d", 1385 entry->node_id); 1386 return 0; 1387 } 1388 1389 switch (entry->src_id) { 1390 case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1391 amdgpu_fence_process(&adev->vcn.inst[inst].ring_enc[0]); 1392 break; 1393 default: 1394 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", 1395 entry->src_id, entry->src_data[0]); 1396 break; 1397 } 1398 1399 return 0; 1400 } 1401 1402 static const struct amdgpu_irq_src_funcs vcn_v4_0_3_irq_funcs = { 1403 .set = vcn_v4_0_3_set_interrupt_state, 1404 .process = vcn_v4_0_3_process_interrupt, 1405 }; 1406 1407 /** 1408 * vcn_v4_0_3_set_irq_funcs - set VCN block interrupt irq functions 1409 * 1410 * @adev: amdgpu_device pointer 1411 * 1412 * Set VCN block interrupt irq functions 1413 */ 1414 static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev) 1415 { 1416 int i; 1417 1418 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1419 adev->vcn.inst->irq.num_types++; 1420 } 1421 adev->vcn.inst->irq.funcs = &vcn_v4_0_3_irq_funcs; 1422 } 1423 1424 static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = { 1425 .name = "vcn_v4_0_3", 1426 .early_init = vcn_v4_0_3_early_init, 1427 .late_init = NULL, 1428 .sw_init = vcn_v4_0_3_sw_init, 1429 .sw_fini = vcn_v4_0_3_sw_fini, 1430 .hw_init = vcn_v4_0_3_hw_init, 1431 .hw_fini = vcn_v4_0_3_hw_fini, 1432 .suspend = vcn_v4_0_3_suspend, 1433 .resume = vcn_v4_0_3_resume, 1434 .is_idle = vcn_v4_0_3_is_idle, 1435 .wait_for_idle = vcn_v4_0_3_wait_for_idle, 1436 .check_soft_reset = NULL, 1437 .pre_soft_reset = NULL, 1438 .soft_reset = NULL, 1439 .post_soft_reset = NULL, 1440 .set_clockgating_state = vcn_v4_0_3_set_clockgating_state, 1441 .set_powergating_state = vcn_v4_0_3_set_powergating_state, 1442 }; 1443 1444 const struct amdgpu_ip_block_version vcn_v4_0_3_ip_block = { 1445 .type = AMD_IP_BLOCK_TYPE_VCN, 1446 .major = 4, 1447 .minor = 0, 1448 .rev = 3, 1449 .funcs = &vcn_v4_0_3_ip_funcs, 1450 }; 1451 1452 static const struct amdgpu_ras_err_status_reg_entry vcn_v4_0_3_ue_reg_list[] = { 1453 {AMDGPU_RAS_REG_ENTRY(VCN, 0, regVCN_UE_ERR_STATUS_LO_VIDD, regVCN_UE_ERR_STATUS_HI_VIDD), 1454 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "VIDD"}, 1455 {AMDGPU_RAS_REG_ENTRY(VCN, 0, regVCN_UE_ERR_STATUS_LO_VIDV, regVCN_UE_ERR_STATUS_HI_VIDV), 1456 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "VIDV"}, 1457 }; 1458 1459 static void vcn_v4_0_3_inst_query_ras_error_count(struct amdgpu_device *adev, 1460 uint32_t vcn_inst, 1461 void *ras_err_status) 1462 { 1463 struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status; 1464 1465 /* vcn v4_0_3 only support query uncorrectable errors */ 1466 amdgpu_ras_inst_query_ras_error_count(adev, 1467 vcn_v4_0_3_ue_reg_list, 1468 ARRAY_SIZE(vcn_v4_0_3_ue_reg_list), 1469 NULL, 0, GET_INST(VCN, vcn_inst), 1470 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 1471 &err_data->ue_count); 1472 } 1473 1474 static void vcn_v4_0_3_query_ras_error_count(struct amdgpu_device *adev, 1475 void *ras_err_status) 1476 { 1477 uint32_t i; 1478 1479 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) { 1480 dev_warn(adev->dev, "VCN RAS is not supported\n"); 1481 return; 1482 } 1483 1484 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1485 vcn_v4_0_3_inst_query_ras_error_count(adev, i, ras_err_status); 1486 } 1487 1488 static void vcn_v4_0_3_inst_reset_ras_error_count(struct amdgpu_device *adev, 1489 uint32_t vcn_inst) 1490 { 1491 amdgpu_ras_inst_reset_ras_error_count(adev, 1492 vcn_v4_0_3_ue_reg_list, 1493 ARRAY_SIZE(vcn_v4_0_3_ue_reg_list), 1494 GET_INST(VCN, vcn_inst)); 1495 } 1496 1497 static void vcn_v4_0_3_reset_ras_error_count(struct amdgpu_device *adev) 1498 { 1499 uint32_t i; 1500 1501 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) { 1502 dev_warn(adev->dev, "VCN RAS is not supported\n"); 1503 return; 1504 } 1505 1506 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1507 vcn_v4_0_3_inst_reset_ras_error_count(adev, i); 1508 } 1509 1510 static const struct amdgpu_ras_block_hw_ops vcn_v4_0_3_ras_hw_ops = { 1511 .query_ras_error_count = vcn_v4_0_3_query_ras_error_count, 1512 .reset_ras_error_count = vcn_v4_0_3_reset_ras_error_count, 1513 }; 1514 1515 static struct amdgpu_vcn_ras vcn_v4_0_3_ras = { 1516 .ras_block = { 1517 .hw_ops = &vcn_v4_0_3_ras_hw_ops, 1518 }, 1519 }; 1520 1521 static void vcn_v4_0_3_set_ras_funcs(struct amdgpu_device *adev) 1522 { 1523 adev->vcn.ras = &vcn_v4_0_3_ras; 1524 } 1525 1526 static void vcn_v4_0_3_enable_ras(struct amdgpu_device *adev, 1527 int inst_idx, bool indirect) 1528 { 1529 uint32_t tmp; 1530 1531 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) 1532 return; 1533 1534 tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK | 1535 VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK | 1536 VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK | 1537 VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK; 1538 WREG32_SOC15_DPG_MODE(inst_idx, 1539 SOC15_DPG_MODE_OFFSET(VCN, 0, regVCN_RAS_CNTL), 1540 tmp, 0, indirect); 1541 1542 tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK; 1543 WREG32_SOC15_DPG_MODE(inst_idx, 1544 SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_SYS_INT_EN), 1545 tmp, 0, indirect); 1546 } 1547