1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_vcn.h" 27 #include "amdgpu_pm.h" 28 #include "amdgpu_cs.h" 29 #include "soc15.h" 30 #include "soc15d.h" 31 #include "soc15_hw_ip.h" 32 #include "vcn_v2_0.h" 33 34 #include "vcn/vcn_4_0_0_offset.h" 35 #include "vcn/vcn_4_0_0_sh_mask.h" 36 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 37 38 #include <drm/drm_drv.h> 39 40 #define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL 41 #define mmUVD_DPG_LMA_CTL_BASE_IDX regUVD_DPG_LMA_CTL_BASE_IDX 42 #define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA 43 #define mmUVD_DPG_LMA_DATA_BASE_IDX regUVD_DPG_LMA_DATA_BASE_IDX 44 45 #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00 46 #define VCN1_VID_SOC_ADDRESS_3_0 0x48300 47 48 #define RDECODE_MSG_CREATE 0x00000000 49 #define RDECODE_MESSAGE_CREATE 0x00000001 50 51 static int amdgpu_ih_clientid_vcns[] = { 52 SOC15_IH_CLIENTID_VCN, 53 SOC15_IH_CLIENTID_VCN1 54 }; 55 56 static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev); 57 static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev); 58 static int vcn_v4_0_set_powergating_state(void *handle, 59 enum amd_powergating_state state); 60 static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev, 61 int inst_idx, struct dpg_pause_state *new_state); 62 63 /** 64 * vcn_v4_0_early_init - set function pointers 65 * 66 * @handle: amdgpu_device pointer 67 * 68 * Set ring and irq function pointers 69 */ 70 static int vcn_v4_0_early_init(void *handle) 71 { 72 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 73 74 /* re-use enc ring as unified ring */ 75 adev->vcn.num_enc_rings = 1; 76 77 vcn_v4_0_set_unified_ring_funcs(adev); 78 vcn_v4_0_set_irq_funcs(adev); 79 80 return 0; 81 } 82 83 /** 84 * vcn_v4_0_sw_init - sw init for VCN block 85 * 86 * @handle: amdgpu_device pointer 87 * 88 * Load firmware and sw initialization 89 */ 90 static int vcn_v4_0_sw_init(void *handle) 91 { 92 struct amdgpu_ring *ring; 93 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 94 int i, r; 95 96 r = amdgpu_vcn_sw_init(adev); 97 if (r) 98 return r; 99 100 amdgpu_vcn_setup_ucode(adev); 101 102 r = amdgpu_vcn_resume(adev); 103 if (r) 104 return r; 105 106 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 107 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 108 109 if (adev->vcn.harvest_config & (1 << i)) 110 continue; 111 112 atomic_set(&adev->vcn.inst[i].sched_score, 0); 113 114 /* VCN UNIFIED TRAP */ 115 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 116 VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); 117 if (r) 118 return r; 119 120 ring = &adev->vcn.inst[i].ring_enc[0]; 121 ring->use_doorbell = true; 122 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + 8 * i; 123 124 sprintf(ring->name, "vcn_unified_%d", i); 125 126 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 127 AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score); 128 if (r) 129 return r; 130 131 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 132 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); 133 fw_shared->sq.is_enabled = 1; 134 135 if (amdgpu_vcnfw_log) 136 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]); 137 } 138 139 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 140 adev->vcn.pause_dpg_mode = vcn_v4_0_pause_dpg_mode; 141 142 return 0; 143 } 144 145 /** 146 * vcn_v4_0_sw_fini - sw fini for VCN block 147 * 148 * @handle: amdgpu_device pointer 149 * 150 * VCN suspend and free up sw allocation 151 */ 152 static int vcn_v4_0_sw_fini(void *handle) 153 { 154 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 155 int i, r, idx; 156 157 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 158 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 159 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 160 161 if (adev->vcn.harvest_config & (1 << i)) 162 continue; 163 164 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 165 fw_shared->present_flag_0 = 0; 166 fw_shared->sq.is_enabled = 0; 167 } 168 169 drm_dev_exit(idx); 170 } 171 172 r = amdgpu_vcn_suspend(adev); 173 if (r) 174 return r; 175 176 r = amdgpu_vcn_sw_fini(adev); 177 178 return r; 179 } 180 181 /** 182 * vcn_v4_0_hw_init - start and test VCN block 183 * 184 * @handle: amdgpu_device pointer 185 * 186 * Initialize the hardware, boot up the VCPU and do some testing 187 */ 188 static int vcn_v4_0_hw_init(void *handle) 189 { 190 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 191 struct amdgpu_ring *ring; 192 int i, r; 193 194 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 195 if (adev->vcn.harvest_config & (1 << i)) 196 continue; 197 198 ring = &adev->vcn.inst[i].ring_enc[0]; 199 200 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 201 ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i); 202 203 r = amdgpu_ring_test_helper(ring); 204 if (r) 205 goto done; 206 } 207 208 done: 209 if (!r) 210 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 211 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 212 213 return r; 214 } 215 216 /** 217 * vcn_v4_0_hw_fini - stop the hardware block 218 * 219 * @handle: amdgpu_device pointer 220 * 221 * Stop the VCN block, mark ring as not ready any more 222 */ 223 static int vcn_v4_0_hw_fini(void *handle) 224 { 225 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 226 int i; 227 228 cancel_delayed_work_sync(&adev->vcn.idle_work); 229 230 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 231 if (adev->vcn.harvest_config & (1 << i)) 232 continue; 233 234 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 235 (adev->vcn.cur_state != AMD_PG_STATE_GATE && 236 RREG32_SOC15(VCN, i, regUVD_STATUS))) { 237 vcn_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 238 } 239 } 240 241 return 0; 242 } 243 244 /** 245 * vcn_v4_0_suspend - suspend VCN block 246 * 247 * @handle: amdgpu_device pointer 248 * 249 * HW fini and suspend VCN block 250 */ 251 static int vcn_v4_0_suspend(void *handle) 252 { 253 int r; 254 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 255 256 r = vcn_v4_0_hw_fini(adev); 257 if (r) 258 return r; 259 260 r = amdgpu_vcn_suspend(adev); 261 262 return r; 263 } 264 265 /** 266 * vcn_v4_0_resume - resume VCN block 267 * 268 * @handle: amdgpu_device pointer 269 * 270 * Resume firmware and hw init VCN block 271 */ 272 static int vcn_v4_0_resume(void *handle) 273 { 274 int r; 275 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 276 277 r = amdgpu_vcn_resume(adev); 278 if (r) 279 return r; 280 281 r = vcn_v4_0_hw_init(adev); 282 283 return r; 284 } 285 286 /** 287 * vcn_v4_0_mc_resume - memory controller programming 288 * 289 * @adev: amdgpu_device pointer 290 * @inst: instance number 291 * 292 * Let the VCN memory controller know it's offsets 293 */ 294 static void vcn_v4_0_mc_resume(struct amdgpu_device *adev, int inst) 295 { 296 uint32_t offset, size; 297 const struct common_firmware_header *hdr; 298 299 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 300 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 301 302 /* cache window 0: fw */ 303 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 304 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 305 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 306 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 307 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 308 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0); 309 offset = 0; 310 } else { 311 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 312 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 313 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 314 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 315 offset = size; 316 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 317 } 318 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size); 319 320 /* cache window 1: stack */ 321 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 322 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 323 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 324 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 325 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0); 326 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 327 328 /* cache window 2: context */ 329 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 330 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 331 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 332 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 333 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0); 334 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 335 336 /* non-cache window */ 337 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 338 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 339 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 340 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 341 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); 342 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0, 343 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 344 } 345 346 /** 347 * vcn_v4_0_mc_resume_dpg_mode - memory controller programming for dpg mode 348 * 349 * @adev: amdgpu_device pointer 350 * @inst_idx: instance number index 351 * @indirect: indirectly write sram 352 * 353 * Let the VCN memory controller know it's offsets with dpg mode 354 */ 355 static void vcn_v4_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 356 { 357 uint32_t offset, size; 358 const struct common_firmware_header *hdr; 359 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 360 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 361 362 /* cache window 0: fw */ 363 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 364 if (!indirect) { 365 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 366 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 367 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); 368 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 369 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 370 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); 371 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 372 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 373 } else { 374 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 375 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 376 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 377 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 378 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 379 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 380 } 381 offset = 0; 382 } else { 383 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 384 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 385 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 386 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 387 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 388 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 389 offset = size; 390 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 391 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 392 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 393 } 394 395 if (!indirect) 396 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 397 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 398 else 399 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 400 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 401 402 /* cache window 1: stack */ 403 if (!indirect) { 404 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 405 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 406 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 407 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 408 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 409 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 410 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 411 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 412 } else { 413 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 414 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 415 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 416 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 417 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 418 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 419 } 420 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 421 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 422 423 /* cache window 2: context */ 424 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 425 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 426 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 427 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 428 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 429 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 430 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 431 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 432 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 433 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 434 435 /* non-cache window */ 436 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 437 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 438 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 439 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 440 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 441 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 442 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 443 VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 444 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 445 VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0), 446 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); 447 448 /* VCN global tiling registers */ 449 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 450 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 451 } 452 453 /** 454 * vcn_v4_0_disable_static_power_gating - disable VCN static power gating 455 * 456 * @adev: amdgpu_device pointer 457 * @inst: instance number 458 * 459 * Disable static power gating for VCN block 460 */ 461 static void vcn_v4_0_disable_static_power_gating(struct amdgpu_device *adev, int inst) 462 { 463 uint32_t data = 0; 464 465 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 466 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 467 | 1 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT 468 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 469 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 470 | 2 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT 471 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 472 | 2 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT 473 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 474 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 475 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 476 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 477 | 2 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT 478 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 479 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 480 481 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data); 482 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, 483 UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF); 484 } else { 485 uint32_t value; 486 487 value = (inst) ? 0x2200800 : 0; 488 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 489 | 1 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT 490 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 491 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 492 | 1 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT 493 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 494 | 1 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT 495 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 496 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 497 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 498 | 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 499 | 1 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT 500 | 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 501 | 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 502 503 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data); 504 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, value, 0x3F3FFFFF); 505 } 506 507 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 508 data &= ~0x103; 509 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 510 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 511 UVD_POWER_STATUS__UVD_PG_EN_MASK; 512 513 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 514 515 return; 516 } 517 518 /** 519 * vcn_v4_0_enable_static_power_gating - enable VCN static power gating 520 * 521 * @adev: amdgpu_device pointer 522 * @inst: instance number 523 * 524 * Enable static power gating for VCN block 525 */ 526 static void vcn_v4_0_enable_static_power_gating(struct amdgpu_device *adev, int inst) 527 { 528 uint32_t data; 529 530 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 531 /* Before power off, this indicator has to be turned on */ 532 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 533 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 534 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 535 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 536 537 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 538 | 2 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT 539 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 540 | 2 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT 541 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 542 | 2 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT 543 | 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 544 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 545 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 546 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 547 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 548 | 2 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT 549 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 550 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 551 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data); 552 553 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 554 | 2 << UVD_PGFSM_STATUS__UVDS_PWR_STATUS__SHIFT 555 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 556 | 2 << UVD_PGFSM_STATUS__UVDTC_PWR_STATUS__SHIFT 557 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 558 | 2 << UVD_PGFSM_STATUS__UVDTA_PWR_STATUS__SHIFT 559 | 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT 560 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 561 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 562 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 563 | 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT 564 | 2 << UVD_PGFSM_STATUS__UVDTB_PWR_STATUS__SHIFT 565 | 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT 566 | 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT); 567 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, data, 0x3F3FFFFF); 568 } 569 570 return; 571 } 572 573 /** 574 * vcn_v4_0_disable_clock_gating - disable VCN clock gating 575 * 576 * @adev: amdgpu_device pointer 577 * @inst: instance number 578 * 579 * Disable clock gating for VCN block 580 */ 581 static void vcn_v4_0_disable_clock_gating(struct amdgpu_device *adev, int inst) 582 { 583 uint32_t data; 584 585 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 586 return; 587 588 /* VCN disable CGC */ 589 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 590 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 591 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 592 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 593 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 594 595 data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE); 596 data &= ~(UVD_CGC_GATE__SYS_MASK 597 | UVD_CGC_GATE__UDEC_MASK 598 | UVD_CGC_GATE__MPEG2_MASK 599 | UVD_CGC_GATE__REGS_MASK 600 | UVD_CGC_GATE__RBC_MASK 601 | UVD_CGC_GATE__LMI_MC_MASK 602 | UVD_CGC_GATE__LMI_UMC_MASK 603 | UVD_CGC_GATE__IDCT_MASK 604 | UVD_CGC_GATE__MPRD_MASK 605 | UVD_CGC_GATE__MPC_MASK 606 | UVD_CGC_GATE__LBSI_MASK 607 | UVD_CGC_GATE__LRBBM_MASK 608 | UVD_CGC_GATE__UDEC_RE_MASK 609 | UVD_CGC_GATE__UDEC_CM_MASK 610 | UVD_CGC_GATE__UDEC_IT_MASK 611 | UVD_CGC_GATE__UDEC_DB_MASK 612 | UVD_CGC_GATE__UDEC_MP_MASK 613 | UVD_CGC_GATE__WCB_MASK 614 | UVD_CGC_GATE__VCPU_MASK 615 | UVD_CGC_GATE__MMSCH_MASK); 616 617 WREG32_SOC15(VCN, inst, regUVD_CGC_GATE, data); 618 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF); 619 620 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 621 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 622 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 623 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 624 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 625 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 626 | UVD_CGC_CTRL__SYS_MODE_MASK 627 | UVD_CGC_CTRL__UDEC_MODE_MASK 628 | UVD_CGC_CTRL__MPEG2_MODE_MASK 629 | UVD_CGC_CTRL__REGS_MODE_MASK 630 | UVD_CGC_CTRL__RBC_MODE_MASK 631 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 632 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 633 | UVD_CGC_CTRL__IDCT_MODE_MASK 634 | UVD_CGC_CTRL__MPRD_MODE_MASK 635 | UVD_CGC_CTRL__MPC_MODE_MASK 636 | UVD_CGC_CTRL__LBSI_MODE_MASK 637 | UVD_CGC_CTRL__LRBBM_MODE_MASK 638 | UVD_CGC_CTRL__WCB_MODE_MASK 639 | UVD_CGC_CTRL__VCPU_MODE_MASK 640 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 641 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 642 643 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE); 644 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 645 | UVD_SUVD_CGC_GATE__SIT_MASK 646 | UVD_SUVD_CGC_GATE__SMP_MASK 647 | UVD_SUVD_CGC_GATE__SCM_MASK 648 | UVD_SUVD_CGC_GATE__SDB_MASK 649 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 650 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 651 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 652 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 653 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 654 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 655 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 656 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 657 | UVD_SUVD_CGC_GATE__SCLR_MASK 658 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 659 | UVD_SUVD_CGC_GATE__ENT_MASK 660 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 661 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 662 | UVD_SUVD_CGC_GATE__SITE_MASK 663 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 664 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 665 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 666 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 667 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 668 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE, data); 669 670 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); 671 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 672 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 673 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 674 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 675 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 676 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 677 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 678 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 679 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 680 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 681 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data); 682 } 683 684 /** 685 * vcn_v4_0_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode 686 * 687 * @adev: amdgpu_device pointer 688 * @sram_sel: sram select 689 * @inst_idx: instance number index 690 * @indirect: indirectly write sram 691 * 692 * Disable clock gating for VCN block with dpg mode 693 */ 694 static void vcn_v4_0_disable_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel, 695 int inst_idx, uint8_t indirect) 696 { 697 uint32_t reg_data = 0; 698 699 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 700 return; 701 702 /* enable sw clock gating control */ 703 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 704 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 705 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 706 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 707 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 708 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 709 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 710 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 711 UVD_CGC_CTRL__SYS_MODE_MASK | 712 UVD_CGC_CTRL__UDEC_MODE_MASK | 713 UVD_CGC_CTRL__MPEG2_MODE_MASK | 714 UVD_CGC_CTRL__REGS_MODE_MASK | 715 UVD_CGC_CTRL__RBC_MODE_MASK | 716 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 717 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 718 UVD_CGC_CTRL__IDCT_MODE_MASK | 719 UVD_CGC_CTRL__MPRD_MODE_MASK | 720 UVD_CGC_CTRL__MPC_MODE_MASK | 721 UVD_CGC_CTRL__LBSI_MODE_MASK | 722 UVD_CGC_CTRL__LRBBM_MODE_MASK | 723 UVD_CGC_CTRL__WCB_MODE_MASK | 724 UVD_CGC_CTRL__VCPU_MODE_MASK); 725 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 726 VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); 727 728 /* turn off clock gating */ 729 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 730 VCN, inst_idx, regUVD_CGC_GATE), 0, sram_sel, indirect); 731 732 /* turn on SUVD clock gating */ 733 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 734 VCN, inst_idx, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 735 736 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 737 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 738 VCN, inst_idx, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 739 } 740 741 /** 742 * vcn_v4_0_enable_clock_gating - enable VCN clock gating 743 * 744 * @adev: amdgpu_device pointer 745 * @inst: instance number 746 * 747 * Enable clock gating for VCN block 748 */ 749 static void vcn_v4_0_enable_clock_gating(struct amdgpu_device *adev, int inst) 750 { 751 uint32_t data; 752 753 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 754 return; 755 756 /* enable VCN CGC */ 757 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 758 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 759 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 760 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 761 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 762 763 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 764 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 765 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 766 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 767 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 768 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 769 | UVD_CGC_CTRL__SYS_MODE_MASK 770 | UVD_CGC_CTRL__UDEC_MODE_MASK 771 | UVD_CGC_CTRL__MPEG2_MODE_MASK 772 | UVD_CGC_CTRL__REGS_MODE_MASK 773 | UVD_CGC_CTRL__RBC_MODE_MASK 774 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 775 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 776 | UVD_CGC_CTRL__IDCT_MODE_MASK 777 | UVD_CGC_CTRL__MPRD_MODE_MASK 778 | UVD_CGC_CTRL__MPC_MODE_MASK 779 | UVD_CGC_CTRL__LBSI_MODE_MASK 780 | UVD_CGC_CTRL__LRBBM_MODE_MASK 781 | UVD_CGC_CTRL__WCB_MODE_MASK 782 | UVD_CGC_CTRL__VCPU_MODE_MASK 783 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 784 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 785 786 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); 787 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 788 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 789 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 790 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 791 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 792 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 793 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 794 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 795 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 796 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 797 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data); 798 799 return; 800 } 801 802 /** 803 * vcn_v4_0_start_dpg_mode - VCN start with dpg mode 804 * 805 * @adev: amdgpu_device pointer 806 * @inst_idx: instance number index 807 * @indirect: indirectly write sram 808 * 809 * Start VCN block with dpg mode 810 */ 811 static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 812 { 813 volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 814 struct amdgpu_ring *ring; 815 uint32_t tmp; 816 817 /* disable register anti-hang mechanism */ 818 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1, 819 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 820 /* enable dynamic power gating mode */ 821 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS); 822 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 823 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 824 WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp); 825 826 if (indirect) 827 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 828 829 /* enable clock gating */ 830 vcn_v4_0_disable_clock_gating_dpg_mode(adev, 0, inst_idx, indirect); 831 832 /* enable VCPU clock */ 833 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 834 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK; 835 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 836 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 837 838 /* disable master interupt */ 839 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 840 VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect); 841 842 /* setup regUVD_LMI_CTRL */ 843 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 844 UVD_LMI_CTRL__REQ_MODE_MASK | 845 UVD_LMI_CTRL__CRC_RESET_MASK | 846 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 847 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 848 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 849 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 850 0x00100000L); 851 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 852 VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect); 853 854 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 855 VCN, inst_idx, regUVD_MPC_CNTL), 856 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 857 858 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 859 VCN, inst_idx, regUVD_MPC_SET_MUXA0), 860 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 861 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 862 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 863 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 864 865 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 866 VCN, inst_idx, regUVD_MPC_SET_MUXB0), 867 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 868 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 869 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 870 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 871 872 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 873 VCN, inst_idx, regUVD_MPC_SET_MUX), 874 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 875 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 876 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 877 878 vcn_v4_0_mc_resume_dpg_mode(adev, inst_idx, indirect); 879 880 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 881 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 882 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 883 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 884 885 /* enable LMI MC and UMC channels */ 886 tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT; 887 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 888 VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect); 889 890 /* enable master interrupt */ 891 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 892 VCN, inst_idx, regUVD_MASTINT_EN), 893 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 894 895 896 if (indirect) 897 psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, 898 (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr - 899 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr)); 900 901 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 902 903 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr); 904 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 905 WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4); 906 907 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 908 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 909 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 910 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 911 WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0); 912 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0); 913 914 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR); 915 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp); 916 ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 917 918 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 919 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 920 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 921 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 922 923 WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL, 924 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 925 VCN_RB1_DB_CTRL__EN_MASK); 926 927 return 0; 928 } 929 930 931 /** 932 * vcn_v4_0_start - VCN start 933 * 934 * @adev: amdgpu_device pointer 935 * 936 * Start VCN block 937 */ 938 static int vcn_v4_0_start(struct amdgpu_device *adev) 939 { 940 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 941 struct amdgpu_ring *ring; 942 uint32_t tmp; 943 int i, j, k, r; 944 945 if (adev->pm.dpm_enabled) 946 amdgpu_dpm_enable_uvd(adev, true); 947 948 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 949 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 950 951 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 952 r = vcn_v4_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram); 953 continue; 954 } 955 956 /* disable VCN power gating */ 957 vcn_v4_0_disable_static_power_gating(adev, i); 958 959 /* set VCN status busy */ 960 tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY; 961 WREG32_SOC15(VCN, i, regUVD_STATUS, tmp); 962 963 /*SW clock gating */ 964 vcn_v4_0_disable_clock_gating(adev, i); 965 966 /* enable VCPU clock */ 967 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 968 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 969 970 /* disable master interrupt */ 971 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0, 972 ~UVD_MASTINT_EN__VCPU_EN_MASK); 973 974 /* enable LMI MC and UMC channels */ 975 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0, 976 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 977 978 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 979 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 980 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 981 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 982 983 /* setup regUVD_LMI_CTRL */ 984 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL); 985 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp | 986 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 987 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 988 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 989 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 990 991 /* setup regUVD_MPC_CNTL */ 992 tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL); 993 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 994 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 995 WREG32_SOC15(VCN, i, regUVD_MPC_CNTL, tmp); 996 997 /* setup UVD_MPC_SET_MUXA0 */ 998 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0, 999 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1000 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1001 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1002 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1003 1004 /* setup UVD_MPC_SET_MUXB0 */ 1005 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXB0, 1006 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1007 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1008 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1009 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1010 1011 /* setup UVD_MPC_SET_MUX */ 1012 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX, 1013 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1014 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1015 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1016 1017 vcn_v4_0_mc_resume(adev, i); 1018 1019 /* VCN global tiling registers */ 1020 WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG, 1021 adev->gfx.config.gb_addr_config); 1022 1023 /* unblock VCPU register access */ 1024 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0, 1025 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1026 1027 /* release VCPU reset to boot */ 1028 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1029 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1030 1031 for (j = 0; j < 10; ++j) { 1032 uint32_t status; 1033 1034 for (k = 0; k < 100; ++k) { 1035 status = RREG32_SOC15(VCN, i, regUVD_STATUS); 1036 if (status & 2) 1037 break; 1038 mdelay(10); 1039 if (amdgpu_emu_mode==1) 1040 msleep(1); 1041 } 1042 1043 if (amdgpu_emu_mode==1) { 1044 r = -1; 1045 if (status & 2) { 1046 r = 0; 1047 break; 1048 } 1049 } else { 1050 r = 0; 1051 if (status & 2) 1052 break; 1053 1054 dev_err(adev->dev, "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i); 1055 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1056 UVD_VCPU_CNTL__BLK_RST_MASK, 1057 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1058 mdelay(10); 1059 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1060 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1061 1062 mdelay(10); 1063 r = -1; 1064 } 1065 } 1066 1067 if (r) { 1068 dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i); 1069 return r; 1070 } 1071 1072 /* enable master interrupt */ 1073 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 1074 UVD_MASTINT_EN__VCPU_EN_MASK, 1075 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1076 1077 /* clear the busy bit of VCN_STATUS */ 1078 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0, 1079 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1080 1081 ring = &adev->vcn.inst[i].ring_enc[0]; 1082 WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL, 1083 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 1084 VCN_RB1_DB_CTRL__EN_MASK); 1085 1086 WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr); 1087 WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1088 WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4); 1089 1090 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 1091 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 1092 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 1093 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 1094 WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0); 1095 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0); 1096 1097 tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR); 1098 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp); 1099 ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR); 1100 1101 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 1102 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 1103 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 1104 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 1105 } 1106 1107 return 0; 1108 } 1109 1110 /** 1111 * vcn_v4_0_stop_dpg_mode - VCN stop with dpg mode 1112 * 1113 * @adev: amdgpu_device pointer 1114 * @inst_idx: instance number index 1115 * 1116 * Stop VCN block with dpg mode 1117 */ 1118 static int vcn_v4_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) 1119 { 1120 uint32_t tmp; 1121 1122 /* Wait for power status to be 1 */ 1123 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, 1124 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1125 1126 /* wait for read ptr to be equal to write ptr */ 1127 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 1128 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1129 1130 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, 1131 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1132 1133 /* disable dynamic power gating mode */ 1134 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0, 1135 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1136 return 0; 1137 } 1138 1139 /** 1140 * vcn_v4_0_stop - VCN stop 1141 * 1142 * @adev: amdgpu_device pointer 1143 * 1144 * Stop VCN block 1145 */ 1146 static int vcn_v4_0_stop(struct amdgpu_device *adev) 1147 { 1148 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1149 uint32_t tmp; 1150 int i, r = 0; 1151 1152 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1153 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1154 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; 1155 1156 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1157 r = vcn_v4_0_stop_dpg_mode(adev, i); 1158 continue; 1159 } 1160 1161 /* wait for vcn idle */ 1162 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1163 if (r) 1164 return r; 1165 1166 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1167 UVD_LMI_STATUS__READ_CLEAN_MASK | 1168 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1169 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1170 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 1171 if (r) 1172 return r; 1173 1174 /* disable LMI UMC channel */ 1175 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2); 1176 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1177 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp); 1178 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1179 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1180 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 1181 if (r) 1182 return r; 1183 1184 /* block VCPU register access */ 1185 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 1186 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1187 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1188 1189 /* reset VCPU */ 1190 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1191 UVD_VCPU_CNTL__BLK_RST_MASK, 1192 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1193 1194 /* disable VCPU clock */ 1195 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1196 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1197 1198 /* apply soft reset */ 1199 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1200 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1201 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1202 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1203 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1204 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1205 1206 /* clear status */ 1207 WREG32_SOC15(VCN, i, regUVD_STATUS, 0); 1208 1209 /* apply HW clock gating */ 1210 vcn_v4_0_enable_clock_gating(adev, i); 1211 1212 /* enable VCN power gating */ 1213 vcn_v4_0_enable_static_power_gating(adev, i); 1214 } 1215 1216 if (adev->pm.dpm_enabled) 1217 amdgpu_dpm_enable_uvd(adev, false); 1218 1219 return 0; 1220 } 1221 1222 /** 1223 * vcn_v4_0_pause_dpg_mode - VCN pause with dpg mode 1224 * 1225 * @adev: amdgpu_device pointer 1226 * @inst_idx: instance number index 1227 * @new_state: pause state 1228 * 1229 * Pause dpg mode for VCN block 1230 */ 1231 static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx, 1232 struct dpg_pause_state *new_state) 1233 { 1234 uint32_t reg_data = 0; 1235 int ret_code; 1236 1237 /* pause/unpause if state is changed */ 1238 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1239 DRM_DEV_DEBUG(adev->dev, "dpg pause state changed %d -> %d", 1240 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1241 reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) & 1242 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1243 1244 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1245 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1, 1246 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1247 1248 if (!ret_code) { 1249 /* pause DPG */ 1250 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1251 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1252 1253 /* wait for ACK */ 1254 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE, 1255 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1256 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1257 1258 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1259 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1260 } 1261 } else { 1262 /* unpause dpg, no need to wait */ 1263 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1264 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1265 } 1266 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1267 } 1268 1269 return 0; 1270 } 1271 1272 /** 1273 * vcn_v4_0_unified_ring_get_rptr - get unified read pointer 1274 * 1275 * @ring: amdgpu_ring pointer 1276 * 1277 * Returns the current hardware unified read pointer 1278 */ 1279 static uint64_t vcn_v4_0_unified_ring_get_rptr(struct amdgpu_ring *ring) 1280 { 1281 struct amdgpu_device *adev = ring->adev; 1282 1283 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1284 DRM_ERROR("wrong ring id is identified in %s", __func__); 1285 1286 return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR); 1287 } 1288 1289 /** 1290 * vcn_v4_0_unified_ring_get_wptr - get unified write pointer 1291 * 1292 * @ring: amdgpu_ring pointer 1293 * 1294 * Returns the current hardware unified write pointer 1295 */ 1296 static uint64_t vcn_v4_0_unified_ring_get_wptr(struct amdgpu_ring *ring) 1297 { 1298 struct amdgpu_device *adev = ring->adev; 1299 1300 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1301 DRM_ERROR("wrong ring id is identified in %s", __func__); 1302 1303 if (ring->use_doorbell) 1304 return *ring->wptr_cpu_addr; 1305 else 1306 return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR); 1307 } 1308 1309 /** 1310 * vcn_v4_0_unified_ring_set_wptr - set enc write pointer 1311 * 1312 * @ring: amdgpu_ring pointer 1313 * 1314 * Commits the enc write pointer to the hardware 1315 */ 1316 static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring) 1317 { 1318 struct amdgpu_device *adev = ring->adev; 1319 1320 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1321 DRM_ERROR("wrong ring id is identified in %s", __func__); 1322 1323 if (ring->use_doorbell) { 1324 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1325 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1326 } else { 1327 WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1328 } 1329 } 1330 1331 static int vcn_v4_0_limit_sched(struct amdgpu_cs_parser *p) 1332 { 1333 struct drm_gpu_scheduler **scheds; 1334 1335 /* The create msg must be in the first IB submitted */ 1336 if (atomic_read(&p->entity->fence_seq)) 1337 return -EINVAL; 1338 1339 scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_ENC] 1340 [AMDGPU_RING_PRIO_0].sched; 1341 drm_sched_entity_modify_sched(p->entity, scheds, 1); 1342 return 0; 1343 } 1344 1345 static int vcn_v4_0_dec_msg(struct amdgpu_cs_parser *p, uint64_t addr) 1346 { 1347 struct ttm_operation_ctx ctx = { false, false }; 1348 struct amdgpu_bo_va_mapping *map; 1349 uint32_t *msg, num_buffers; 1350 struct amdgpu_bo *bo; 1351 uint64_t start, end; 1352 unsigned int i; 1353 void *ptr; 1354 int r; 1355 1356 addr &= AMDGPU_GMC_HOLE_MASK; 1357 r = amdgpu_cs_find_mapping(p, addr, &bo, &map); 1358 if (r) { 1359 DRM_ERROR("Can't find BO for addr 0x%08llx\n", addr); 1360 return r; 1361 } 1362 1363 start = map->start * AMDGPU_GPU_PAGE_SIZE; 1364 end = (map->last + 1) * AMDGPU_GPU_PAGE_SIZE; 1365 if (addr & 0x7) { 1366 DRM_ERROR("VCN messages must be 8 byte aligned!\n"); 1367 return -EINVAL; 1368 } 1369 1370 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1371 amdgpu_bo_placement_from_domain(bo, bo->allowed_domains); 1372 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 1373 if (r) { 1374 DRM_ERROR("Failed validating the VCN message BO (%d)!\n", r); 1375 return r; 1376 } 1377 1378 r = amdgpu_bo_kmap(bo, &ptr); 1379 if (r) { 1380 DRM_ERROR("Failed mapping the VCN message (%d)!\n", r); 1381 return r; 1382 } 1383 1384 msg = ptr + addr - start; 1385 1386 /* Check length */ 1387 if (msg[1] > end - addr) { 1388 r = -EINVAL; 1389 goto out; 1390 } 1391 1392 if (msg[3] != RDECODE_MSG_CREATE) 1393 goto out; 1394 1395 num_buffers = msg[2]; 1396 for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) { 1397 uint32_t offset, size, *create; 1398 1399 if (msg[0] != RDECODE_MESSAGE_CREATE) 1400 continue; 1401 1402 offset = msg[1]; 1403 size = msg[2]; 1404 1405 if (offset + size > end) { 1406 r = -EINVAL; 1407 goto out; 1408 } 1409 1410 create = ptr + addr + offset - start; 1411 1412 /* H246, HEVC and VP9 can run on any instance */ 1413 if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11) 1414 continue; 1415 1416 r = vcn_v4_0_limit_sched(p); 1417 if (r) 1418 goto out; 1419 } 1420 1421 out: 1422 amdgpu_bo_kunmap(bo); 1423 return r; 1424 } 1425 1426 #define RADEON_VCN_ENGINE_TYPE_DECODE (0x00000003) 1427 1428 static int vcn_v4_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, 1429 struct amdgpu_job *job, 1430 struct amdgpu_ib *ib) 1431 { 1432 struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched); 1433 struct amdgpu_vcn_decode_buffer *decode_buffer = NULL; 1434 uint32_t val; 1435 int r = 0; 1436 1437 /* The first instance can decode anything */ 1438 if (!ring->me) 1439 return r; 1440 1441 /* unified queue ib header has 8 double words. */ 1442 if (ib->length_dw < 8) 1443 return r; 1444 1445 val = amdgpu_ib_get_value(ib, 6); //RADEON_VCN_ENGINE_TYPE 1446 1447 if (val == RADEON_VCN_ENGINE_TYPE_DECODE) { 1448 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&ib->ptr[10]; 1449 1450 if (decode_buffer->valid_buf_flag & 0x1) 1451 r = vcn_v4_0_dec_msg(p, ((u64)decode_buffer->msg_buffer_address_hi) << 32 | 1452 decode_buffer->msg_buffer_address_lo); 1453 } 1454 return r; 1455 } 1456 1457 static const struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = { 1458 .type = AMDGPU_RING_TYPE_VCN_ENC, 1459 .align_mask = 0x3f, 1460 .nop = VCN_ENC_CMD_NO_OP, 1461 .vmhub = AMDGPU_MMHUB_0, 1462 .get_rptr = vcn_v4_0_unified_ring_get_rptr, 1463 .get_wptr = vcn_v4_0_unified_ring_get_wptr, 1464 .set_wptr = vcn_v4_0_unified_ring_set_wptr, 1465 .patch_cs_in_place = vcn_v4_0_ring_patch_cs_in_place, 1466 .emit_frame_size = 1467 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1468 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1469 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1470 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1471 1, /* vcn_v2_0_enc_ring_insert_end */ 1472 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1473 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1474 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1475 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 1476 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1477 .test_ib = amdgpu_vcn_unified_ring_test_ib, 1478 .insert_nop = amdgpu_ring_insert_nop, 1479 .insert_end = vcn_v2_0_enc_ring_insert_end, 1480 .pad_ib = amdgpu_ring_generic_pad_ib, 1481 .begin_use = amdgpu_vcn_ring_begin_use, 1482 .end_use = amdgpu_vcn_ring_end_use, 1483 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 1484 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 1485 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1486 }; 1487 1488 /** 1489 * vcn_v4_0_set_unified_ring_funcs - set unified ring functions 1490 * 1491 * @adev: amdgpu_device pointer 1492 * 1493 * Set unified ring functions 1494 */ 1495 static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev) 1496 { 1497 int i; 1498 1499 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1500 if (adev->vcn.harvest_config & (1 << i)) 1501 continue; 1502 1503 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_unified_ring_vm_funcs; 1504 adev->vcn.inst[i].ring_enc[0].me = i; 1505 1506 DRM_INFO("VCN(%d) encode/decode are enabled in VM mode\n", i); 1507 } 1508 } 1509 1510 /** 1511 * vcn_v4_0_is_idle - check VCN block is idle 1512 * 1513 * @handle: amdgpu_device pointer 1514 * 1515 * Check whether VCN block is idle 1516 */ 1517 static bool vcn_v4_0_is_idle(void *handle) 1518 { 1519 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1520 int i, ret = 1; 1521 1522 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1523 if (adev->vcn.harvest_config & (1 << i)) 1524 continue; 1525 1526 ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE); 1527 } 1528 1529 return ret; 1530 } 1531 1532 /** 1533 * vcn_v4_0_wait_for_idle - wait for VCN block idle 1534 * 1535 * @handle: amdgpu_device pointer 1536 * 1537 * Wait for VCN block idle 1538 */ 1539 static int vcn_v4_0_wait_for_idle(void *handle) 1540 { 1541 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1542 int i, ret = 0; 1543 1544 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1545 if (adev->vcn.harvest_config & (1 << i)) 1546 continue; 1547 1548 ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 1549 UVD_STATUS__IDLE); 1550 if (ret) 1551 return ret; 1552 } 1553 1554 return ret; 1555 } 1556 1557 /** 1558 * vcn_v4_0_set_clockgating_state - set VCN block clockgating state 1559 * 1560 * @handle: amdgpu_device pointer 1561 * @state: clock gating state 1562 * 1563 * Set VCN block clockgating state 1564 */ 1565 static int vcn_v4_0_set_clockgating_state(void *handle, enum amd_clockgating_state state) 1566 { 1567 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1568 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 1569 int i; 1570 1571 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1572 if (adev->vcn.harvest_config & (1 << i)) 1573 continue; 1574 1575 if (enable) { 1576 if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE) 1577 return -EBUSY; 1578 vcn_v4_0_enable_clock_gating(adev, i); 1579 } else { 1580 vcn_v4_0_disable_clock_gating(adev, i); 1581 } 1582 } 1583 1584 return 0; 1585 } 1586 1587 /** 1588 * vcn_v4_0_set_powergating_state - set VCN block powergating state 1589 * 1590 * @handle: amdgpu_device pointer 1591 * @state: power gating state 1592 * 1593 * Set VCN block powergating state 1594 */ 1595 static int vcn_v4_0_set_powergating_state(void *handle, enum amd_powergating_state state) 1596 { 1597 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1598 int ret; 1599 1600 if(state == adev->vcn.cur_state) 1601 return 0; 1602 1603 if (state == AMD_PG_STATE_GATE) 1604 ret = vcn_v4_0_stop(adev); 1605 else 1606 ret = vcn_v4_0_start(adev); 1607 1608 if(!ret) 1609 adev->vcn.cur_state = state; 1610 1611 return ret; 1612 } 1613 1614 /** 1615 * vcn_v4_0_set_interrupt_state - set VCN block interrupt state 1616 * 1617 * @adev: amdgpu_device pointer 1618 * @source: interrupt sources 1619 * @type: interrupt types 1620 * @state: interrupt states 1621 * 1622 * Set VCN block interrupt state 1623 */ 1624 static int vcn_v4_0_set_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 1625 unsigned type, enum amdgpu_interrupt_state state) 1626 { 1627 return 0; 1628 } 1629 1630 /** 1631 * vcn_v4_0_process_interrupt - process VCN block interrupt 1632 * 1633 * @adev: amdgpu_device pointer 1634 * @source: interrupt sources 1635 * @entry: interrupt entry from clients and sources 1636 * 1637 * Process VCN block interrupt 1638 */ 1639 static int vcn_v4_0_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 1640 struct amdgpu_iv_entry *entry) 1641 { 1642 uint32_t ip_instance; 1643 1644 switch (entry->client_id) { 1645 case SOC15_IH_CLIENTID_VCN: 1646 ip_instance = 0; 1647 break; 1648 case SOC15_IH_CLIENTID_VCN1: 1649 ip_instance = 1; 1650 break; 1651 default: 1652 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 1653 return 0; 1654 } 1655 1656 DRM_DEBUG("IH: VCN TRAP\n"); 1657 1658 switch (entry->src_id) { 1659 case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1660 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 1661 break; 1662 default: 1663 DRM_ERROR("Unhandled interrupt: %d %d\n", 1664 entry->src_id, entry->src_data[0]); 1665 break; 1666 } 1667 1668 return 0; 1669 } 1670 1671 static const struct amdgpu_irq_src_funcs vcn_v4_0_irq_funcs = { 1672 .set = vcn_v4_0_set_interrupt_state, 1673 .process = vcn_v4_0_process_interrupt, 1674 }; 1675 1676 /** 1677 * vcn_v4_0_set_irq_funcs - set VCN block interrupt irq functions 1678 * 1679 * @adev: amdgpu_device pointer 1680 * 1681 * Set VCN block interrupt irq functions 1682 */ 1683 static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev) 1684 { 1685 int i; 1686 1687 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1688 if (adev->vcn.harvest_config & (1 << i)) 1689 continue; 1690 1691 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1; 1692 adev->vcn.inst[i].irq.funcs = &vcn_v4_0_irq_funcs; 1693 } 1694 } 1695 1696 static const struct amd_ip_funcs vcn_v4_0_ip_funcs = { 1697 .name = "vcn_v4_0", 1698 .early_init = vcn_v4_0_early_init, 1699 .late_init = NULL, 1700 .sw_init = vcn_v4_0_sw_init, 1701 .sw_fini = vcn_v4_0_sw_fini, 1702 .hw_init = vcn_v4_0_hw_init, 1703 .hw_fini = vcn_v4_0_hw_fini, 1704 .suspend = vcn_v4_0_suspend, 1705 .resume = vcn_v4_0_resume, 1706 .is_idle = vcn_v4_0_is_idle, 1707 .wait_for_idle = vcn_v4_0_wait_for_idle, 1708 .check_soft_reset = NULL, 1709 .pre_soft_reset = NULL, 1710 .soft_reset = NULL, 1711 .post_soft_reset = NULL, 1712 .set_clockgating_state = vcn_v4_0_set_clockgating_state, 1713 .set_powergating_state = vcn_v4_0_set_powergating_state, 1714 }; 1715 1716 const struct amdgpu_ip_block_version vcn_v4_0_ip_block = 1717 { 1718 .type = AMD_IP_BLOCK_TYPE_VCN, 1719 .major = 4, 1720 .minor = 0, 1721 .rev = 0, 1722 .funcs = &vcn_v4_0_ip_funcs, 1723 }; 1724