1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_vcn.h" 27 #include "amdgpu_pm.h" 28 #include "amdgpu_cs.h" 29 #include "soc15.h" 30 #include "soc15d.h" 31 #include "soc15_hw_ip.h" 32 #include "vcn_v2_0.h" 33 #include "mmsch_v4_0.h" 34 #include "vcn_v4_0.h" 35 36 #include "vcn/vcn_4_0_0_offset.h" 37 #include "vcn/vcn_4_0_0_sh_mask.h" 38 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 39 40 #include <drm/drm_drv.h> 41 42 #define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL 43 #define mmUVD_DPG_LMA_CTL_BASE_IDX regUVD_DPG_LMA_CTL_BASE_IDX 44 #define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA 45 #define mmUVD_DPG_LMA_DATA_BASE_IDX regUVD_DPG_LMA_DATA_BASE_IDX 46 47 #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00 48 #define VCN1_VID_SOC_ADDRESS_3_0 0x48300 49 50 #define VCN_HARVEST_MMSCH 0 51 52 #define RDECODE_MSG_CREATE 0x00000000 53 #define RDECODE_MESSAGE_CREATE 0x00000001 54 55 static int amdgpu_ih_clientid_vcns[] = { 56 SOC15_IH_CLIENTID_VCN, 57 SOC15_IH_CLIENTID_VCN1 58 }; 59 60 static int vcn_v4_0_start_sriov(struct amdgpu_device *adev); 61 static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev); 62 static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev); 63 static int vcn_v4_0_set_powergating_state(void *handle, 64 enum amd_powergating_state state); 65 static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev, 66 int inst_idx, struct dpg_pause_state *new_state); 67 static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring); 68 static void vcn_v4_0_set_ras_funcs(struct amdgpu_device *adev); 69 70 /** 71 * vcn_v4_0_early_init - set function pointers and load microcode 72 * 73 * @handle: amdgpu_device pointer 74 * 75 * Set ring and irq function pointers 76 * Load microcode from filesystem 77 */ 78 static int vcn_v4_0_early_init(void *handle) 79 { 80 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 81 82 if (amdgpu_sriov_vf(adev)) { 83 adev->vcn.harvest_config = VCN_HARVEST_MMSCH; 84 for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) { 85 if (amdgpu_vcn_is_disabled_vcn(adev, VCN_ENCODE_RING, i)) { 86 adev->vcn.harvest_config |= 1 << i; 87 dev_info(adev->dev, "VCN%d is disabled by hypervisor\n", i); 88 } 89 } 90 } 91 92 /* re-use enc ring as unified ring */ 93 adev->vcn.num_enc_rings = 1; 94 95 vcn_v4_0_set_unified_ring_funcs(adev); 96 vcn_v4_0_set_irq_funcs(adev); 97 vcn_v4_0_set_ras_funcs(adev); 98 99 return amdgpu_vcn_early_init(adev); 100 } 101 102 /** 103 * vcn_v4_0_sw_init - sw init for VCN block 104 * 105 * @handle: amdgpu_device pointer 106 * 107 * Load firmware and sw initialization 108 */ 109 static int vcn_v4_0_sw_init(void *handle) 110 { 111 struct amdgpu_ring *ring; 112 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 113 int i, r; 114 115 r = amdgpu_vcn_sw_init(adev); 116 if (r) 117 return r; 118 119 amdgpu_vcn_setup_ucode(adev); 120 121 r = amdgpu_vcn_resume(adev); 122 if (r) 123 return r; 124 125 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 126 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 127 128 if (adev->vcn.harvest_config & (1 << i)) 129 continue; 130 131 atomic_set(&adev->vcn.inst[i].sched_score, 0); 132 133 /* VCN UNIFIED TRAP */ 134 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 135 VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); 136 if (r) 137 return r; 138 139 /* VCN POISON TRAP */ 140 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 141 VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[i].irq); 142 if (r) 143 return r; 144 145 ring = &adev->vcn.inst[i].ring_enc[0]; 146 ring->use_doorbell = true; 147 if (amdgpu_sriov_vf(adev)) 148 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + i * (adev->vcn.num_enc_rings + 1) + 1; 149 else 150 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + 8 * i; 151 152 sprintf(ring->name, "vcn_unified_%d", i); 153 154 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 155 AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score); 156 if (r) 157 return r; 158 159 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 160 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); 161 fw_shared->sq.is_enabled = 1; 162 163 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG); 164 fw_shared->smu_dpm_interface.smu_interface_type = (adev->flags & AMD_IS_APU) ? 165 AMDGPU_VCN_SMU_DPM_INTERFACE_APU : AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU; 166 167 if (amdgpu_sriov_vf(adev)) 168 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG); 169 170 if (amdgpu_vcnfw_log) 171 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]); 172 } 173 174 if (amdgpu_sriov_vf(adev)) { 175 r = amdgpu_virt_alloc_mm_table(adev); 176 if (r) 177 return r; 178 } 179 180 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 181 adev->vcn.pause_dpg_mode = vcn_v4_0_pause_dpg_mode; 182 183 return 0; 184 } 185 186 /** 187 * vcn_v4_0_sw_fini - sw fini for VCN block 188 * 189 * @handle: amdgpu_device pointer 190 * 191 * VCN suspend and free up sw allocation 192 */ 193 static int vcn_v4_0_sw_fini(void *handle) 194 { 195 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 196 int i, r, idx; 197 198 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 199 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 200 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 201 202 if (adev->vcn.harvest_config & (1 << i)) 203 continue; 204 205 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 206 fw_shared->present_flag_0 = 0; 207 fw_shared->sq.is_enabled = 0; 208 } 209 210 drm_dev_exit(idx); 211 } 212 213 if (amdgpu_sriov_vf(adev)) 214 amdgpu_virt_free_mm_table(adev); 215 216 r = amdgpu_vcn_suspend(adev); 217 if (r) 218 return r; 219 220 r = amdgpu_vcn_sw_fini(adev); 221 222 return r; 223 } 224 225 /** 226 * vcn_v4_0_hw_init - start and test VCN block 227 * 228 * @handle: amdgpu_device pointer 229 * 230 * Initialize the hardware, boot up the VCPU and do some testing 231 */ 232 static int vcn_v4_0_hw_init(void *handle) 233 { 234 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 235 struct amdgpu_ring *ring; 236 int i, r; 237 238 if (amdgpu_sriov_vf(adev)) { 239 r = vcn_v4_0_start_sriov(adev); 240 if (r) 241 goto done; 242 243 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 244 if (adev->vcn.harvest_config & (1 << i)) 245 continue; 246 247 ring = &adev->vcn.inst[i].ring_enc[0]; 248 ring->wptr = 0; 249 ring->wptr_old = 0; 250 vcn_v4_0_unified_ring_set_wptr(ring); 251 ring->sched.ready = true; 252 253 } 254 } else { 255 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 256 if (adev->vcn.harvest_config & (1 << i)) 257 continue; 258 259 ring = &adev->vcn.inst[i].ring_enc[0]; 260 261 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 262 ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i); 263 264 r = amdgpu_ring_test_helper(ring); 265 if (r) 266 goto done; 267 268 } 269 } 270 271 done: 272 if (!r) 273 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 274 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 275 276 return r; 277 } 278 279 /** 280 * vcn_v4_0_hw_fini - stop the hardware block 281 * 282 * @handle: amdgpu_device pointer 283 * 284 * Stop the VCN block, mark ring as not ready any more 285 */ 286 static int vcn_v4_0_hw_fini(void *handle) 287 { 288 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 289 int i; 290 291 cancel_delayed_work_sync(&adev->vcn.idle_work); 292 293 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 294 if (adev->vcn.harvest_config & (1 << i)) 295 continue; 296 if (!amdgpu_sriov_vf(adev)) { 297 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 298 (adev->vcn.cur_state != AMD_PG_STATE_GATE && 299 RREG32_SOC15(VCN, i, regUVD_STATUS))) { 300 vcn_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 301 } 302 } 303 304 amdgpu_irq_put(adev, &adev->vcn.inst[i].irq, 0); 305 } 306 307 return 0; 308 } 309 310 /** 311 * vcn_v4_0_suspend - suspend VCN block 312 * 313 * @handle: amdgpu_device pointer 314 * 315 * HW fini and suspend VCN block 316 */ 317 static int vcn_v4_0_suspend(void *handle) 318 { 319 int r; 320 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 321 322 r = vcn_v4_0_hw_fini(adev); 323 if (r) 324 return r; 325 326 r = amdgpu_vcn_suspend(adev); 327 328 return r; 329 } 330 331 /** 332 * vcn_v4_0_resume - resume VCN block 333 * 334 * @handle: amdgpu_device pointer 335 * 336 * Resume firmware and hw init VCN block 337 */ 338 static int vcn_v4_0_resume(void *handle) 339 { 340 int r; 341 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 342 343 r = amdgpu_vcn_resume(adev); 344 if (r) 345 return r; 346 347 r = vcn_v4_0_hw_init(adev); 348 349 return r; 350 } 351 352 /** 353 * vcn_v4_0_mc_resume - memory controller programming 354 * 355 * @adev: amdgpu_device pointer 356 * @inst: instance number 357 * 358 * Let the VCN memory controller know it's offsets 359 */ 360 static void vcn_v4_0_mc_resume(struct amdgpu_device *adev, int inst) 361 { 362 uint32_t offset, size; 363 const struct common_firmware_header *hdr; 364 365 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 366 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 367 368 /* cache window 0: fw */ 369 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 370 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 371 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 372 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 373 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 374 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0); 375 offset = 0; 376 } else { 377 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 378 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 379 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 380 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 381 offset = size; 382 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 383 } 384 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size); 385 386 /* cache window 1: stack */ 387 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 388 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 389 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 390 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 391 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0); 392 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 393 394 /* cache window 2: context */ 395 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 396 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 397 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 398 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 399 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0); 400 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 401 402 /* non-cache window */ 403 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 404 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 405 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 406 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 407 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); 408 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0, 409 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 410 } 411 412 /** 413 * vcn_v4_0_mc_resume_dpg_mode - memory controller programming for dpg mode 414 * 415 * @adev: amdgpu_device pointer 416 * @inst_idx: instance number index 417 * @indirect: indirectly write sram 418 * 419 * Let the VCN memory controller know it's offsets with dpg mode 420 */ 421 static void vcn_v4_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 422 { 423 uint32_t offset, size; 424 const struct common_firmware_header *hdr; 425 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 426 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 427 428 /* cache window 0: fw */ 429 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 430 if (!indirect) { 431 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 432 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 433 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); 434 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 435 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 436 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); 437 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 438 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 439 } else { 440 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 441 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 442 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 443 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 444 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 445 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 446 } 447 offset = 0; 448 } else { 449 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 450 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 451 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 452 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 453 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 454 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 455 offset = size; 456 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 457 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 458 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 459 } 460 461 if (!indirect) 462 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 463 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 464 else 465 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 466 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 467 468 /* cache window 1: stack */ 469 if (!indirect) { 470 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 471 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 472 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 473 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 474 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 475 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 476 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 477 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 478 } else { 479 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 480 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 481 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 482 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 483 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 484 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 485 } 486 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 487 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 488 489 /* cache window 2: context */ 490 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 491 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 492 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 493 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 494 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 495 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 496 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 497 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 498 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 499 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 500 501 /* non-cache window */ 502 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 503 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 504 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 505 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 506 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 507 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 508 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 509 VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 510 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 511 VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0), 512 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); 513 514 /* VCN global tiling registers */ 515 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 516 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 517 } 518 519 /** 520 * vcn_v4_0_disable_static_power_gating - disable VCN static power gating 521 * 522 * @adev: amdgpu_device pointer 523 * @inst: instance number 524 * 525 * Disable static power gating for VCN block 526 */ 527 static void vcn_v4_0_disable_static_power_gating(struct amdgpu_device *adev, int inst) 528 { 529 uint32_t data = 0; 530 531 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 532 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 533 | 1 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT 534 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 535 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 536 | 2 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT 537 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 538 | 2 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT 539 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 540 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 541 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 542 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 543 | 2 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT 544 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 545 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 546 547 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data); 548 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, 549 UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF); 550 } else { 551 uint32_t value; 552 553 value = (inst) ? 0x2200800 : 0; 554 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 555 | 1 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT 556 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 557 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 558 | 1 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT 559 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 560 | 1 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT 561 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 562 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 563 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 564 | 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 565 | 1 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT 566 | 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 567 | 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 568 569 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data); 570 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, value, 0x3F3FFFFF); 571 } 572 573 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 574 data &= ~0x103; 575 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 576 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 577 UVD_POWER_STATUS__UVD_PG_EN_MASK; 578 579 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 580 581 return; 582 } 583 584 /** 585 * vcn_v4_0_enable_static_power_gating - enable VCN static power gating 586 * 587 * @adev: amdgpu_device pointer 588 * @inst: instance number 589 * 590 * Enable static power gating for VCN block 591 */ 592 static void vcn_v4_0_enable_static_power_gating(struct amdgpu_device *adev, int inst) 593 { 594 uint32_t data; 595 596 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 597 /* Before power off, this indicator has to be turned on */ 598 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 599 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 600 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 601 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 602 603 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 604 | 2 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT 605 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 606 | 2 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT 607 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 608 | 2 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT 609 | 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 610 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 611 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 612 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 613 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 614 | 2 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT 615 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 616 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 617 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data); 618 619 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 620 | 2 << UVD_PGFSM_STATUS__UVDS_PWR_STATUS__SHIFT 621 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 622 | 2 << UVD_PGFSM_STATUS__UVDTC_PWR_STATUS__SHIFT 623 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 624 | 2 << UVD_PGFSM_STATUS__UVDTA_PWR_STATUS__SHIFT 625 | 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT 626 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 627 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 628 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 629 | 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT 630 | 2 << UVD_PGFSM_STATUS__UVDTB_PWR_STATUS__SHIFT 631 | 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT 632 | 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT); 633 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, data, 0x3F3FFFFF); 634 } 635 636 return; 637 } 638 639 /** 640 * vcn_v4_0_disable_clock_gating - disable VCN clock gating 641 * 642 * @adev: amdgpu_device pointer 643 * @inst: instance number 644 * 645 * Disable clock gating for VCN block 646 */ 647 static void vcn_v4_0_disable_clock_gating(struct amdgpu_device *adev, int inst) 648 { 649 uint32_t data; 650 651 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 652 return; 653 654 /* VCN disable CGC */ 655 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 656 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 657 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 658 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 659 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 660 661 data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE); 662 data &= ~(UVD_CGC_GATE__SYS_MASK 663 | UVD_CGC_GATE__UDEC_MASK 664 | UVD_CGC_GATE__MPEG2_MASK 665 | UVD_CGC_GATE__REGS_MASK 666 | UVD_CGC_GATE__RBC_MASK 667 | UVD_CGC_GATE__LMI_MC_MASK 668 | UVD_CGC_GATE__LMI_UMC_MASK 669 | UVD_CGC_GATE__IDCT_MASK 670 | UVD_CGC_GATE__MPRD_MASK 671 | UVD_CGC_GATE__MPC_MASK 672 | UVD_CGC_GATE__LBSI_MASK 673 | UVD_CGC_GATE__LRBBM_MASK 674 | UVD_CGC_GATE__UDEC_RE_MASK 675 | UVD_CGC_GATE__UDEC_CM_MASK 676 | UVD_CGC_GATE__UDEC_IT_MASK 677 | UVD_CGC_GATE__UDEC_DB_MASK 678 | UVD_CGC_GATE__UDEC_MP_MASK 679 | UVD_CGC_GATE__WCB_MASK 680 | UVD_CGC_GATE__VCPU_MASK 681 | UVD_CGC_GATE__MMSCH_MASK); 682 683 WREG32_SOC15(VCN, inst, regUVD_CGC_GATE, data); 684 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF); 685 686 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 687 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 688 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 689 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 690 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 691 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 692 | UVD_CGC_CTRL__SYS_MODE_MASK 693 | UVD_CGC_CTRL__UDEC_MODE_MASK 694 | UVD_CGC_CTRL__MPEG2_MODE_MASK 695 | UVD_CGC_CTRL__REGS_MODE_MASK 696 | UVD_CGC_CTRL__RBC_MODE_MASK 697 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 698 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 699 | UVD_CGC_CTRL__IDCT_MODE_MASK 700 | UVD_CGC_CTRL__MPRD_MODE_MASK 701 | UVD_CGC_CTRL__MPC_MODE_MASK 702 | UVD_CGC_CTRL__LBSI_MODE_MASK 703 | UVD_CGC_CTRL__LRBBM_MODE_MASK 704 | UVD_CGC_CTRL__WCB_MODE_MASK 705 | UVD_CGC_CTRL__VCPU_MODE_MASK 706 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 707 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 708 709 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE); 710 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 711 | UVD_SUVD_CGC_GATE__SIT_MASK 712 | UVD_SUVD_CGC_GATE__SMP_MASK 713 | UVD_SUVD_CGC_GATE__SCM_MASK 714 | UVD_SUVD_CGC_GATE__SDB_MASK 715 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 716 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 717 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 718 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 719 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 720 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 721 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 722 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 723 | UVD_SUVD_CGC_GATE__SCLR_MASK 724 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 725 | UVD_SUVD_CGC_GATE__ENT_MASK 726 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 727 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 728 | UVD_SUVD_CGC_GATE__SITE_MASK 729 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 730 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 731 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 732 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 733 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 734 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE, data); 735 736 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); 737 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 738 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 739 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 740 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 741 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 742 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 743 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 744 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 745 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 746 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 747 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data); 748 } 749 750 /** 751 * vcn_v4_0_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode 752 * 753 * @adev: amdgpu_device pointer 754 * @sram_sel: sram select 755 * @inst_idx: instance number index 756 * @indirect: indirectly write sram 757 * 758 * Disable clock gating for VCN block with dpg mode 759 */ 760 static void vcn_v4_0_disable_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel, 761 int inst_idx, uint8_t indirect) 762 { 763 uint32_t reg_data = 0; 764 765 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 766 return; 767 768 /* enable sw clock gating control */ 769 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 770 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 771 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 772 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 773 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 774 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 775 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 776 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 777 UVD_CGC_CTRL__SYS_MODE_MASK | 778 UVD_CGC_CTRL__UDEC_MODE_MASK | 779 UVD_CGC_CTRL__MPEG2_MODE_MASK | 780 UVD_CGC_CTRL__REGS_MODE_MASK | 781 UVD_CGC_CTRL__RBC_MODE_MASK | 782 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 783 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 784 UVD_CGC_CTRL__IDCT_MODE_MASK | 785 UVD_CGC_CTRL__MPRD_MODE_MASK | 786 UVD_CGC_CTRL__MPC_MODE_MASK | 787 UVD_CGC_CTRL__LBSI_MODE_MASK | 788 UVD_CGC_CTRL__LRBBM_MODE_MASK | 789 UVD_CGC_CTRL__WCB_MODE_MASK | 790 UVD_CGC_CTRL__VCPU_MODE_MASK); 791 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 792 VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); 793 794 /* turn off clock gating */ 795 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 796 VCN, inst_idx, regUVD_CGC_GATE), 0, sram_sel, indirect); 797 798 /* turn on SUVD clock gating */ 799 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 800 VCN, inst_idx, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 801 802 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 803 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 804 VCN, inst_idx, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 805 } 806 807 /** 808 * vcn_v4_0_enable_clock_gating - enable VCN clock gating 809 * 810 * @adev: amdgpu_device pointer 811 * @inst: instance number 812 * 813 * Enable clock gating for VCN block 814 */ 815 static void vcn_v4_0_enable_clock_gating(struct amdgpu_device *adev, int inst) 816 { 817 uint32_t data; 818 819 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 820 return; 821 822 /* enable VCN CGC */ 823 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 824 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 825 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 826 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 827 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 828 829 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 830 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 831 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 832 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 833 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 834 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 835 | UVD_CGC_CTRL__SYS_MODE_MASK 836 | UVD_CGC_CTRL__UDEC_MODE_MASK 837 | UVD_CGC_CTRL__MPEG2_MODE_MASK 838 | UVD_CGC_CTRL__REGS_MODE_MASK 839 | UVD_CGC_CTRL__RBC_MODE_MASK 840 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 841 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 842 | UVD_CGC_CTRL__IDCT_MODE_MASK 843 | UVD_CGC_CTRL__MPRD_MODE_MASK 844 | UVD_CGC_CTRL__MPC_MODE_MASK 845 | UVD_CGC_CTRL__LBSI_MODE_MASK 846 | UVD_CGC_CTRL__LRBBM_MODE_MASK 847 | UVD_CGC_CTRL__WCB_MODE_MASK 848 | UVD_CGC_CTRL__VCPU_MODE_MASK 849 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 850 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 851 852 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); 853 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 854 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 855 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 856 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 857 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 858 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 859 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 860 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 861 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 862 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 863 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data); 864 865 return; 866 } 867 868 static void vcn_v4_0_enable_ras(struct amdgpu_device *adev, int inst_idx, 869 bool indirect) 870 { 871 uint32_t tmp; 872 873 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) 874 return; 875 876 tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK | 877 VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK | 878 VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK | 879 VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK; 880 WREG32_SOC15_DPG_MODE(inst_idx, 881 SOC15_DPG_MODE_OFFSET(VCN, 0, regVCN_RAS_CNTL), 882 tmp, 0, indirect); 883 884 tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK; 885 WREG32_SOC15_DPG_MODE(inst_idx, 886 SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_SYS_INT_EN), 887 tmp, 0, indirect); 888 } 889 890 /** 891 * vcn_v4_0_start_dpg_mode - VCN start with dpg mode 892 * 893 * @adev: amdgpu_device pointer 894 * @inst_idx: instance number index 895 * @indirect: indirectly write sram 896 * 897 * Start VCN block with dpg mode 898 */ 899 static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 900 { 901 volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 902 struct amdgpu_ring *ring; 903 uint32_t tmp; 904 905 /* disable register anti-hang mechanism */ 906 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1, 907 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 908 /* enable dynamic power gating mode */ 909 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS); 910 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 911 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 912 WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp); 913 914 if (indirect) 915 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 916 917 /* enable clock gating */ 918 vcn_v4_0_disable_clock_gating_dpg_mode(adev, 0, inst_idx, indirect); 919 920 /* enable VCPU clock */ 921 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 922 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK; 923 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 924 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 925 926 /* disable master interupt */ 927 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 928 VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect); 929 930 /* setup regUVD_LMI_CTRL */ 931 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 932 UVD_LMI_CTRL__REQ_MODE_MASK | 933 UVD_LMI_CTRL__CRC_RESET_MASK | 934 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 935 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 936 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 937 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 938 0x00100000L); 939 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 940 VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect); 941 942 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 943 VCN, inst_idx, regUVD_MPC_CNTL), 944 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 945 946 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 947 VCN, inst_idx, regUVD_MPC_SET_MUXA0), 948 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 949 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 950 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 951 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 952 953 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 954 VCN, inst_idx, regUVD_MPC_SET_MUXB0), 955 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 956 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 957 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 958 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 959 960 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 961 VCN, inst_idx, regUVD_MPC_SET_MUX), 962 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 963 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 964 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 965 966 vcn_v4_0_mc_resume_dpg_mode(adev, inst_idx, indirect); 967 968 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 969 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 970 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 971 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 972 973 /* enable LMI MC and UMC channels */ 974 tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT; 975 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 976 VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect); 977 978 vcn_v4_0_enable_ras(adev, inst_idx, indirect); 979 980 /* enable master interrupt */ 981 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 982 VCN, inst_idx, regUVD_MASTINT_EN), 983 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 984 985 986 if (indirect) 987 psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, 988 (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr - 989 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr)); 990 991 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 992 993 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr); 994 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 995 WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4); 996 997 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 998 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 999 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 1000 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 1001 WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0); 1002 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0); 1003 1004 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR); 1005 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp); 1006 ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 1007 1008 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 1009 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 1010 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 1011 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 1012 1013 WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL, 1014 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 1015 VCN_RB1_DB_CTRL__EN_MASK); 1016 1017 return 0; 1018 } 1019 1020 1021 /** 1022 * vcn_v4_0_start - VCN start 1023 * 1024 * @adev: amdgpu_device pointer 1025 * 1026 * Start VCN block 1027 */ 1028 static int vcn_v4_0_start(struct amdgpu_device *adev) 1029 { 1030 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1031 struct amdgpu_ring *ring; 1032 uint32_t tmp; 1033 int i, j, k, r; 1034 1035 if (adev->pm.dpm_enabled) 1036 amdgpu_dpm_enable_uvd(adev, true); 1037 1038 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1039 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1040 1041 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1042 r = vcn_v4_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram); 1043 continue; 1044 } 1045 1046 /* disable VCN power gating */ 1047 vcn_v4_0_disable_static_power_gating(adev, i); 1048 1049 /* set VCN status busy */ 1050 tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY; 1051 WREG32_SOC15(VCN, i, regUVD_STATUS, tmp); 1052 1053 /*SW clock gating */ 1054 vcn_v4_0_disable_clock_gating(adev, i); 1055 1056 /* enable VCPU clock */ 1057 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1058 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 1059 1060 /* disable master interrupt */ 1061 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0, 1062 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1063 1064 /* enable LMI MC and UMC channels */ 1065 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0, 1066 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1067 1068 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1069 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1070 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1071 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1072 1073 /* setup regUVD_LMI_CTRL */ 1074 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL); 1075 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp | 1076 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1077 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1078 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1079 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1080 1081 /* setup regUVD_MPC_CNTL */ 1082 tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL); 1083 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1084 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1085 WREG32_SOC15(VCN, i, regUVD_MPC_CNTL, tmp); 1086 1087 /* setup UVD_MPC_SET_MUXA0 */ 1088 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0, 1089 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1090 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1091 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1092 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1093 1094 /* setup UVD_MPC_SET_MUXB0 */ 1095 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXB0, 1096 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1097 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1098 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1099 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1100 1101 /* setup UVD_MPC_SET_MUX */ 1102 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX, 1103 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1104 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1105 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1106 1107 vcn_v4_0_mc_resume(adev, i); 1108 1109 /* VCN global tiling registers */ 1110 WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG, 1111 adev->gfx.config.gb_addr_config); 1112 1113 /* unblock VCPU register access */ 1114 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0, 1115 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1116 1117 /* release VCPU reset to boot */ 1118 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1119 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1120 1121 for (j = 0; j < 10; ++j) { 1122 uint32_t status; 1123 1124 for (k = 0; k < 100; ++k) { 1125 status = RREG32_SOC15(VCN, i, regUVD_STATUS); 1126 if (status & 2) 1127 break; 1128 mdelay(10); 1129 if (amdgpu_emu_mode==1) 1130 msleep(1); 1131 } 1132 1133 if (amdgpu_emu_mode==1) { 1134 r = -1; 1135 if (status & 2) { 1136 r = 0; 1137 break; 1138 } 1139 } else { 1140 r = 0; 1141 if (status & 2) 1142 break; 1143 1144 dev_err(adev->dev, "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i); 1145 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1146 UVD_VCPU_CNTL__BLK_RST_MASK, 1147 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1148 mdelay(10); 1149 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1150 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1151 1152 mdelay(10); 1153 r = -1; 1154 } 1155 } 1156 1157 if (r) { 1158 dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i); 1159 return r; 1160 } 1161 1162 /* enable master interrupt */ 1163 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 1164 UVD_MASTINT_EN__VCPU_EN_MASK, 1165 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1166 1167 /* clear the busy bit of VCN_STATUS */ 1168 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0, 1169 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1170 1171 ring = &adev->vcn.inst[i].ring_enc[0]; 1172 WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL, 1173 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 1174 VCN_RB1_DB_CTRL__EN_MASK); 1175 1176 WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr); 1177 WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1178 WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4); 1179 1180 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 1181 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 1182 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 1183 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 1184 WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0); 1185 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0); 1186 1187 tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR); 1188 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp); 1189 ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR); 1190 1191 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 1192 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 1193 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 1194 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 1195 } 1196 1197 return 0; 1198 } 1199 1200 static int vcn_v4_0_start_sriov(struct amdgpu_device *adev) 1201 { 1202 int i; 1203 struct amdgpu_ring *ring_enc; 1204 uint64_t cache_addr; 1205 uint64_t rb_enc_addr; 1206 uint64_t ctx_addr; 1207 uint32_t param, resp, expected; 1208 uint32_t offset, cache_size; 1209 uint32_t tmp, timeout; 1210 1211 struct amdgpu_mm_table *table = &adev->virt.mm_table; 1212 uint32_t *table_loc; 1213 uint32_t table_size; 1214 uint32_t size, size_dw; 1215 uint32_t init_status; 1216 uint32_t enabled_vcn; 1217 1218 struct mmsch_v4_0_cmd_direct_write 1219 direct_wt = { {0} }; 1220 struct mmsch_v4_0_cmd_direct_read_modify_write 1221 direct_rd_mod_wt = { {0} }; 1222 struct mmsch_v4_0_cmd_end end = { {0} }; 1223 struct mmsch_v4_0_init_header header; 1224 1225 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1226 volatile struct amdgpu_fw_shared_rb_setup *rb_setup; 1227 1228 direct_wt.cmd_header.command_type = 1229 MMSCH_COMMAND__DIRECT_REG_WRITE; 1230 direct_rd_mod_wt.cmd_header.command_type = 1231 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1232 end.cmd_header.command_type = 1233 MMSCH_COMMAND__END; 1234 1235 header.version = MMSCH_VERSION; 1236 header.total_size = sizeof(struct mmsch_v4_0_init_header) >> 2; 1237 for (i = 0; i < AMDGPU_MAX_VCN_INSTANCES; i++) { 1238 header.inst[i].init_status = 0; 1239 header.inst[i].table_offset = 0; 1240 header.inst[i].table_size = 0; 1241 } 1242 1243 table_loc = (uint32_t *)table->cpu_addr; 1244 table_loc += header.total_size; 1245 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1246 if (adev->vcn.harvest_config & (1 << i)) 1247 continue; 1248 1249 table_size = 0; 1250 1251 MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i, 1252 regUVD_STATUS), 1253 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 1254 1255 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 1256 1257 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1258 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1259 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1260 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo); 1261 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1262 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1263 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi); 1264 offset = 0; 1265 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1266 regUVD_VCPU_CACHE_OFFSET0), 1267 0); 1268 } else { 1269 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1270 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1271 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 1272 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1273 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1274 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 1275 offset = cache_size; 1276 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1277 regUVD_VCPU_CACHE_OFFSET0), 1278 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 1279 } 1280 1281 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1282 regUVD_VCPU_CACHE_SIZE0), 1283 cache_size); 1284 1285 cache_addr = adev->vcn.inst[i].gpu_addr + offset; 1286 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1287 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 1288 lower_32_bits(cache_addr)); 1289 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1290 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 1291 upper_32_bits(cache_addr)); 1292 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1293 regUVD_VCPU_CACHE_OFFSET1), 1294 0); 1295 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1296 regUVD_VCPU_CACHE_SIZE1), 1297 AMDGPU_VCN_STACK_SIZE); 1298 1299 cache_addr = adev->vcn.inst[i].gpu_addr + offset + 1300 AMDGPU_VCN_STACK_SIZE; 1301 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1302 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 1303 lower_32_bits(cache_addr)); 1304 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1305 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 1306 upper_32_bits(cache_addr)); 1307 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1308 regUVD_VCPU_CACHE_OFFSET2), 1309 0); 1310 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1311 regUVD_VCPU_CACHE_SIZE2), 1312 AMDGPU_VCN_CONTEXT_SIZE); 1313 1314 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1315 rb_setup = &fw_shared->rb_setup; 1316 1317 ring_enc = &adev->vcn.inst[i].ring_enc[0]; 1318 ring_enc->wptr = 0; 1319 rb_enc_addr = ring_enc->gpu_addr; 1320 1321 rb_setup->is_rb_enabled_flags |= RB_ENABLED; 1322 rb_setup->rb_addr_lo = lower_32_bits(rb_enc_addr); 1323 rb_setup->rb_addr_hi = upper_32_bits(rb_enc_addr); 1324 rb_setup->rb_size = ring_enc->ring_size / 4; 1325 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG); 1326 1327 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1328 regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 1329 lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); 1330 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1331 regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 1332 upper_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); 1333 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1334 regUVD_VCPU_NONCACHE_SIZE0), 1335 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 1336 1337 /* add end packet */ 1338 MMSCH_V4_0_INSERT_END(); 1339 1340 /* refine header */ 1341 header.inst[i].init_status = 0; 1342 header.inst[i].table_offset = header.total_size; 1343 header.inst[i].table_size = table_size; 1344 header.total_size += table_size; 1345 } 1346 1347 /* Update init table header in memory */ 1348 size = sizeof(struct mmsch_v4_0_init_header); 1349 table_loc = (uint32_t *)table->cpu_addr; 1350 memcpy((void *)table_loc, &header, size); 1351 1352 /* message MMSCH (in VCN[0]) to initialize this client 1353 * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr 1354 * of memory descriptor location 1355 */ 1356 ctx_addr = table->gpu_addr; 1357 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 1358 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 1359 1360 /* 2, update vmid of descriptor */ 1361 tmp = RREG32_SOC15(VCN, 0, regMMSCH_VF_VMID); 1362 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1363 /* use domain0 for MM scheduler */ 1364 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1365 WREG32_SOC15(VCN, 0, regMMSCH_VF_VMID, tmp); 1366 1367 /* 3, notify mmsch about the size of this descriptor */ 1368 size = header.total_size; 1369 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_SIZE, size); 1370 1371 /* 4, set resp to zero */ 1372 WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP, 0); 1373 1374 /* 5, kick off the initialization and wait until 1375 * MMSCH_VF_MAILBOX_RESP becomes non-zero 1376 */ 1377 param = 0x00000001; 1378 WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_HOST, param); 1379 tmp = 0; 1380 timeout = 1000; 1381 resp = 0; 1382 expected = MMSCH_VF_MAILBOX_RESP__OK; 1383 while (resp != expected) { 1384 resp = RREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP); 1385 if (resp != 0) 1386 break; 1387 1388 udelay(10); 1389 tmp = tmp + 10; 1390 if (tmp >= timeout) { 1391 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 1392 " waiting for regMMSCH_VF_MAILBOX_RESP "\ 1393 "(expected=0x%08x, readback=0x%08x)\n", 1394 tmp, expected, resp); 1395 return -EBUSY; 1396 } 1397 } 1398 enabled_vcn = amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, 0) ? 1 : 0; 1399 init_status = ((struct mmsch_v4_0_init_header *)(table_loc))->inst[enabled_vcn].init_status; 1400 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE 1401 && init_status != MMSCH_VF_ENGINE_STATUS__PASS) 1402 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init "\ 1403 "status for VCN%x: 0x%x\n", resp, enabled_vcn, init_status); 1404 1405 return 0; 1406 } 1407 1408 /** 1409 * vcn_v4_0_stop_dpg_mode - VCN stop with dpg mode 1410 * 1411 * @adev: amdgpu_device pointer 1412 * @inst_idx: instance number index 1413 * 1414 * Stop VCN block with dpg mode 1415 */ 1416 static void vcn_v4_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) 1417 { 1418 uint32_t tmp; 1419 1420 /* Wait for power status to be 1 */ 1421 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, 1422 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1423 1424 /* wait for read ptr to be equal to write ptr */ 1425 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 1426 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1427 1428 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, 1429 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1430 1431 /* disable dynamic power gating mode */ 1432 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0, 1433 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1434 } 1435 1436 /** 1437 * vcn_v4_0_stop - VCN stop 1438 * 1439 * @adev: amdgpu_device pointer 1440 * 1441 * Stop VCN block 1442 */ 1443 static int vcn_v4_0_stop(struct amdgpu_device *adev) 1444 { 1445 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1446 uint32_t tmp; 1447 int i, r = 0; 1448 1449 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1450 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1451 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; 1452 1453 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1454 vcn_v4_0_stop_dpg_mode(adev, i); 1455 continue; 1456 } 1457 1458 /* wait for vcn idle */ 1459 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1460 if (r) 1461 return r; 1462 1463 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1464 UVD_LMI_STATUS__READ_CLEAN_MASK | 1465 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1466 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1467 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 1468 if (r) 1469 return r; 1470 1471 /* disable LMI UMC channel */ 1472 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2); 1473 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1474 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp); 1475 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1476 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1477 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 1478 if (r) 1479 return r; 1480 1481 /* block VCPU register access */ 1482 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 1483 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1484 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1485 1486 /* reset VCPU */ 1487 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1488 UVD_VCPU_CNTL__BLK_RST_MASK, 1489 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1490 1491 /* disable VCPU clock */ 1492 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1493 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1494 1495 /* apply soft reset */ 1496 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1497 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1498 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1499 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1500 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1501 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1502 1503 /* clear status */ 1504 WREG32_SOC15(VCN, i, regUVD_STATUS, 0); 1505 1506 /* apply HW clock gating */ 1507 vcn_v4_0_enable_clock_gating(adev, i); 1508 1509 /* enable VCN power gating */ 1510 vcn_v4_0_enable_static_power_gating(adev, i); 1511 } 1512 1513 if (adev->pm.dpm_enabled) 1514 amdgpu_dpm_enable_uvd(adev, false); 1515 1516 return 0; 1517 } 1518 1519 /** 1520 * vcn_v4_0_pause_dpg_mode - VCN pause with dpg mode 1521 * 1522 * @adev: amdgpu_device pointer 1523 * @inst_idx: instance number index 1524 * @new_state: pause state 1525 * 1526 * Pause dpg mode for VCN block 1527 */ 1528 static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx, 1529 struct dpg_pause_state *new_state) 1530 { 1531 uint32_t reg_data = 0; 1532 int ret_code; 1533 1534 /* pause/unpause if state is changed */ 1535 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1536 DRM_DEV_DEBUG(adev->dev, "dpg pause state changed %d -> %d", 1537 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1538 reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) & 1539 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1540 1541 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1542 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1, 1543 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1544 1545 if (!ret_code) { 1546 /* pause DPG */ 1547 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1548 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1549 1550 /* wait for ACK */ 1551 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE, 1552 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1553 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1554 1555 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1556 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1557 } 1558 } else { 1559 /* unpause dpg, no need to wait */ 1560 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1561 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1562 } 1563 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1564 } 1565 1566 return 0; 1567 } 1568 1569 /** 1570 * vcn_v4_0_unified_ring_get_rptr - get unified read pointer 1571 * 1572 * @ring: amdgpu_ring pointer 1573 * 1574 * Returns the current hardware unified read pointer 1575 */ 1576 static uint64_t vcn_v4_0_unified_ring_get_rptr(struct amdgpu_ring *ring) 1577 { 1578 struct amdgpu_device *adev = ring->adev; 1579 1580 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1581 DRM_ERROR("wrong ring id is identified in %s", __func__); 1582 1583 return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR); 1584 } 1585 1586 /** 1587 * vcn_v4_0_unified_ring_get_wptr - get unified write pointer 1588 * 1589 * @ring: amdgpu_ring pointer 1590 * 1591 * Returns the current hardware unified write pointer 1592 */ 1593 static uint64_t vcn_v4_0_unified_ring_get_wptr(struct amdgpu_ring *ring) 1594 { 1595 struct amdgpu_device *adev = ring->adev; 1596 1597 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1598 DRM_ERROR("wrong ring id is identified in %s", __func__); 1599 1600 if (ring->use_doorbell) 1601 return *ring->wptr_cpu_addr; 1602 else 1603 return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR); 1604 } 1605 1606 /** 1607 * vcn_v4_0_unified_ring_set_wptr - set enc write pointer 1608 * 1609 * @ring: amdgpu_ring pointer 1610 * 1611 * Commits the enc write pointer to the hardware 1612 */ 1613 static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring) 1614 { 1615 struct amdgpu_device *adev = ring->adev; 1616 1617 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1618 DRM_ERROR("wrong ring id is identified in %s", __func__); 1619 1620 if (ring->use_doorbell) { 1621 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1622 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1623 } else { 1624 WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1625 } 1626 } 1627 1628 static int vcn_v4_0_limit_sched(struct amdgpu_cs_parser *p, 1629 struct amdgpu_job *job) 1630 { 1631 struct drm_gpu_scheduler **scheds; 1632 1633 /* The create msg must be in the first IB submitted */ 1634 if (atomic_read(&job->base.entity->fence_seq)) 1635 return -EINVAL; 1636 1637 /* if VCN0 is harvested, we can't support AV1 */ 1638 if (p->adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) 1639 return -EINVAL; 1640 1641 scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_ENC] 1642 [AMDGPU_RING_PRIO_0].sched; 1643 drm_sched_entity_modify_sched(job->base.entity, scheds, 1); 1644 return 0; 1645 } 1646 1647 static int vcn_v4_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job, 1648 uint64_t addr) 1649 { 1650 struct ttm_operation_ctx ctx = { false, false }; 1651 struct amdgpu_bo_va_mapping *map; 1652 uint32_t *msg, num_buffers; 1653 struct amdgpu_bo *bo; 1654 uint64_t start, end; 1655 unsigned int i; 1656 void *ptr; 1657 int r; 1658 1659 addr &= AMDGPU_GMC_HOLE_MASK; 1660 r = amdgpu_cs_find_mapping(p, addr, &bo, &map); 1661 if (r) { 1662 DRM_ERROR("Can't find BO for addr 0x%08llx\n", addr); 1663 return r; 1664 } 1665 1666 start = map->start * AMDGPU_GPU_PAGE_SIZE; 1667 end = (map->last + 1) * AMDGPU_GPU_PAGE_SIZE; 1668 if (addr & 0x7) { 1669 DRM_ERROR("VCN messages must be 8 byte aligned!\n"); 1670 return -EINVAL; 1671 } 1672 1673 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1674 amdgpu_bo_placement_from_domain(bo, bo->allowed_domains); 1675 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 1676 if (r) { 1677 DRM_ERROR("Failed validating the VCN message BO (%d)!\n", r); 1678 return r; 1679 } 1680 1681 r = amdgpu_bo_kmap(bo, &ptr); 1682 if (r) { 1683 DRM_ERROR("Failed mapping the VCN message (%d)!\n", r); 1684 return r; 1685 } 1686 1687 msg = ptr + addr - start; 1688 1689 /* Check length */ 1690 if (msg[1] > end - addr) { 1691 r = -EINVAL; 1692 goto out; 1693 } 1694 1695 if (msg[3] != RDECODE_MSG_CREATE) 1696 goto out; 1697 1698 num_buffers = msg[2]; 1699 for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) { 1700 uint32_t offset, size, *create; 1701 1702 if (msg[0] != RDECODE_MESSAGE_CREATE) 1703 continue; 1704 1705 offset = msg[1]; 1706 size = msg[2]; 1707 1708 if (offset + size > end) { 1709 r = -EINVAL; 1710 goto out; 1711 } 1712 1713 create = ptr + addr + offset - start; 1714 1715 /* H264, HEVC and VP9 can run on any instance */ 1716 if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11) 1717 continue; 1718 1719 r = vcn_v4_0_limit_sched(p, job); 1720 if (r) 1721 goto out; 1722 } 1723 1724 out: 1725 amdgpu_bo_kunmap(bo); 1726 return r; 1727 } 1728 1729 #define RADEON_VCN_ENGINE_TYPE_ENCODE (0x00000002) 1730 #define RADEON_VCN_ENGINE_TYPE_DECODE (0x00000003) 1731 1732 #define RADEON_VCN_ENGINE_INFO (0x30000001) 1733 #define RADEON_VCN_ENGINE_INFO_MAX_OFFSET 16 1734 1735 #define RENCODE_ENCODE_STANDARD_AV1 2 1736 #define RENCODE_IB_PARAM_SESSION_INIT 0x00000003 1737 #define RENCODE_IB_PARAM_SESSION_INIT_MAX_OFFSET 64 1738 1739 /* return the offset in ib if id is found, -1 otherwise 1740 * to speed up the searching we only search upto max_offset 1741 */ 1742 static int vcn_v4_0_enc_find_ib_param(struct amdgpu_ib *ib, uint32_t id, int max_offset) 1743 { 1744 int i; 1745 1746 for (i = 0; i < ib->length_dw && i < max_offset && ib->ptr[i] >= 8; i += ib->ptr[i]/4) { 1747 if (ib->ptr[i + 1] == id) 1748 return i; 1749 } 1750 return -1; 1751 } 1752 1753 static int vcn_v4_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, 1754 struct amdgpu_job *job, 1755 struct amdgpu_ib *ib) 1756 { 1757 struct amdgpu_ring *ring = amdgpu_job_ring(job); 1758 struct amdgpu_vcn_decode_buffer *decode_buffer; 1759 uint64_t addr; 1760 uint32_t val; 1761 int idx; 1762 1763 /* The first instance can decode anything */ 1764 if (!ring->me) 1765 return 0; 1766 1767 /* RADEON_VCN_ENGINE_INFO is at the top of ib block */ 1768 idx = vcn_v4_0_enc_find_ib_param(ib, RADEON_VCN_ENGINE_INFO, 1769 RADEON_VCN_ENGINE_INFO_MAX_OFFSET); 1770 if (idx < 0) /* engine info is missing */ 1771 return 0; 1772 1773 val = amdgpu_ib_get_value(ib, idx + 2); /* RADEON_VCN_ENGINE_TYPE */ 1774 if (val == RADEON_VCN_ENGINE_TYPE_DECODE) { 1775 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&ib->ptr[idx + 6]; 1776 1777 if (!(decode_buffer->valid_buf_flag & 0x1)) 1778 return 0; 1779 1780 addr = ((u64)decode_buffer->msg_buffer_address_hi) << 32 | 1781 decode_buffer->msg_buffer_address_lo; 1782 return vcn_v4_0_dec_msg(p, job, addr); 1783 } else if (val == RADEON_VCN_ENGINE_TYPE_ENCODE) { 1784 idx = vcn_v4_0_enc_find_ib_param(ib, RENCODE_IB_PARAM_SESSION_INIT, 1785 RENCODE_IB_PARAM_SESSION_INIT_MAX_OFFSET); 1786 if (idx >= 0 && ib->ptr[idx + 2] == RENCODE_ENCODE_STANDARD_AV1) 1787 return vcn_v4_0_limit_sched(p, job); 1788 } 1789 return 0; 1790 } 1791 1792 static const struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = { 1793 .type = AMDGPU_RING_TYPE_VCN_ENC, 1794 .align_mask = 0x3f, 1795 .nop = VCN_ENC_CMD_NO_OP, 1796 .vmhub = AMDGPU_MMHUB_0, 1797 .get_rptr = vcn_v4_0_unified_ring_get_rptr, 1798 .get_wptr = vcn_v4_0_unified_ring_get_wptr, 1799 .set_wptr = vcn_v4_0_unified_ring_set_wptr, 1800 .patch_cs_in_place = vcn_v4_0_ring_patch_cs_in_place, 1801 .emit_frame_size = 1802 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1803 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1804 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1805 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1806 1, /* vcn_v2_0_enc_ring_insert_end */ 1807 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1808 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1809 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1810 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 1811 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1812 .test_ib = amdgpu_vcn_unified_ring_test_ib, 1813 .insert_nop = amdgpu_ring_insert_nop, 1814 .insert_end = vcn_v2_0_enc_ring_insert_end, 1815 .pad_ib = amdgpu_ring_generic_pad_ib, 1816 .begin_use = amdgpu_vcn_ring_begin_use, 1817 .end_use = amdgpu_vcn_ring_end_use, 1818 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 1819 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 1820 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1821 }; 1822 1823 /** 1824 * vcn_v4_0_set_unified_ring_funcs - set unified ring functions 1825 * 1826 * @adev: amdgpu_device pointer 1827 * 1828 * Set unified ring functions 1829 */ 1830 static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev) 1831 { 1832 int i; 1833 1834 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1835 if (adev->vcn.harvest_config & (1 << i)) 1836 continue; 1837 1838 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_unified_ring_vm_funcs; 1839 adev->vcn.inst[i].ring_enc[0].me = i; 1840 1841 DRM_INFO("VCN(%d) encode/decode are enabled in VM mode\n", i); 1842 } 1843 } 1844 1845 /** 1846 * vcn_v4_0_is_idle - check VCN block is idle 1847 * 1848 * @handle: amdgpu_device pointer 1849 * 1850 * Check whether VCN block is idle 1851 */ 1852 static bool vcn_v4_0_is_idle(void *handle) 1853 { 1854 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1855 int i, ret = 1; 1856 1857 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1858 if (adev->vcn.harvest_config & (1 << i)) 1859 continue; 1860 1861 ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE); 1862 } 1863 1864 return ret; 1865 } 1866 1867 /** 1868 * vcn_v4_0_wait_for_idle - wait for VCN block idle 1869 * 1870 * @handle: amdgpu_device pointer 1871 * 1872 * Wait for VCN block idle 1873 */ 1874 static int vcn_v4_0_wait_for_idle(void *handle) 1875 { 1876 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1877 int i, ret = 0; 1878 1879 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1880 if (adev->vcn.harvest_config & (1 << i)) 1881 continue; 1882 1883 ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 1884 UVD_STATUS__IDLE); 1885 if (ret) 1886 return ret; 1887 } 1888 1889 return ret; 1890 } 1891 1892 /** 1893 * vcn_v4_0_set_clockgating_state - set VCN block clockgating state 1894 * 1895 * @handle: amdgpu_device pointer 1896 * @state: clock gating state 1897 * 1898 * Set VCN block clockgating state 1899 */ 1900 static int vcn_v4_0_set_clockgating_state(void *handle, enum amd_clockgating_state state) 1901 { 1902 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1903 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 1904 int i; 1905 1906 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1907 if (adev->vcn.harvest_config & (1 << i)) 1908 continue; 1909 1910 if (enable) { 1911 if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE) 1912 return -EBUSY; 1913 vcn_v4_0_enable_clock_gating(adev, i); 1914 } else { 1915 vcn_v4_0_disable_clock_gating(adev, i); 1916 } 1917 } 1918 1919 return 0; 1920 } 1921 1922 /** 1923 * vcn_v4_0_set_powergating_state - set VCN block powergating state 1924 * 1925 * @handle: amdgpu_device pointer 1926 * @state: power gating state 1927 * 1928 * Set VCN block powergating state 1929 */ 1930 static int vcn_v4_0_set_powergating_state(void *handle, enum amd_powergating_state state) 1931 { 1932 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1933 int ret; 1934 1935 /* for SRIOV, guest should not control VCN Power-gating 1936 * MMSCH FW should control Power-gating and clock-gating 1937 * guest should avoid touching CGC and PG 1938 */ 1939 if (amdgpu_sriov_vf(adev)) { 1940 adev->vcn.cur_state = AMD_PG_STATE_UNGATE; 1941 return 0; 1942 } 1943 1944 if(state == adev->vcn.cur_state) 1945 return 0; 1946 1947 if (state == AMD_PG_STATE_GATE) 1948 ret = vcn_v4_0_stop(adev); 1949 else 1950 ret = vcn_v4_0_start(adev); 1951 1952 if(!ret) 1953 adev->vcn.cur_state = state; 1954 1955 return ret; 1956 } 1957 1958 /** 1959 * vcn_v4_0_set_interrupt_state - set VCN block interrupt state 1960 * 1961 * @adev: amdgpu_device pointer 1962 * @source: interrupt sources 1963 * @type: interrupt types 1964 * @state: interrupt states 1965 * 1966 * Set VCN block interrupt state 1967 */ 1968 static int vcn_v4_0_set_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 1969 unsigned type, enum amdgpu_interrupt_state state) 1970 { 1971 return 0; 1972 } 1973 1974 /** 1975 * vcn_v4_0_process_interrupt - process VCN block interrupt 1976 * 1977 * @adev: amdgpu_device pointer 1978 * @source: interrupt sources 1979 * @entry: interrupt entry from clients and sources 1980 * 1981 * Process VCN block interrupt 1982 */ 1983 static int vcn_v4_0_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 1984 struct amdgpu_iv_entry *entry) 1985 { 1986 uint32_t ip_instance; 1987 1988 switch (entry->client_id) { 1989 case SOC15_IH_CLIENTID_VCN: 1990 ip_instance = 0; 1991 break; 1992 case SOC15_IH_CLIENTID_VCN1: 1993 ip_instance = 1; 1994 break; 1995 default: 1996 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 1997 return 0; 1998 } 1999 2000 DRM_DEBUG("IH: VCN TRAP\n"); 2001 2002 switch (entry->src_id) { 2003 case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 2004 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 2005 break; 2006 case VCN_4_0__SRCID_UVD_POISON: 2007 amdgpu_vcn_process_poison_irq(adev, source, entry); 2008 break; 2009 default: 2010 DRM_ERROR("Unhandled interrupt: %d %d\n", 2011 entry->src_id, entry->src_data[0]); 2012 break; 2013 } 2014 2015 return 0; 2016 } 2017 2018 static const struct amdgpu_irq_src_funcs vcn_v4_0_irq_funcs = { 2019 .set = vcn_v4_0_set_interrupt_state, 2020 .process = vcn_v4_0_process_interrupt, 2021 }; 2022 2023 /** 2024 * vcn_v4_0_set_irq_funcs - set VCN block interrupt irq functions 2025 * 2026 * @adev: amdgpu_device pointer 2027 * 2028 * Set VCN block interrupt irq functions 2029 */ 2030 static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev) 2031 { 2032 int i; 2033 2034 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2035 if (adev->vcn.harvest_config & (1 << i)) 2036 continue; 2037 2038 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1; 2039 adev->vcn.inst[i].irq.funcs = &vcn_v4_0_irq_funcs; 2040 } 2041 } 2042 2043 static const struct amd_ip_funcs vcn_v4_0_ip_funcs = { 2044 .name = "vcn_v4_0", 2045 .early_init = vcn_v4_0_early_init, 2046 .late_init = NULL, 2047 .sw_init = vcn_v4_0_sw_init, 2048 .sw_fini = vcn_v4_0_sw_fini, 2049 .hw_init = vcn_v4_0_hw_init, 2050 .hw_fini = vcn_v4_0_hw_fini, 2051 .suspend = vcn_v4_0_suspend, 2052 .resume = vcn_v4_0_resume, 2053 .is_idle = vcn_v4_0_is_idle, 2054 .wait_for_idle = vcn_v4_0_wait_for_idle, 2055 .check_soft_reset = NULL, 2056 .pre_soft_reset = NULL, 2057 .soft_reset = NULL, 2058 .post_soft_reset = NULL, 2059 .set_clockgating_state = vcn_v4_0_set_clockgating_state, 2060 .set_powergating_state = vcn_v4_0_set_powergating_state, 2061 }; 2062 2063 const struct amdgpu_ip_block_version vcn_v4_0_ip_block = 2064 { 2065 .type = AMD_IP_BLOCK_TYPE_VCN, 2066 .major = 4, 2067 .minor = 0, 2068 .rev = 0, 2069 .funcs = &vcn_v4_0_ip_funcs, 2070 }; 2071 2072 static uint32_t vcn_v4_0_query_poison_by_instance(struct amdgpu_device *adev, 2073 uint32_t instance, uint32_t sub_block) 2074 { 2075 uint32_t poison_stat = 0, reg_value = 0; 2076 2077 switch (sub_block) { 2078 case AMDGPU_VCN_V4_0_VCPU_VCODEC: 2079 reg_value = RREG32_SOC15(VCN, instance, regUVD_RAS_VCPU_VCODEC_STATUS); 2080 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF); 2081 break; 2082 default: 2083 break; 2084 } 2085 2086 if (poison_stat) 2087 dev_info(adev->dev, "Poison detected in VCN%d, sub_block%d\n", 2088 instance, sub_block); 2089 2090 return poison_stat; 2091 } 2092 2093 static bool vcn_v4_0_query_ras_poison_status(struct amdgpu_device *adev) 2094 { 2095 uint32_t inst, sub; 2096 uint32_t poison_stat = 0; 2097 2098 for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++) 2099 for (sub = 0; sub < AMDGPU_VCN_V4_0_MAX_SUB_BLOCK; sub++) 2100 poison_stat += 2101 vcn_v4_0_query_poison_by_instance(adev, inst, sub); 2102 2103 return !!poison_stat; 2104 } 2105 2106 const struct amdgpu_ras_block_hw_ops vcn_v4_0_ras_hw_ops = { 2107 .query_poison_status = vcn_v4_0_query_ras_poison_status, 2108 }; 2109 2110 static struct amdgpu_vcn_ras vcn_v4_0_ras = { 2111 .ras_block = { 2112 .hw_ops = &vcn_v4_0_ras_hw_ops, 2113 }, 2114 }; 2115 2116 static void vcn_v4_0_set_ras_funcs(struct amdgpu_device *adev) 2117 { 2118 switch (adev->ip_versions[VCN_HWIP][0]) { 2119 case IP_VERSION(4, 0, 0): 2120 adev->vcn.ras = &vcn_v4_0_ras; 2121 break; 2122 default: 2123 break; 2124 } 2125 2126 amdgpu_vcn_set_ras_funcs(adev); 2127 } 2128