1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_vcn.h" 27 #include "amdgpu_pm.h" 28 #include "amdgpu_cs.h" 29 #include "soc15.h" 30 #include "soc15d.h" 31 #include "soc15_hw_ip.h" 32 #include "vcn_v2_0.h" 33 #include "mmsch_v4_0.h" 34 #include "vcn_v4_0.h" 35 36 #include "vcn/vcn_4_0_0_offset.h" 37 #include "vcn/vcn_4_0_0_sh_mask.h" 38 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 39 40 #include <drm/drm_drv.h> 41 42 #define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL 43 #define mmUVD_DPG_LMA_CTL_BASE_IDX regUVD_DPG_LMA_CTL_BASE_IDX 44 #define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA 45 #define mmUVD_DPG_LMA_DATA_BASE_IDX regUVD_DPG_LMA_DATA_BASE_IDX 46 47 #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00 48 #define VCN1_VID_SOC_ADDRESS_3_0 0x48300 49 50 #define VCN_HARVEST_MMSCH 0 51 52 #define RDECODE_MSG_CREATE 0x00000000 53 #define RDECODE_MESSAGE_CREATE 0x00000001 54 55 static int amdgpu_ih_clientid_vcns[] = { 56 SOC15_IH_CLIENTID_VCN, 57 SOC15_IH_CLIENTID_VCN1 58 }; 59 60 static int vcn_v4_0_start_sriov(struct amdgpu_device *adev); 61 static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev); 62 static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev); 63 static int vcn_v4_0_set_powergating_state(void *handle, 64 enum amd_powergating_state state); 65 static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev, 66 int inst_idx, struct dpg_pause_state *new_state); 67 static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring); 68 static void vcn_v4_0_set_ras_funcs(struct amdgpu_device *adev); 69 70 /** 71 * vcn_v4_0_early_init - set function pointers 72 * 73 * @handle: amdgpu_device pointer 74 * 75 * Set ring and irq function pointers 76 */ 77 static int vcn_v4_0_early_init(void *handle) 78 { 79 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 80 81 if (amdgpu_sriov_vf(adev)) 82 adev->vcn.harvest_config = VCN_HARVEST_MMSCH; 83 84 /* re-use enc ring as unified ring */ 85 adev->vcn.num_enc_rings = 1; 86 87 vcn_v4_0_set_unified_ring_funcs(adev); 88 vcn_v4_0_set_irq_funcs(adev); 89 vcn_v4_0_set_ras_funcs(adev); 90 91 return 0; 92 } 93 94 /** 95 * vcn_v4_0_sw_init - sw init for VCN block 96 * 97 * @handle: amdgpu_device pointer 98 * 99 * Load firmware and sw initialization 100 */ 101 static int vcn_v4_0_sw_init(void *handle) 102 { 103 struct amdgpu_ring *ring; 104 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 105 int i, r; 106 107 r = amdgpu_vcn_sw_init(adev); 108 if (r) 109 return r; 110 111 amdgpu_vcn_setup_ucode(adev); 112 113 r = amdgpu_vcn_resume(adev); 114 if (r) 115 return r; 116 117 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 118 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 119 120 if (adev->vcn.harvest_config & (1 << i)) 121 continue; 122 123 atomic_set(&adev->vcn.inst[i].sched_score, 0); 124 125 /* VCN UNIFIED TRAP */ 126 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 127 VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); 128 if (r) 129 return r; 130 131 /* VCN POISON TRAP */ 132 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 133 VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[i].irq); 134 if (r) 135 return r; 136 137 ring = &adev->vcn.inst[i].ring_enc[0]; 138 ring->use_doorbell = true; 139 if (amdgpu_sriov_vf(adev)) 140 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + i * (adev->vcn.num_enc_rings + 1) + 1; 141 else 142 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + 8 * i; 143 144 sprintf(ring->name, "vcn_unified_%d", i); 145 146 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 147 AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score); 148 if (r) 149 return r; 150 151 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 152 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); 153 fw_shared->sq.is_enabled = 1; 154 155 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG); 156 fw_shared->smu_dpm_interface.smu_interface_type = (adev->flags & AMD_IS_APU) ? 157 AMDGPU_VCN_SMU_DPM_INTERFACE_APU : AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU; 158 159 if (amdgpu_sriov_vf(adev)) 160 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG); 161 162 if (amdgpu_vcnfw_log) 163 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]); 164 } 165 166 if (amdgpu_sriov_vf(adev)) { 167 r = amdgpu_virt_alloc_mm_table(adev); 168 if (r) 169 return r; 170 } 171 172 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 173 adev->vcn.pause_dpg_mode = vcn_v4_0_pause_dpg_mode; 174 175 return 0; 176 } 177 178 /** 179 * vcn_v4_0_sw_fini - sw fini for VCN block 180 * 181 * @handle: amdgpu_device pointer 182 * 183 * VCN suspend and free up sw allocation 184 */ 185 static int vcn_v4_0_sw_fini(void *handle) 186 { 187 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 188 int i, r, idx; 189 190 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 191 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 192 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 193 194 if (adev->vcn.harvest_config & (1 << i)) 195 continue; 196 197 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 198 fw_shared->present_flag_0 = 0; 199 fw_shared->sq.is_enabled = 0; 200 } 201 202 drm_dev_exit(idx); 203 } 204 205 if (amdgpu_sriov_vf(adev)) 206 amdgpu_virt_free_mm_table(adev); 207 208 r = amdgpu_vcn_suspend(adev); 209 if (r) 210 return r; 211 212 r = amdgpu_vcn_sw_fini(adev); 213 214 return r; 215 } 216 217 /** 218 * vcn_v4_0_hw_init - start and test VCN block 219 * 220 * @handle: amdgpu_device pointer 221 * 222 * Initialize the hardware, boot up the VCPU and do some testing 223 */ 224 static int vcn_v4_0_hw_init(void *handle) 225 { 226 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 227 struct amdgpu_ring *ring; 228 int i, r; 229 230 if (amdgpu_sriov_vf(adev)) { 231 r = vcn_v4_0_start_sriov(adev); 232 if (r) 233 goto done; 234 235 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 236 if (adev->vcn.harvest_config & (1 << i)) 237 continue; 238 239 ring = &adev->vcn.inst[i].ring_enc[0]; 240 if (amdgpu_vcn_is_disabled_vcn(adev, VCN_ENCODE_RING, i)) { 241 ring->sched.ready = false; 242 ring->no_scheduler = true; 243 dev_info(adev->dev, "ring %s is disabled by hypervisor\n", ring->name); 244 } else { 245 ring->wptr = 0; 246 ring->wptr_old = 0; 247 vcn_v4_0_unified_ring_set_wptr(ring); 248 ring->sched.ready = true; 249 } 250 } 251 } else { 252 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 253 if (adev->vcn.harvest_config & (1 << i)) 254 continue; 255 256 ring = &adev->vcn.inst[i].ring_enc[0]; 257 258 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 259 ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i); 260 261 r = amdgpu_ring_test_helper(ring); 262 if (r) 263 goto done; 264 265 } 266 } 267 268 done: 269 if (!r) 270 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 271 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 272 273 return r; 274 } 275 276 /** 277 * vcn_v4_0_hw_fini - stop the hardware block 278 * 279 * @handle: amdgpu_device pointer 280 * 281 * Stop the VCN block, mark ring as not ready any more 282 */ 283 static int vcn_v4_0_hw_fini(void *handle) 284 { 285 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 286 int i; 287 288 cancel_delayed_work_sync(&adev->vcn.idle_work); 289 290 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 291 if (adev->vcn.harvest_config & (1 << i)) 292 continue; 293 if (!amdgpu_sriov_vf(adev)) { 294 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 295 (adev->vcn.cur_state != AMD_PG_STATE_GATE && 296 RREG32_SOC15(VCN, i, regUVD_STATUS))) { 297 vcn_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 298 } 299 } 300 301 amdgpu_irq_put(adev, &adev->vcn.inst[i].irq, 0); 302 } 303 304 return 0; 305 } 306 307 /** 308 * vcn_v4_0_suspend - suspend VCN block 309 * 310 * @handle: amdgpu_device pointer 311 * 312 * HW fini and suspend VCN block 313 */ 314 static int vcn_v4_0_suspend(void *handle) 315 { 316 int r; 317 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 318 319 r = vcn_v4_0_hw_fini(adev); 320 if (r) 321 return r; 322 323 r = amdgpu_vcn_suspend(adev); 324 325 return r; 326 } 327 328 /** 329 * vcn_v4_0_resume - resume VCN block 330 * 331 * @handle: amdgpu_device pointer 332 * 333 * Resume firmware and hw init VCN block 334 */ 335 static int vcn_v4_0_resume(void *handle) 336 { 337 int r; 338 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 339 340 r = amdgpu_vcn_resume(adev); 341 if (r) 342 return r; 343 344 r = vcn_v4_0_hw_init(adev); 345 346 return r; 347 } 348 349 /** 350 * vcn_v4_0_mc_resume - memory controller programming 351 * 352 * @adev: amdgpu_device pointer 353 * @inst: instance number 354 * 355 * Let the VCN memory controller know it's offsets 356 */ 357 static void vcn_v4_0_mc_resume(struct amdgpu_device *adev, int inst) 358 { 359 uint32_t offset, size; 360 const struct common_firmware_header *hdr; 361 362 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 363 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 364 365 /* cache window 0: fw */ 366 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 367 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 368 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 369 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 370 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 371 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0); 372 offset = 0; 373 } else { 374 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 375 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 376 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 377 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 378 offset = size; 379 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 380 } 381 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size); 382 383 /* cache window 1: stack */ 384 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 385 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 386 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 387 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 388 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0); 389 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 390 391 /* cache window 2: context */ 392 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 393 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 394 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 395 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 396 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0); 397 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 398 399 /* non-cache window */ 400 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 401 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 402 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 403 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 404 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); 405 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0, 406 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 407 } 408 409 /** 410 * vcn_v4_0_mc_resume_dpg_mode - memory controller programming for dpg mode 411 * 412 * @adev: amdgpu_device pointer 413 * @inst_idx: instance number index 414 * @indirect: indirectly write sram 415 * 416 * Let the VCN memory controller know it's offsets with dpg mode 417 */ 418 static void vcn_v4_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 419 { 420 uint32_t offset, size; 421 const struct common_firmware_header *hdr; 422 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 423 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 424 425 /* cache window 0: fw */ 426 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 427 if (!indirect) { 428 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 429 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 430 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); 431 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 432 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 433 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); 434 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 435 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 436 } else { 437 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 438 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 439 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 440 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 441 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 442 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 443 } 444 offset = 0; 445 } else { 446 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 447 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 448 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 449 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 450 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 451 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 452 offset = size; 453 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 454 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 455 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 456 } 457 458 if (!indirect) 459 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 460 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 461 else 462 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 463 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 464 465 /* cache window 1: stack */ 466 if (!indirect) { 467 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 468 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 469 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 470 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 471 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 472 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 473 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 474 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 475 } else { 476 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 477 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 478 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 479 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 480 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 481 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 482 } 483 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 484 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 485 486 /* cache window 2: context */ 487 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 488 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 489 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 490 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 491 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 492 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 493 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 494 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 495 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 496 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 497 498 /* non-cache window */ 499 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 500 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 501 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 502 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 503 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 504 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 505 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 506 VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 507 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 508 VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0), 509 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); 510 511 /* VCN global tiling registers */ 512 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 513 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 514 } 515 516 /** 517 * vcn_v4_0_disable_static_power_gating - disable VCN static power gating 518 * 519 * @adev: amdgpu_device pointer 520 * @inst: instance number 521 * 522 * Disable static power gating for VCN block 523 */ 524 static void vcn_v4_0_disable_static_power_gating(struct amdgpu_device *adev, int inst) 525 { 526 uint32_t data = 0; 527 528 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 529 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 530 | 1 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT 531 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 532 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 533 | 2 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT 534 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 535 | 2 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT 536 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 537 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 538 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 539 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 540 | 2 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT 541 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 542 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 543 544 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data); 545 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, 546 UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF); 547 } else { 548 uint32_t value; 549 550 value = (inst) ? 0x2200800 : 0; 551 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 552 | 1 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT 553 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 554 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 555 | 1 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT 556 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 557 | 1 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT 558 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 559 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 560 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 561 | 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 562 | 1 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT 563 | 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 564 | 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 565 566 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data); 567 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, value, 0x3F3FFFFF); 568 } 569 570 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 571 data &= ~0x103; 572 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 573 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 574 UVD_POWER_STATUS__UVD_PG_EN_MASK; 575 576 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 577 578 return; 579 } 580 581 /** 582 * vcn_v4_0_enable_static_power_gating - enable VCN static power gating 583 * 584 * @adev: amdgpu_device pointer 585 * @inst: instance number 586 * 587 * Enable static power gating for VCN block 588 */ 589 static void vcn_v4_0_enable_static_power_gating(struct amdgpu_device *adev, int inst) 590 { 591 uint32_t data; 592 593 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 594 /* Before power off, this indicator has to be turned on */ 595 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 596 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 597 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 598 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 599 600 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 601 | 2 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT 602 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 603 | 2 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT 604 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 605 | 2 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT 606 | 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 607 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 608 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 609 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 610 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 611 | 2 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT 612 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 613 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 614 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data); 615 616 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 617 | 2 << UVD_PGFSM_STATUS__UVDS_PWR_STATUS__SHIFT 618 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 619 | 2 << UVD_PGFSM_STATUS__UVDTC_PWR_STATUS__SHIFT 620 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 621 | 2 << UVD_PGFSM_STATUS__UVDTA_PWR_STATUS__SHIFT 622 | 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT 623 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 624 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 625 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 626 | 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT 627 | 2 << UVD_PGFSM_STATUS__UVDTB_PWR_STATUS__SHIFT 628 | 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT 629 | 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT); 630 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, data, 0x3F3FFFFF); 631 } 632 633 return; 634 } 635 636 /** 637 * vcn_v4_0_disable_clock_gating - disable VCN clock gating 638 * 639 * @adev: amdgpu_device pointer 640 * @inst: instance number 641 * 642 * Disable clock gating for VCN block 643 */ 644 static void vcn_v4_0_disable_clock_gating(struct amdgpu_device *adev, int inst) 645 { 646 uint32_t data; 647 648 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 649 return; 650 651 /* VCN disable CGC */ 652 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 653 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 654 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 655 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 656 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 657 658 data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE); 659 data &= ~(UVD_CGC_GATE__SYS_MASK 660 | UVD_CGC_GATE__UDEC_MASK 661 | UVD_CGC_GATE__MPEG2_MASK 662 | UVD_CGC_GATE__REGS_MASK 663 | UVD_CGC_GATE__RBC_MASK 664 | UVD_CGC_GATE__LMI_MC_MASK 665 | UVD_CGC_GATE__LMI_UMC_MASK 666 | UVD_CGC_GATE__IDCT_MASK 667 | UVD_CGC_GATE__MPRD_MASK 668 | UVD_CGC_GATE__MPC_MASK 669 | UVD_CGC_GATE__LBSI_MASK 670 | UVD_CGC_GATE__LRBBM_MASK 671 | UVD_CGC_GATE__UDEC_RE_MASK 672 | UVD_CGC_GATE__UDEC_CM_MASK 673 | UVD_CGC_GATE__UDEC_IT_MASK 674 | UVD_CGC_GATE__UDEC_DB_MASK 675 | UVD_CGC_GATE__UDEC_MP_MASK 676 | UVD_CGC_GATE__WCB_MASK 677 | UVD_CGC_GATE__VCPU_MASK 678 | UVD_CGC_GATE__MMSCH_MASK); 679 680 WREG32_SOC15(VCN, inst, regUVD_CGC_GATE, data); 681 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF); 682 683 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 684 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 685 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 686 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 687 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 688 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 689 | UVD_CGC_CTRL__SYS_MODE_MASK 690 | UVD_CGC_CTRL__UDEC_MODE_MASK 691 | UVD_CGC_CTRL__MPEG2_MODE_MASK 692 | UVD_CGC_CTRL__REGS_MODE_MASK 693 | UVD_CGC_CTRL__RBC_MODE_MASK 694 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 695 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 696 | UVD_CGC_CTRL__IDCT_MODE_MASK 697 | UVD_CGC_CTRL__MPRD_MODE_MASK 698 | UVD_CGC_CTRL__MPC_MODE_MASK 699 | UVD_CGC_CTRL__LBSI_MODE_MASK 700 | UVD_CGC_CTRL__LRBBM_MODE_MASK 701 | UVD_CGC_CTRL__WCB_MODE_MASK 702 | UVD_CGC_CTRL__VCPU_MODE_MASK 703 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 704 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 705 706 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE); 707 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 708 | UVD_SUVD_CGC_GATE__SIT_MASK 709 | UVD_SUVD_CGC_GATE__SMP_MASK 710 | UVD_SUVD_CGC_GATE__SCM_MASK 711 | UVD_SUVD_CGC_GATE__SDB_MASK 712 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 713 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 714 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 715 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 716 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 717 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 718 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 719 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 720 | UVD_SUVD_CGC_GATE__SCLR_MASK 721 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 722 | UVD_SUVD_CGC_GATE__ENT_MASK 723 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 724 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 725 | UVD_SUVD_CGC_GATE__SITE_MASK 726 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 727 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 728 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 729 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 730 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 731 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE, data); 732 733 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); 734 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 735 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 736 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 737 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 738 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 739 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 740 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 741 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 742 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 743 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 744 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data); 745 } 746 747 /** 748 * vcn_v4_0_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode 749 * 750 * @adev: amdgpu_device pointer 751 * @sram_sel: sram select 752 * @inst_idx: instance number index 753 * @indirect: indirectly write sram 754 * 755 * Disable clock gating for VCN block with dpg mode 756 */ 757 static void vcn_v4_0_disable_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel, 758 int inst_idx, uint8_t indirect) 759 { 760 uint32_t reg_data = 0; 761 762 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 763 return; 764 765 /* enable sw clock gating control */ 766 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 767 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 768 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 769 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 770 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 771 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 772 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 773 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 774 UVD_CGC_CTRL__SYS_MODE_MASK | 775 UVD_CGC_CTRL__UDEC_MODE_MASK | 776 UVD_CGC_CTRL__MPEG2_MODE_MASK | 777 UVD_CGC_CTRL__REGS_MODE_MASK | 778 UVD_CGC_CTRL__RBC_MODE_MASK | 779 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 780 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 781 UVD_CGC_CTRL__IDCT_MODE_MASK | 782 UVD_CGC_CTRL__MPRD_MODE_MASK | 783 UVD_CGC_CTRL__MPC_MODE_MASK | 784 UVD_CGC_CTRL__LBSI_MODE_MASK | 785 UVD_CGC_CTRL__LRBBM_MODE_MASK | 786 UVD_CGC_CTRL__WCB_MODE_MASK | 787 UVD_CGC_CTRL__VCPU_MODE_MASK); 788 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 789 VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); 790 791 /* turn off clock gating */ 792 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 793 VCN, inst_idx, regUVD_CGC_GATE), 0, sram_sel, indirect); 794 795 /* turn on SUVD clock gating */ 796 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 797 VCN, inst_idx, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 798 799 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 800 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 801 VCN, inst_idx, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 802 } 803 804 /** 805 * vcn_v4_0_enable_clock_gating - enable VCN clock gating 806 * 807 * @adev: amdgpu_device pointer 808 * @inst: instance number 809 * 810 * Enable clock gating for VCN block 811 */ 812 static void vcn_v4_0_enable_clock_gating(struct amdgpu_device *adev, int inst) 813 { 814 uint32_t data; 815 816 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 817 return; 818 819 /* enable VCN CGC */ 820 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 821 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 822 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 823 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 824 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 825 826 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 827 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 828 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 829 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 830 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 831 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 832 | UVD_CGC_CTRL__SYS_MODE_MASK 833 | UVD_CGC_CTRL__UDEC_MODE_MASK 834 | UVD_CGC_CTRL__MPEG2_MODE_MASK 835 | UVD_CGC_CTRL__REGS_MODE_MASK 836 | UVD_CGC_CTRL__RBC_MODE_MASK 837 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 838 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 839 | UVD_CGC_CTRL__IDCT_MODE_MASK 840 | UVD_CGC_CTRL__MPRD_MODE_MASK 841 | UVD_CGC_CTRL__MPC_MODE_MASK 842 | UVD_CGC_CTRL__LBSI_MODE_MASK 843 | UVD_CGC_CTRL__LRBBM_MODE_MASK 844 | UVD_CGC_CTRL__WCB_MODE_MASK 845 | UVD_CGC_CTRL__VCPU_MODE_MASK 846 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 847 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 848 849 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); 850 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 851 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 852 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 853 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 854 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 855 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 856 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 857 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 858 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 859 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 860 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data); 861 862 return; 863 } 864 865 static void vcn_v4_0_enable_ras(struct amdgpu_device *adev, int inst_idx, 866 bool indirect) 867 { 868 uint32_t tmp; 869 870 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) 871 return; 872 873 tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK | 874 VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK | 875 VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK | 876 VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK; 877 WREG32_SOC15_DPG_MODE(inst_idx, 878 SOC15_DPG_MODE_OFFSET(VCN, 0, regVCN_RAS_CNTL), 879 tmp, 0, indirect); 880 881 tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK; 882 WREG32_SOC15_DPG_MODE(inst_idx, 883 SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_SYS_INT_EN), 884 tmp, 0, indirect); 885 } 886 887 /** 888 * vcn_v4_0_start_dpg_mode - VCN start with dpg mode 889 * 890 * @adev: amdgpu_device pointer 891 * @inst_idx: instance number index 892 * @indirect: indirectly write sram 893 * 894 * Start VCN block with dpg mode 895 */ 896 static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 897 { 898 volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 899 struct amdgpu_ring *ring; 900 uint32_t tmp; 901 902 /* disable register anti-hang mechanism */ 903 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1, 904 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 905 /* enable dynamic power gating mode */ 906 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS); 907 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 908 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 909 WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp); 910 911 if (indirect) 912 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 913 914 /* enable clock gating */ 915 vcn_v4_0_disable_clock_gating_dpg_mode(adev, 0, inst_idx, indirect); 916 917 /* enable VCPU clock */ 918 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 919 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK; 920 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 921 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 922 923 /* disable master interupt */ 924 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 925 VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect); 926 927 /* setup regUVD_LMI_CTRL */ 928 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 929 UVD_LMI_CTRL__REQ_MODE_MASK | 930 UVD_LMI_CTRL__CRC_RESET_MASK | 931 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 932 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 933 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 934 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 935 0x00100000L); 936 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 937 VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect); 938 939 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 940 VCN, inst_idx, regUVD_MPC_CNTL), 941 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 942 943 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 944 VCN, inst_idx, regUVD_MPC_SET_MUXA0), 945 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 946 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 947 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 948 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 949 950 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 951 VCN, inst_idx, regUVD_MPC_SET_MUXB0), 952 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 953 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 954 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 955 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 956 957 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 958 VCN, inst_idx, regUVD_MPC_SET_MUX), 959 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 960 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 961 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 962 963 vcn_v4_0_mc_resume_dpg_mode(adev, inst_idx, indirect); 964 965 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 966 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 967 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 968 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 969 970 /* enable LMI MC and UMC channels */ 971 tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT; 972 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 973 VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect); 974 975 vcn_v4_0_enable_ras(adev, inst_idx, indirect); 976 977 /* enable master interrupt */ 978 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 979 VCN, inst_idx, regUVD_MASTINT_EN), 980 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 981 982 983 if (indirect) 984 psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, 985 (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr - 986 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr)); 987 988 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 989 990 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr); 991 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 992 WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4); 993 994 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 995 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 996 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 997 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 998 WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0); 999 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0); 1000 1001 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR); 1002 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp); 1003 ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 1004 1005 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 1006 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 1007 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 1008 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 1009 1010 WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL, 1011 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 1012 VCN_RB1_DB_CTRL__EN_MASK); 1013 1014 return 0; 1015 } 1016 1017 1018 /** 1019 * vcn_v4_0_start - VCN start 1020 * 1021 * @adev: amdgpu_device pointer 1022 * 1023 * Start VCN block 1024 */ 1025 static int vcn_v4_0_start(struct amdgpu_device *adev) 1026 { 1027 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1028 struct amdgpu_ring *ring; 1029 uint32_t tmp; 1030 int i, j, k, r; 1031 1032 if (adev->pm.dpm_enabled) 1033 amdgpu_dpm_enable_uvd(adev, true); 1034 1035 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1036 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1037 1038 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1039 r = vcn_v4_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram); 1040 continue; 1041 } 1042 1043 /* disable VCN power gating */ 1044 vcn_v4_0_disable_static_power_gating(adev, i); 1045 1046 /* set VCN status busy */ 1047 tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY; 1048 WREG32_SOC15(VCN, i, regUVD_STATUS, tmp); 1049 1050 /*SW clock gating */ 1051 vcn_v4_0_disable_clock_gating(adev, i); 1052 1053 /* enable VCPU clock */ 1054 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1055 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 1056 1057 /* disable master interrupt */ 1058 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0, 1059 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1060 1061 /* enable LMI MC and UMC channels */ 1062 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0, 1063 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1064 1065 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1066 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1067 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1068 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1069 1070 /* setup regUVD_LMI_CTRL */ 1071 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL); 1072 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp | 1073 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1074 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1075 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1076 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1077 1078 /* setup regUVD_MPC_CNTL */ 1079 tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL); 1080 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1081 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1082 WREG32_SOC15(VCN, i, regUVD_MPC_CNTL, tmp); 1083 1084 /* setup UVD_MPC_SET_MUXA0 */ 1085 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0, 1086 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1087 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1088 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1089 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1090 1091 /* setup UVD_MPC_SET_MUXB0 */ 1092 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXB0, 1093 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1094 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1095 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1096 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1097 1098 /* setup UVD_MPC_SET_MUX */ 1099 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX, 1100 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1101 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1102 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1103 1104 vcn_v4_0_mc_resume(adev, i); 1105 1106 /* VCN global tiling registers */ 1107 WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG, 1108 adev->gfx.config.gb_addr_config); 1109 1110 /* unblock VCPU register access */ 1111 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0, 1112 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1113 1114 /* release VCPU reset to boot */ 1115 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1116 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1117 1118 for (j = 0; j < 10; ++j) { 1119 uint32_t status; 1120 1121 for (k = 0; k < 100; ++k) { 1122 status = RREG32_SOC15(VCN, i, regUVD_STATUS); 1123 if (status & 2) 1124 break; 1125 mdelay(10); 1126 if (amdgpu_emu_mode==1) 1127 msleep(1); 1128 } 1129 1130 if (amdgpu_emu_mode==1) { 1131 r = -1; 1132 if (status & 2) { 1133 r = 0; 1134 break; 1135 } 1136 } else { 1137 r = 0; 1138 if (status & 2) 1139 break; 1140 1141 dev_err(adev->dev, "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i); 1142 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1143 UVD_VCPU_CNTL__BLK_RST_MASK, 1144 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1145 mdelay(10); 1146 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1147 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1148 1149 mdelay(10); 1150 r = -1; 1151 } 1152 } 1153 1154 if (r) { 1155 dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i); 1156 return r; 1157 } 1158 1159 /* enable master interrupt */ 1160 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 1161 UVD_MASTINT_EN__VCPU_EN_MASK, 1162 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1163 1164 /* clear the busy bit of VCN_STATUS */ 1165 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0, 1166 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1167 1168 ring = &adev->vcn.inst[i].ring_enc[0]; 1169 WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL, 1170 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 1171 VCN_RB1_DB_CTRL__EN_MASK); 1172 1173 WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr); 1174 WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1175 WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4); 1176 1177 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 1178 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 1179 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 1180 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 1181 WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0); 1182 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0); 1183 1184 tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR); 1185 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp); 1186 ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR); 1187 1188 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 1189 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 1190 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 1191 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 1192 } 1193 1194 return 0; 1195 } 1196 1197 static int vcn_v4_0_start_sriov(struct amdgpu_device *adev) 1198 { 1199 int i; 1200 struct amdgpu_ring *ring_enc; 1201 uint64_t cache_addr; 1202 uint64_t rb_enc_addr; 1203 uint64_t ctx_addr; 1204 uint32_t param, resp, expected; 1205 uint32_t offset, cache_size; 1206 uint32_t tmp, timeout; 1207 1208 struct amdgpu_mm_table *table = &adev->virt.mm_table; 1209 uint32_t *table_loc; 1210 uint32_t table_size; 1211 uint32_t size, size_dw; 1212 uint32_t init_status; 1213 uint32_t enabled_vcn; 1214 1215 struct mmsch_v4_0_cmd_direct_write 1216 direct_wt = { {0} }; 1217 struct mmsch_v4_0_cmd_direct_read_modify_write 1218 direct_rd_mod_wt = { {0} }; 1219 struct mmsch_v4_0_cmd_end end = { {0} }; 1220 struct mmsch_v4_0_init_header header; 1221 1222 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1223 volatile struct amdgpu_fw_shared_rb_setup *rb_setup; 1224 1225 direct_wt.cmd_header.command_type = 1226 MMSCH_COMMAND__DIRECT_REG_WRITE; 1227 direct_rd_mod_wt.cmd_header.command_type = 1228 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1229 end.cmd_header.command_type = 1230 MMSCH_COMMAND__END; 1231 1232 header.version = MMSCH_VERSION; 1233 header.total_size = sizeof(struct mmsch_v4_0_init_header) >> 2; 1234 for (i = 0; i < AMDGPU_MAX_VCN_INSTANCES; i++) { 1235 header.inst[i].init_status = 0; 1236 header.inst[i].table_offset = 0; 1237 header.inst[i].table_size = 0; 1238 } 1239 1240 table_loc = (uint32_t *)table->cpu_addr; 1241 table_loc += header.total_size; 1242 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1243 if (adev->vcn.harvest_config & (1 << i)) 1244 continue; 1245 1246 table_size = 0; 1247 1248 MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i, 1249 regUVD_STATUS), 1250 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 1251 1252 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 1253 1254 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1255 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1256 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1257 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo); 1258 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1259 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1260 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi); 1261 offset = 0; 1262 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1263 regUVD_VCPU_CACHE_OFFSET0), 1264 0); 1265 } else { 1266 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1267 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1268 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 1269 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1270 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1271 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 1272 offset = cache_size; 1273 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1274 regUVD_VCPU_CACHE_OFFSET0), 1275 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 1276 } 1277 1278 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1279 regUVD_VCPU_CACHE_SIZE0), 1280 cache_size); 1281 1282 cache_addr = adev->vcn.inst[i].gpu_addr + offset; 1283 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1284 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 1285 lower_32_bits(cache_addr)); 1286 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1287 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 1288 upper_32_bits(cache_addr)); 1289 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1290 regUVD_VCPU_CACHE_OFFSET1), 1291 0); 1292 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1293 regUVD_VCPU_CACHE_SIZE1), 1294 AMDGPU_VCN_STACK_SIZE); 1295 1296 cache_addr = adev->vcn.inst[i].gpu_addr + offset + 1297 AMDGPU_VCN_STACK_SIZE; 1298 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1299 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 1300 lower_32_bits(cache_addr)); 1301 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1302 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 1303 upper_32_bits(cache_addr)); 1304 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1305 regUVD_VCPU_CACHE_OFFSET2), 1306 0); 1307 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1308 regUVD_VCPU_CACHE_SIZE2), 1309 AMDGPU_VCN_CONTEXT_SIZE); 1310 1311 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1312 rb_setup = &fw_shared->rb_setup; 1313 1314 ring_enc = &adev->vcn.inst[i].ring_enc[0]; 1315 ring_enc->wptr = 0; 1316 rb_enc_addr = ring_enc->gpu_addr; 1317 1318 rb_setup->is_rb_enabled_flags |= RB_ENABLED; 1319 rb_setup->rb_addr_lo = lower_32_bits(rb_enc_addr); 1320 rb_setup->rb_addr_hi = upper_32_bits(rb_enc_addr); 1321 rb_setup->rb_size = ring_enc->ring_size / 4; 1322 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG); 1323 1324 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1325 regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 1326 lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); 1327 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1328 regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 1329 upper_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); 1330 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1331 regUVD_VCPU_NONCACHE_SIZE0), 1332 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 1333 1334 /* add end packet */ 1335 MMSCH_V4_0_INSERT_END(); 1336 1337 /* refine header */ 1338 header.inst[i].init_status = 0; 1339 header.inst[i].table_offset = header.total_size; 1340 header.inst[i].table_size = table_size; 1341 header.total_size += table_size; 1342 } 1343 1344 /* Update init table header in memory */ 1345 size = sizeof(struct mmsch_v4_0_init_header); 1346 table_loc = (uint32_t *)table->cpu_addr; 1347 memcpy((void *)table_loc, &header, size); 1348 1349 /* message MMSCH (in VCN[0]) to initialize this client 1350 * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr 1351 * of memory descriptor location 1352 */ 1353 ctx_addr = table->gpu_addr; 1354 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 1355 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 1356 1357 /* 2, update vmid of descriptor */ 1358 tmp = RREG32_SOC15(VCN, 0, regMMSCH_VF_VMID); 1359 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1360 /* use domain0 for MM scheduler */ 1361 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1362 WREG32_SOC15(VCN, 0, regMMSCH_VF_VMID, tmp); 1363 1364 /* 3, notify mmsch about the size of this descriptor */ 1365 size = header.total_size; 1366 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_SIZE, size); 1367 1368 /* 4, set resp to zero */ 1369 WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP, 0); 1370 1371 /* 5, kick off the initialization and wait until 1372 * MMSCH_VF_MAILBOX_RESP becomes non-zero 1373 */ 1374 param = 0x00000001; 1375 WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_HOST, param); 1376 tmp = 0; 1377 timeout = 1000; 1378 resp = 0; 1379 expected = MMSCH_VF_MAILBOX_RESP__OK; 1380 while (resp != expected) { 1381 resp = RREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP); 1382 if (resp != 0) 1383 break; 1384 1385 udelay(10); 1386 tmp = tmp + 10; 1387 if (tmp >= timeout) { 1388 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 1389 " waiting for regMMSCH_VF_MAILBOX_RESP "\ 1390 "(expected=0x%08x, readback=0x%08x)\n", 1391 tmp, expected, resp); 1392 return -EBUSY; 1393 } 1394 } 1395 enabled_vcn = amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, 0) ? 1 : 0; 1396 init_status = ((struct mmsch_v4_0_init_header *)(table_loc))->inst[enabled_vcn].init_status; 1397 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE 1398 && init_status != MMSCH_VF_ENGINE_STATUS__PASS) 1399 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init "\ 1400 "status for VCN%x: 0x%x\n", resp, enabled_vcn, init_status); 1401 1402 return 0; 1403 } 1404 1405 /** 1406 * vcn_v4_0_stop_dpg_mode - VCN stop with dpg mode 1407 * 1408 * @adev: amdgpu_device pointer 1409 * @inst_idx: instance number index 1410 * 1411 * Stop VCN block with dpg mode 1412 */ 1413 static void vcn_v4_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) 1414 { 1415 uint32_t tmp; 1416 1417 /* Wait for power status to be 1 */ 1418 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, 1419 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1420 1421 /* wait for read ptr to be equal to write ptr */ 1422 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 1423 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1424 1425 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, 1426 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1427 1428 /* disable dynamic power gating mode */ 1429 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0, 1430 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1431 } 1432 1433 /** 1434 * vcn_v4_0_stop - VCN stop 1435 * 1436 * @adev: amdgpu_device pointer 1437 * 1438 * Stop VCN block 1439 */ 1440 static int vcn_v4_0_stop(struct amdgpu_device *adev) 1441 { 1442 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1443 uint32_t tmp; 1444 int i, r = 0; 1445 1446 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1447 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1448 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; 1449 1450 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1451 vcn_v4_0_stop_dpg_mode(adev, i); 1452 continue; 1453 } 1454 1455 /* wait for vcn idle */ 1456 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1457 if (r) 1458 return r; 1459 1460 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1461 UVD_LMI_STATUS__READ_CLEAN_MASK | 1462 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1463 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1464 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 1465 if (r) 1466 return r; 1467 1468 /* disable LMI UMC channel */ 1469 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2); 1470 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1471 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp); 1472 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1473 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1474 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 1475 if (r) 1476 return r; 1477 1478 /* block VCPU register access */ 1479 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 1480 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1481 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1482 1483 /* reset VCPU */ 1484 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1485 UVD_VCPU_CNTL__BLK_RST_MASK, 1486 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1487 1488 /* disable VCPU clock */ 1489 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1490 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1491 1492 /* apply soft reset */ 1493 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1494 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1495 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1496 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1497 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1498 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1499 1500 /* clear status */ 1501 WREG32_SOC15(VCN, i, regUVD_STATUS, 0); 1502 1503 /* apply HW clock gating */ 1504 vcn_v4_0_enable_clock_gating(adev, i); 1505 1506 /* enable VCN power gating */ 1507 vcn_v4_0_enable_static_power_gating(adev, i); 1508 } 1509 1510 if (adev->pm.dpm_enabled) 1511 amdgpu_dpm_enable_uvd(adev, false); 1512 1513 return 0; 1514 } 1515 1516 /** 1517 * vcn_v4_0_pause_dpg_mode - VCN pause with dpg mode 1518 * 1519 * @adev: amdgpu_device pointer 1520 * @inst_idx: instance number index 1521 * @new_state: pause state 1522 * 1523 * Pause dpg mode for VCN block 1524 */ 1525 static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx, 1526 struct dpg_pause_state *new_state) 1527 { 1528 uint32_t reg_data = 0; 1529 int ret_code; 1530 1531 /* pause/unpause if state is changed */ 1532 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1533 DRM_DEV_DEBUG(adev->dev, "dpg pause state changed %d -> %d", 1534 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1535 reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) & 1536 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1537 1538 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1539 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1, 1540 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1541 1542 if (!ret_code) { 1543 /* pause DPG */ 1544 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1545 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1546 1547 /* wait for ACK */ 1548 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE, 1549 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1550 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1551 1552 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1553 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1554 } 1555 } else { 1556 /* unpause dpg, no need to wait */ 1557 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1558 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1559 } 1560 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1561 } 1562 1563 return 0; 1564 } 1565 1566 /** 1567 * vcn_v4_0_unified_ring_get_rptr - get unified read pointer 1568 * 1569 * @ring: amdgpu_ring pointer 1570 * 1571 * Returns the current hardware unified read pointer 1572 */ 1573 static uint64_t vcn_v4_0_unified_ring_get_rptr(struct amdgpu_ring *ring) 1574 { 1575 struct amdgpu_device *adev = ring->adev; 1576 1577 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1578 DRM_ERROR("wrong ring id is identified in %s", __func__); 1579 1580 return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR); 1581 } 1582 1583 /** 1584 * vcn_v4_0_unified_ring_get_wptr - get unified write pointer 1585 * 1586 * @ring: amdgpu_ring pointer 1587 * 1588 * Returns the current hardware unified write pointer 1589 */ 1590 static uint64_t vcn_v4_0_unified_ring_get_wptr(struct amdgpu_ring *ring) 1591 { 1592 struct amdgpu_device *adev = ring->adev; 1593 1594 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1595 DRM_ERROR("wrong ring id is identified in %s", __func__); 1596 1597 if (ring->use_doorbell) 1598 return *ring->wptr_cpu_addr; 1599 else 1600 return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR); 1601 } 1602 1603 /** 1604 * vcn_v4_0_unified_ring_set_wptr - set enc write pointer 1605 * 1606 * @ring: amdgpu_ring pointer 1607 * 1608 * Commits the enc write pointer to the hardware 1609 */ 1610 static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring) 1611 { 1612 struct amdgpu_device *adev = ring->adev; 1613 1614 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1615 DRM_ERROR("wrong ring id is identified in %s", __func__); 1616 1617 if (ring->use_doorbell) { 1618 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1619 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1620 } else { 1621 WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1622 } 1623 } 1624 1625 static int vcn_v4_0_limit_sched(struct amdgpu_cs_parser *p, 1626 struct amdgpu_job *job) 1627 { 1628 struct drm_gpu_scheduler **scheds; 1629 1630 /* The create msg must be in the first IB submitted */ 1631 if (atomic_read(&job->base.entity->fence_seq)) 1632 return -EINVAL; 1633 1634 scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_ENC] 1635 [AMDGPU_RING_PRIO_0].sched; 1636 drm_sched_entity_modify_sched(job->base.entity, scheds, 1); 1637 return 0; 1638 } 1639 1640 static int vcn_v4_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job, 1641 uint64_t addr) 1642 { 1643 struct ttm_operation_ctx ctx = { false, false }; 1644 struct amdgpu_bo_va_mapping *map; 1645 uint32_t *msg, num_buffers; 1646 struct amdgpu_bo *bo; 1647 uint64_t start, end; 1648 unsigned int i; 1649 void *ptr; 1650 int r; 1651 1652 addr &= AMDGPU_GMC_HOLE_MASK; 1653 r = amdgpu_cs_find_mapping(p, addr, &bo, &map); 1654 if (r) { 1655 DRM_ERROR("Can't find BO for addr 0x%08llx\n", addr); 1656 return r; 1657 } 1658 1659 start = map->start * AMDGPU_GPU_PAGE_SIZE; 1660 end = (map->last + 1) * AMDGPU_GPU_PAGE_SIZE; 1661 if (addr & 0x7) { 1662 DRM_ERROR("VCN messages must be 8 byte aligned!\n"); 1663 return -EINVAL; 1664 } 1665 1666 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1667 amdgpu_bo_placement_from_domain(bo, bo->allowed_domains); 1668 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 1669 if (r) { 1670 DRM_ERROR("Failed validating the VCN message BO (%d)!\n", r); 1671 return r; 1672 } 1673 1674 r = amdgpu_bo_kmap(bo, &ptr); 1675 if (r) { 1676 DRM_ERROR("Failed mapping the VCN message (%d)!\n", r); 1677 return r; 1678 } 1679 1680 msg = ptr + addr - start; 1681 1682 /* Check length */ 1683 if (msg[1] > end - addr) { 1684 r = -EINVAL; 1685 goto out; 1686 } 1687 1688 if (msg[3] != RDECODE_MSG_CREATE) 1689 goto out; 1690 1691 num_buffers = msg[2]; 1692 for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) { 1693 uint32_t offset, size, *create; 1694 1695 if (msg[0] != RDECODE_MESSAGE_CREATE) 1696 continue; 1697 1698 offset = msg[1]; 1699 size = msg[2]; 1700 1701 if (offset + size > end) { 1702 r = -EINVAL; 1703 goto out; 1704 } 1705 1706 create = ptr + addr + offset - start; 1707 1708 /* H246, HEVC and VP9 can run on any instance */ 1709 if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11) 1710 continue; 1711 1712 r = vcn_v4_0_limit_sched(p, job); 1713 if (r) 1714 goto out; 1715 } 1716 1717 out: 1718 amdgpu_bo_kunmap(bo); 1719 return r; 1720 } 1721 1722 #define RADEON_VCN_ENGINE_TYPE_DECODE (0x00000003) 1723 1724 static int vcn_v4_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, 1725 struct amdgpu_job *job, 1726 struct amdgpu_ib *ib) 1727 { 1728 struct amdgpu_ring *ring = amdgpu_job_ring(job); 1729 struct amdgpu_vcn_decode_buffer *decode_buffer; 1730 uint64_t addr; 1731 uint32_t val; 1732 1733 /* The first instance can decode anything */ 1734 if (!ring->me) 1735 return 0; 1736 1737 /* unified queue ib header has 8 double words. */ 1738 if (ib->length_dw < 8) 1739 return 0; 1740 1741 val = amdgpu_ib_get_value(ib, 6); //RADEON_VCN_ENGINE_TYPE 1742 if (val != RADEON_VCN_ENGINE_TYPE_DECODE) 1743 return 0; 1744 1745 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&ib->ptr[10]; 1746 1747 if (!(decode_buffer->valid_buf_flag & 0x1)) 1748 return 0; 1749 1750 addr = ((u64)decode_buffer->msg_buffer_address_hi) << 32 | 1751 decode_buffer->msg_buffer_address_lo; 1752 return vcn_v4_0_dec_msg(p, job, addr); 1753 } 1754 1755 static const struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = { 1756 .type = AMDGPU_RING_TYPE_VCN_ENC, 1757 .align_mask = 0x3f, 1758 .nop = VCN_ENC_CMD_NO_OP, 1759 .vmhub = AMDGPU_MMHUB_0, 1760 .get_rptr = vcn_v4_0_unified_ring_get_rptr, 1761 .get_wptr = vcn_v4_0_unified_ring_get_wptr, 1762 .set_wptr = vcn_v4_0_unified_ring_set_wptr, 1763 .patch_cs_in_place = vcn_v4_0_ring_patch_cs_in_place, 1764 .emit_frame_size = 1765 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1766 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1767 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1768 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1769 1, /* vcn_v2_0_enc_ring_insert_end */ 1770 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1771 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1772 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1773 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 1774 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1775 .test_ib = amdgpu_vcn_unified_ring_test_ib, 1776 .insert_nop = amdgpu_ring_insert_nop, 1777 .insert_end = vcn_v2_0_enc_ring_insert_end, 1778 .pad_ib = amdgpu_ring_generic_pad_ib, 1779 .begin_use = amdgpu_vcn_ring_begin_use, 1780 .end_use = amdgpu_vcn_ring_end_use, 1781 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 1782 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 1783 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1784 }; 1785 1786 /** 1787 * vcn_v4_0_set_unified_ring_funcs - set unified ring functions 1788 * 1789 * @adev: amdgpu_device pointer 1790 * 1791 * Set unified ring functions 1792 */ 1793 static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev) 1794 { 1795 int i; 1796 1797 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1798 if (adev->vcn.harvest_config & (1 << i)) 1799 continue; 1800 1801 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_unified_ring_vm_funcs; 1802 adev->vcn.inst[i].ring_enc[0].me = i; 1803 1804 DRM_INFO("VCN(%d) encode/decode are enabled in VM mode\n", i); 1805 } 1806 } 1807 1808 /** 1809 * vcn_v4_0_is_idle - check VCN block is idle 1810 * 1811 * @handle: amdgpu_device pointer 1812 * 1813 * Check whether VCN block is idle 1814 */ 1815 static bool vcn_v4_0_is_idle(void *handle) 1816 { 1817 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1818 int i, ret = 1; 1819 1820 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1821 if (adev->vcn.harvest_config & (1 << i)) 1822 continue; 1823 1824 ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE); 1825 } 1826 1827 return ret; 1828 } 1829 1830 /** 1831 * vcn_v4_0_wait_for_idle - wait for VCN block idle 1832 * 1833 * @handle: amdgpu_device pointer 1834 * 1835 * Wait for VCN block idle 1836 */ 1837 static int vcn_v4_0_wait_for_idle(void *handle) 1838 { 1839 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1840 int i, ret = 0; 1841 1842 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1843 if (adev->vcn.harvest_config & (1 << i)) 1844 continue; 1845 1846 ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 1847 UVD_STATUS__IDLE); 1848 if (ret) 1849 return ret; 1850 } 1851 1852 return ret; 1853 } 1854 1855 /** 1856 * vcn_v4_0_set_clockgating_state - set VCN block clockgating state 1857 * 1858 * @handle: amdgpu_device pointer 1859 * @state: clock gating state 1860 * 1861 * Set VCN block clockgating state 1862 */ 1863 static int vcn_v4_0_set_clockgating_state(void *handle, enum amd_clockgating_state state) 1864 { 1865 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1866 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 1867 int i; 1868 1869 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1870 if (adev->vcn.harvest_config & (1 << i)) 1871 continue; 1872 1873 if (enable) { 1874 if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE) 1875 return -EBUSY; 1876 vcn_v4_0_enable_clock_gating(adev, i); 1877 } else { 1878 vcn_v4_0_disable_clock_gating(adev, i); 1879 } 1880 } 1881 1882 return 0; 1883 } 1884 1885 /** 1886 * vcn_v4_0_set_powergating_state - set VCN block powergating state 1887 * 1888 * @handle: amdgpu_device pointer 1889 * @state: power gating state 1890 * 1891 * Set VCN block powergating state 1892 */ 1893 static int vcn_v4_0_set_powergating_state(void *handle, enum amd_powergating_state state) 1894 { 1895 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1896 int ret; 1897 1898 /* for SRIOV, guest should not control VCN Power-gating 1899 * MMSCH FW should control Power-gating and clock-gating 1900 * guest should avoid touching CGC and PG 1901 */ 1902 if (amdgpu_sriov_vf(adev)) { 1903 adev->vcn.cur_state = AMD_PG_STATE_UNGATE; 1904 return 0; 1905 } 1906 1907 if(state == adev->vcn.cur_state) 1908 return 0; 1909 1910 if (state == AMD_PG_STATE_GATE) 1911 ret = vcn_v4_0_stop(adev); 1912 else 1913 ret = vcn_v4_0_start(adev); 1914 1915 if(!ret) 1916 adev->vcn.cur_state = state; 1917 1918 return ret; 1919 } 1920 1921 /** 1922 * vcn_v4_0_set_interrupt_state - set VCN block interrupt state 1923 * 1924 * @adev: amdgpu_device pointer 1925 * @source: interrupt sources 1926 * @type: interrupt types 1927 * @state: interrupt states 1928 * 1929 * Set VCN block interrupt state 1930 */ 1931 static int vcn_v4_0_set_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 1932 unsigned type, enum amdgpu_interrupt_state state) 1933 { 1934 return 0; 1935 } 1936 1937 /** 1938 * vcn_v4_0_process_interrupt - process VCN block interrupt 1939 * 1940 * @adev: amdgpu_device pointer 1941 * @source: interrupt sources 1942 * @entry: interrupt entry from clients and sources 1943 * 1944 * Process VCN block interrupt 1945 */ 1946 static int vcn_v4_0_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 1947 struct amdgpu_iv_entry *entry) 1948 { 1949 uint32_t ip_instance; 1950 1951 switch (entry->client_id) { 1952 case SOC15_IH_CLIENTID_VCN: 1953 ip_instance = 0; 1954 break; 1955 case SOC15_IH_CLIENTID_VCN1: 1956 ip_instance = 1; 1957 break; 1958 default: 1959 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 1960 return 0; 1961 } 1962 1963 DRM_DEBUG("IH: VCN TRAP\n"); 1964 1965 switch (entry->src_id) { 1966 case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1967 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 1968 break; 1969 case VCN_4_0__SRCID_UVD_POISON: 1970 amdgpu_vcn_process_poison_irq(adev, source, entry); 1971 break; 1972 default: 1973 DRM_ERROR("Unhandled interrupt: %d %d\n", 1974 entry->src_id, entry->src_data[0]); 1975 break; 1976 } 1977 1978 return 0; 1979 } 1980 1981 static const struct amdgpu_irq_src_funcs vcn_v4_0_irq_funcs = { 1982 .set = vcn_v4_0_set_interrupt_state, 1983 .process = vcn_v4_0_process_interrupt, 1984 }; 1985 1986 /** 1987 * vcn_v4_0_set_irq_funcs - set VCN block interrupt irq functions 1988 * 1989 * @adev: amdgpu_device pointer 1990 * 1991 * Set VCN block interrupt irq functions 1992 */ 1993 static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev) 1994 { 1995 int i; 1996 1997 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1998 if (adev->vcn.harvest_config & (1 << i)) 1999 continue; 2000 2001 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1; 2002 adev->vcn.inst[i].irq.funcs = &vcn_v4_0_irq_funcs; 2003 } 2004 } 2005 2006 static const struct amd_ip_funcs vcn_v4_0_ip_funcs = { 2007 .name = "vcn_v4_0", 2008 .early_init = vcn_v4_0_early_init, 2009 .late_init = NULL, 2010 .sw_init = vcn_v4_0_sw_init, 2011 .sw_fini = vcn_v4_0_sw_fini, 2012 .hw_init = vcn_v4_0_hw_init, 2013 .hw_fini = vcn_v4_0_hw_fini, 2014 .suspend = vcn_v4_0_suspend, 2015 .resume = vcn_v4_0_resume, 2016 .is_idle = vcn_v4_0_is_idle, 2017 .wait_for_idle = vcn_v4_0_wait_for_idle, 2018 .check_soft_reset = NULL, 2019 .pre_soft_reset = NULL, 2020 .soft_reset = NULL, 2021 .post_soft_reset = NULL, 2022 .set_clockgating_state = vcn_v4_0_set_clockgating_state, 2023 .set_powergating_state = vcn_v4_0_set_powergating_state, 2024 }; 2025 2026 const struct amdgpu_ip_block_version vcn_v4_0_ip_block = 2027 { 2028 .type = AMD_IP_BLOCK_TYPE_VCN, 2029 .major = 4, 2030 .minor = 0, 2031 .rev = 0, 2032 .funcs = &vcn_v4_0_ip_funcs, 2033 }; 2034 2035 static uint32_t vcn_v4_0_query_poison_by_instance(struct amdgpu_device *adev, 2036 uint32_t instance, uint32_t sub_block) 2037 { 2038 uint32_t poison_stat = 0, reg_value = 0; 2039 2040 switch (sub_block) { 2041 case AMDGPU_VCN_V4_0_VCPU_VCODEC: 2042 reg_value = RREG32_SOC15(VCN, instance, regUVD_RAS_VCPU_VCODEC_STATUS); 2043 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF); 2044 break; 2045 default: 2046 break; 2047 } 2048 2049 if (poison_stat) 2050 dev_info(adev->dev, "Poison detected in VCN%d, sub_block%d\n", 2051 instance, sub_block); 2052 2053 return poison_stat; 2054 } 2055 2056 static bool vcn_v4_0_query_ras_poison_status(struct amdgpu_device *adev) 2057 { 2058 uint32_t inst, sub; 2059 uint32_t poison_stat = 0; 2060 2061 for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++) 2062 for (sub = 0; sub < AMDGPU_VCN_V4_0_MAX_SUB_BLOCK; sub++) 2063 poison_stat += 2064 vcn_v4_0_query_poison_by_instance(adev, inst, sub); 2065 2066 return !!poison_stat; 2067 } 2068 2069 const struct amdgpu_ras_block_hw_ops vcn_v4_0_ras_hw_ops = { 2070 .query_poison_status = vcn_v4_0_query_ras_poison_status, 2071 }; 2072 2073 static struct amdgpu_vcn_ras vcn_v4_0_ras = { 2074 .ras_block = { 2075 .hw_ops = &vcn_v4_0_ras_hw_ops, 2076 }, 2077 }; 2078 2079 static void vcn_v4_0_set_ras_funcs(struct amdgpu_device *adev) 2080 { 2081 switch (adev->ip_versions[VCN_HWIP][0]) { 2082 case IP_VERSION(4, 0, 0): 2083 adev->vcn.ras = &vcn_v4_0_ras; 2084 break; 2085 default: 2086 break; 2087 } 2088 2089 amdgpu_vcn_set_ras_funcs(adev); 2090 } 2091