18da1170aSLeo Liu /* 28da1170aSLeo Liu * Copyright 2021 Advanced Micro Devices, Inc. 38da1170aSLeo Liu * 48da1170aSLeo Liu * Permission is hereby granted, free of charge, to any person obtaining a 58da1170aSLeo Liu * copy of this software and associated documentation files (the "Software"), 68da1170aSLeo Liu * to deal in the Software without restriction, including without limitation 78da1170aSLeo Liu * the rights to use, copy, modify, merge, publish, distribute, sublicense, 88da1170aSLeo Liu * and/or sell copies of the Software, and to permit persons to whom the 98da1170aSLeo Liu * Software is furnished to do so, subject to the following conditions: 108da1170aSLeo Liu * 118da1170aSLeo Liu * The above copyright notice and this permission notice shall be included in 128da1170aSLeo Liu * all copies or substantial portions of the Software. 138da1170aSLeo Liu * 148da1170aSLeo Liu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 158da1170aSLeo Liu * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 168da1170aSLeo Liu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 178da1170aSLeo Liu * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 188da1170aSLeo Liu * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 198da1170aSLeo Liu * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 208da1170aSLeo Liu * OTHER DEALINGS IN THE SOFTWARE. 218da1170aSLeo Liu * 228da1170aSLeo Liu */ 238da1170aSLeo Liu 248da1170aSLeo Liu #include <linux/firmware.h> 258da1170aSLeo Liu #include "amdgpu.h" 268da1170aSLeo Liu #include "amdgpu_vcn.h" 278da1170aSLeo Liu #include "amdgpu_pm.h" 280b15205cSSonny Jiang #include "amdgpu_cs.h" 298da1170aSLeo Liu #include "soc15.h" 308da1170aSLeo Liu #include "soc15d.h" 318da1170aSLeo Liu #include "soc15_hw_ip.h" 328da1170aSLeo Liu #include "vcn_v2_0.h" 33aa44beb5SJane Jian #include "mmsch_v4_0.h" 34377d0221STao Zhou #include "vcn_v4_0.h" 358da1170aSLeo Liu 368da1170aSLeo Liu #include "vcn/vcn_4_0_0_offset.h" 378da1170aSLeo Liu #include "vcn/vcn_4_0_0_sh_mask.h" 388da1170aSLeo Liu #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 398da1170aSLeo Liu 408da1170aSLeo Liu #include <drm/drm_drv.h> 418da1170aSLeo Liu 428da1170aSLeo Liu #define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL 438da1170aSLeo Liu #define mmUVD_DPG_LMA_CTL_BASE_IDX regUVD_DPG_LMA_CTL_BASE_IDX 448da1170aSLeo Liu #define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA 458da1170aSLeo Liu #define mmUVD_DPG_LMA_DATA_BASE_IDX regUVD_DPG_LMA_DATA_BASE_IDX 468da1170aSLeo Liu 478da1170aSLeo Liu #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00 488da1170aSLeo Liu #define VCN1_VID_SOC_ADDRESS_3_0 0x48300 498da1170aSLeo Liu 50aa44beb5SJane Jian #define VCN_HARVEST_MMSCH 0 51aa44beb5SJane Jian 520b15205cSSonny Jiang #define RDECODE_MSG_CREATE 0x00000000 530b15205cSSonny Jiang #define RDECODE_MESSAGE_CREATE 0x00000001 540b15205cSSonny Jiang 558da1170aSLeo Liu static int amdgpu_ih_clientid_vcns[] = { 568da1170aSLeo Liu SOC15_IH_CLIENTID_VCN, 578da1170aSLeo Liu SOC15_IH_CLIENTID_VCN1 588da1170aSLeo Liu }; 598da1170aSLeo Liu 60aa44beb5SJane Jian static int vcn_v4_0_start_sriov(struct amdgpu_device *adev); 61bb4f196bSRuijing Dong static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev); 628da1170aSLeo Liu static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev); 638da1170aSLeo Liu static int vcn_v4_0_set_powergating_state(void *handle, 648da1170aSLeo Liu enum amd_powergating_state state); 658da1170aSLeo Liu static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev, 668da1170aSLeo Liu int inst_idx, struct dpg_pause_state *new_state); 67aa44beb5SJane Jian static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring); 68377d0221STao Zhou static void vcn_v4_0_set_ras_funcs(struct amdgpu_device *adev); 698da1170aSLeo Liu 708da1170aSLeo Liu /** 7169939009SMario Limonciello * vcn_v4_0_early_init - set function pointers and load microcode 728da1170aSLeo Liu * 738da1170aSLeo Liu * @handle: amdgpu_device pointer 748da1170aSLeo Liu * 758da1170aSLeo Liu * Set ring and irq function pointers 7669939009SMario Limonciello * Load microcode from filesystem 778da1170aSLeo Liu */ 788da1170aSLeo Liu static int vcn_v4_0_early_init(void *handle) 798da1170aSLeo Liu { 808da1170aSLeo Liu struct amdgpu_device *adev = (struct amdgpu_device *)handle; 81e68d1e07Sbobzhou int i; 828da1170aSLeo Liu 836dcb38a1SJane Jian if (amdgpu_sriov_vf(adev)) { 84aa44beb5SJane Jian adev->vcn.harvest_config = VCN_HARVEST_MMSCH; 85e68d1e07Sbobzhou for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 866dcb38a1SJane Jian if (amdgpu_vcn_is_disabled_vcn(adev, VCN_ENCODE_RING, i)) { 876dcb38a1SJane Jian adev->vcn.harvest_config |= 1 << i; 886dcb38a1SJane Jian dev_info(adev->dev, "VCN%d is disabled by hypervisor\n", i); 896dcb38a1SJane Jian } 906dcb38a1SJane Jian } 916dcb38a1SJane Jian } 92aa44beb5SJane Jian 93bb4f196bSRuijing Dong /* re-use enc ring as unified ring */ 948da1170aSLeo Liu adev->vcn.num_enc_rings = 1; 958da1170aSLeo Liu 96bb4f196bSRuijing Dong vcn_v4_0_set_unified_ring_funcs(adev); 978da1170aSLeo Liu vcn_v4_0_set_irq_funcs(adev); 98377d0221STao Zhou vcn_v4_0_set_ras_funcs(adev); 998da1170aSLeo Liu 10069939009SMario Limonciello return amdgpu_vcn_early_init(adev); 1018da1170aSLeo Liu } 1028da1170aSLeo Liu 1038da1170aSLeo Liu /** 1048da1170aSLeo Liu * vcn_v4_0_sw_init - sw init for VCN block 1058da1170aSLeo Liu * 1068da1170aSLeo Liu * @handle: amdgpu_device pointer 1078da1170aSLeo Liu * 1088da1170aSLeo Liu * Load firmware and sw initialization 1098da1170aSLeo Liu */ 1108da1170aSLeo Liu static int vcn_v4_0_sw_init(void *handle) 1118da1170aSLeo Liu { 1128da1170aSLeo Liu struct amdgpu_ring *ring; 1138da1170aSLeo Liu struct amdgpu_device *adev = (struct amdgpu_device *)handle; 114bb4f196bSRuijing Dong int i, r; 1158da1170aSLeo Liu 1168da1170aSLeo Liu r = amdgpu_vcn_sw_init(adev); 1178da1170aSLeo Liu if (r) 1188da1170aSLeo Liu return r; 1198da1170aSLeo Liu 1208da1170aSLeo Liu amdgpu_vcn_setup_ucode(adev); 1218da1170aSLeo Liu 1228da1170aSLeo Liu r = amdgpu_vcn_resume(adev); 1238da1170aSLeo Liu if (r) 1248da1170aSLeo Liu return r; 1258da1170aSLeo Liu 1268da1170aSLeo Liu for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1278da1170aSLeo Liu volatile struct amdgpu_vcn4_fw_shared *fw_shared; 128bb4f196bSRuijing Dong 1298da1170aSLeo Liu if (adev->vcn.harvest_config & (1 << i)) 1308da1170aSLeo Liu continue; 1318da1170aSLeo Liu 1328da1170aSLeo Liu atomic_set(&adev->vcn.inst[i].sched_score, 0); 1338da1170aSLeo Liu 134bb4f196bSRuijing Dong /* VCN UNIFIED TRAP */ 1358da1170aSLeo Liu r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 136bb4f196bSRuijing Dong VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); 1378da1170aSLeo Liu if (r) 1388da1170aSLeo Liu return r; 1398da1170aSLeo Liu 140ea5309deSTao Zhou /* VCN POISON TRAP */ 141ea5309deSTao Zhou r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 142ea5309deSTao Zhou VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[i].irq); 143ea5309deSTao Zhou if (r) 144ea5309deSTao Zhou return r; 145ea5309deSTao Zhou 146bb4f196bSRuijing Dong ring = &adev->vcn.inst[i].ring_enc[0]; 1478da1170aSLeo Liu ring->use_doorbell = true; 148aa44beb5SJane Jian if (amdgpu_sriov_vf(adev)) 14998928baeSJane Jian ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + i * (adev->vcn.num_enc_rings + 1) + 1; 150aa44beb5SJane Jian else 151bb4f196bSRuijing Dong ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + 8 * i; 152*f4caf584SHawking Zhang ring->vm_hub = AMDGPU_MMHUB0(0); 153bb4f196bSRuijing Dong sprintf(ring->name, "vcn_unified_%d", i); 1548da1170aSLeo Liu 1558da1170aSLeo Liu r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 156bb4f196bSRuijing Dong AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score); 1578da1170aSLeo Liu if (r) 1588da1170aSLeo Liu return r; 1598da1170aSLeo Liu 1608da1170aSLeo Liu fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 161bb4f196bSRuijing Dong fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); 1628da1170aSLeo Liu fw_shared->sq.is_enabled = 1; 1638da1170aSLeo Liu 164167be852SRuijing Dong fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG); 165167be852SRuijing Dong fw_shared->smu_dpm_interface.smu_interface_type = (adev->flags & AMD_IS_APU) ? 166167be852SRuijing Dong AMDGPU_VCN_SMU_DPM_INTERFACE_APU : AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU; 167167be852SRuijing Dong 168aa44beb5SJane Jian if (amdgpu_sriov_vf(adev)) 169aa44beb5SJane Jian fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG); 170aa44beb5SJane Jian 1718da1170aSLeo Liu if (amdgpu_vcnfw_log) 1728da1170aSLeo Liu amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]); 1738da1170aSLeo Liu } 1748da1170aSLeo Liu 175aa44beb5SJane Jian if (amdgpu_sriov_vf(adev)) { 176aa44beb5SJane Jian r = amdgpu_virt_alloc_mm_table(adev); 177aa44beb5SJane Jian if (r) 178aa44beb5SJane Jian return r; 179aa44beb5SJane Jian } 180aa44beb5SJane Jian 1818da1170aSLeo Liu if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1828da1170aSLeo Liu adev->vcn.pause_dpg_mode = vcn_v4_0_pause_dpg_mode; 183bb4f196bSRuijing Dong 184f81c31d9SHawking Zhang r = amdgpu_vcn_ras_sw_init(adev); 185f81c31d9SHawking Zhang if (r) 186f81c31d9SHawking Zhang return r; 187f81c31d9SHawking Zhang 1888da1170aSLeo Liu return 0; 1898da1170aSLeo Liu } 1908da1170aSLeo Liu 1918da1170aSLeo Liu /** 1928da1170aSLeo Liu * vcn_v4_0_sw_fini - sw fini for VCN block 1938da1170aSLeo Liu * 1948da1170aSLeo Liu * @handle: amdgpu_device pointer 1958da1170aSLeo Liu * 1968da1170aSLeo Liu * VCN suspend and free up sw allocation 1978da1170aSLeo Liu */ 1988da1170aSLeo Liu static int vcn_v4_0_sw_fini(void *handle) 1998da1170aSLeo Liu { 2008da1170aSLeo Liu struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2018da1170aSLeo Liu int i, r, idx; 2028da1170aSLeo Liu 2038585732bSGuchun Chen if (drm_dev_enter(adev_to_drm(adev), &idx)) { 2048da1170aSLeo Liu for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 2058da1170aSLeo Liu volatile struct amdgpu_vcn4_fw_shared *fw_shared; 2068da1170aSLeo Liu 2078da1170aSLeo Liu if (adev->vcn.harvest_config & (1 << i)) 2088da1170aSLeo Liu continue; 2098da1170aSLeo Liu 2108da1170aSLeo Liu fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 2118da1170aSLeo Liu fw_shared->present_flag_0 = 0; 2128da1170aSLeo Liu fw_shared->sq.is_enabled = 0; 2138da1170aSLeo Liu } 2148da1170aSLeo Liu 2158da1170aSLeo Liu drm_dev_exit(idx); 2168da1170aSLeo Liu } 2178da1170aSLeo Liu 218aa44beb5SJane Jian if (amdgpu_sriov_vf(adev)) 219aa44beb5SJane Jian amdgpu_virt_free_mm_table(adev); 220aa44beb5SJane Jian 2218da1170aSLeo Liu r = amdgpu_vcn_suspend(adev); 2228da1170aSLeo Liu if (r) 2238da1170aSLeo Liu return r; 2248da1170aSLeo Liu 2258da1170aSLeo Liu r = amdgpu_vcn_sw_fini(adev); 2268da1170aSLeo Liu 2278da1170aSLeo Liu return r; 2288da1170aSLeo Liu } 2298da1170aSLeo Liu 2308da1170aSLeo Liu /** 2318da1170aSLeo Liu * vcn_v4_0_hw_init - start and test VCN block 2328da1170aSLeo Liu * 2338da1170aSLeo Liu * @handle: amdgpu_device pointer 2348da1170aSLeo Liu * 2358da1170aSLeo Liu * Initialize the hardware, boot up the VCPU and do some testing 2368da1170aSLeo Liu */ 2378da1170aSLeo Liu static int vcn_v4_0_hw_init(void *handle) 2388da1170aSLeo Liu { 2398da1170aSLeo Liu struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2408da1170aSLeo Liu struct amdgpu_ring *ring; 241bb4f196bSRuijing Dong int i, r; 2428da1170aSLeo Liu 243aa44beb5SJane Jian if (amdgpu_sriov_vf(adev)) { 244aa44beb5SJane Jian r = vcn_v4_0_start_sriov(adev); 245aa44beb5SJane Jian if (r) 246aa44beb5SJane Jian goto done; 247aa44beb5SJane Jian 248aa44beb5SJane Jian for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 249aa44beb5SJane Jian if (adev->vcn.harvest_config & (1 << i)) 250aa44beb5SJane Jian continue; 251aa44beb5SJane Jian 252aa44beb5SJane Jian ring = &adev->vcn.inst[i].ring_enc[0]; 253aa44beb5SJane Jian ring->wptr = 0; 254aa44beb5SJane Jian ring->wptr_old = 0; 255aa44beb5SJane Jian vcn_v4_0_unified_ring_set_wptr(ring); 256aa44beb5SJane Jian ring->sched.ready = true; 2576dcb38a1SJane Jian 258aa44beb5SJane Jian } 259aa44beb5SJane Jian } else { 2608da1170aSLeo Liu for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2618da1170aSLeo Liu if (adev->vcn.harvest_config & (1 << i)) 2628da1170aSLeo Liu continue; 263bb4f196bSRuijing Dong 2648da1170aSLeo Liu ring = &adev->vcn.inst[i].ring_enc[0]; 2658da1170aSLeo Liu 2668da1170aSLeo Liu adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 2678da1170aSLeo Liu ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i); 2688da1170aSLeo Liu 2698da1170aSLeo Liu r = amdgpu_ring_test_helper(ring); 2708da1170aSLeo Liu if (r) 2718da1170aSLeo Liu goto done; 272aa44beb5SJane Jian 273aa44beb5SJane Jian } 2748da1170aSLeo Liu } 2758da1170aSLeo Liu 2768da1170aSLeo Liu done: 2778da1170aSLeo Liu if (!r) 2788da1170aSLeo Liu DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 2798da1170aSLeo Liu (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 2808da1170aSLeo Liu 2818da1170aSLeo Liu return r; 2828da1170aSLeo Liu } 2838da1170aSLeo Liu 2848da1170aSLeo Liu /** 2858da1170aSLeo Liu * vcn_v4_0_hw_fini - stop the hardware block 2868da1170aSLeo Liu * 2878da1170aSLeo Liu * @handle: amdgpu_device pointer 2888da1170aSLeo Liu * 2898da1170aSLeo Liu * Stop the VCN block, mark ring as not ready any more 2908da1170aSLeo Liu */ 2918da1170aSLeo Liu static int vcn_v4_0_hw_fini(void *handle) 2928da1170aSLeo Liu { 2938da1170aSLeo Liu struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2948da1170aSLeo Liu int i; 2958da1170aSLeo Liu 2968da1170aSLeo Liu cancel_delayed_work_sync(&adev->vcn.idle_work); 2978da1170aSLeo Liu 2988da1170aSLeo Liu for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2998da1170aSLeo Liu if (adev->vcn.harvest_config & (1 << i)) 3008da1170aSLeo Liu continue; 301aa44beb5SJane Jian if (!amdgpu_sriov_vf(adev)) { 3028da1170aSLeo Liu if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 3038da1170aSLeo Liu (adev->vcn.cur_state != AMD_PG_STATE_GATE && 3048da1170aSLeo Liu RREG32_SOC15(VCN, i, regUVD_STATUS))) { 3058da1170aSLeo Liu vcn_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 3068da1170aSLeo Liu } 3078da1170aSLeo Liu } 3088da1170aSLeo Liu 309ea5309deSTao Zhou amdgpu_irq_put(adev, &adev->vcn.inst[i].irq, 0); 310aa44beb5SJane Jian } 311aa44beb5SJane Jian 3128da1170aSLeo Liu return 0; 3138da1170aSLeo Liu } 3148da1170aSLeo Liu 3158da1170aSLeo Liu /** 3168da1170aSLeo Liu * vcn_v4_0_suspend - suspend VCN block 3178da1170aSLeo Liu * 3188da1170aSLeo Liu * @handle: amdgpu_device pointer 3198da1170aSLeo Liu * 3208da1170aSLeo Liu * HW fini and suspend VCN block 3218da1170aSLeo Liu */ 3228da1170aSLeo Liu static int vcn_v4_0_suspend(void *handle) 3238da1170aSLeo Liu { 3248da1170aSLeo Liu int r; 3258da1170aSLeo Liu struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3268da1170aSLeo Liu 3278da1170aSLeo Liu r = vcn_v4_0_hw_fini(adev); 3288da1170aSLeo Liu if (r) 3298da1170aSLeo Liu return r; 3308da1170aSLeo Liu 3318da1170aSLeo Liu r = amdgpu_vcn_suspend(adev); 3328da1170aSLeo Liu 3338da1170aSLeo Liu return r; 3348da1170aSLeo Liu } 3358da1170aSLeo Liu 3368da1170aSLeo Liu /** 3378da1170aSLeo Liu * vcn_v4_0_resume - resume VCN block 3388da1170aSLeo Liu * 3398da1170aSLeo Liu * @handle: amdgpu_device pointer 3408da1170aSLeo Liu * 3418da1170aSLeo Liu * Resume firmware and hw init VCN block 3428da1170aSLeo Liu */ 3438da1170aSLeo Liu static int vcn_v4_0_resume(void *handle) 3448da1170aSLeo Liu { 3458da1170aSLeo Liu int r; 3468da1170aSLeo Liu struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3478da1170aSLeo Liu 3488da1170aSLeo Liu r = amdgpu_vcn_resume(adev); 3498da1170aSLeo Liu if (r) 3508da1170aSLeo Liu return r; 3518da1170aSLeo Liu 3528da1170aSLeo Liu r = vcn_v4_0_hw_init(adev); 3538da1170aSLeo Liu 3548da1170aSLeo Liu return r; 3558da1170aSLeo Liu } 3568da1170aSLeo Liu 3578da1170aSLeo Liu /** 3588da1170aSLeo Liu * vcn_v4_0_mc_resume - memory controller programming 3598da1170aSLeo Liu * 3608da1170aSLeo Liu * @adev: amdgpu_device pointer 3618da1170aSLeo Liu * @inst: instance number 3628da1170aSLeo Liu * 3638da1170aSLeo Liu * Let the VCN memory controller know it's offsets 3648da1170aSLeo Liu */ 3658da1170aSLeo Liu static void vcn_v4_0_mc_resume(struct amdgpu_device *adev, int inst) 3668da1170aSLeo Liu { 3678da1170aSLeo Liu uint32_t offset, size; 3688da1170aSLeo Liu const struct common_firmware_header *hdr; 3698da1170aSLeo Liu 3708da1170aSLeo Liu hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 3718da1170aSLeo Liu size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 3728da1170aSLeo Liu 3738da1170aSLeo Liu /* cache window 0: fw */ 3748da1170aSLeo Liu if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 3758da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 3768da1170aSLeo Liu (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 3778da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 3788da1170aSLeo Liu (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 3798da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0); 3808da1170aSLeo Liu offset = 0; 3818da1170aSLeo Liu } else { 3828da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 3838da1170aSLeo Liu lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 3848da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 3858da1170aSLeo Liu upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 3868da1170aSLeo Liu offset = size; 3878da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 3888da1170aSLeo Liu } 3898da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size); 3908da1170aSLeo Liu 3918da1170aSLeo Liu /* cache window 1: stack */ 3928da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 3938da1170aSLeo Liu lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 3948da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 3958da1170aSLeo Liu upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 3968da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0); 3978da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 3988da1170aSLeo Liu 3998da1170aSLeo Liu /* cache window 2: context */ 4008da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 4018da1170aSLeo Liu lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 4028da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 4038da1170aSLeo Liu upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 4048da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0); 4058da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 4068da1170aSLeo Liu 4078da1170aSLeo Liu /* non-cache window */ 4088da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 4098da1170aSLeo Liu lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 4108da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 4118da1170aSLeo Liu upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 4128da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); 4138da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0, 4148da1170aSLeo Liu AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 4158da1170aSLeo Liu } 4168da1170aSLeo Liu 4178da1170aSLeo Liu /** 4188da1170aSLeo Liu * vcn_v4_0_mc_resume_dpg_mode - memory controller programming for dpg mode 4198da1170aSLeo Liu * 4208da1170aSLeo Liu * @adev: amdgpu_device pointer 4218da1170aSLeo Liu * @inst_idx: instance number index 4228da1170aSLeo Liu * @indirect: indirectly write sram 4238da1170aSLeo Liu * 4248da1170aSLeo Liu * Let the VCN memory controller know it's offsets with dpg mode 4258da1170aSLeo Liu */ 4268da1170aSLeo Liu static void vcn_v4_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 4278da1170aSLeo Liu { 4288da1170aSLeo Liu uint32_t offset, size; 4298da1170aSLeo Liu const struct common_firmware_header *hdr; 4308da1170aSLeo Liu hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 4318da1170aSLeo Liu size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 4328da1170aSLeo Liu 4338da1170aSLeo Liu /* cache window 0: fw */ 4348da1170aSLeo Liu if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 4358da1170aSLeo Liu if (!indirect) { 4368da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 4378da1170aSLeo Liu VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 4388da1170aSLeo Liu (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); 4398da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 4408da1170aSLeo Liu VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 4418da1170aSLeo Liu (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); 4428da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 4438da1170aSLeo Liu VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 4448da1170aSLeo Liu } else { 4458da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 4468da1170aSLeo Liu VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 4478da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 4488da1170aSLeo Liu VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 4498da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 4508da1170aSLeo Liu VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 4518da1170aSLeo Liu } 4528da1170aSLeo Liu offset = 0; 4538da1170aSLeo Liu } else { 4548da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 4558da1170aSLeo Liu VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 4568da1170aSLeo Liu lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 4578da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 4588da1170aSLeo Liu VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 4598da1170aSLeo Liu upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 4608da1170aSLeo Liu offset = size; 4618da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 4628da1170aSLeo Liu VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 4638da1170aSLeo Liu AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 4648da1170aSLeo Liu } 4658da1170aSLeo Liu 4668da1170aSLeo Liu if (!indirect) 4678da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 4688da1170aSLeo Liu VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 4698da1170aSLeo Liu else 4708da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 4718da1170aSLeo Liu VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 4728da1170aSLeo Liu 4738da1170aSLeo Liu /* cache window 1: stack */ 4748da1170aSLeo Liu if (!indirect) { 4758da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 4768da1170aSLeo Liu VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 4778da1170aSLeo Liu lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 4788da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 4798da1170aSLeo Liu VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 4808da1170aSLeo Liu upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 4818da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 4828da1170aSLeo Liu VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 4838da1170aSLeo Liu } else { 4848da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 4858da1170aSLeo Liu VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 4868da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 4878da1170aSLeo Liu VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 4888da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 4898da1170aSLeo Liu VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 4908da1170aSLeo Liu } 4918da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 4928da1170aSLeo Liu VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 4938da1170aSLeo Liu 4948da1170aSLeo Liu /* cache window 2: context */ 4958da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 4968da1170aSLeo Liu VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 4978da1170aSLeo Liu lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 4988da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 4998da1170aSLeo Liu VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 5008da1170aSLeo Liu upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 5018da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 5028da1170aSLeo Liu VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 5038da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 5048da1170aSLeo Liu VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 5058da1170aSLeo Liu 5068da1170aSLeo Liu /* non-cache window */ 5078da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 5088da1170aSLeo Liu VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 5098da1170aSLeo Liu lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 5108da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 5118da1170aSLeo Liu VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 5128da1170aSLeo Liu upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 5138da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 5148da1170aSLeo Liu VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 5158da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 5168da1170aSLeo Liu VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0), 5178da1170aSLeo Liu AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); 5188da1170aSLeo Liu 5198da1170aSLeo Liu /* VCN global tiling registers */ 5208da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 5218da1170aSLeo Liu VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 5228da1170aSLeo Liu } 5238da1170aSLeo Liu 5248da1170aSLeo Liu /** 5258da1170aSLeo Liu * vcn_v4_0_disable_static_power_gating - disable VCN static power gating 5268da1170aSLeo Liu * 5278da1170aSLeo Liu * @adev: amdgpu_device pointer 5288da1170aSLeo Liu * @inst: instance number 5298da1170aSLeo Liu * 5308da1170aSLeo Liu * Disable static power gating for VCN block 5318da1170aSLeo Liu */ 5328da1170aSLeo Liu static void vcn_v4_0_disable_static_power_gating(struct amdgpu_device *adev, int inst) 5338da1170aSLeo Liu { 5348da1170aSLeo Liu uint32_t data = 0; 5358da1170aSLeo Liu 5368da1170aSLeo Liu if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 5378da1170aSLeo Liu data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 5388da1170aSLeo Liu | 1 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT 5398da1170aSLeo Liu | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 5408da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 5418da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT 5428da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 5438da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT 5448da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 5458da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 5468da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 5478da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 5488da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT 5498da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 5508da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 5518da1170aSLeo Liu 5528da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data); 5538da1170aSLeo Liu SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, 5548da1170aSLeo Liu UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF); 5558da1170aSLeo Liu } else { 5568da1170aSLeo Liu uint32_t value; 5578da1170aSLeo Liu 5588da1170aSLeo Liu value = (inst) ? 0x2200800 : 0; 5598da1170aSLeo Liu data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 5608da1170aSLeo Liu | 1 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT 5618da1170aSLeo Liu | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 5628da1170aSLeo Liu | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 5638da1170aSLeo Liu | 1 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT 5648da1170aSLeo Liu | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 5658da1170aSLeo Liu | 1 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT 5668da1170aSLeo Liu | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 5678da1170aSLeo Liu | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 5688da1170aSLeo Liu | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 5698da1170aSLeo Liu | 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 5708da1170aSLeo Liu | 1 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT 5718da1170aSLeo Liu | 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 5728da1170aSLeo Liu | 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 5738da1170aSLeo Liu 5748da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data); 5758da1170aSLeo Liu SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, value, 0x3F3FFFFF); 5768da1170aSLeo Liu } 5778da1170aSLeo Liu 5788da1170aSLeo Liu data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 5798da1170aSLeo Liu data &= ~0x103; 5808da1170aSLeo Liu if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 5818da1170aSLeo Liu data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 5828da1170aSLeo Liu UVD_POWER_STATUS__UVD_PG_EN_MASK; 5838da1170aSLeo Liu 5848da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 5858da1170aSLeo Liu 5868da1170aSLeo Liu return; 5878da1170aSLeo Liu } 5888da1170aSLeo Liu 5898da1170aSLeo Liu /** 5908da1170aSLeo Liu * vcn_v4_0_enable_static_power_gating - enable VCN static power gating 5918da1170aSLeo Liu * 5928da1170aSLeo Liu * @adev: amdgpu_device pointer 5938da1170aSLeo Liu * @inst: instance number 5948da1170aSLeo Liu * 5958da1170aSLeo Liu * Enable static power gating for VCN block 5968da1170aSLeo Liu */ 5978da1170aSLeo Liu static void vcn_v4_0_enable_static_power_gating(struct amdgpu_device *adev, int inst) 5988da1170aSLeo Liu { 5998da1170aSLeo Liu uint32_t data; 6008da1170aSLeo Liu 6018da1170aSLeo Liu if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 6028da1170aSLeo Liu /* Before power off, this indicator has to be turned on */ 6038da1170aSLeo Liu data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 6048da1170aSLeo Liu data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 6058da1170aSLeo Liu data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 6068da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 6078da1170aSLeo Liu 6088da1170aSLeo Liu data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 6098da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT 6108da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 6118da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT 6128da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 6138da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT 6148da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 6158da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 6168da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 6178da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 6188da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 6198da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT 6208da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 6218da1170aSLeo Liu | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 6228da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data); 6238da1170aSLeo Liu 6248da1170aSLeo Liu data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 6258da1170aSLeo Liu | 2 << UVD_PGFSM_STATUS__UVDS_PWR_STATUS__SHIFT 6268da1170aSLeo Liu | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 6278da1170aSLeo Liu | 2 << UVD_PGFSM_STATUS__UVDTC_PWR_STATUS__SHIFT 6288da1170aSLeo Liu | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 6298da1170aSLeo Liu | 2 << UVD_PGFSM_STATUS__UVDTA_PWR_STATUS__SHIFT 6308da1170aSLeo Liu | 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT 6318da1170aSLeo Liu | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 6328da1170aSLeo Liu | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 6338da1170aSLeo Liu | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 6348da1170aSLeo Liu | 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT 6358da1170aSLeo Liu | 2 << UVD_PGFSM_STATUS__UVDTB_PWR_STATUS__SHIFT 6368da1170aSLeo Liu | 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT 6378da1170aSLeo Liu | 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT); 6388da1170aSLeo Liu SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, data, 0x3F3FFFFF); 6398da1170aSLeo Liu } 6408da1170aSLeo Liu 6418da1170aSLeo Liu return; 6428da1170aSLeo Liu } 6438da1170aSLeo Liu 6448da1170aSLeo Liu /** 6458da1170aSLeo Liu * vcn_v4_0_disable_clock_gating - disable VCN clock gating 6468da1170aSLeo Liu * 6478da1170aSLeo Liu * @adev: amdgpu_device pointer 6488da1170aSLeo Liu * @inst: instance number 6498da1170aSLeo Liu * 6508da1170aSLeo Liu * Disable clock gating for VCN block 6518da1170aSLeo Liu */ 6528da1170aSLeo Liu static void vcn_v4_0_disable_clock_gating(struct amdgpu_device *adev, int inst) 6538da1170aSLeo Liu { 6548da1170aSLeo Liu uint32_t data; 6558da1170aSLeo Liu 6568da1170aSLeo Liu if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 6578da1170aSLeo Liu return; 6588da1170aSLeo Liu 6598da1170aSLeo Liu /* VCN disable CGC */ 6608da1170aSLeo Liu data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 6618da1170aSLeo Liu data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 6628da1170aSLeo Liu data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 6638da1170aSLeo Liu data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 6648da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 6658da1170aSLeo Liu 6668da1170aSLeo Liu data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE); 6678da1170aSLeo Liu data &= ~(UVD_CGC_GATE__SYS_MASK 6688da1170aSLeo Liu | UVD_CGC_GATE__UDEC_MASK 6698da1170aSLeo Liu | UVD_CGC_GATE__MPEG2_MASK 6708da1170aSLeo Liu | UVD_CGC_GATE__REGS_MASK 6718da1170aSLeo Liu | UVD_CGC_GATE__RBC_MASK 6728da1170aSLeo Liu | UVD_CGC_GATE__LMI_MC_MASK 6738da1170aSLeo Liu | UVD_CGC_GATE__LMI_UMC_MASK 6748da1170aSLeo Liu | UVD_CGC_GATE__IDCT_MASK 6758da1170aSLeo Liu | UVD_CGC_GATE__MPRD_MASK 6768da1170aSLeo Liu | UVD_CGC_GATE__MPC_MASK 6778da1170aSLeo Liu | UVD_CGC_GATE__LBSI_MASK 6788da1170aSLeo Liu | UVD_CGC_GATE__LRBBM_MASK 6798da1170aSLeo Liu | UVD_CGC_GATE__UDEC_RE_MASK 6808da1170aSLeo Liu | UVD_CGC_GATE__UDEC_CM_MASK 6818da1170aSLeo Liu | UVD_CGC_GATE__UDEC_IT_MASK 6828da1170aSLeo Liu | UVD_CGC_GATE__UDEC_DB_MASK 6838da1170aSLeo Liu | UVD_CGC_GATE__UDEC_MP_MASK 6848da1170aSLeo Liu | UVD_CGC_GATE__WCB_MASK 6858da1170aSLeo Liu | UVD_CGC_GATE__VCPU_MASK 6868da1170aSLeo Liu | UVD_CGC_GATE__MMSCH_MASK); 6878da1170aSLeo Liu 6888da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_CGC_GATE, data); 6898da1170aSLeo Liu SOC15_WAIT_ON_RREG(VCN, inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF); 6908da1170aSLeo Liu 6918da1170aSLeo Liu data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 6928da1170aSLeo Liu data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 6938da1170aSLeo Liu | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 6948da1170aSLeo Liu | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 6958da1170aSLeo Liu | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 6968da1170aSLeo Liu | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 6978da1170aSLeo Liu | UVD_CGC_CTRL__SYS_MODE_MASK 6988da1170aSLeo Liu | UVD_CGC_CTRL__UDEC_MODE_MASK 6998da1170aSLeo Liu | UVD_CGC_CTRL__MPEG2_MODE_MASK 7008da1170aSLeo Liu | UVD_CGC_CTRL__REGS_MODE_MASK 7018da1170aSLeo Liu | UVD_CGC_CTRL__RBC_MODE_MASK 7028da1170aSLeo Liu | UVD_CGC_CTRL__LMI_MC_MODE_MASK 7038da1170aSLeo Liu | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 7048da1170aSLeo Liu | UVD_CGC_CTRL__IDCT_MODE_MASK 7058da1170aSLeo Liu | UVD_CGC_CTRL__MPRD_MODE_MASK 7068da1170aSLeo Liu | UVD_CGC_CTRL__MPC_MODE_MASK 7078da1170aSLeo Liu | UVD_CGC_CTRL__LBSI_MODE_MASK 7088da1170aSLeo Liu | UVD_CGC_CTRL__LRBBM_MODE_MASK 7098da1170aSLeo Liu | UVD_CGC_CTRL__WCB_MODE_MASK 7108da1170aSLeo Liu | UVD_CGC_CTRL__VCPU_MODE_MASK 7118da1170aSLeo Liu | UVD_CGC_CTRL__MMSCH_MODE_MASK); 7128da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 7138da1170aSLeo Liu 7148da1170aSLeo Liu data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE); 7158da1170aSLeo Liu data |= (UVD_SUVD_CGC_GATE__SRE_MASK 7168da1170aSLeo Liu | UVD_SUVD_CGC_GATE__SIT_MASK 7178da1170aSLeo Liu | UVD_SUVD_CGC_GATE__SMP_MASK 7188da1170aSLeo Liu | UVD_SUVD_CGC_GATE__SCM_MASK 7198da1170aSLeo Liu | UVD_SUVD_CGC_GATE__SDB_MASK 7208da1170aSLeo Liu | UVD_SUVD_CGC_GATE__SRE_H264_MASK 7218da1170aSLeo Liu | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 7228da1170aSLeo Liu | UVD_SUVD_CGC_GATE__SIT_H264_MASK 7238da1170aSLeo Liu | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 7248da1170aSLeo Liu | UVD_SUVD_CGC_GATE__SCM_H264_MASK 7258da1170aSLeo Liu | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 7268da1170aSLeo Liu | UVD_SUVD_CGC_GATE__SDB_H264_MASK 7278da1170aSLeo Liu | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 7288da1170aSLeo Liu | UVD_SUVD_CGC_GATE__SCLR_MASK 7298da1170aSLeo Liu | UVD_SUVD_CGC_GATE__UVD_SC_MASK 7308da1170aSLeo Liu | UVD_SUVD_CGC_GATE__ENT_MASK 7318da1170aSLeo Liu | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 7328da1170aSLeo Liu | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 7338da1170aSLeo Liu | UVD_SUVD_CGC_GATE__SITE_MASK 7348da1170aSLeo Liu | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 7358da1170aSLeo Liu | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 7368da1170aSLeo Liu | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 7378da1170aSLeo Liu | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 7388da1170aSLeo Liu | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 7398da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE, data); 7408da1170aSLeo Liu 7418da1170aSLeo Liu data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); 7428da1170aSLeo Liu data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 7438da1170aSLeo Liu | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 7448da1170aSLeo Liu | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 7458da1170aSLeo Liu | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 7468da1170aSLeo Liu | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 7478da1170aSLeo Liu | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 7488da1170aSLeo Liu | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 7498da1170aSLeo Liu | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 7508da1170aSLeo Liu | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 7518da1170aSLeo Liu | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 7528da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data); 7538da1170aSLeo Liu } 7548da1170aSLeo Liu 7558da1170aSLeo Liu /** 7568da1170aSLeo Liu * vcn_v4_0_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode 7578da1170aSLeo Liu * 7588da1170aSLeo Liu * @adev: amdgpu_device pointer 7598da1170aSLeo Liu * @sram_sel: sram select 7608da1170aSLeo Liu * @inst_idx: instance number index 7618da1170aSLeo Liu * @indirect: indirectly write sram 7628da1170aSLeo Liu * 7638da1170aSLeo Liu * Disable clock gating for VCN block with dpg mode 7648da1170aSLeo Liu */ 7658da1170aSLeo Liu static void vcn_v4_0_disable_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel, 7668da1170aSLeo Liu int inst_idx, uint8_t indirect) 7678da1170aSLeo Liu { 7688da1170aSLeo Liu uint32_t reg_data = 0; 7698da1170aSLeo Liu 7708da1170aSLeo Liu if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 7718da1170aSLeo Liu return; 7728da1170aSLeo Liu 7738da1170aSLeo Liu /* enable sw clock gating control */ 7748da1170aSLeo Liu reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 7758da1170aSLeo Liu reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 7768da1170aSLeo Liu reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 7778da1170aSLeo Liu reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 7788da1170aSLeo Liu UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 7798da1170aSLeo Liu UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 7808da1170aSLeo Liu UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 7818da1170aSLeo Liu UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 7828da1170aSLeo Liu UVD_CGC_CTRL__SYS_MODE_MASK | 7838da1170aSLeo Liu UVD_CGC_CTRL__UDEC_MODE_MASK | 7848da1170aSLeo Liu UVD_CGC_CTRL__MPEG2_MODE_MASK | 7858da1170aSLeo Liu UVD_CGC_CTRL__REGS_MODE_MASK | 7868da1170aSLeo Liu UVD_CGC_CTRL__RBC_MODE_MASK | 7878da1170aSLeo Liu UVD_CGC_CTRL__LMI_MC_MODE_MASK | 7888da1170aSLeo Liu UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 7898da1170aSLeo Liu UVD_CGC_CTRL__IDCT_MODE_MASK | 7908da1170aSLeo Liu UVD_CGC_CTRL__MPRD_MODE_MASK | 7918da1170aSLeo Liu UVD_CGC_CTRL__MPC_MODE_MASK | 7928da1170aSLeo Liu UVD_CGC_CTRL__LBSI_MODE_MASK | 7938da1170aSLeo Liu UVD_CGC_CTRL__LRBBM_MODE_MASK | 7948da1170aSLeo Liu UVD_CGC_CTRL__WCB_MODE_MASK | 7958da1170aSLeo Liu UVD_CGC_CTRL__VCPU_MODE_MASK); 7968da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 7978da1170aSLeo Liu VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); 7988da1170aSLeo Liu 7998da1170aSLeo Liu /* turn off clock gating */ 8008da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 8018da1170aSLeo Liu VCN, inst_idx, regUVD_CGC_GATE), 0, sram_sel, indirect); 8028da1170aSLeo Liu 8038da1170aSLeo Liu /* turn on SUVD clock gating */ 8048da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 8058da1170aSLeo Liu VCN, inst_idx, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 8068da1170aSLeo Liu 8078da1170aSLeo Liu /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 8088da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 8098da1170aSLeo Liu VCN, inst_idx, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 8108da1170aSLeo Liu } 8118da1170aSLeo Liu 8128da1170aSLeo Liu /** 8138da1170aSLeo Liu * vcn_v4_0_enable_clock_gating - enable VCN clock gating 8148da1170aSLeo Liu * 8158da1170aSLeo Liu * @adev: amdgpu_device pointer 8168da1170aSLeo Liu * @inst: instance number 8178da1170aSLeo Liu * 8188da1170aSLeo Liu * Enable clock gating for VCN block 8198da1170aSLeo Liu */ 8208da1170aSLeo Liu static void vcn_v4_0_enable_clock_gating(struct amdgpu_device *adev, int inst) 8218da1170aSLeo Liu { 8228da1170aSLeo Liu uint32_t data; 8238da1170aSLeo Liu 8248da1170aSLeo Liu if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 8258da1170aSLeo Liu return; 8268da1170aSLeo Liu 8278da1170aSLeo Liu /* enable VCN CGC */ 8288da1170aSLeo Liu data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 8298da1170aSLeo Liu data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 8308da1170aSLeo Liu data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 8318da1170aSLeo Liu data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 8328da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 8338da1170aSLeo Liu 8348da1170aSLeo Liu data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 8358da1170aSLeo Liu data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 8368da1170aSLeo Liu | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 8378da1170aSLeo Liu | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 8388da1170aSLeo Liu | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 8398da1170aSLeo Liu | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 8408da1170aSLeo Liu | UVD_CGC_CTRL__SYS_MODE_MASK 8418da1170aSLeo Liu | UVD_CGC_CTRL__UDEC_MODE_MASK 8428da1170aSLeo Liu | UVD_CGC_CTRL__MPEG2_MODE_MASK 8438da1170aSLeo Liu | UVD_CGC_CTRL__REGS_MODE_MASK 8448da1170aSLeo Liu | UVD_CGC_CTRL__RBC_MODE_MASK 8458da1170aSLeo Liu | UVD_CGC_CTRL__LMI_MC_MODE_MASK 8468da1170aSLeo Liu | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 8478da1170aSLeo Liu | UVD_CGC_CTRL__IDCT_MODE_MASK 8488da1170aSLeo Liu | UVD_CGC_CTRL__MPRD_MODE_MASK 8498da1170aSLeo Liu | UVD_CGC_CTRL__MPC_MODE_MASK 8508da1170aSLeo Liu | UVD_CGC_CTRL__LBSI_MODE_MASK 8518da1170aSLeo Liu | UVD_CGC_CTRL__LRBBM_MODE_MASK 8528da1170aSLeo Liu | UVD_CGC_CTRL__WCB_MODE_MASK 8538da1170aSLeo Liu | UVD_CGC_CTRL__VCPU_MODE_MASK 8548da1170aSLeo Liu | UVD_CGC_CTRL__MMSCH_MODE_MASK); 8558da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 8568da1170aSLeo Liu 8578da1170aSLeo Liu data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); 8588da1170aSLeo Liu data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 8598da1170aSLeo Liu | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 8608da1170aSLeo Liu | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 8618da1170aSLeo Liu | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 8628da1170aSLeo Liu | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 8638da1170aSLeo Liu | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 8648da1170aSLeo Liu | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 8658da1170aSLeo Liu | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 8668da1170aSLeo Liu | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 8678da1170aSLeo Liu | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 8688da1170aSLeo Liu WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data); 8698da1170aSLeo Liu 8708da1170aSLeo Liu return; 8718da1170aSLeo Liu } 8728da1170aSLeo Liu 8730422c34cSTao Zhou static void vcn_v4_0_enable_ras(struct amdgpu_device *adev, int inst_idx, 8740422c34cSTao Zhou bool indirect) 8750422c34cSTao Zhou { 8760422c34cSTao Zhou uint32_t tmp; 8770422c34cSTao Zhou 8780422c34cSTao Zhou if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) 8790422c34cSTao Zhou return; 8800422c34cSTao Zhou 8810422c34cSTao Zhou tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK | 8820422c34cSTao Zhou VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK | 8830422c34cSTao Zhou VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK | 8840422c34cSTao Zhou VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK; 8850422c34cSTao Zhou WREG32_SOC15_DPG_MODE(inst_idx, 8860422c34cSTao Zhou SOC15_DPG_MODE_OFFSET(VCN, 0, regVCN_RAS_CNTL), 8870422c34cSTao Zhou tmp, 0, indirect); 8880422c34cSTao Zhou 8890422c34cSTao Zhou tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK; 8900422c34cSTao Zhou WREG32_SOC15_DPG_MODE(inst_idx, 8910422c34cSTao Zhou SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_SYS_INT_EN), 8920422c34cSTao Zhou tmp, 0, indirect); 8930422c34cSTao Zhou } 8940422c34cSTao Zhou 8958da1170aSLeo Liu /** 8968da1170aSLeo Liu * vcn_v4_0_start_dpg_mode - VCN start with dpg mode 8978da1170aSLeo Liu * 8988da1170aSLeo Liu * @adev: amdgpu_device pointer 8998da1170aSLeo Liu * @inst_idx: instance number index 9008da1170aSLeo Liu * @indirect: indirectly write sram 9018da1170aSLeo Liu * 9028da1170aSLeo Liu * Start VCN block with dpg mode 9038da1170aSLeo Liu */ 9048da1170aSLeo Liu static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 9058da1170aSLeo Liu { 9068da1170aSLeo Liu volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 9078da1170aSLeo Liu struct amdgpu_ring *ring; 9088da1170aSLeo Liu uint32_t tmp; 9098da1170aSLeo Liu 9108da1170aSLeo Liu /* disable register anti-hang mechanism */ 9118da1170aSLeo Liu WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1, 9128da1170aSLeo Liu ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 9138da1170aSLeo Liu /* enable dynamic power gating mode */ 9148da1170aSLeo Liu tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS); 9158da1170aSLeo Liu tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 9168da1170aSLeo Liu tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 9178da1170aSLeo Liu WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp); 9188da1170aSLeo Liu 9198da1170aSLeo Liu if (indirect) 9208da1170aSLeo Liu adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 9218da1170aSLeo Liu 9228da1170aSLeo Liu /* enable clock gating */ 9238da1170aSLeo Liu vcn_v4_0_disable_clock_gating_dpg_mode(adev, 0, inst_idx, indirect); 9248da1170aSLeo Liu 9258da1170aSLeo Liu /* enable VCPU clock */ 9268da1170aSLeo Liu tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 9278da1170aSLeo Liu tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK; 9288da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 9298da1170aSLeo Liu VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 9308da1170aSLeo Liu 9318da1170aSLeo Liu /* disable master interupt */ 9328da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 9338da1170aSLeo Liu VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect); 9348da1170aSLeo Liu 9358da1170aSLeo Liu /* setup regUVD_LMI_CTRL */ 9368da1170aSLeo Liu tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 9378da1170aSLeo Liu UVD_LMI_CTRL__REQ_MODE_MASK | 9388da1170aSLeo Liu UVD_LMI_CTRL__CRC_RESET_MASK | 9398da1170aSLeo Liu UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 9408da1170aSLeo Liu UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 9418da1170aSLeo Liu UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 9428da1170aSLeo Liu (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 9438da1170aSLeo Liu 0x00100000L); 9448da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 9458da1170aSLeo Liu VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect); 9468da1170aSLeo Liu 9478da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 9488da1170aSLeo Liu VCN, inst_idx, regUVD_MPC_CNTL), 9498da1170aSLeo Liu 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 9508da1170aSLeo Liu 9518da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 9528da1170aSLeo Liu VCN, inst_idx, regUVD_MPC_SET_MUXA0), 9538da1170aSLeo Liu ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 9548da1170aSLeo Liu (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 9558da1170aSLeo Liu (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 9568da1170aSLeo Liu (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 9578da1170aSLeo Liu 9588da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 9598da1170aSLeo Liu VCN, inst_idx, regUVD_MPC_SET_MUXB0), 9608da1170aSLeo Liu ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 9618da1170aSLeo Liu (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 9628da1170aSLeo Liu (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 9638da1170aSLeo Liu (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 9648da1170aSLeo Liu 9658da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 9668da1170aSLeo Liu VCN, inst_idx, regUVD_MPC_SET_MUX), 9678da1170aSLeo Liu ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 9688da1170aSLeo Liu (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 9698da1170aSLeo Liu (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 9708da1170aSLeo Liu 9718da1170aSLeo Liu vcn_v4_0_mc_resume_dpg_mode(adev, inst_idx, indirect); 9728da1170aSLeo Liu 9738da1170aSLeo Liu tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 9748da1170aSLeo Liu tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 9758da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 9768da1170aSLeo Liu VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 9778da1170aSLeo Liu 9788da1170aSLeo Liu /* enable LMI MC and UMC channels */ 9798da1170aSLeo Liu tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT; 9808da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 9818da1170aSLeo Liu VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect); 9828da1170aSLeo Liu 9830422c34cSTao Zhou vcn_v4_0_enable_ras(adev, inst_idx, indirect); 9840422c34cSTao Zhou 9858da1170aSLeo Liu /* enable master interrupt */ 9868da1170aSLeo Liu WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 9878da1170aSLeo Liu VCN, inst_idx, regUVD_MASTINT_EN), 9888da1170aSLeo Liu UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 9898da1170aSLeo Liu 9908da1170aSLeo Liu 9918da1170aSLeo Liu if (indirect) 9928da1170aSLeo Liu psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, 9938da1170aSLeo Liu (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr - 9948da1170aSLeo Liu (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr)); 9958da1170aSLeo Liu 9968da1170aSLeo Liu ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 9978da1170aSLeo Liu 9988da1170aSLeo Liu WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr); 9998da1170aSLeo Liu WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 10008da1170aSLeo Liu WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4); 1001bb4f196bSRuijing Dong 1002bb4f196bSRuijing Dong tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 1003bb4f196bSRuijing Dong tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 1004bb4f196bSRuijing Dong WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 1005bb4f196bSRuijing Dong fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 1006bb4f196bSRuijing Dong WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0); 1007bb4f196bSRuijing Dong WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0); 1008bb4f196bSRuijing Dong 10098da1170aSLeo Liu tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR); 10108da1170aSLeo Liu WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp); 10118da1170aSLeo Liu ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 10128da1170aSLeo Liu 1013bb4f196bSRuijing Dong tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 1014bb4f196bSRuijing Dong tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 1015bb4f196bSRuijing Dong WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 1016bb4f196bSRuijing Dong fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 1017bb4f196bSRuijing Dong 10188da1170aSLeo Liu WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL, 10198da1170aSLeo Liu ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 10208da1170aSLeo Liu VCN_RB1_DB_CTRL__EN_MASK); 1021bb4f196bSRuijing Dong 10228da1170aSLeo Liu return 0; 10238da1170aSLeo Liu } 10248da1170aSLeo Liu 10258da1170aSLeo Liu 10268da1170aSLeo Liu /** 10278da1170aSLeo Liu * vcn_v4_0_start - VCN start 10288da1170aSLeo Liu * 10298da1170aSLeo Liu * @adev: amdgpu_device pointer 10308da1170aSLeo Liu * 10318da1170aSLeo Liu * Start VCN block 10328da1170aSLeo Liu */ 10338da1170aSLeo Liu static int vcn_v4_0_start(struct amdgpu_device *adev) 10348da1170aSLeo Liu { 10358da1170aSLeo Liu volatile struct amdgpu_vcn4_fw_shared *fw_shared; 10368da1170aSLeo Liu struct amdgpu_ring *ring; 10378da1170aSLeo Liu uint32_t tmp; 10388da1170aSLeo Liu int i, j, k, r; 10398da1170aSLeo Liu 10408da1170aSLeo Liu if (adev->pm.dpm_enabled) 10418da1170aSLeo Liu amdgpu_dpm_enable_uvd(adev, true); 10428da1170aSLeo Liu 10438da1170aSLeo Liu for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1044bb4f196bSRuijing Dong fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1045bb4f196bSRuijing Dong 10468da1170aSLeo Liu if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 10478da1170aSLeo Liu r = vcn_v4_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram); 10488da1170aSLeo Liu continue; 10498da1170aSLeo Liu } 10508da1170aSLeo Liu 10518da1170aSLeo Liu /* disable VCN power gating */ 10528da1170aSLeo Liu vcn_v4_0_disable_static_power_gating(adev, i); 10538da1170aSLeo Liu 10548da1170aSLeo Liu /* set VCN status busy */ 10558da1170aSLeo Liu tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY; 10568da1170aSLeo Liu WREG32_SOC15(VCN, i, regUVD_STATUS, tmp); 10578da1170aSLeo Liu 10588da1170aSLeo Liu /*SW clock gating */ 10598da1170aSLeo Liu vcn_v4_0_disable_clock_gating(adev, i); 10608da1170aSLeo Liu 10618da1170aSLeo Liu /* enable VCPU clock */ 10628da1170aSLeo Liu WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 10638da1170aSLeo Liu UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 10648da1170aSLeo Liu 10658da1170aSLeo Liu /* disable master interrupt */ 10668da1170aSLeo Liu WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0, 10678da1170aSLeo Liu ~UVD_MASTINT_EN__VCPU_EN_MASK); 10688da1170aSLeo Liu 10698da1170aSLeo Liu /* enable LMI MC and UMC channels */ 10708da1170aSLeo Liu WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0, 10718da1170aSLeo Liu ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 10728da1170aSLeo Liu 10738da1170aSLeo Liu tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 10748da1170aSLeo Liu tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 10758da1170aSLeo Liu tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 10768da1170aSLeo Liu WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 10778da1170aSLeo Liu 10788da1170aSLeo Liu /* setup regUVD_LMI_CTRL */ 10798da1170aSLeo Liu tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL); 10808da1170aSLeo Liu WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp | 10818da1170aSLeo Liu UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 10828da1170aSLeo Liu UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 10838da1170aSLeo Liu UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 10848da1170aSLeo Liu UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 10858da1170aSLeo Liu 10868da1170aSLeo Liu /* setup regUVD_MPC_CNTL */ 10878da1170aSLeo Liu tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL); 10888da1170aSLeo Liu tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 10898da1170aSLeo Liu tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 10908da1170aSLeo Liu WREG32_SOC15(VCN, i, regUVD_MPC_CNTL, tmp); 10918da1170aSLeo Liu 10928da1170aSLeo Liu /* setup UVD_MPC_SET_MUXA0 */ 10938da1170aSLeo Liu WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0, 10948da1170aSLeo Liu ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 10958da1170aSLeo Liu (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 10968da1170aSLeo Liu (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 10978da1170aSLeo Liu (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 10988da1170aSLeo Liu 10998da1170aSLeo Liu /* setup UVD_MPC_SET_MUXB0 */ 11008da1170aSLeo Liu WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXB0, 11018da1170aSLeo Liu ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 11028da1170aSLeo Liu (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 11038da1170aSLeo Liu (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 11048da1170aSLeo Liu (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 11058da1170aSLeo Liu 11068da1170aSLeo Liu /* setup UVD_MPC_SET_MUX */ 11078da1170aSLeo Liu WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX, 11088da1170aSLeo Liu ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 11098da1170aSLeo Liu (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 11108da1170aSLeo Liu (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 11118da1170aSLeo Liu 11128da1170aSLeo Liu vcn_v4_0_mc_resume(adev, i); 11138da1170aSLeo Liu 11148da1170aSLeo Liu /* VCN global tiling registers */ 11158da1170aSLeo Liu WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG, 11168da1170aSLeo Liu adev->gfx.config.gb_addr_config); 11178da1170aSLeo Liu 11188da1170aSLeo Liu /* unblock VCPU register access */ 11198da1170aSLeo Liu WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0, 11208da1170aSLeo Liu ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 11218da1170aSLeo Liu 11228da1170aSLeo Liu /* release VCPU reset to boot */ 11238da1170aSLeo Liu WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 11248da1170aSLeo Liu ~UVD_VCPU_CNTL__BLK_RST_MASK); 11258da1170aSLeo Liu 11268da1170aSLeo Liu for (j = 0; j < 10; ++j) { 11278da1170aSLeo Liu uint32_t status; 11288da1170aSLeo Liu 11298da1170aSLeo Liu for (k = 0; k < 100; ++k) { 11308da1170aSLeo Liu status = RREG32_SOC15(VCN, i, regUVD_STATUS); 11318da1170aSLeo Liu if (status & 2) 11328da1170aSLeo Liu break; 11338da1170aSLeo Liu mdelay(10); 11348da1170aSLeo Liu if (amdgpu_emu_mode==1) 11358da1170aSLeo Liu msleep(1); 11368da1170aSLeo Liu } 11378da1170aSLeo Liu 11388da1170aSLeo Liu if (amdgpu_emu_mode==1) { 1139736f7308SSonny Jiang r = -1; 11408da1170aSLeo Liu if (status & 2) { 11418da1170aSLeo Liu r = 0; 11428da1170aSLeo Liu break; 11438da1170aSLeo Liu } 11448da1170aSLeo Liu } else { 11458da1170aSLeo Liu r = 0; 11468da1170aSLeo Liu if (status & 2) 11478da1170aSLeo Liu break; 11488da1170aSLeo Liu 1149bb4f196bSRuijing Dong dev_err(adev->dev, "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i); 11508da1170aSLeo Liu WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 11518da1170aSLeo Liu UVD_VCPU_CNTL__BLK_RST_MASK, 11528da1170aSLeo Liu ~UVD_VCPU_CNTL__BLK_RST_MASK); 11538da1170aSLeo Liu mdelay(10); 11548da1170aSLeo Liu WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 11558da1170aSLeo Liu ~UVD_VCPU_CNTL__BLK_RST_MASK); 11568da1170aSLeo Liu 11578da1170aSLeo Liu mdelay(10); 11588da1170aSLeo Liu r = -1; 11598da1170aSLeo Liu } 11608da1170aSLeo Liu } 11618da1170aSLeo Liu 11628da1170aSLeo Liu if (r) { 1163bb4f196bSRuijing Dong dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i); 11648da1170aSLeo Liu return r; 11658da1170aSLeo Liu } 11668da1170aSLeo Liu 11678da1170aSLeo Liu /* enable master interrupt */ 11688da1170aSLeo Liu WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 11698da1170aSLeo Liu UVD_MASTINT_EN__VCPU_EN_MASK, 11708da1170aSLeo Liu ~UVD_MASTINT_EN__VCPU_EN_MASK); 11718da1170aSLeo Liu 11728da1170aSLeo Liu /* clear the busy bit of VCN_STATUS */ 11738da1170aSLeo Liu WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0, 11748da1170aSLeo Liu ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 11758da1170aSLeo Liu 11768da1170aSLeo Liu ring = &adev->vcn.inst[i].ring_enc[0]; 11778da1170aSLeo Liu WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL, 11788da1170aSLeo Liu ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 11798da1170aSLeo Liu VCN_RB1_DB_CTRL__EN_MASK); 1180bb4f196bSRuijing Dong 11818da1170aSLeo Liu WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr); 11828da1170aSLeo Liu WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 11838da1170aSLeo Liu WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4); 1184bb4f196bSRuijing Dong 1185bb4f196bSRuijing Dong tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 1186bb4f196bSRuijing Dong tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 1187bb4f196bSRuijing Dong WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 1188bb4f196bSRuijing Dong fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 1189bb4f196bSRuijing Dong WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0); 1190bb4f196bSRuijing Dong WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0); 1191bb4f196bSRuijing Dong 1192bb4f196bSRuijing Dong tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR); 1193bb4f196bSRuijing Dong WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp); 1194bb4f196bSRuijing Dong ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR); 1195bb4f196bSRuijing Dong 1196bb4f196bSRuijing Dong tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 1197bb4f196bSRuijing Dong tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 1198bb4f196bSRuijing Dong WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 11998da1170aSLeo Liu fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 12008da1170aSLeo Liu } 12018da1170aSLeo Liu 12028da1170aSLeo Liu return 0; 12038da1170aSLeo Liu } 12048da1170aSLeo Liu 1205aa44beb5SJane Jian static int vcn_v4_0_start_sriov(struct amdgpu_device *adev) 1206aa44beb5SJane Jian { 1207aa44beb5SJane Jian int i; 1208aa44beb5SJane Jian struct amdgpu_ring *ring_enc; 1209aa44beb5SJane Jian uint64_t cache_addr; 1210aa44beb5SJane Jian uint64_t rb_enc_addr; 1211aa44beb5SJane Jian uint64_t ctx_addr; 1212aa44beb5SJane Jian uint32_t param, resp, expected; 1213aa44beb5SJane Jian uint32_t offset, cache_size; 1214aa44beb5SJane Jian uint32_t tmp, timeout; 1215aa44beb5SJane Jian 1216aa44beb5SJane Jian struct amdgpu_mm_table *table = &adev->virt.mm_table; 1217aa44beb5SJane Jian uint32_t *table_loc; 1218aa44beb5SJane Jian uint32_t table_size; 1219aa44beb5SJane Jian uint32_t size, size_dw; 1220aa44beb5SJane Jian uint32_t init_status; 1221aa44beb5SJane Jian uint32_t enabled_vcn; 1222aa44beb5SJane Jian 1223aa44beb5SJane Jian struct mmsch_v4_0_cmd_direct_write 1224aa44beb5SJane Jian direct_wt = { {0} }; 1225aa44beb5SJane Jian struct mmsch_v4_0_cmd_direct_read_modify_write 1226aa44beb5SJane Jian direct_rd_mod_wt = { {0} }; 1227aa44beb5SJane Jian struct mmsch_v4_0_cmd_end end = { {0} }; 1228aa44beb5SJane Jian struct mmsch_v4_0_init_header header; 1229aa44beb5SJane Jian 1230aa44beb5SJane Jian volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1231aa44beb5SJane Jian volatile struct amdgpu_fw_shared_rb_setup *rb_setup; 1232aa44beb5SJane Jian 1233aa44beb5SJane Jian direct_wt.cmd_header.command_type = 1234aa44beb5SJane Jian MMSCH_COMMAND__DIRECT_REG_WRITE; 1235aa44beb5SJane Jian direct_rd_mod_wt.cmd_header.command_type = 1236aa44beb5SJane Jian MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1237aa44beb5SJane Jian end.cmd_header.command_type = 1238aa44beb5SJane Jian MMSCH_COMMAND__END; 1239aa44beb5SJane Jian 1240aa44beb5SJane Jian header.version = MMSCH_VERSION; 1241aa44beb5SJane Jian header.total_size = sizeof(struct mmsch_v4_0_init_header) >> 2; 1242aa44beb5SJane Jian for (i = 0; i < AMDGPU_MAX_VCN_INSTANCES; i++) { 1243aa44beb5SJane Jian header.inst[i].init_status = 0; 1244aa44beb5SJane Jian header.inst[i].table_offset = 0; 1245aa44beb5SJane Jian header.inst[i].table_size = 0; 1246aa44beb5SJane Jian } 1247aa44beb5SJane Jian 1248aa44beb5SJane Jian table_loc = (uint32_t *)table->cpu_addr; 1249aa44beb5SJane Jian table_loc += header.total_size; 1250aa44beb5SJane Jian for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1251aa44beb5SJane Jian if (adev->vcn.harvest_config & (1 << i)) 1252aa44beb5SJane Jian continue; 1253aa44beb5SJane Jian 1254aa44beb5SJane Jian table_size = 0; 1255aa44beb5SJane Jian 1256aa44beb5SJane Jian MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i, 1257aa44beb5SJane Jian regUVD_STATUS), 1258aa44beb5SJane Jian ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 1259aa44beb5SJane Jian 1260aa44beb5SJane Jian cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 1261aa44beb5SJane Jian 1262aa44beb5SJane Jian if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1263aa44beb5SJane Jian MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1264aa44beb5SJane Jian regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1265aa44beb5SJane Jian adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo); 1266aa44beb5SJane Jian MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1267aa44beb5SJane Jian regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1268aa44beb5SJane Jian adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi); 1269aa44beb5SJane Jian offset = 0; 1270aa44beb5SJane Jian MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1271aa44beb5SJane Jian regUVD_VCPU_CACHE_OFFSET0), 1272aa44beb5SJane Jian 0); 1273aa44beb5SJane Jian } else { 1274aa44beb5SJane Jian MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1275aa44beb5SJane Jian regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1276aa44beb5SJane Jian lower_32_bits(adev->vcn.inst[i].gpu_addr)); 1277aa44beb5SJane Jian MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1278aa44beb5SJane Jian regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1279aa44beb5SJane Jian upper_32_bits(adev->vcn.inst[i].gpu_addr)); 1280aa44beb5SJane Jian offset = cache_size; 1281aa44beb5SJane Jian MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1282aa44beb5SJane Jian regUVD_VCPU_CACHE_OFFSET0), 1283aa44beb5SJane Jian AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 1284aa44beb5SJane Jian } 1285aa44beb5SJane Jian 1286aa44beb5SJane Jian MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1287aa44beb5SJane Jian regUVD_VCPU_CACHE_SIZE0), 1288aa44beb5SJane Jian cache_size); 1289aa44beb5SJane Jian 1290aa44beb5SJane Jian cache_addr = adev->vcn.inst[i].gpu_addr + offset; 1291aa44beb5SJane Jian MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1292aa44beb5SJane Jian regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 1293aa44beb5SJane Jian lower_32_bits(cache_addr)); 1294aa44beb5SJane Jian MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1295aa44beb5SJane Jian regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 1296aa44beb5SJane Jian upper_32_bits(cache_addr)); 1297aa44beb5SJane Jian MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1298aa44beb5SJane Jian regUVD_VCPU_CACHE_OFFSET1), 1299aa44beb5SJane Jian 0); 1300aa44beb5SJane Jian MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1301aa44beb5SJane Jian regUVD_VCPU_CACHE_SIZE1), 1302aa44beb5SJane Jian AMDGPU_VCN_STACK_SIZE); 1303aa44beb5SJane Jian 1304aa44beb5SJane Jian cache_addr = adev->vcn.inst[i].gpu_addr + offset + 1305aa44beb5SJane Jian AMDGPU_VCN_STACK_SIZE; 1306aa44beb5SJane Jian MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1307aa44beb5SJane Jian regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 1308aa44beb5SJane Jian lower_32_bits(cache_addr)); 1309aa44beb5SJane Jian MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1310aa44beb5SJane Jian regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 1311aa44beb5SJane Jian upper_32_bits(cache_addr)); 1312aa44beb5SJane Jian MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1313aa44beb5SJane Jian regUVD_VCPU_CACHE_OFFSET2), 1314aa44beb5SJane Jian 0); 1315aa44beb5SJane Jian MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1316aa44beb5SJane Jian regUVD_VCPU_CACHE_SIZE2), 1317aa44beb5SJane Jian AMDGPU_VCN_CONTEXT_SIZE); 1318aa44beb5SJane Jian 1319aa44beb5SJane Jian fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1320aa44beb5SJane Jian rb_setup = &fw_shared->rb_setup; 1321aa44beb5SJane Jian 1322aa44beb5SJane Jian ring_enc = &adev->vcn.inst[i].ring_enc[0]; 1323aa44beb5SJane Jian ring_enc->wptr = 0; 1324aa44beb5SJane Jian rb_enc_addr = ring_enc->gpu_addr; 1325aa44beb5SJane Jian 1326aa44beb5SJane Jian rb_setup->is_rb_enabled_flags |= RB_ENABLED; 1327aa44beb5SJane Jian rb_setup->rb_addr_lo = lower_32_bits(rb_enc_addr); 1328aa44beb5SJane Jian rb_setup->rb_addr_hi = upper_32_bits(rb_enc_addr); 1329aa44beb5SJane Jian rb_setup->rb_size = ring_enc->ring_size / 4; 1330aa44beb5SJane Jian fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG); 1331aa44beb5SJane Jian 1332aa44beb5SJane Jian MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1333aa44beb5SJane Jian regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 1334aa44beb5SJane Jian lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); 1335aa44beb5SJane Jian MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1336aa44beb5SJane Jian regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 1337aa44beb5SJane Jian upper_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); 1338aa44beb5SJane Jian MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1339aa44beb5SJane Jian regUVD_VCPU_NONCACHE_SIZE0), 1340aa44beb5SJane Jian AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 1341aa44beb5SJane Jian 1342aa44beb5SJane Jian /* add end packet */ 1343aa44beb5SJane Jian MMSCH_V4_0_INSERT_END(); 1344aa44beb5SJane Jian 1345aa44beb5SJane Jian /* refine header */ 1346aa44beb5SJane Jian header.inst[i].init_status = 0; 1347aa44beb5SJane Jian header.inst[i].table_offset = header.total_size; 1348aa44beb5SJane Jian header.inst[i].table_size = table_size; 1349aa44beb5SJane Jian header.total_size += table_size; 1350aa44beb5SJane Jian } 1351aa44beb5SJane Jian 1352aa44beb5SJane Jian /* Update init table header in memory */ 1353aa44beb5SJane Jian size = sizeof(struct mmsch_v4_0_init_header); 1354aa44beb5SJane Jian table_loc = (uint32_t *)table->cpu_addr; 1355aa44beb5SJane Jian memcpy((void *)table_loc, &header, size); 1356aa44beb5SJane Jian 1357aa44beb5SJane Jian /* message MMSCH (in VCN[0]) to initialize this client 1358aa44beb5SJane Jian * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr 1359aa44beb5SJane Jian * of memory descriptor location 1360aa44beb5SJane Jian */ 1361aa44beb5SJane Jian ctx_addr = table->gpu_addr; 1362aa44beb5SJane Jian WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 1363aa44beb5SJane Jian WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 1364aa44beb5SJane Jian 1365aa44beb5SJane Jian /* 2, update vmid of descriptor */ 1366aa44beb5SJane Jian tmp = RREG32_SOC15(VCN, 0, regMMSCH_VF_VMID); 1367aa44beb5SJane Jian tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1368aa44beb5SJane Jian /* use domain0 for MM scheduler */ 1369aa44beb5SJane Jian tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1370aa44beb5SJane Jian WREG32_SOC15(VCN, 0, regMMSCH_VF_VMID, tmp); 1371aa44beb5SJane Jian 1372aa44beb5SJane Jian /* 3, notify mmsch about the size of this descriptor */ 1373aa44beb5SJane Jian size = header.total_size; 1374aa44beb5SJane Jian WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_SIZE, size); 1375aa44beb5SJane Jian 1376aa44beb5SJane Jian /* 4, set resp to zero */ 1377aa44beb5SJane Jian WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP, 0); 1378aa44beb5SJane Jian 1379aa44beb5SJane Jian /* 5, kick off the initialization and wait until 1380aa44beb5SJane Jian * MMSCH_VF_MAILBOX_RESP becomes non-zero 1381aa44beb5SJane Jian */ 1382aa44beb5SJane Jian param = 0x00000001; 1383aa44beb5SJane Jian WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_HOST, param); 1384aa44beb5SJane Jian tmp = 0; 1385aa44beb5SJane Jian timeout = 1000; 1386aa44beb5SJane Jian resp = 0; 1387aa44beb5SJane Jian expected = MMSCH_VF_MAILBOX_RESP__OK; 1388aa44beb5SJane Jian while (resp != expected) { 1389aa44beb5SJane Jian resp = RREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP); 1390aa44beb5SJane Jian if (resp != 0) 1391aa44beb5SJane Jian break; 1392aa44beb5SJane Jian 1393aa44beb5SJane Jian udelay(10); 1394aa44beb5SJane Jian tmp = tmp + 10; 1395aa44beb5SJane Jian if (tmp >= timeout) { 1396aa44beb5SJane Jian DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 1397aa44beb5SJane Jian " waiting for regMMSCH_VF_MAILBOX_RESP "\ 1398aa44beb5SJane Jian "(expected=0x%08x, readback=0x%08x)\n", 1399aa44beb5SJane Jian tmp, expected, resp); 1400aa44beb5SJane Jian return -EBUSY; 1401aa44beb5SJane Jian } 1402aa44beb5SJane Jian } 1403aa44beb5SJane Jian enabled_vcn = amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, 0) ? 1 : 0; 1404aa44beb5SJane Jian init_status = ((struct mmsch_v4_0_init_header *)(table_loc))->inst[enabled_vcn].init_status; 1405aa44beb5SJane Jian if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE 1406aa44beb5SJane Jian && init_status != MMSCH_VF_ENGINE_STATUS__PASS) 1407aa44beb5SJane Jian DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init "\ 1408aa44beb5SJane Jian "status for VCN%x: 0x%x\n", resp, enabled_vcn, init_status); 1409aa44beb5SJane Jian 1410aa44beb5SJane Jian return 0; 1411aa44beb5SJane Jian } 1412aa44beb5SJane Jian 14138da1170aSLeo Liu /** 14148da1170aSLeo Liu * vcn_v4_0_stop_dpg_mode - VCN stop with dpg mode 14158da1170aSLeo Liu * 14168da1170aSLeo Liu * @adev: amdgpu_device pointer 14178da1170aSLeo Liu * @inst_idx: instance number index 14188da1170aSLeo Liu * 14198da1170aSLeo Liu * Stop VCN block with dpg mode 14208da1170aSLeo Liu */ 1421385bf5a8SKhalid Masum static void vcn_v4_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) 14228da1170aSLeo Liu { 14238da1170aSLeo Liu uint32_t tmp; 14248da1170aSLeo Liu 14258da1170aSLeo Liu /* Wait for power status to be 1 */ 14268da1170aSLeo Liu SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, 14278da1170aSLeo Liu UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 14288da1170aSLeo Liu 14298da1170aSLeo Liu /* wait for read ptr to be equal to write ptr */ 14308da1170aSLeo Liu tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 14318da1170aSLeo Liu SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); 14328da1170aSLeo Liu 14338da1170aSLeo Liu SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, 14348da1170aSLeo Liu UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 14358da1170aSLeo Liu 14368da1170aSLeo Liu /* disable dynamic power gating mode */ 14378da1170aSLeo Liu WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0, 14388da1170aSLeo Liu ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 14398da1170aSLeo Liu } 14408da1170aSLeo Liu 14418da1170aSLeo Liu /** 14428da1170aSLeo Liu * vcn_v4_0_stop - VCN stop 14438da1170aSLeo Liu * 14448da1170aSLeo Liu * @adev: amdgpu_device pointer 14458da1170aSLeo Liu * 14468da1170aSLeo Liu * Stop VCN block 14478da1170aSLeo Liu */ 14488da1170aSLeo Liu static int vcn_v4_0_stop(struct amdgpu_device *adev) 14498da1170aSLeo Liu { 1450bb4f196bSRuijing Dong volatile struct amdgpu_vcn4_fw_shared *fw_shared; 14518da1170aSLeo Liu uint32_t tmp; 14528da1170aSLeo Liu int i, r = 0; 14538da1170aSLeo Liu 14548da1170aSLeo Liu for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1455bb4f196bSRuijing Dong fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1456bb4f196bSRuijing Dong fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; 1457bb4f196bSRuijing Dong 14588da1170aSLeo Liu if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1459385bf5a8SKhalid Masum vcn_v4_0_stop_dpg_mode(adev, i); 14608da1170aSLeo Liu continue; 14618da1170aSLeo Liu } 14628da1170aSLeo Liu 14638da1170aSLeo Liu /* wait for vcn idle */ 14648da1170aSLeo Liu r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); 14658da1170aSLeo Liu if (r) 14668da1170aSLeo Liu return r; 14678da1170aSLeo Liu 14688da1170aSLeo Liu tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 14698da1170aSLeo Liu UVD_LMI_STATUS__READ_CLEAN_MASK | 14708da1170aSLeo Liu UVD_LMI_STATUS__WRITE_CLEAN_MASK | 14718da1170aSLeo Liu UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 14728da1170aSLeo Liu r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 14738da1170aSLeo Liu if (r) 14748da1170aSLeo Liu return r; 14758da1170aSLeo Liu 14768da1170aSLeo Liu /* disable LMI UMC channel */ 14778da1170aSLeo Liu tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2); 14788da1170aSLeo Liu tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 14798da1170aSLeo Liu WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp); 14808da1170aSLeo Liu tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 14818da1170aSLeo Liu UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 14828da1170aSLeo Liu r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 14838da1170aSLeo Liu if (r) 14848da1170aSLeo Liu return r; 14858da1170aSLeo Liu 14868da1170aSLeo Liu /* block VCPU register access */ 14878da1170aSLeo Liu WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 14888da1170aSLeo Liu UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 14898da1170aSLeo Liu ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 14908da1170aSLeo Liu 14918da1170aSLeo Liu /* reset VCPU */ 14928da1170aSLeo Liu WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 14938da1170aSLeo Liu UVD_VCPU_CNTL__BLK_RST_MASK, 14948da1170aSLeo Liu ~UVD_VCPU_CNTL__BLK_RST_MASK); 14958da1170aSLeo Liu 14968da1170aSLeo Liu /* disable VCPU clock */ 14978da1170aSLeo Liu WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 14988da1170aSLeo Liu ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 14998da1170aSLeo Liu 15008da1170aSLeo Liu /* apply soft reset */ 15018da1170aSLeo Liu tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 15028da1170aSLeo Liu tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 15038da1170aSLeo Liu WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 15048da1170aSLeo Liu tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 15058da1170aSLeo Liu tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 15068da1170aSLeo Liu WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 15078da1170aSLeo Liu 15088da1170aSLeo Liu /* clear status */ 15098da1170aSLeo Liu WREG32_SOC15(VCN, i, regUVD_STATUS, 0); 15108da1170aSLeo Liu 15118da1170aSLeo Liu /* apply HW clock gating */ 15128da1170aSLeo Liu vcn_v4_0_enable_clock_gating(adev, i); 15138da1170aSLeo Liu 15148da1170aSLeo Liu /* enable VCN power gating */ 15158da1170aSLeo Liu vcn_v4_0_enable_static_power_gating(adev, i); 15168da1170aSLeo Liu } 15178da1170aSLeo Liu 15188da1170aSLeo Liu if (adev->pm.dpm_enabled) 15198da1170aSLeo Liu amdgpu_dpm_enable_uvd(adev, false); 15208da1170aSLeo Liu 15218da1170aSLeo Liu return 0; 15228da1170aSLeo Liu } 15238da1170aSLeo Liu 15248da1170aSLeo Liu /** 15258da1170aSLeo Liu * vcn_v4_0_pause_dpg_mode - VCN pause with dpg mode 15268da1170aSLeo Liu * 15278da1170aSLeo Liu * @adev: amdgpu_device pointer 15288da1170aSLeo Liu * @inst_idx: instance number index 15298da1170aSLeo Liu * @new_state: pause state 15308da1170aSLeo Liu * 15318da1170aSLeo Liu * Pause dpg mode for VCN block 15328da1170aSLeo Liu */ 15338da1170aSLeo Liu static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx, 15348da1170aSLeo Liu struct dpg_pause_state *new_state) 15358da1170aSLeo Liu { 15368da1170aSLeo Liu uint32_t reg_data = 0; 15378da1170aSLeo Liu int ret_code; 15388da1170aSLeo Liu 15398da1170aSLeo Liu /* pause/unpause if state is changed */ 15408da1170aSLeo Liu if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 15418da1170aSLeo Liu DRM_DEV_DEBUG(adev->dev, "dpg pause state changed %d -> %d", 15428da1170aSLeo Liu adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 15438da1170aSLeo Liu reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) & 15448da1170aSLeo Liu (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 15458da1170aSLeo Liu 15468da1170aSLeo Liu if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 15478da1170aSLeo Liu ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1, 15488da1170aSLeo Liu UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 15498da1170aSLeo Liu 15508da1170aSLeo Liu if (!ret_code) { 15518da1170aSLeo Liu /* pause DPG */ 15528da1170aSLeo Liu reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 15538da1170aSLeo Liu WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 15548da1170aSLeo Liu 15558da1170aSLeo Liu /* wait for ACK */ 15568da1170aSLeo Liu SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE, 15578da1170aSLeo Liu UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 15588da1170aSLeo Liu UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 15598da1170aSLeo Liu 15608da1170aSLeo Liu SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 15618da1170aSLeo Liu UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 15628da1170aSLeo Liu } 15638da1170aSLeo Liu } else { 15648da1170aSLeo Liu /* unpause dpg, no need to wait */ 15658da1170aSLeo Liu reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 15668da1170aSLeo Liu WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 15678da1170aSLeo Liu } 15688da1170aSLeo Liu adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 15698da1170aSLeo Liu } 15708da1170aSLeo Liu 15718da1170aSLeo Liu return 0; 15728da1170aSLeo Liu } 15738da1170aSLeo Liu 15748da1170aSLeo Liu /** 1575bb4f196bSRuijing Dong * vcn_v4_0_unified_ring_get_rptr - get unified read pointer 15768da1170aSLeo Liu * 15778da1170aSLeo Liu * @ring: amdgpu_ring pointer 15788da1170aSLeo Liu * 1579bb4f196bSRuijing Dong * Returns the current hardware unified read pointer 15808da1170aSLeo Liu */ 1581bb4f196bSRuijing Dong static uint64_t vcn_v4_0_unified_ring_get_rptr(struct amdgpu_ring *ring) 15828da1170aSLeo Liu { 15838da1170aSLeo Liu struct amdgpu_device *adev = ring->adev; 15848da1170aSLeo Liu 1585bb4f196bSRuijing Dong if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1586bb4f196bSRuijing Dong DRM_ERROR("wrong ring id is identified in %s", __func__); 15878da1170aSLeo Liu 15888da1170aSLeo Liu return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR); 15898da1170aSLeo Liu } 15908da1170aSLeo Liu 15918da1170aSLeo Liu /** 1592bb4f196bSRuijing Dong * vcn_v4_0_unified_ring_get_wptr - get unified write pointer 15938da1170aSLeo Liu * 15948da1170aSLeo Liu * @ring: amdgpu_ring pointer 15958da1170aSLeo Liu * 1596bb4f196bSRuijing Dong * Returns the current hardware unified write pointer 15978da1170aSLeo Liu */ 1598bb4f196bSRuijing Dong static uint64_t vcn_v4_0_unified_ring_get_wptr(struct amdgpu_ring *ring) 15998da1170aSLeo Liu { 16008da1170aSLeo Liu struct amdgpu_device *adev = ring->adev; 16018da1170aSLeo Liu 1602bb4f196bSRuijing Dong if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1603bb4f196bSRuijing Dong DRM_ERROR("wrong ring id is identified in %s", __func__); 1604bb4f196bSRuijing Dong 16058da1170aSLeo Liu if (ring->use_doorbell) 16068da1170aSLeo Liu return *ring->wptr_cpu_addr; 16078da1170aSLeo Liu else 16088da1170aSLeo Liu return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR); 16098da1170aSLeo Liu } 16108da1170aSLeo Liu 16118da1170aSLeo Liu /** 1612bb4f196bSRuijing Dong * vcn_v4_0_unified_ring_set_wptr - set enc write pointer 16138da1170aSLeo Liu * 16148da1170aSLeo Liu * @ring: amdgpu_ring pointer 16158da1170aSLeo Liu * 16168da1170aSLeo Liu * Commits the enc write pointer to the hardware 16178da1170aSLeo Liu */ 1618bb4f196bSRuijing Dong static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring) 16198da1170aSLeo Liu { 16208da1170aSLeo Liu struct amdgpu_device *adev = ring->adev; 16218da1170aSLeo Liu 1622bb4f196bSRuijing Dong if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1623bb4f196bSRuijing Dong DRM_ERROR("wrong ring id is identified in %s", __func__); 1624bb4f196bSRuijing Dong 16258da1170aSLeo Liu if (ring->use_doorbell) { 16268da1170aSLeo Liu *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 16278da1170aSLeo Liu WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 16288da1170aSLeo Liu } else { 16298da1170aSLeo Liu WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr)); 16308da1170aSLeo Liu } 16318da1170aSLeo Liu } 16328da1170aSLeo Liu 1633c05d789fSChristian König static int vcn_v4_0_limit_sched(struct amdgpu_cs_parser *p, 1634c05d789fSChristian König struct amdgpu_job *job) 16350b15205cSSonny Jiang { 16360b15205cSSonny Jiang struct drm_gpu_scheduler **scheds; 16370b15205cSSonny Jiang 16380b15205cSSonny Jiang /* The create msg must be in the first IB submitted */ 1639c05d789fSChristian König if (atomic_read(&job->base.entity->fence_seq)) 16400b15205cSSonny Jiang return -EINVAL; 16410b15205cSSonny Jiang 16426482ba5dSAlex Deucher /* if VCN0 is harvested, we can't support AV1 */ 16436482ba5dSAlex Deucher if (p->adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) 16446482ba5dSAlex Deucher return -EINVAL; 16456482ba5dSAlex Deucher 16460b15205cSSonny Jiang scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_ENC] 16470b15205cSSonny Jiang [AMDGPU_RING_PRIO_0].sched; 1648c05d789fSChristian König drm_sched_entity_modify_sched(job->base.entity, scheds, 1); 16490b15205cSSonny Jiang return 0; 16500b15205cSSonny Jiang } 16510b15205cSSonny Jiang 1652c05d789fSChristian König static int vcn_v4_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job, 1653c05d789fSChristian König uint64_t addr) 16540b15205cSSonny Jiang { 16550b15205cSSonny Jiang struct ttm_operation_ctx ctx = { false, false }; 16560b15205cSSonny Jiang struct amdgpu_bo_va_mapping *map; 16570b15205cSSonny Jiang uint32_t *msg, num_buffers; 16580b15205cSSonny Jiang struct amdgpu_bo *bo; 16590b15205cSSonny Jiang uint64_t start, end; 16600b15205cSSonny Jiang unsigned int i; 16610b15205cSSonny Jiang void *ptr; 16620b15205cSSonny Jiang int r; 16630b15205cSSonny Jiang 16640b15205cSSonny Jiang addr &= AMDGPU_GMC_HOLE_MASK; 16650b15205cSSonny Jiang r = amdgpu_cs_find_mapping(p, addr, &bo, &map); 16660b15205cSSonny Jiang if (r) { 16670b15205cSSonny Jiang DRM_ERROR("Can't find BO for addr 0x%08llx\n", addr); 16680b15205cSSonny Jiang return r; 16690b15205cSSonny Jiang } 16700b15205cSSonny Jiang 16710b15205cSSonny Jiang start = map->start * AMDGPU_GPU_PAGE_SIZE; 16720b15205cSSonny Jiang end = (map->last + 1) * AMDGPU_GPU_PAGE_SIZE; 16730b15205cSSonny Jiang if (addr & 0x7) { 16740b15205cSSonny Jiang DRM_ERROR("VCN messages must be 8 byte aligned!\n"); 16750b15205cSSonny Jiang return -EINVAL; 16760b15205cSSonny Jiang } 16770b15205cSSonny Jiang 16780b15205cSSonny Jiang bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 16790b15205cSSonny Jiang amdgpu_bo_placement_from_domain(bo, bo->allowed_domains); 16800b15205cSSonny Jiang r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 16810b15205cSSonny Jiang if (r) { 16820b15205cSSonny Jiang DRM_ERROR("Failed validating the VCN message BO (%d)!\n", r); 16830b15205cSSonny Jiang return r; 16840b15205cSSonny Jiang } 16850b15205cSSonny Jiang 16860b15205cSSonny Jiang r = amdgpu_bo_kmap(bo, &ptr); 16870b15205cSSonny Jiang if (r) { 16880b15205cSSonny Jiang DRM_ERROR("Failed mapping the VCN message (%d)!\n", r); 16890b15205cSSonny Jiang return r; 16900b15205cSSonny Jiang } 16910b15205cSSonny Jiang 16920b15205cSSonny Jiang msg = ptr + addr - start; 16930b15205cSSonny Jiang 16940b15205cSSonny Jiang /* Check length */ 16950b15205cSSonny Jiang if (msg[1] > end - addr) { 16960b15205cSSonny Jiang r = -EINVAL; 16970b15205cSSonny Jiang goto out; 16980b15205cSSonny Jiang } 16990b15205cSSonny Jiang 17000b15205cSSonny Jiang if (msg[3] != RDECODE_MSG_CREATE) 17010b15205cSSonny Jiang goto out; 17020b15205cSSonny Jiang 17030b15205cSSonny Jiang num_buffers = msg[2]; 17040b15205cSSonny Jiang for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) { 17050b15205cSSonny Jiang uint32_t offset, size, *create; 17060b15205cSSonny Jiang 17070b15205cSSonny Jiang if (msg[0] != RDECODE_MESSAGE_CREATE) 17080b15205cSSonny Jiang continue; 17090b15205cSSonny Jiang 17100b15205cSSonny Jiang offset = msg[1]; 17110b15205cSSonny Jiang size = msg[2]; 17120b15205cSSonny Jiang 17130b15205cSSonny Jiang if (offset + size > end) { 17140b15205cSSonny Jiang r = -EINVAL; 17150b15205cSSonny Jiang goto out; 17160b15205cSSonny Jiang } 17170b15205cSSonny Jiang 17180b15205cSSonny Jiang create = ptr + addr + offset - start; 17190b15205cSSonny Jiang 1720f823323bSDavid (Ming Qiang) Wu /* H264, HEVC and VP9 can run on any instance */ 17210b15205cSSonny Jiang if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11) 17220b15205cSSonny Jiang continue; 17230b15205cSSonny Jiang 1724c05d789fSChristian König r = vcn_v4_0_limit_sched(p, job); 17250b15205cSSonny Jiang if (r) 17260b15205cSSonny Jiang goto out; 17270b15205cSSonny Jiang } 17280b15205cSSonny Jiang 17290b15205cSSonny Jiang out: 17300b15205cSSonny Jiang amdgpu_bo_kunmap(bo); 17310b15205cSSonny Jiang return r; 17320b15205cSSonny Jiang } 17330b15205cSSonny Jiang 1734f823323bSDavid (Ming Qiang) Wu #define RADEON_VCN_ENGINE_TYPE_ENCODE (0x00000002) 17350b15205cSSonny Jiang #define RADEON_VCN_ENGINE_TYPE_DECODE (0x00000003) 17360b15205cSSonny Jiang 1737f823323bSDavid (Ming Qiang) Wu #define RADEON_VCN_ENGINE_INFO (0x30000001) 1738f823323bSDavid (Ming Qiang) Wu #define RADEON_VCN_ENGINE_INFO_MAX_OFFSET 16 1739f823323bSDavid (Ming Qiang) Wu 1740f823323bSDavid (Ming Qiang) Wu #define RENCODE_ENCODE_STANDARD_AV1 2 1741f823323bSDavid (Ming Qiang) Wu #define RENCODE_IB_PARAM_SESSION_INIT 0x00000003 1742f823323bSDavid (Ming Qiang) Wu #define RENCODE_IB_PARAM_SESSION_INIT_MAX_OFFSET 64 1743f823323bSDavid (Ming Qiang) Wu 1744f823323bSDavid (Ming Qiang) Wu /* return the offset in ib if id is found, -1 otherwise 1745f823323bSDavid (Ming Qiang) Wu * to speed up the searching we only search upto max_offset 1746f823323bSDavid (Ming Qiang) Wu */ 1747f823323bSDavid (Ming Qiang) Wu static int vcn_v4_0_enc_find_ib_param(struct amdgpu_ib *ib, uint32_t id, int max_offset) 1748f823323bSDavid (Ming Qiang) Wu { 1749f823323bSDavid (Ming Qiang) Wu int i; 1750f823323bSDavid (Ming Qiang) Wu 1751f823323bSDavid (Ming Qiang) Wu for (i = 0; i < ib->length_dw && i < max_offset && ib->ptr[i] >= 8; i += ib->ptr[i]/4) { 1752f823323bSDavid (Ming Qiang) Wu if (ib->ptr[i + 1] == id) 1753f823323bSDavid (Ming Qiang) Wu return i; 1754f823323bSDavid (Ming Qiang) Wu } 1755f823323bSDavid (Ming Qiang) Wu return -1; 1756f823323bSDavid (Ming Qiang) Wu } 1757f823323bSDavid (Ming Qiang) Wu 17580b15205cSSonny Jiang static int vcn_v4_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, 17590b15205cSSonny Jiang struct amdgpu_job *job, 17600b15205cSSonny Jiang struct amdgpu_ib *ib) 17610b15205cSSonny Jiang { 1762c05d789fSChristian König struct amdgpu_ring *ring = amdgpu_job_ring(job); 1763c05d789fSChristian König struct amdgpu_vcn_decode_buffer *decode_buffer; 1764c05d789fSChristian König uint64_t addr; 17650b15205cSSonny Jiang uint32_t val; 1766f823323bSDavid (Ming Qiang) Wu int idx; 17670b15205cSSonny Jiang 17680b15205cSSonny Jiang /* The first instance can decode anything */ 17690b15205cSSonny Jiang if (!ring->me) 1770c05d789fSChristian König return 0; 17710b15205cSSonny Jiang 1772f823323bSDavid (Ming Qiang) Wu /* RADEON_VCN_ENGINE_INFO is at the top of ib block */ 1773f823323bSDavid (Ming Qiang) Wu idx = vcn_v4_0_enc_find_ib_param(ib, RADEON_VCN_ENGINE_INFO, 1774f823323bSDavid (Ming Qiang) Wu RADEON_VCN_ENGINE_INFO_MAX_OFFSET); 1775f823323bSDavid (Ming Qiang) Wu if (idx < 0) /* engine info is missing */ 1776c05d789fSChristian König return 0; 17770b15205cSSonny Jiang 1778f823323bSDavid (Ming Qiang) Wu val = amdgpu_ib_get_value(ib, idx + 2); /* RADEON_VCN_ENGINE_TYPE */ 1779f823323bSDavid (Ming Qiang) Wu if (val == RADEON_VCN_ENGINE_TYPE_DECODE) { 1780f823323bSDavid (Ming Qiang) Wu decode_buffer = (struct amdgpu_vcn_decode_buffer *)&ib->ptr[idx + 6]; 17810b15205cSSonny Jiang 1782c05d789fSChristian König if (!(decode_buffer->valid_buf_flag & 0x1)) 1783c05d789fSChristian König return 0; 1784c05d789fSChristian König 1785c05d789fSChristian König addr = ((u64)decode_buffer->msg_buffer_address_hi) << 32 | 1786c05d789fSChristian König decode_buffer->msg_buffer_address_lo; 1787c05d789fSChristian König return vcn_v4_0_dec_msg(p, job, addr); 1788f823323bSDavid (Ming Qiang) Wu } else if (val == RADEON_VCN_ENGINE_TYPE_ENCODE) { 1789f823323bSDavid (Ming Qiang) Wu idx = vcn_v4_0_enc_find_ib_param(ib, RENCODE_IB_PARAM_SESSION_INIT, 1790f823323bSDavid (Ming Qiang) Wu RENCODE_IB_PARAM_SESSION_INIT_MAX_OFFSET); 1791f823323bSDavid (Ming Qiang) Wu if (idx >= 0 && ib->ptr[idx + 2] == RENCODE_ENCODE_STANDARD_AV1) 1792f823323bSDavid (Ming Qiang) Wu return vcn_v4_0_limit_sched(p, job); 1793f823323bSDavid (Ming Qiang) Wu } 1794f823323bSDavid (Ming Qiang) Wu return 0; 17950b15205cSSonny Jiang } 17960b15205cSSonny Jiang 1797bb4f196bSRuijing Dong static const struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = { 17988da1170aSLeo Liu .type = AMDGPU_RING_TYPE_VCN_ENC, 17998da1170aSLeo Liu .align_mask = 0x3f, 18008da1170aSLeo Liu .nop = VCN_ENC_CMD_NO_OP, 1801bb4f196bSRuijing Dong .get_rptr = vcn_v4_0_unified_ring_get_rptr, 1802bb4f196bSRuijing Dong .get_wptr = vcn_v4_0_unified_ring_get_wptr, 1803bb4f196bSRuijing Dong .set_wptr = vcn_v4_0_unified_ring_set_wptr, 18040b15205cSSonny Jiang .patch_cs_in_place = vcn_v4_0_ring_patch_cs_in_place, 18058da1170aSLeo Liu .emit_frame_size = 18068da1170aSLeo Liu SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 18078da1170aSLeo Liu SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 18088da1170aSLeo Liu 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 18098da1170aSLeo Liu 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 18108da1170aSLeo Liu 1, /* vcn_v2_0_enc_ring_insert_end */ 18118da1170aSLeo Liu .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 18128da1170aSLeo Liu .emit_ib = vcn_v2_0_enc_ring_emit_ib, 18138da1170aSLeo Liu .emit_fence = vcn_v2_0_enc_ring_emit_fence, 18148da1170aSLeo Liu .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 18158da1170aSLeo Liu .test_ring = amdgpu_vcn_enc_ring_test_ring, 1816bb4f196bSRuijing Dong .test_ib = amdgpu_vcn_unified_ring_test_ib, 18178da1170aSLeo Liu .insert_nop = amdgpu_ring_insert_nop, 18188da1170aSLeo Liu .insert_end = vcn_v2_0_enc_ring_insert_end, 18198da1170aSLeo Liu .pad_ib = amdgpu_ring_generic_pad_ib, 18208da1170aSLeo Liu .begin_use = amdgpu_vcn_ring_begin_use, 18218da1170aSLeo Liu .end_use = amdgpu_vcn_ring_end_use, 18228da1170aSLeo Liu .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 18238da1170aSLeo Liu .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 18248da1170aSLeo Liu .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 18258da1170aSLeo Liu }; 18268da1170aSLeo Liu 18278da1170aSLeo Liu /** 1828bb4f196bSRuijing Dong * vcn_v4_0_set_unified_ring_funcs - set unified ring functions 18298da1170aSLeo Liu * 18308da1170aSLeo Liu * @adev: amdgpu_device pointer 18318da1170aSLeo Liu * 1832bb4f196bSRuijing Dong * Set unified ring functions 18338da1170aSLeo Liu */ 1834bb4f196bSRuijing Dong static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev) 18358da1170aSLeo Liu { 18368da1170aSLeo Liu int i; 18378da1170aSLeo Liu 18388da1170aSLeo Liu for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 18398da1170aSLeo Liu if (adev->vcn.harvest_config & (1 << i)) 18408da1170aSLeo Liu continue; 18418da1170aSLeo Liu 1842bb4f196bSRuijing Dong adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_unified_ring_vm_funcs; 1843bb4f196bSRuijing Dong adev->vcn.inst[i].ring_enc[0].me = i; 18448da1170aSLeo Liu 1845bb4f196bSRuijing Dong DRM_INFO("VCN(%d) encode/decode are enabled in VM mode\n", i); 18468da1170aSLeo Liu } 18478da1170aSLeo Liu } 18488da1170aSLeo Liu 18498da1170aSLeo Liu /** 18508da1170aSLeo Liu * vcn_v4_0_is_idle - check VCN block is idle 18518da1170aSLeo Liu * 18528da1170aSLeo Liu * @handle: amdgpu_device pointer 18538da1170aSLeo Liu * 18548da1170aSLeo Liu * Check whether VCN block is idle 18558da1170aSLeo Liu */ 18568da1170aSLeo Liu static bool vcn_v4_0_is_idle(void *handle) 18578da1170aSLeo Liu { 18588da1170aSLeo Liu struct amdgpu_device *adev = (struct amdgpu_device *)handle; 18598da1170aSLeo Liu int i, ret = 1; 18608da1170aSLeo Liu 18618da1170aSLeo Liu for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 18628da1170aSLeo Liu if (adev->vcn.harvest_config & (1 << i)) 18638da1170aSLeo Liu continue; 18648da1170aSLeo Liu 18658da1170aSLeo Liu ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE); 18668da1170aSLeo Liu } 18678da1170aSLeo Liu 18688da1170aSLeo Liu return ret; 18698da1170aSLeo Liu } 18708da1170aSLeo Liu 18718da1170aSLeo Liu /** 18728da1170aSLeo Liu * vcn_v4_0_wait_for_idle - wait for VCN block idle 18738da1170aSLeo Liu * 18748da1170aSLeo Liu * @handle: amdgpu_device pointer 18758da1170aSLeo Liu * 18768da1170aSLeo Liu * Wait for VCN block idle 18778da1170aSLeo Liu */ 18788da1170aSLeo Liu static int vcn_v4_0_wait_for_idle(void *handle) 18798da1170aSLeo Liu { 18808da1170aSLeo Liu struct amdgpu_device *adev = (struct amdgpu_device *)handle; 18818da1170aSLeo Liu int i, ret = 0; 18828da1170aSLeo Liu 18838da1170aSLeo Liu for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 18848da1170aSLeo Liu if (adev->vcn.harvest_config & (1 << i)) 18858da1170aSLeo Liu continue; 18868da1170aSLeo Liu 18878da1170aSLeo Liu ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 18888da1170aSLeo Liu UVD_STATUS__IDLE); 18898da1170aSLeo Liu if (ret) 18908da1170aSLeo Liu return ret; 18918da1170aSLeo Liu } 18928da1170aSLeo Liu 18938da1170aSLeo Liu return ret; 18948da1170aSLeo Liu } 18958da1170aSLeo Liu 18968da1170aSLeo Liu /** 18978da1170aSLeo Liu * vcn_v4_0_set_clockgating_state - set VCN block clockgating state 18988da1170aSLeo Liu * 18998da1170aSLeo Liu * @handle: amdgpu_device pointer 19008da1170aSLeo Liu * @state: clock gating state 19018da1170aSLeo Liu * 19028da1170aSLeo Liu * Set VCN block clockgating state 19038da1170aSLeo Liu */ 19048da1170aSLeo Liu static int vcn_v4_0_set_clockgating_state(void *handle, enum amd_clockgating_state state) 19058da1170aSLeo Liu { 19068da1170aSLeo Liu struct amdgpu_device *adev = (struct amdgpu_device *)handle; 19078da1170aSLeo Liu bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 19088da1170aSLeo Liu int i; 19098da1170aSLeo Liu 19108da1170aSLeo Liu for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 19118da1170aSLeo Liu if (adev->vcn.harvest_config & (1 << i)) 19128da1170aSLeo Liu continue; 19138da1170aSLeo Liu 19148da1170aSLeo Liu if (enable) { 19158da1170aSLeo Liu if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE) 19168da1170aSLeo Liu return -EBUSY; 19178da1170aSLeo Liu vcn_v4_0_enable_clock_gating(adev, i); 19188da1170aSLeo Liu } else { 19198da1170aSLeo Liu vcn_v4_0_disable_clock_gating(adev, i); 19208da1170aSLeo Liu } 19218da1170aSLeo Liu } 19228da1170aSLeo Liu 19238da1170aSLeo Liu return 0; 19248da1170aSLeo Liu } 19258da1170aSLeo Liu 19268da1170aSLeo Liu /** 19278da1170aSLeo Liu * vcn_v4_0_set_powergating_state - set VCN block powergating state 19288da1170aSLeo Liu * 19298da1170aSLeo Liu * @handle: amdgpu_device pointer 19308da1170aSLeo Liu * @state: power gating state 19318da1170aSLeo Liu * 19328da1170aSLeo Liu * Set VCN block powergating state 19338da1170aSLeo Liu */ 19348da1170aSLeo Liu static int vcn_v4_0_set_powergating_state(void *handle, enum amd_powergating_state state) 19358da1170aSLeo Liu { 19368da1170aSLeo Liu struct amdgpu_device *adev = (struct amdgpu_device *)handle; 19378da1170aSLeo Liu int ret; 19388da1170aSLeo Liu 1939aa44beb5SJane Jian /* for SRIOV, guest should not control VCN Power-gating 1940aa44beb5SJane Jian * MMSCH FW should control Power-gating and clock-gating 1941aa44beb5SJane Jian * guest should avoid touching CGC and PG 1942aa44beb5SJane Jian */ 1943aa44beb5SJane Jian if (amdgpu_sriov_vf(adev)) { 1944aa44beb5SJane Jian adev->vcn.cur_state = AMD_PG_STATE_UNGATE; 1945aa44beb5SJane Jian return 0; 1946aa44beb5SJane Jian } 1947aa44beb5SJane Jian 19488da1170aSLeo Liu if(state == adev->vcn.cur_state) 19498da1170aSLeo Liu return 0; 19508da1170aSLeo Liu 19518da1170aSLeo Liu if (state == AMD_PG_STATE_GATE) 19528da1170aSLeo Liu ret = vcn_v4_0_stop(adev); 19538da1170aSLeo Liu else 19548da1170aSLeo Liu ret = vcn_v4_0_start(adev); 19558da1170aSLeo Liu 19568da1170aSLeo Liu if(!ret) 19578da1170aSLeo Liu adev->vcn.cur_state = state; 19588da1170aSLeo Liu 19598da1170aSLeo Liu return ret; 19608da1170aSLeo Liu } 19618da1170aSLeo Liu 19628da1170aSLeo Liu /** 19638da1170aSLeo Liu * vcn_v4_0_set_interrupt_state - set VCN block interrupt state 19648da1170aSLeo Liu * 19658da1170aSLeo Liu * @adev: amdgpu_device pointer 19668da1170aSLeo Liu * @source: interrupt sources 19678da1170aSLeo Liu * @type: interrupt types 19688da1170aSLeo Liu * @state: interrupt states 19698da1170aSLeo Liu * 19708da1170aSLeo Liu * Set VCN block interrupt state 19718da1170aSLeo Liu */ 19728da1170aSLeo Liu static int vcn_v4_0_set_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 19738da1170aSLeo Liu unsigned type, enum amdgpu_interrupt_state state) 19748da1170aSLeo Liu { 19758da1170aSLeo Liu return 0; 19768da1170aSLeo Liu } 19778da1170aSLeo Liu 19788da1170aSLeo Liu /** 19798da1170aSLeo Liu * vcn_v4_0_process_interrupt - process VCN block interrupt 19808da1170aSLeo Liu * 19818da1170aSLeo Liu * @adev: amdgpu_device pointer 19828da1170aSLeo Liu * @source: interrupt sources 19838da1170aSLeo Liu * @entry: interrupt entry from clients and sources 19848da1170aSLeo Liu * 19858da1170aSLeo Liu * Process VCN block interrupt 19868da1170aSLeo Liu */ 19878da1170aSLeo Liu static int vcn_v4_0_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 19888da1170aSLeo Liu struct amdgpu_iv_entry *entry) 19898da1170aSLeo Liu { 19908da1170aSLeo Liu uint32_t ip_instance; 19918da1170aSLeo Liu 19928da1170aSLeo Liu switch (entry->client_id) { 19938da1170aSLeo Liu case SOC15_IH_CLIENTID_VCN: 19948da1170aSLeo Liu ip_instance = 0; 19958da1170aSLeo Liu break; 19968da1170aSLeo Liu case SOC15_IH_CLIENTID_VCN1: 19978da1170aSLeo Liu ip_instance = 1; 19988da1170aSLeo Liu break; 19998da1170aSLeo Liu default: 20008da1170aSLeo Liu DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 20018da1170aSLeo Liu return 0; 20028da1170aSLeo Liu } 20038da1170aSLeo Liu 20048da1170aSLeo Liu DRM_DEBUG("IH: VCN TRAP\n"); 20058da1170aSLeo Liu 20068da1170aSLeo Liu switch (entry->src_id) { 20078da1170aSLeo Liu case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 20088da1170aSLeo Liu amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 20098da1170aSLeo Liu break; 2010ea5309deSTao Zhou case VCN_4_0__SRCID_UVD_POISON: 2011ea5309deSTao Zhou amdgpu_vcn_process_poison_irq(adev, source, entry); 2012ea5309deSTao Zhou break; 20138da1170aSLeo Liu default: 20148da1170aSLeo Liu DRM_ERROR("Unhandled interrupt: %d %d\n", 20158da1170aSLeo Liu entry->src_id, entry->src_data[0]); 20168da1170aSLeo Liu break; 20178da1170aSLeo Liu } 20188da1170aSLeo Liu 20198da1170aSLeo Liu return 0; 20208da1170aSLeo Liu } 20218da1170aSLeo Liu 20228da1170aSLeo Liu static const struct amdgpu_irq_src_funcs vcn_v4_0_irq_funcs = { 20238da1170aSLeo Liu .set = vcn_v4_0_set_interrupt_state, 20248da1170aSLeo Liu .process = vcn_v4_0_process_interrupt, 20258da1170aSLeo Liu }; 20268da1170aSLeo Liu 20278da1170aSLeo Liu /** 20288da1170aSLeo Liu * vcn_v4_0_set_irq_funcs - set VCN block interrupt irq functions 20298da1170aSLeo Liu * 20308da1170aSLeo Liu * @adev: amdgpu_device pointer 20318da1170aSLeo Liu * 20328da1170aSLeo Liu * Set VCN block interrupt irq functions 20338da1170aSLeo Liu */ 20348da1170aSLeo Liu static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev) 20358da1170aSLeo Liu { 20368da1170aSLeo Liu int i; 20378da1170aSLeo Liu 20388da1170aSLeo Liu for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 20398da1170aSLeo Liu if (adev->vcn.harvest_config & (1 << i)) 20408da1170aSLeo Liu continue; 20418da1170aSLeo Liu 20428da1170aSLeo Liu adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1; 20438da1170aSLeo Liu adev->vcn.inst[i].irq.funcs = &vcn_v4_0_irq_funcs; 20448da1170aSLeo Liu } 20458da1170aSLeo Liu } 20468da1170aSLeo Liu 20478da1170aSLeo Liu static const struct amd_ip_funcs vcn_v4_0_ip_funcs = { 20488da1170aSLeo Liu .name = "vcn_v4_0", 20498da1170aSLeo Liu .early_init = vcn_v4_0_early_init, 20508da1170aSLeo Liu .late_init = NULL, 20518da1170aSLeo Liu .sw_init = vcn_v4_0_sw_init, 20528da1170aSLeo Liu .sw_fini = vcn_v4_0_sw_fini, 20538da1170aSLeo Liu .hw_init = vcn_v4_0_hw_init, 20548da1170aSLeo Liu .hw_fini = vcn_v4_0_hw_fini, 20558da1170aSLeo Liu .suspend = vcn_v4_0_suspend, 20568da1170aSLeo Liu .resume = vcn_v4_0_resume, 20578da1170aSLeo Liu .is_idle = vcn_v4_0_is_idle, 20588da1170aSLeo Liu .wait_for_idle = vcn_v4_0_wait_for_idle, 20598da1170aSLeo Liu .check_soft_reset = NULL, 20608da1170aSLeo Liu .pre_soft_reset = NULL, 20618da1170aSLeo Liu .soft_reset = NULL, 20628da1170aSLeo Liu .post_soft_reset = NULL, 20638da1170aSLeo Liu .set_clockgating_state = vcn_v4_0_set_clockgating_state, 20648da1170aSLeo Liu .set_powergating_state = vcn_v4_0_set_powergating_state, 20658da1170aSLeo Liu }; 20668da1170aSLeo Liu 20678da1170aSLeo Liu const struct amdgpu_ip_block_version vcn_v4_0_ip_block = 20688da1170aSLeo Liu { 20698da1170aSLeo Liu .type = AMD_IP_BLOCK_TYPE_VCN, 20708da1170aSLeo Liu .major = 4, 20718da1170aSLeo Liu .minor = 0, 20728da1170aSLeo Liu .rev = 0, 20738da1170aSLeo Liu .funcs = &vcn_v4_0_ip_funcs, 20748da1170aSLeo Liu }; 2075377d0221STao Zhou 2076377d0221STao Zhou static uint32_t vcn_v4_0_query_poison_by_instance(struct amdgpu_device *adev, 2077377d0221STao Zhou uint32_t instance, uint32_t sub_block) 2078377d0221STao Zhou { 2079377d0221STao Zhou uint32_t poison_stat = 0, reg_value = 0; 2080377d0221STao Zhou 2081377d0221STao Zhou switch (sub_block) { 2082377d0221STao Zhou case AMDGPU_VCN_V4_0_VCPU_VCODEC: 2083377d0221STao Zhou reg_value = RREG32_SOC15(VCN, instance, regUVD_RAS_VCPU_VCODEC_STATUS); 2084377d0221STao Zhou poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF); 2085377d0221STao Zhou break; 2086377d0221STao Zhou default: 2087377d0221STao Zhou break; 2088377d0221STao Zhou } 2089377d0221STao Zhou 2090377d0221STao Zhou if (poison_stat) 2091377d0221STao Zhou dev_info(adev->dev, "Poison detected in VCN%d, sub_block%d\n", 2092377d0221STao Zhou instance, sub_block); 2093377d0221STao Zhou 2094377d0221STao Zhou return poison_stat; 2095377d0221STao Zhou } 2096377d0221STao Zhou 2097377d0221STao Zhou static bool vcn_v4_0_query_ras_poison_status(struct amdgpu_device *adev) 2098377d0221STao Zhou { 2099377d0221STao Zhou uint32_t inst, sub; 2100377d0221STao Zhou uint32_t poison_stat = 0; 2101377d0221STao Zhou 2102377d0221STao Zhou for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++) 2103377d0221STao Zhou for (sub = 0; sub < AMDGPU_VCN_V4_0_MAX_SUB_BLOCK; sub++) 2104377d0221STao Zhou poison_stat += 2105377d0221STao Zhou vcn_v4_0_query_poison_by_instance(adev, inst, sub); 2106377d0221STao Zhou 2107377d0221STao Zhou return !!poison_stat; 2108377d0221STao Zhou } 2109377d0221STao Zhou 2110377d0221STao Zhou const struct amdgpu_ras_block_hw_ops vcn_v4_0_ras_hw_ops = { 2111377d0221STao Zhou .query_poison_status = vcn_v4_0_query_ras_poison_status, 2112377d0221STao Zhou }; 2113377d0221STao Zhou 2114377d0221STao Zhou static struct amdgpu_vcn_ras vcn_v4_0_ras = { 2115377d0221STao Zhou .ras_block = { 2116377d0221STao Zhou .hw_ops = &vcn_v4_0_ras_hw_ops, 2117377d0221STao Zhou }, 2118377d0221STao Zhou }; 2119377d0221STao Zhou 2120377d0221STao Zhou static void vcn_v4_0_set_ras_funcs(struct amdgpu_device *adev) 2121377d0221STao Zhou { 2122377d0221STao Zhou switch (adev->ip_versions[VCN_HWIP][0]) { 2123377d0221STao Zhou case IP_VERSION(4, 0, 0): 2124377d0221STao Zhou adev->vcn.ras = &vcn_v4_0_ras; 2125377d0221STao Zhou break; 2126377d0221STao Zhou default: 2127377d0221STao Zhou break; 2128377d0221STao Zhou } 2129377d0221STao Zhou } 2130