1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_vcn.h" 27 #include "amdgpu_pm.h" 28 #include "amdgpu_cs.h" 29 #include "soc15.h" 30 #include "soc15d.h" 31 #include "vcn_v2_0.h" 32 #include "mmsch_v3_0.h" 33 #include "vcn_sw_ring.h" 34 35 #include "vcn/vcn_3_0_0_offset.h" 36 #include "vcn/vcn_3_0_0_sh_mask.h" 37 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 38 39 #include <drm/drm_drv.h> 40 41 #define VCN_VID_SOC_ADDRESS_2_0 0x1fa00 42 #define VCN1_VID_SOC_ADDRESS_3_0 0x48200 43 44 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x27 45 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x0f 46 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x10 47 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x11 48 #define mmUVD_NO_OP_INTERNAL_OFFSET 0x29 49 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x66 50 #define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d 51 52 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x431 53 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x3b4 54 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x3b5 55 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x25c 56 57 #define VCN_INSTANCES_SIENNA_CICHLID 2 58 #define DEC_SW_RING_ENABLED FALSE 59 60 #define RDECODE_MSG_CREATE 0x00000000 61 #define RDECODE_MESSAGE_CREATE 0x00000001 62 63 static int amdgpu_ih_clientid_vcns[] = { 64 SOC15_IH_CLIENTID_VCN, 65 SOC15_IH_CLIENTID_VCN1 66 }; 67 68 static int vcn_v3_0_start_sriov(struct amdgpu_device *adev); 69 static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev); 70 static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev); 71 static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev); 72 static int vcn_v3_0_set_powergating_state(void *handle, 73 enum amd_powergating_state state); 74 static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev, 75 int inst_idx, struct dpg_pause_state *new_state); 76 77 static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring); 78 static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring); 79 80 /** 81 * vcn_v3_0_early_init - set function pointers and load microcode 82 * 83 * @handle: amdgpu_device pointer 84 * 85 * Set ring and irq function pointers 86 * Load microcode from filesystem 87 */ 88 static int vcn_v3_0_early_init(void *handle) 89 { 90 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 91 92 if (amdgpu_sriov_vf(adev)) { 93 adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID; 94 adev->vcn.harvest_config = 0; 95 adev->vcn.num_enc_rings = 1; 96 97 } else { 98 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 | 99 AMDGPU_VCN_HARVEST_VCN1)) 100 /* both instances are harvested, disable the block */ 101 return -ENOENT; 102 103 if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(3, 0, 33)) 104 adev->vcn.num_enc_rings = 0; 105 else 106 adev->vcn.num_enc_rings = 2; 107 } 108 109 vcn_v3_0_set_dec_ring_funcs(adev); 110 vcn_v3_0_set_enc_ring_funcs(adev); 111 vcn_v3_0_set_irq_funcs(adev); 112 113 return amdgpu_vcn_early_init(adev); 114 } 115 116 /** 117 * vcn_v3_0_sw_init - sw init for VCN block 118 * 119 * @handle: amdgpu_device pointer 120 * 121 * Load firmware and sw initialization 122 */ 123 static int vcn_v3_0_sw_init(void *handle) 124 { 125 struct amdgpu_ring *ring; 126 int i, j, r; 127 int vcn_doorbell_index = 0; 128 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 129 130 r = amdgpu_vcn_sw_init(adev); 131 if (r) 132 return r; 133 134 amdgpu_vcn_setup_ucode(adev); 135 136 r = amdgpu_vcn_resume(adev); 137 if (r) 138 return r; 139 140 /* 141 * Note: doorbell assignment is fixed for SRIOV multiple VCN engines 142 * Formula: 143 * vcn_db_base = adev->doorbell_index.vcn.vcn_ring0_1 << 1; 144 * dec_ring_i = vcn_db_base + i * (adev->vcn.num_enc_rings + 1) 145 * enc_ring_i,j = vcn_db_base + i * (adev->vcn.num_enc_rings + 1) + 1 + j 146 */ 147 if (amdgpu_sriov_vf(adev)) { 148 vcn_doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1; 149 /* get DWORD offset */ 150 vcn_doorbell_index = vcn_doorbell_index << 1; 151 } 152 153 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 154 volatile struct amdgpu_fw_shared *fw_shared; 155 156 if (adev->vcn.harvest_config & (1 << i)) 157 continue; 158 159 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; 160 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; 161 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; 162 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; 163 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; 164 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; 165 166 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; 167 adev->vcn.inst[i].external.scratch9 = SOC15_REG_OFFSET(VCN, i, mmUVD_SCRATCH9); 168 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; 169 adev->vcn.inst[i].external.data0 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA0); 170 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; 171 adev->vcn.inst[i].external.data1 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA1); 172 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; 173 adev->vcn.inst[i].external.cmd = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_CMD); 174 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; 175 adev->vcn.inst[i].external.nop = SOC15_REG_OFFSET(VCN, i, mmUVD_NO_OP); 176 177 /* VCN DEC TRAP */ 178 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 179 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[i].irq); 180 if (r) 181 return r; 182 183 atomic_set(&adev->vcn.inst[i].sched_score, 0); 184 185 ring = &adev->vcn.inst[i].ring_dec; 186 ring->use_doorbell = true; 187 if (amdgpu_sriov_vf(adev)) { 188 ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1); 189 } else { 190 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i; 191 } 192 ring->vm_hub = AMDGPU_MMHUB_0; 193 sprintf(ring->name, "vcn_dec_%d", i); 194 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 195 AMDGPU_RING_PRIO_DEFAULT, 196 &adev->vcn.inst[i].sched_score); 197 if (r) 198 return r; 199 200 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 201 enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(j); 202 203 /* VCN ENC TRAP */ 204 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 205 j + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); 206 if (r) 207 return r; 208 209 ring = &adev->vcn.inst[i].ring_enc[j]; 210 ring->use_doorbell = true; 211 if (amdgpu_sriov_vf(adev)) { 212 ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1) + 1 + j; 213 } else { 214 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + j + 8 * i; 215 } 216 ring->vm_hub = AMDGPU_MMHUB_0; 217 sprintf(ring->name, "vcn_enc_%d.%d", i, j); 218 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 219 hw_prio, &adev->vcn.inst[i].sched_score); 220 if (r) 221 return r; 222 } 223 224 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 225 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SW_RING_FLAG) | 226 cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG) | 227 cpu_to_le32(AMDGPU_VCN_FW_SHARED_FLAG_0_RB); 228 fw_shared->sw_ring.is_enabled = cpu_to_le32(DEC_SW_RING_ENABLED); 229 fw_shared->present_flag_0 |= AMDGPU_VCN_SMU_VERSION_INFO_FLAG; 230 if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(3, 1, 2)) 231 fw_shared->smu_interface_info.smu_interface_type = 2; 232 else if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(3, 1, 1)) 233 fw_shared->smu_interface_info.smu_interface_type = 1; 234 235 if (amdgpu_vcnfw_log) 236 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]); 237 } 238 239 if (amdgpu_sriov_vf(adev)) { 240 r = amdgpu_virt_alloc_mm_table(adev); 241 if (r) 242 return r; 243 } 244 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 245 adev->vcn.pause_dpg_mode = vcn_v3_0_pause_dpg_mode; 246 247 return 0; 248 } 249 250 /** 251 * vcn_v3_0_sw_fini - sw fini for VCN block 252 * 253 * @handle: amdgpu_device pointer 254 * 255 * VCN suspend and free up sw allocation 256 */ 257 static int vcn_v3_0_sw_fini(void *handle) 258 { 259 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 260 int i, r, idx; 261 262 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 263 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 264 volatile struct amdgpu_fw_shared *fw_shared; 265 266 if (adev->vcn.harvest_config & (1 << i)) 267 continue; 268 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 269 fw_shared->present_flag_0 = 0; 270 fw_shared->sw_ring.is_enabled = false; 271 } 272 273 drm_dev_exit(idx); 274 } 275 276 if (amdgpu_sriov_vf(adev)) 277 amdgpu_virt_free_mm_table(adev); 278 279 r = amdgpu_vcn_suspend(adev); 280 if (r) 281 return r; 282 283 r = amdgpu_vcn_sw_fini(adev); 284 285 return r; 286 } 287 288 /** 289 * vcn_v3_0_hw_init - start and test VCN block 290 * 291 * @handle: amdgpu_device pointer 292 * 293 * Initialize the hardware, boot up the VCPU and do some testing 294 */ 295 static int vcn_v3_0_hw_init(void *handle) 296 { 297 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 298 struct amdgpu_ring *ring; 299 int i, j, r; 300 301 if (amdgpu_sriov_vf(adev)) { 302 r = vcn_v3_0_start_sriov(adev); 303 if (r) 304 goto done; 305 306 /* initialize VCN dec and enc ring buffers */ 307 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 308 if (adev->vcn.harvest_config & (1 << i)) 309 continue; 310 311 ring = &adev->vcn.inst[i].ring_dec; 312 if (amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, i)) { 313 ring->sched.ready = false; 314 ring->no_scheduler = true; 315 dev_info(adev->dev, "ring %s is disabled by hypervisor\n", ring->name); 316 } else { 317 ring->wptr = 0; 318 ring->wptr_old = 0; 319 vcn_v3_0_dec_ring_set_wptr(ring); 320 ring->sched.ready = true; 321 } 322 323 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 324 ring = &adev->vcn.inst[i].ring_enc[j]; 325 if (amdgpu_vcn_is_disabled_vcn(adev, VCN_ENCODE_RING, i)) { 326 ring->sched.ready = false; 327 ring->no_scheduler = true; 328 dev_info(adev->dev, "ring %s is disabled by hypervisor\n", ring->name); 329 } else { 330 ring->wptr = 0; 331 ring->wptr_old = 0; 332 vcn_v3_0_enc_ring_set_wptr(ring); 333 ring->sched.ready = true; 334 } 335 } 336 } 337 } else { 338 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 339 if (adev->vcn.harvest_config & (1 << i)) 340 continue; 341 342 ring = &adev->vcn.inst[i].ring_dec; 343 344 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 345 ring->doorbell_index, i); 346 347 r = amdgpu_ring_test_helper(ring); 348 if (r) 349 goto done; 350 351 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 352 ring = &adev->vcn.inst[i].ring_enc[j]; 353 r = amdgpu_ring_test_helper(ring); 354 if (r) 355 goto done; 356 } 357 } 358 } 359 360 done: 361 if (!r) 362 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 363 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 364 365 return r; 366 } 367 368 /** 369 * vcn_v3_0_hw_fini - stop the hardware block 370 * 371 * @handle: amdgpu_device pointer 372 * 373 * Stop the VCN block, mark ring as not ready any more 374 */ 375 static int vcn_v3_0_hw_fini(void *handle) 376 { 377 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 378 int i; 379 380 cancel_delayed_work_sync(&adev->vcn.idle_work); 381 382 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 383 if (adev->vcn.harvest_config & (1 << i)) 384 continue; 385 386 if (!amdgpu_sriov_vf(adev)) { 387 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 388 (adev->vcn.cur_state != AMD_PG_STATE_GATE && 389 RREG32_SOC15(VCN, i, mmUVD_STATUS))) { 390 vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 391 } 392 } 393 } 394 395 return 0; 396 } 397 398 /** 399 * vcn_v3_0_suspend - suspend VCN block 400 * 401 * @handle: amdgpu_device pointer 402 * 403 * HW fini and suspend VCN block 404 */ 405 static int vcn_v3_0_suspend(void *handle) 406 { 407 int r; 408 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 409 410 r = vcn_v3_0_hw_fini(adev); 411 if (r) 412 return r; 413 414 r = amdgpu_vcn_suspend(adev); 415 416 return r; 417 } 418 419 /** 420 * vcn_v3_0_resume - resume VCN block 421 * 422 * @handle: amdgpu_device pointer 423 * 424 * Resume firmware and hw init VCN block 425 */ 426 static int vcn_v3_0_resume(void *handle) 427 { 428 int r; 429 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 430 431 r = amdgpu_vcn_resume(adev); 432 if (r) 433 return r; 434 435 r = vcn_v3_0_hw_init(adev); 436 437 return r; 438 } 439 440 /** 441 * vcn_v3_0_mc_resume - memory controller programming 442 * 443 * @adev: amdgpu_device pointer 444 * @inst: instance number 445 * 446 * Let the VCN memory controller know it's offsets 447 */ 448 static void vcn_v3_0_mc_resume(struct amdgpu_device *adev, int inst) 449 { 450 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 451 uint32_t offset; 452 453 /* cache window 0: fw */ 454 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 455 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 456 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 457 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 458 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 459 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 0); 460 offset = 0; 461 } else { 462 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 463 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 464 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 465 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 466 offset = size; 467 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 468 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 469 } 470 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE0, size); 471 472 /* cache window 1: stack */ 473 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 474 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 475 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 476 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 477 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET1, 0); 478 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 479 480 /* cache window 2: context */ 481 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 482 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 483 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 484 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 485 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET2, 0); 486 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 487 488 /* non-cache window */ 489 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 490 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 491 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 492 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 493 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_OFFSET0, 0); 494 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_SIZE0, 495 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); 496 } 497 498 static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 499 { 500 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 501 uint32_t offset; 502 503 /* cache window 0: fw */ 504 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 505 if (!indirect) { 506 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 507 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 508 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); 509 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 510 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 511 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); 512 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 513 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 514 } else { 515 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 516 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 517 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 518 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 519 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 520 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 521 } 522 offset = 0; 523 } else { 524 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 525 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 526 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 527 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 528 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 529 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 530 offset = size; 531 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 532 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 533 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 534 } 535 536 if (!indirect) 537 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 538 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 539 else 540 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 541 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 542 543 /* cache window 1: stack */ 544 if (!indirect) { 545 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 546 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 547 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 548 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 549 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 550 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 551 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 552 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 553 } else { 554 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 555 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 556 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 557 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 558 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 559 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 560 } 561 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 562 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 563 564 /* cache window 2: context */ 565 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 566 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 567 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 568 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 569 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 570 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 571 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 572 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 573 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 574 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 575 576 /* non-cache window */ 577 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 578 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 579 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 580 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 581 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 582 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 583 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 584 VCN, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 585 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 586 VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), 587 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); 588 589 /* VCN global tiling registers */ 590 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 591 UVD, inst_idx, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 592 } 593 594 static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int inst) 595 { 596 uint32_t data = 0; 597 598 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 599 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 600 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 601 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 602 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 603 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 604 | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 605 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 606 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 607 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 608 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 609 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 610 | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 611 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 612 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 613 614 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 615 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 616 UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF); 617 } else { 618 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 619 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 620 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 621 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 622 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 623 | 1 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 624 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 625 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 626 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 627 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 628 | 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 629 | 1 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 630 | 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 631 | 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 632 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 633 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 0, 0x3F3FFFFF); 634 } 635 636 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); 637 data &= ~0x103; 638 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 639 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 640 UVD_POWER_STATUS__UVD_PG_EN_MASK; 641 642 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); 643 } 644 645 static void vcn_v3_0_enable_static_power_gating(struct amdgpu_device *adev, int inst) 646 { 647 uint32_t data; 648 649 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 650 /* Before power off, this indicator has to be turned on */ 651 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); 652 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 653 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 654 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); 655 656 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 657 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 658 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 659 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 660 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 661 | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 662 | 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 663 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 664 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 665 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 666 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 667 | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 668 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 669 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 670 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 671 672 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 673 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 674 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 675 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 676 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 677 | 2 << UVD_PGFSM_STATUS__UVDIRL_PWR_STATUS__SHIFT 678 | 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT 679 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 680 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 681 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 682 | 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT 683 | 2 << UVD_PGFSM_STATUS__UVDATD_PWR_STATUS__SHIFT 684 | 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT 685 | 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT); 686 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, data, 0x3F3FFFFF); 687 } 688 } 689 690 /** 691 * vcn_v3_0_disable_clock_gating - disable VCN clock gating 692 * 693 * @adev: amdgpu_device pointer 694 * @inst: instance number 695 * 696 * Disable clock gating for VCN block 697 */ 698 static void vcn_v3_0_disable_clock_gating(struct amdgpu_device *adev, int inst) 699 { 700 uint32_t data; 701 702 /* VCN disable CGC */ 703 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 704 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 705 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 706 else 707 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 708 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 709 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 710 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 711 712 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_GATE); 713 data &= ~(UVD_CGC_GATE__SYS_MASK 714 | UVD_CGC_GATE__UDEC_MASK 715 | UVD_CGC_GATE__MPEG2_MASK 716 | UVD_CGC_GATE__REGS_MASK 717 | UVD_CGC_GATE__RBC_MASK 718 | UVD_CGC_GATE__LMI_MC_MASK 719 | UVD_CGC_GATE__LMI_UMC_MASK 720 | UVD_CGC_GATE__IDCT_MASK 721 | UVD_CGC_GATE__MPRD_MASK 722 | UVD_CGC_GATE__MPC_MASK 723 | UVD_CGC_GATE__LBSI_MASK 724 | UVD_CGC_GATE__LRBBM_MASK 725 | UVD_CGC_GATE__UDEC_RE_MASK 726 | UVD_CGC_GATE__UDEC_CM_MASK 727 | UVD_CGC_GATE__UDEC_IT_MASK 728 | UVD_CGC_GATE__UDEC_DB_MASK 729 | UVD_CGC_GATE__UDEC_MP_MASK 730 | UVD_CGC_GATE__WCB_MASK 731 | UVD_CGC_GATE__VCPU_MASK 732 | UVD_CGC_GATE__MMSCH_MASK); 733 734 WREG32_SOC15(VCN, inst, mmUVD_CGC_GATE, data); 735 736 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); 737 738 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 739 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 740 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 741 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 742 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 743 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 744 | UVD_CGC_CTRL__SYS_MODE_MASK 745 | UVD_CGC_CTRL__UDEC_MODE_MASK 746 | UVD_CGC_CTRL__MPEG2_MODE_MASK 747 | UVD_CGC_CTRL__REGS_MODE_MASK 748 | UVD_CGC_CTRL__RBC_MODE_MASK 749 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 750 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 751 | UVD_CGC_CTRL__IDCT_MODE_MASK 752 | UVD_CGC_CTRL__MPRD_MODE_MASK 753 | UVD_CGC_CTRL__MPC_MODE_MASK 754 | UVD_CGC_CTRL__LBSI_MODE_MASK 755 | UVD_CGC_CTRL__LRBBM_MODE_MASK 756 | UVD_CGC_CTRL__WCB_MODE_MASK 757 | UVD_CGC_CTRL__VCPU_MODE_MASK 758 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 759 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 760 761 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE); 762 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 763 | UVD_SUVD_CGC_GATE__SIT_MASK 764 | UVD_SUVD_CGC_GATE__SMP_MASK 765 | UVD_SUVD_CGC_GATE__SCM_MASK 766 | UVD_SUVD_CGC_GATE__SDB_MASK 767 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 768 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 769 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 770 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 771 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 772 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 773 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 774 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 775 | UVD_SUVD_CGC_GATE__SCLR_MASK 776 | UVD_SUVD_CGC_GATE__ENT_MASK 777 | UVD_SUVD_CGC_GATE__IME_MASK 778 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 779 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 780 | UVD_SUVD_CGC_GATE__SITE_MASK 781 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 782 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 783 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 784 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 785 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK 786 | UVD_SUVD_CGC_GATE__EFC_MASK 787 | UVD_SUVD_CGC_GATE__SAOE_MASK 788 | UVD_SUVD_CGC_GATE__SRE_AV1_MASK 789 | UVD_SUVD_CGC_GATE__FBC_PCLK_MASK 790 | UVD_SUVD_CGC_GATE__FBC_CCLK_MASK 791 | UVD_SUVD_CGC_GATE__SCM_AV1_MASK 792 | UVD_SUVD_CGC_GATE__SMPA_MASK); 793 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE, data); 794 795 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2); 796 data |= (UVD_SUVD_CGC_GATE2__MPBE0_MASK 797 | UVD_SUVD_CGC_GATE2__MPBE1_MASK 798 | UVD_SUVD_CGC_GATE2__SIT_AV1_MASK 799 | UVD_SUVD_CGC_GATE2__SDB_AV1_MASK 800 | UVD_SUVD_CGC_GATE2__MPC1_MASK); 801 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2, data); 802 803 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL); 804 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 805 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 806 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 807 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 808 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 809 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 810 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 811 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 812 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 813 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 814 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK 815 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK 816 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK 817 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK 818 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 819 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 820 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK 821 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK 822 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK); 823 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data); 824 } 825 826 static void vcn_v3_0_clock_gating_dpg_mode(struct amdgpu_device *adev, 827 uint8_t sram_sel, int inst_idx, uint8_t indirect) 828 { 829 uint32_t reg_data = 0; 830 831 /* enable sw clock gating control */ 832 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 833 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 834 else 835 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 836 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 837 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 838 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 839 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 840 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 841 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 842 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 843 UVD_CGC_CTRL__SYS_MODE_MASK | 844 UVD_CGC_CTRL__UDEC_MODE_MASK | 845 UVD_CGC_CTRL__MPEG2_MODE_MASK | 846 UVD_CGC_CTRL__REGS_MODE_MASK | 847 UVD_CGC_CTRL__RBC_MODE_MASK | 848 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 849 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 850 UVD_CGC_CTRL__IDCT_MODE_MASK | 851 UVD_CGC_CTRL__MPRD_MODE_MASK | 852 UVD_CGC_CTRL__MPC_MODE_MASK | 853 UVD_CGC_CTRL__LBSI_MODE_MASK | 854 UVD_CGC_CTRL__LRBBM_MODE_MASK | 855 UVD_CGC_CTRL__WCB_MODE_MASK | 856 UVD_CGC_CTRL__VCPU_MODE_MASK | 857 UVD_CGC_CTRL__MMSCH_MODE_MASK); 858 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 859 VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); 860 861 /* turn off clock gating */ 862 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 863 VCN, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect); 864 865 /* turn on SUVD clock gating */ 866 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 867 VCN, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 868 869 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 870 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 871 VCN, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 872 } 873 874 /** 875 * vcn_v3_0_enable_clock_gating - enable VCN clock gating 876 * 877 * @adev: amdgpu_device pointer 878 * @inst: instance number 879 * 880 * Enable clock gating for VCN block 881 */ 882 static void vcn_v3_0_enable_clock_gating(struct amdgpu_device *adev, int inst) 883 { 884 uint32_t data; 885 886 /* enable VCN CGC */ 887 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 888 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 889 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 890 else 891 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 892 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 893 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 894 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 895 896 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 897 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 898 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 899 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 900 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 901 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 902 | UVD_CGC_CTRL__SYS_MODE_MASK 903 | UVD_CGC_CTRL__UDEC_MODE_MASK 904 | UVD_CGC_CTRL__MPEG2_MODE_MASK 905 | UVD_CGC_CTRL__REGS_MODE_MASK 906 | UVD_CGC_CTRL__RBC_MODE_MASK 907 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 908 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 909 | UVD_CGC_CTRL__IDCT_MODE_MASK 910 | UVD_CGC_CTRL__MPRD_MODE_MASK 911 | UVD_CGC_CTRL__MPC_MODE_MASK 912 | UVD_CGC_CTRL__LBSI_MODE_MASK 913 | UVD_CGC_CTRL__LRBBM_MODE_MASK 914 | UVD_CGC_CTRL__WCB_MODE_MASK 915 | UVD_CGC_CTRL__VCPU_MODE_MASK 916 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 917 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 918 919 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL); 920 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 921 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 922 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 923 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 924 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 925 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 926 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 927 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 928 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 929 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 930 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK 931 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK 932 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK 933 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK 934 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 935 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 936 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK 937 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK 938 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK); 939 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data); 940 } 941 942 static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 943 { 944 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 945 struct amdgpu_ring *ring; 946 uint32_t rb_bufsz, tmp; 947 948 /* disable register anti-hang mechanism */ 949 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1, 950 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 951 /* enable dynamic power gating mode */ 952 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS); 953 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 954 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 955 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp); 956 957 if (indirect) 958 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 959 960 /* enable clock gating */ 961 vcn_v3_0_clock_gating_dpg_mode(adev, 0, inst_idx, indirect); 962 963 /* enable VCPU clock */ 964 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 965 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 966 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK; 967 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 968 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 969 970 /* disable master interupt */ 971 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 972 VCN, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect); 973 974 /* setup mmUVD_LMI_CTRL */ 975 tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 976 UVD_LMI_CTRL__REQ_MODE_MASK | 977 UVD_LMI_CTRL__CRC_RESET_MASK | 978 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 979 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 980 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 981 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 982 0x00100000L); 983 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 984 VCN, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect); 985 986 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 987 VCN, inst_idx, mmUVD_MPC_CNTL), 988 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 989 990 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 991 VCN, inst_idx, mmUVD_MPC_SET_MUXA0), 992 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 993 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 994 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 995 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 996 997 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 998 VCN, inst_idx, mmUVD_MPC_SET_MUXB0), 999 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1000 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1001 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1002 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 1003 1004 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1005 VCN, inst_idx, mmUVD_MPC_SET_MUX), 1006 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1007 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1008 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 1009 1010 vcn_v3_0_mc_resume_dpg_mode(adev, inst_idx, indirect); 1011 1012 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1013 VCN, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect); 1014 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1015 VCN, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect); 1016 1017 /* enable LMI MC and UMC channels */ 1018 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1019 VCN, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect); 1020 1021 /* unblock VCPU register access */ 1022 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1023 VCN, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect); 1024 1025 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 1026 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 1027 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1028 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 1029 1030 /* enable master interrupt */ 1031 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1032 VCN, inst_idx, mmUVD_MASTINT_EN), 1033 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 1034 1035 /* add nop to workaround PSP size check */ 1036 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1037 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 1038 1039 if (indirect) 1040 psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, 1041 (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr - 1042 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr)); 1043 1044 ring = &adev->vcn.inst[inst_idx].ring_dec; 1045 /* force RBC into idle state */ 1046 rb_bufsz = order_base_2(ring->ring_size); 1047 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1048 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1049 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1050 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1051 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1052 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp); 1053 1054 /* Stall DPG before WPTR/RPTR reset */ 1055 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1056 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1057 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1058 fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1059 1060 /* set the write pointer delay */ 1061 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0); 1062 1063 /* set the wb address */ 1064 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR, 1065 (upper_32_bits(ring->gpu_addr) >> 2)); 1066 1067 /* programm the RB_BASE for ring buffer */ 1068 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1069 lower_32_bits(ring->gpu_addr)); 1070 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1071 upper_32_bits(ring->gpu_addr)); 1072 1073 /* Initialize the ring buffer's read and write pointers */ 1074 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0); 1075 1076 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0); 1077 1078 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR); 1079 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, 1080 lower_32_bits(ring->wptr)); 1081 1082 /* Reset FW shared memory RBC WPTR/RPTR */ 1083 fw_shared->rb.rptr = 0; 1084 fw_shared->rb.wptr = lower_32_bits(ring->wptr); 1085 1086 /*resetting done, fw can check RB ring */ 1087 fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1088 1089 /* Unstall DPG */ 1090 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1091 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1092 1093 return 0; 1094 } 1095 1096 static int vcn_v3_0_start(struct amdgpu_device *adev) 1097 { 1098 volatile struct amdgpu_fw_shared *fw_shared; 1099 struct amdgpu_ring *ring; 1100 uint32_t rb_bufsz, tmp; 1101 int i, j, k, r; 1102 1103 if (adev->pm.dpm_enabled) 1104 amdgpu_dpm_enable_uvd(adev, true); 1105 1106 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1107 if (adev->vcn.harvest_config & (1 << i)) 1108 continue; 1109 1110 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG){ 1111 r = vcn_v3_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram); 1112 continue; 1113 } 1114 1115 /* disable VCN power gating */ 1116 vcn_v3_0_disable_static_power_gating(adev, i); 1117 1118 /* set VCN status busy */ 1119 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 1120 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp); 1121 1122 /*SW clock gating */ 1123 vcn_v3_0_disable_clock_gating(adev, i); 1124 1125 /* enable VCPU clock */ 1126 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1127 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 1128 1129 /* disable master interrupt */ 1130 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0, 1131 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1132 1133 /* enable LMI MC and UMC channels */ 1134 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0, 1135 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1136 1137 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1138 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1139 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1140 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1141 1142 /* setup mmUVD_LMI_CTRL */ 1143 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL); 1144 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | 1145 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1146 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1147 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1148 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1149 1150 /* setup mmUVD_MPC_CNTL */ 1151 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL); 1152 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1153 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1154 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp); 1155 1156 /* setup UVD_MPC_SET_MUXA0 */ 1157 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0, 1158 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1159 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1160 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1161 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1162 1163 /* setup UVD_MPC_SET_MUXB0 */ 1164 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0, 1165 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1166 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1167 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1168 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1169 1170 /* setup mmUVD_MPC_SET_MUX */ 1171 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX, 1172 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1173 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1174 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1175 1176 vcn_v3_0_mc_resume(adev, i); 1177 1178 /* VCN global tiling registers */ 1179 WREG32_SOC15(VCN, i, mmUVD_GFX10_ADDR_CONFIG, 1180 adev->gfx.config.gb_addr_config); 1181 1182 /* unblock VCPU register access */ 1183 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0, 1184 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1185 1186 /* release VCPU reset to boot */ 1187 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1188 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1189 1190 for (j = 0; j < 10; ++j) { 1191 uint32_t status; 1192 1193 for (k = 0; k < 100; ++k) { 1194 status = RREG32_SOC15(VCN, i, mmUVD_STATUS); 1195 if (status & 2) 1196 break; 1197 mdelay(10); 1198 } 1199 r = 0; 1200 if (status & 2) 1201 break; 1202 1203 DRM_ERROR("VCN[%d] decode not responding, trying to reset the VCPU!!!\n", i); 1204 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1205 UVD_VCPU_CNTL__BLK_RST_MASK, 1206 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1207 mdelay(10); 1208 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1209 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1210 1211 mdelay(10); 1212 r = -1; 1213 } 1214 1215 if (r) { 1216 DRM_ERROR("VCN[%d] decode not responding, giving up!!!\n", i); 1217 return r; 1218 } 1219 1220 /* enable master interrupt */ 1221 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 1222 UVD_MASTINT_EN__VCPU_EN_MASK, 1223 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1224 1225 /* clear the busy bit of VCN_STATUS */ 1226 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0, 1227 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1228 1229 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0); 1230 1231 ring = &adev->vcn.inst[i].ring_dec; 1232 /* force RBC into idle state */ 1233 rb_bufsz = order_base_2(ring->ring_size); 1234 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1235 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1236 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1237 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1238 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1239 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp); 1240 1241 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1242 fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1243 1244 /* programm the RB_BASE for ring buffer */ 1245 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1246 lower_32_bits(ring->gpu_addr)); 1247 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1248 upper_32_bits(ring->gpu_addr)); 1249 1250 /* Initialize the ring buffer's read and write pointers */ 1251 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0); 1252 1253 WREG32_SOC15(VCN, i, mmUVD_SCRATCH2, 0); 1254 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR); 1255 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR, 1256 lower_32_bits(ring->wptr)); 1257 fw_shared->rb.wptr = lower_32_bits(ring->wptr); 1258 fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1259 1260 if (adev->ip_versions[UVD_HWIP][0] != IP_VERSION(3, 0, 33)) { 1261 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1262 ring = &adev->vcn.inst[i].ring_enc[0]; 1263 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1264 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1265 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr); 1266 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1267 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4); 1268 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1269 1270 fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1271 ring = &adev->vcn.inst[i].ring_enc[1]; 1272 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1273 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1274 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1275 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1276 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4); 1277 fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1278 } 1279 } 1280 1281 return 0; 1282 } 1283 1284 static int vcn_v3_0_start_sriov(struct amdgpu_device *adev) 1285 { 1286 int i, j; 1287 struct amdgpu_ring *ring; 1288 uint64_t cache_addr; 1289 uint64_t rb_addr; 1290 uint64_t ctx_addr; 1291 uint32_t param, resp, expected; 1292 uint32_t offset, cache_size; 1293 uint32_t tmp, timeout; 1294 1295 struct amdgpu_mm_table *table = &adev->virt.mm_table; 1296 uint32_t *table_loc; 1297 uint32_t table_size; 1298 uint32_t size, size_dw; 1299 1300 struct mmsch_v3_0_cmd_direct_write 1301 direct_wt = { {0} }; 1302 struct mmsch_v3_0_cmd_direct_read_modify_write 1303 direct_rd_mod_wt = { {0} }; 1304 struct mmsch_v3_0_cmd_end end = { {0} }; 1305 struct mmsch_v3_0_init_header header; 1306 1307 direct_wt.cmd_header.command_type = 1308 MMSCH_COMMAND__DIRECT_REG_WRITE; 1309 direct_rd_mod_wt.cmd_header.command_type = 1310 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1311 end.cmd_header.command_type = 1312 MMSCH_COMMAND__END; 1313 1314 header.version = MMSCH_VERSION; 1315 header.total_size = sizeof(struct mmsch_v3_0_init_header) >> 2; 1316 for (i = 0; i < AMDGPU_MAX_VCN_INSTANCES; i++) { 1317 header.inst[i].init_status = 0; 1318 header.inst[i].table_offset = 0; 1319 header.inst[i].table_size = 0; 1320 } 1321 1322 table_loc = (uint32_t *)table->cpu_addr; 1323 table_loc += header.total_size; 1324 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1325 if (adev->vcn.harvest_config & (1 << i)) 1326 continue; 1327 1328 table_size = 0; 1329 1330 MMSCH_V3_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i, 1331 mmUVD_STATUS), 1332 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 1333 1334 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 1335 1336 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1337 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1338 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1339 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo); 1340 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1341 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1342 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi); 1343 offset = 0; 1344 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1345 mmUVD_VCPU_CACHE_OFFSET0), 1346 0); 1347 } else { 1348 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1349 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1350 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 1351 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1352 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1353 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 1354 offset = cache_size; 1355 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1356 mmUVD_VCPU_CACHE_OFFSET0), 1357 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 1358 } 1359 1360 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1361 mmUVD_VCPU_CACHE_SIZE0), 1362 cache_size); 1363 1364 cache_addr = adev->vcn.inst[i].gpu_addr + offset; 1365 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1366 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 1367 lower_32_bits(cache_addr)); 1368 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1369 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 1370 upper_32_bits(cache_addr)); 1371 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1372 mmUVD_VCPU_CACHE_OFFSET1), 1373 0); 1374 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1375 mmUVD_VCPU_CACHE_SIZE1), 1376 AMDGPU_VCN_STACK_SIZE); 1377 1378 cache_addr = adev->vcn.inst[i].gpu_addr + offset + 1379 AMDGPU_VCN_STACK_SIZE; 1380 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1381 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 1382 lower_32_bits(cache_addr)); 1383 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1384 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 1385 upper_32_bits(cache_addr)); 1386 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1387 mmUVD_VCPU_CACHE_OFFSET2), 1388 0); 1389 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1390 mmUVD_VCPU_CACHE_SIZE2), 1391 AMDGPU_VCN_CONTEXT_SIZE); 1392 1393 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 1394 ring = &adev->vcn.inst[i].ring_enc[j]; 1395 ring->wptr = 0; 1396 rb_addr = ring->gpu_addr; 1397 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1398 mmUVD_RB_BASE_LO), 1399 lower_32_bits(rb_addr)); 1400 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1401 mmUVD_RB_BASE_HI), 1402 upper_32_bits(rb_addr)); 1403 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1404 mmUVD_RB_SIZE), 1405 ring->ring_size / 4); 1406 } 1407 1408 ring = &adev->vcn.inst[i].ring_dec; 1409 ring->wptr = 0; 1410 rb_addr = ring->gpu_addr; 1411 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1412 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW), 1413 lower_32_bits(rb_addr)); 1414 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1415 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH), 1416 upper_32_bits(rb_addr)); 1417 /* force RBC into idle state */ 1418 tmp = order_base_2(ring->ring_size); 1419 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp); 1420 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1421 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1422 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1423 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1424 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1425 mmUVD_RBC_RB_CNTL), 1426 tmp); 1427 1428 /* add end packet */ 1429 MMSCH_V3_0_INSERT_END(); 1430 1431 /* refine header */ 1432 header.inst[i].init_status = 0; 1433 header.inst[i].table_offset = header.total_size; 1434 header.inst[i].table_size = table_size; 1435 header.total_size += table_size; 1436 } 1437 1438 /* Update init table header in memory */ 1439 size = sizeof(struct mmsch_v3_0_init_header); 1440 table_loc = (uint32_t *)table->cpu_addr; 1441 memcpy((void *)table_loc, &header, size); 1442 1443 /* message MMSCH (in VCN[0]) to initialize this client 1444 * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr 1445 * of memory descriptor location 1446 */ 1447 ctx_addr = table->gpu_addr; 1448 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 1449 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 1450 1451 /* 2, update vmid of descriptor */ 1452 tmp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID); 1453 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1454 /* use domain0 for MM scheduler */ 1455 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1456 WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, tmp); 1457 1458 /* 3, notify mmsch about the size of this descriptor */ 1459 size = header.total_size; 1460 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size); 1461 1462 /* 4, set resp to zero */ 1463 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0); 1464 1465 /* 5, kick off the initialization and wait until 1466 * MMSCH_VF_MAILBOX_RESP becomes non-zero 1467 */ 1468 param = 0x10000001; 1469 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, param); 1470 tmp = 0; 1471 timeout = 1000; 1472 resp = 0; 1473 expected = param + 1; 1474 while (resp != expected) { 1475 resp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); 1476 if (resp == expected) 1477 break; 1478 1479 udelay(10); 1480 tmp = tmp + 10; 1481 if (tmp >= timeout) { 1482 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 1483 " waiting for mmMMSCH_VF_MAILBOX_RESP "\ 1484 "(expected=0x%08x, readback=0x%08x)\n", 1485 tmp, expected, resp); 1486 return -EBUSY; 1487 } 1488 } 1489 1490 return 0; 1491 } 1492 1493 static int vcn_v3_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) 1494 { 1495 struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE}; 1496 uint32_t tmp; 1497 1498 vcn_v3_0_pause_dpg_mode(adev, inst_idx, &state); 1499 1500 /* Wait for power status to be 1 */ 1501 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1502 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1503 1504 /* wait for read ptr to be equal to write ptr */ 1505 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR); 1506 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1507 1508 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2); 1509 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); 1510 1511 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1512 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); 1513 1514 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1515 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1516 1517 /* disable dynamic power gating mode */ 1518 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0, 1519 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1520 1521 return 0; 1522 } 1523 1524 static int vcn_v3_0_stop(struct amdgpu_device *adev) 1525 { 1526 uint32_t tmp; 1527 int i, r = 0; 1528 1529 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1530 if (adev->vcn.harvest_config & (1 << i)) 1531 continue; 1532 1533 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1534 r = vcn_v3_0_stop_dpg_mode(adev, i); 1535 continue; 1536 } 1537 1538 /* wait for vcn idle */ 1539 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1540 if (r) 1541 return r; 1542 1543 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1544 UVD_LMI_STATUS__READ_CLEAN_MASK | 1545 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1546 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1547 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1548 if (r) 1549 return r; 1550 1551 /* disable LMI UMC channel */ 1552 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2); 1553 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1554 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp); 1555 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK| 1556 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1557 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1558 if (r) 1559 return r; 1560 1561 /* block VCPU register access */ 1562 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 1563 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1564 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1565 1566 /* reset VCPU */ 1567 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1568 UVD_VCPU_CNTL__BLK_RST_MASK, 1569 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1570 1571 /* disable VCPU clock */ 1572 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1573 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1574 1575 /* apply soft reset */ 1576 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1577 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1578 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1579 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1580 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1581 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1582 1583 /* clear status */ 1584 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0); 1585 1586 /* apply HW clock gating */ 1587 vcn_v3_0_enable_clock_gating(adev, i); 1588 1589 /* enable VCN power gating */ 1590 vcn_v3_0_enable_static_power_gating(adev, i); 1591 } 1592 1593 if (adev->pm.dpm_enabled) 1594 amdgpu_dpm_enable_uvd(adev, false); 1595 1596 return 0; 1597 } 1598 1599 static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev, 1600 int inst_idx, struct dpg_pause_state *new_state) 1601 { 1602 volatile struct amdgpu_fw_shared *fw_shared; 1603 struct amdgpu_ring *ring; 1604 uint32_t reg_data = 0; 1605 int ret_code; 1606 1607 /* pause/unpause if state is changed */ 1608 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1609 DRM_DEBUG("dpg pause state changed %d -> %d", 1610 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1611 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) & 1612 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1613 1614 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1615 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, 1616 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1617 1618 if (!ret_code) { 1619 /* pause DPG */ 1620 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1621 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1622 1623 /* wait for ACK */ 1624 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE, 1625 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1626 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1627 1628 /* Stall DPG before WPTR/RPTR reset */ 1629 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1630 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1631 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1632 1633 if (adev->ip_versions[UVD_HWIP][0] != IP_VERSION(3, 0, 33)) { 1634 /* Restore */ 1635 fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 1636 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1637 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 1638 ring->wptr = 0; 1639 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr); 1640 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1641 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4); 1642 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1643 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1644 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1645 1646 fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1647 ring = &adev->vcn.inst[inst_idx].ring_enc[1]; 1648 ring->wptr = 0; 1649 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1650 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1651 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4); 1652 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1653 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1654 fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1655 1656 /* restore wptr/rptr with pointers saved in FW shared memory*/ 1657 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, fw_shared->rb.rptr); 1658 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, fw_shared->rb.wptr); 1659 } 1660 1661 /* Unstall DPG */ 1662 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1663 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1664 1665 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1666 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1667 } 1668 } else { 1669 /* unpause dpg, no need to wait */ 1670 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1671 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1672 } 1673 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1674 } 1675 1676 return 0; 1677 } 1678 1679 /** 1680 * vcn_v3_0_dec_ring_get_rptr - get read pointer 1681 * 1682 * @ring: amdgpu_ring pointer 1683 * 1684 * Returns the current hardware read pointer 1685 */ 1686 static uint64_t vcn_v3_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 1687 { 1688 struct amdgpu_device *adev = ring->adev; 1689 1690 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR); 1691 } 1692 1693 /** 1694 * vcn_v3_0_dec_ring_get_wptr - get write pointer 1695 * 1696 * @ring: amdgpu_ring pointer 1697 * 1698 * Returns the current hardware write pointer 1699 */ 1700 static uint64_t vcn_v3_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 1701 { 1702 struct amdgpu_device *adev = ring->adev; 1703 1704 if (ring->use_doorbell) 1705 return *ring->wptr_cpu_addr; 1706 else 1707 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR); 1708 } 1709 1710 /** 1711 * vcn_v3_0_dec_ring_set_wptr - set write pointer 1712 * 1713 * @ring: amdgpu_ring pointer 1714 * 1715 * Commits the write pointer to the hardware 1716 */ 1717 static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 1718 { 1719 struct amdgpu_device *adev = ring->adev; 1720 volatile struct amdgpu_fw_shared *fw_shared; 1721 1722 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1723 /*whenever update RBC_RB_WPTR, we save the wptr in shared rb.wptr and scratch2 */ 1724 fw_shared = adev->vcn.inst[ring->me].fw_shared.cpu_addr; 1725 fw_shared->rb.wptr = lower_32_bits(ring->wptr); 1726 WREG32_SOC15(VCN, ring->me, mmUVD_SCRATCH2, 1727 lower_32_bits(ring->wptr)); 1728 } 1729 1730 if (ring->use_doorbell) { 1731 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1732 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1733 } else { 1734 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1735 } 1736 } 1737 1738 static const struct amdgpu_ring_funcs vcn_v3_0_dec_sw_ring_vm_funcs = { 1739 .type = AMDGPU_RING_TYPE_VCN_DEC, 1740 .align_mask = 0x3f, 1741 .nop = VCN_DEC_SW_CMD_NO_OP, 1742 .secure_submission_supported = true, 1743 .get_rptr = vcn_v3_0_dec_ring_get_rptr, 1744 .get_wptr = vcn_v3_0_dec_ring_get_wptr, 1745 .set_wptr = vcn_v3_0_dec_ring_set_wptr, 1746 .emit_frame_size = 1747 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1748 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1749 VCN_SW_RING_EMIT_FRAME_SIZE, 1750 .emit_ib_size = 5, /* vcn_dec_sw_ring_emit_ib */ 1751 .emit_ib = vcn_dec_sw_ring_emit_ib, 1752 .emit_fence = vcn_dec_sw_ring_emit_fence, 1753 .emit_vm_flush = vcn_dec_sw_ring_emit_vm_flush, 1754 .test_ring = amdgpu_vcn_dec_sw_ring_test_ring, 1755 .test_ib = NULL,//amdgpu_vcn_dec_sw_ring_test_ib, 1756 .insert_nop = amdgpu_ring_insert_nop, 1757 .insert_end = vcn_dec_sw_ring_insert_end, 1758 .pad_ib = amdgpu_ring_generic_pad_ib, 1759 .begin_use = amdgpu_vcn_ring_begin_use, 1760 .end_use = amdgpu_vcn_ring_end_use, 1761 .emit_wreg = vcn_dec_sw_ring_emit_wreg, 1762 .emit_reg_wait = vcn_dec_sw_ring_emit_reg_wait, 1763 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1764 }; 1765 1766 static int vcn_v3_0_limit_sched(struct amdgpu_cs_parser *p, 1767 struct amdgpu_job *job) 1768 { 1769 struct drm_gpu_scheduler **scheds; 1770 1771 /* The create msg must be in the first IB submitted */ 1772 if (atomic_read(&job->base.entity->fence_seq)) 1773 return -EINVAL; 1774 1775 /* if VCN0 is harvested, we can't support AV1 */ 1776 if (p->adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) 1777 return -EINVAL; 1778 1779 scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_DEC] 1780 [AMDGPU_RING_PRIO_DEFAULT].sched; 1781 drm_sched_entity_modify_sched(job->base.entity, scheds, 1); 1782 return 0; 1783 } 1784 1785 static int vcn_v3_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job, 1786 uint64_t addr) 1787 { 1788 struct ttm_operation_ctx ctx = { false, false }; 1789 struct amdgpu_bo_va_mapping *map; 1790 uint32_t *msg, num_buffers; 1791 struct amdgpu_bo *bo; 1792 uint64_t start, end; 1793 unsigned int i; 1794 void * ptr; 1795 int r; 1796 1797 addr &= AMDGPU_GMC_HOLE_MASK; 1798 r = amdgpu_cs_find_mapping(p, addr, &bo, &map); 1799 if (r) { 1800 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 1801 return r; 1802 } 1803 1804 start = map->start * AMDGPU_GPU_PAGE_SIZE; 1805 end = (map->last + 1) * AMDGPU_GPU_PAGE_SIZE; 1806 if (addr & 0x7) { 1807 DRM_ERROR("VCN messages must be 8 byte aligned!\n"); 1808 return -EINVAL; 1809 } 1810 1811 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1812 amdgpu_bo_placement_from_domain(bo, bo->allowed_domains); 1813 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 1814 if (r) { 1815 DRM_ERROR("Failed validating the VCN message BO (%d)!\n", r); 1816 return r; 1817 } 1818 1819 r = amdgpu_bo_kmap(bo, &ptr); 1820 if (r) { 1821 DRM_ERROR("Failed mapping the VCN message (%d)!\n", r); 1822 return r; 1823 } 1824 1825 msg = ptr + addr - start; 1826 1827 /* Check length */ 1828 if (msg[1] > end - addr) { 1829 r = -EINVAL; 1830 goto out; 1831 } 1832 1833 if (msg[3] != RDECODE_MSG_CREATE) 1834 goto out; 1835 1836 num_buffers = msg[2]; 1837 for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) { 1838 uint32_t offset, size, *create; 1839 1840 if (msg[0] != RDECODE_MESSAGE_CREATE) 1841 continue; 1842 1843 offset = msg[1]; 1844 size = msg[2]; 1845 1846 if (offset + size > end) { 1847 r = -EINVAL; 1848 goto out; 1849 } 1850 1851 create = ptr + addr + offset - start; 1852 1853 /* H246, HEVC and VP9 can run on any instance */ 1854 if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11) 1855 continue; 1856 1857 r = vcn_v3_0_limit_sched(p, job); 1858 if (r) 1859 goto out; 1860 } 1861 1862 out: 1863 amdgpu_bo_kunmap(bo); 1864 return r; 1865 } 1866 1867 static int vcn_v3_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, 1868 struct amdgpu_job *job, 1869 struct amdgpu_ib *ib) 1870 { 1871 struct amdgpu_ring *ring = amdgpu_job_ring(job); 1872 uint32_t msg_lo = 0, msg_hi = 0; 1873 unsigned i; 1874 int r; 1875 1876 /* The first instance can decode anything */ 1877 if (!ring->me) 1878 return 0; 1879 1880 for (i = 0; i < ib->length_dw; i += 2) { 1881 uint32_t reg = amdgpu_ib_get_value(ib, i); 1882 uint32_t val = amdgpu_ib_get_value(ib, i + 1); 1883 1884 if (reg == PACKET0(p->adev->vcn.internal.data0, 0)) { 1885 msg_lo = val; 1886 } else if (reg == PACKET0(p->adev->vcn.internal.data1, 0)) { 1887 msg_hi = val; 1888 } else if (reg == PACKET0(p->adev->vcn.internal.cmd, 0) && 1889 val == 0) { 1890 r = vcn_v3_0_dec_msg(p, job, 1891 ((u64)msg_hi) << 32 | msg_lo); 1892 if (r) 1893 return r; 1894 } 1895 } 1896 return 0; 1897 } 1898 1899 static const struct amdgpu_ring_funcs vcn_v3_0_dec_ring_vm_funcs = { 1900 .type = AMDGPU_RING_TYPE_VCN_DEC, 1901 .align_mask = 0xf, 1902 .secure_submission_supported = true, 1903 .get_rptr = vcn_v3_0_dec_ring_get_rptr, 1904 .get_wptr = vcn_v3_0_dec_ring_get_wptr, 1905 .set_wptr = vcn_v3_0_dec_ring_set_wptr, 1906 .patch_cs_in_place = vcn_v3_0_ring_patch_cs_in_place, 1907 .emit_frame_size = 1908 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1909 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1910 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */ 1911 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */ 1912 6, 1913 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */ 1914 .emit_ib = vcn_v2_0_dec_ring_emit_ib, 1915 .emit_fence = vcn_v2_0_dec_ring_emit_fence, 1916 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush, 1917 .test_ring = vcn_v2_0_dec_ring_test_ring, 1918 .test_ib = amdgpu_vcn_dec_ring_test_ib, 1919 .insert_nop = vcn_v2_0_dec_ring_insert_nop, 1920 .insert_start = vcn_v2_0_dec_ring_insert_start, 1921 .insert_end = vcn_v2_0_dec_ring_insert_end, 1922 .pad_ib = amdgpu_ring_generic_pad_ib, 1923 .begin_use = amdgpu_vcn_ring_begin_use, 1924 .end_use = amdgpu_vcn_ring_end_use, 1925 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg, 1926 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait, 1927 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1928 }; 1929 1930 /** 1931 * vcn_v3_0_enc_ring_get_rptr - get enc read pointer 1932 * 1933 * @ring: amdgpu_ring pointer 1934 * 1935 * Returns the current hardware enc read pointer 1936 */ 1937 static uint64_t vcn_v3_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 1938 { 1939 struct amdgpu_device *adev = ring->adev; 1940 1941 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) 1942 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR); 1943 else 1944 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2); 1945 } 1946 1947 /** 1948 * vcn_v3_0_enc_ring_get_wptr - get enc write pointer 1949 * 1950 * @ring: amdgpu_ring pointer 1951 * 1952 * Returns the current hardware enc write pointer 1953 */ 1954 static uint64_t vcn_v3_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 1955 { 1956 struct amdgpu_device *adev = ring->adev; 1957 1958 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 1959 if (ring->use_doorbell) 1960 return *ring->wptr_cpu_addr; 1961 else 1962 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR); 1963 } else { 1964 if (ring->use_doorbell) 1965 return *ring->wptr_cpu_addr; 1966 else 1967 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2); 1968 } 1969 } 1970 1971 /** 1972 * vcn_v3_0_enc_ring_set_wptr - set enc write pointer 1973 * 1974 * @ring: amdgpu_ring pointer 1975 * 1976 * Commits the enc write pointer to the hardware 1977 */ 1978 static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 1979 { 1980 struct amdgpu_device *adev = ring->adev; 1981 1982 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 1983 if (ring->use_doorbell) { 1984 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1985 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1986 } else { 1987 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1988 } 1989 } else { 1990 if (ring->use_doorbell) { 1991 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1992 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1993 } else { 1994 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1995 } 1996 } 1997 } 1998 1999 static const struct amdgpu_ring_funcs vcn_v3_0_enc_ring_vm_funcs = { 2000 .type = AMDGPU_RING_TYPE_VCN_ENC, 2001 .align_mask = 0x3f, 2002 .nop = VCN_ENC_CMD_NO_OP, 2003 .get_rptr = vcn_v3_0_enc_ring_get_rptr, 2004 .get_wptr = vcn_v3_0_enc_ring_get_wptr, 2005 .set_wptr = vcn_v3_0_enc_ring_set_wptr, 2006 .emit_frame_size = 2007 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2008 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 2009 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 2010 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 2011 1, /* vcn_v2_0_enc_ring_insert_end */ 2012 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 2013 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 2014 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 2015 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 2016 .test_ring = amdgpu_vcn_enc_ring_test_ring, 2017 .test_ib = amdgpu_vcn_enc_ring_test_ib, 2018 .insert_nop = amdgpu_ring_insert_nop, 2019 .insert_end = vcn_v2_0_enc_ring_insert_end, 2020 .pad_ib = amdgpu_ring_generic_pad_ib, 2021 .begin_use = amdgpu_vcn_ring_begin_use, 2022 .end_use = amdgpu_vcn_ring_end_use, 2023 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 2024 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 2025 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2026 }; 2027 2028 static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev) 2029 { 2030 int i; 2031 2032 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2033 if (adev->vcn.harvest_config & (1 << i)) 2034 continue; 2035 2036 if (!DEC_SW_RING_ENABLED) 2037 adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_ring_vm_funcs; 2038 else 2039 adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_sw_ring_vm_funcs; 2040 adev->vcn.inst[i].ring_dec.me = i; 2041 DRM_INFO("VCN(%d) decode%s is enabled in VM mode\n", i, 2042 DEC_SW_RING_ENABLED?"(Software Ring)":""); 2043 } 2044 } 2045 2046 static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev) 2047 { 2048 int i, j; 2049 2050 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2051 if (adev->vcn.harvest_config & (1 << i)) 2052 continue; 2053 2054 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 2055 adev->vcn.inst[i].ring_enc[j].funcs = &vcn_v3_0_enc_ring_vm_funcs; 2056 adev->vcn.inst[i].ring_enc[j].me = i; 2057 } 2058 if (adev->vcn.num_enc_rings > 0) 2059 DRM_INFO("VCN(%d) encode is enabled in VM mode\n", i); 2060 } 2061 } 2062 2063 static bool vcn_v3_0_is_idle(void *handle) 2064 { 2065 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2066 int i, ret = 1; 2067 2068 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2069 if (adev->vcn.harvest_config & (1 << i)) 2070 continue; 2071 2072 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); 2073 } 2074 2075 return ret; 2076 } 2077 2078 static int vcn_v3_0_wait_for_idle(void *handle) 2079 { 2080 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2081 int i, ret = 0; 2082 2083 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2084 if (adev->vcn.harvest_config & (1 << i)) 2085 continue; 2086 2087 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 2088 UVD_STATUS__IDLE); 2089 if (ret) 2090 return ret; 2091 } 2092 2093 return ret; 2094 } 2095 2096 static int vcn_v3_0_set_clockgating_state(void *handle, 2097 enum amd_clockgating_state state) 2098 { 2099 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2100 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 2101 int i; 2102 2103 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2104 if (adev->vcn.harvest_config & (1 << i)) 2105 continue; 2106 2107 if (enable) { 2108 if (RREG32_SOC15(VCN, i, mmUVD_STATUS) != UVD_STATUS__IDLE) 2109 return -EBUSY; 2110 vcn_v3_0_enable_clock_gating(adev, i); 2111 } else { 2112 vcn_v3_0_disable_clock_gating(adev, i); 2113 } 2114 } 2115 2116 return 0; 2117 } 2118 2119 static int vcn_v3_0_set_powergating_state(void *handle, 2120 enum amd_powergating_state state) 2121 { 2122 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2123 int ret; 2124 2125 /* for SRIOV, guest should not control VCN Power-gating 2126 * MMSCH FW should control Power-gating and clock-gating 2127 * guest should avoid touching CGC and PG 2128 */ 2129 if (amdgpu_sriov_vf(adev)) { 2130 adev->vcn.cur_state = AMD_PG_STATE_UNGATE; 2131 return 0; 2132 } 2133 2134 if(state == adev->vcn.cur_state) 2135 return 0; 2136 2137 if (state == AMD_PG_STATE_GATE) 2138 ret = vcn_v3_0_stop(adev); 2139 else 2140 ret = vcn_v3_0_start(adev); 2141 2142 if(!ret) 2143 adev->vcn.cur_state = state; 2144 2145 return ret; 2146 } 2147 2148 static int vcn_v3_0_set_interrupt_state(struct amdgpu_device *adev, 2149 struct amdgpu_irq_src *source, 2150 unsigned type, 2151 enum amdgpu_interrupt_state state) 2152 { 2153 return 0; 2154 } 2155 2156 static int vcn_v3_0_process_interrupt(struct amdgpu_device *adev, 2157 struct amdgpu_irq_src *source, 2158 struct amdgpu_iv_entry *entry) 2159 { 2160 uint32_t ip_instance; 2161 2162 switch (entry->client_id) { 2163 case SOC15_IH_CLIENTID_VCN: 2164 ip_instance = 0; 2165 break; 2166 case SOC15_IH_CLIENTID_VCN1: 2167 ip_instance = 1; 2168 break; 2169 default: 2170 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 2171 return 0; 2172 } 2173 2174 DRM_DEBUG("IH: VCN TRAP\n"); 2175 2176 switch (entry->src_id) { 2177 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT: 2178 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec); 2179 break; 2180 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 2181 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 2182 break; 2183 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY: 2184 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]); 2185 break; 2186 default: 2187 DRM_ERROR("Unhandled interrupt: %d %d\n", 2188 entry->src_id, entry->src_data[0]); 2189 break; 2190 } 2191 2192 return 0; 2193 } 2194 2195 static const struct amdgpu_irq_src_funcs vcn_v3_0_irq_funcs = { 2196 .set = vcn_v3_0_set_interrupt_state, 2197 .process = vcn_v3_0_process_interrupt, 2198 }; 2199 2200 static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev) 2201 { 2202 int i; 2203 2204 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2205 if (adev->vcn.harvest_config & (1 << i)) 2206 continue; 2207 2208 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1; 2209 adev->vcn.inst[i].irq.funcs = &vcn_v3_0_irq_funcs; 2210 } 2211 } 2212 2213 static const struct amd_ip_funcs vcn_v3_0_ip_funcs = { 2214 .name = "vcn_v3_0", 2215 .early_init = vcn_v3_0_early_init, 2216 .late_init = NULL, 2217 .sw_init = vcn_v3_0_sw_init, 2218 .sw_fini = vcn_v3_0_sw_fini, 2219 .hw_init = vcn_v3_0_hw_init, 2220 .hw_fini = vcn_v3_0_hw_fini, 2221 .suspend = vcn_v3_0_suspend, 2222 .resume = vcn_v3_0_resume, 2223 .is_idle = vcn_v3_0_is_idle, 2224 .wait_for_idle = vcn_v3_0_wait_for_idle, 2225 .check_soft_reset = NULL, 2226 .pre_soft_reset = NULL, 2227 .soft_reset = NULL, 2228 .post_soft_reset = NULL, 2229 .set_clockgating_state = vcn_v3_0_set_clockgating_state, 2230 .set_powergating_state = vcn_v3_0_set_powergating_state, 2231 }; 2232 2233 const struct amdgpu_ip_block_version vcn_v3_0_ip_block = 2234 { 2235 .type = AMD_IP_BLOCK_TYPE_VCN, 2236 .major = 3, 2237 .minor = 0, 2238 .rev = 0, 2239 .funcs = &vcn_v3_0_ip_funcs, 2240 }; 2241