1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_vcn.h" 27 #include "amdgpu_pm.h" 28 #include "soc15.h" 29 #include "soc15d.h" 30 #include "vcn_v2_0.h" 31 #include "mmsch_v3_0.h" 32 33 #include "vcn/vcn_3_0_0_offset.h" 34 #include "vcn/vcn_3_0_0_sh_mask.h" 35 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 36 37 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x27 38 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x0f 39 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x10 40 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x11 41 #define mmUVD_NO_OP_INTERNAL_OFFSET 0x29 42 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x66 43 #define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d 44 45 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x431 46 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x3b4 47 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x3b5 48 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x25c 49 50 #define VCN_INSTANCES_SIENNA_CICHLID 2 51 #define DEC_SW_RING_ENABLED FALSE 52 53 #define RDECODE_MSG_CREATE 0x00000000 54 #define RDECODE_MESSAGE_CREATE 0x00000001 55 56 static int amdgpu_ih_clientid_vcns[] = { 57 SOC15_IH_CLIENTID_VCN, 58 SOC15_IH_CLIENTID_VCN1 59 }; 60 61 static int amdgpu_ucode_id_vcns[] = { 62 AMDGPU_UCODE_ID_VCN, 63 AMDGPU_UCODE_ID_VCN1 64 }; 65 66 static int vcn_v3_0_start_sriov(struct amdgpu_device *adev); 67 static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev); 68 static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev); 69 static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev); 70 static int vcn_v3_0_set_powergating_state(void *handle, 71 enum amd_powergating_state state); 72 static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev, 73 int inst_idx, struct dpg_pause_state *new_state); 74 75 static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring); 76 static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring); 77 78 /** 79 * vcn_v3_0_early_init - set function pointers 80 * 81 * @handle: amdgpu_device pointer 82 * 83 * Set ring and irq function pointers 84 */ 85 static int vcn_v3_0_early_init(void *handle) 86 { 87 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 88 89 if (amdgpu_sriov_vf(adev)) { 90 adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID; 91 adev->vcn.harvest_config = 0; 92 adev->vcn.num_enc_rings = 1; 93 94 } else { 95 if (adev->asic_type == CHIP_SIENNA_CICHLID) { 96 u32 harvest; 97 int i; 98 99 adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID; 100 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 101 harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING); 102 if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK) 103 adev->vcn.harvest_config |= 1 << i; 104 } 105 106 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 | 107 AMDGPU_VCN_HARVEST_VCN1)) 108 /* both instances are harvested, disable the block */ 109 return -ENOENT; 110 } else 111 adev->vcn.num_vcn_inst = 1; 112 113 adev->vcn.num_enc_rings = 2; 114 } 115 116 vcn_v3_0_set_dec_ring_funcs(adev); 117 vcn_v3_0_set_enc_ring_funcs(adev); 118 vcn_v3_0_set_irq_funcs(adev); 119 120 return 0; 121 } 122 123 /** 124 * vcn_v3_0_sw_init - sw init for VCN block 125 * 126 * @handle: amdgpu_device pointer 127 * 128 * Load firmware and sw initialization 129 */ 130 static int vcn_v3_0_sw_init(void *handle) 131 { 132 struct amdgpu_ring *ring; 133 int i, j, r; 134 int vcn_doorbell_index = 0; 135 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 136 137 r = amdgpu_vcn_sw_init(adev); 138 if (r) 139 return r; 140 141 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 142 const struct common_firmware_header *hdr; 143 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 144 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN; 145 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw; 146 adev->firmware.fw_size += 147 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 148 149 if (adev->vcn.num_vcn_inst == VCN_INSTANCES_SIENNA_CICHLID) { 150 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].ucode_id = AMDGPU_UCODE_ID_VCN1; 151 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].fw = adev->vcn.fw; 152 adev->firmware.fw_size += 153 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 154 } 155 DRM_INFO("PSP loading VCN firmware\n"); 156 } 157 158 r = amdgpu_vcn_resume(adev); 159 if (r) 160 return r; 161 162 /* 163 * Note: doorbell assignment is fixed for SRIOV multiple VCN engines 164 * Formula: 165 * vcn_db_base = adev->doorbell_index.vcn.vcn_ring0_1 << 1; 166 * dec_ring_i = vcn_db_base + i * (adev->vcn.num_enc_rings + 1) 167 * enc_ring_i,j = vcn_db_base + i * (adev->vcn.num_enc_rings + 1) + 1 + j 168 */ 169 if (amdgpu_sriov_vf(adev)) { 170 vcn_doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1; 171 /* get DWORD offset */ 172 vcn_doorbell_index = vcn_doorbell_index << 1; 173 } 174 175 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 176 volatile struct amdgpu_fw_shared *fw_shared; 177 178 if (adev->vcn.harvest_config & (1 << i)) 179 continue; 180 181 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; 182 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; 183 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; 184 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; 185 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; 186 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; 187 188 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; 189 adev->vcn.inst[i].external.scratch9 = SOC15_REG_OFFSET(VCN, i, mmUVD_SCRATCH9); 190 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; 191 adev->vcn.inst[i].external.data0 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA0); 192 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; 193 adev->vcn.inst[i].external.data1 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA1); 194 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; 195 adev->vcn.inst[i].external.cmd = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_CMD); 196 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; 197 adev->vcn.inst[i].external.nop = SOC15_REG_OFFSET(VCN, i, mmUVD_NO_OP); 198 199 /* VCN DEC TRAP */ 200 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 201 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[i].irq); 202 if (r) 203 return r; 204 205 atomic_set(&adev->vcn.inst[i].sched_score, 0); 206 207 ring = &adev->vcn.inst[i].ring_dec; 208 ring->use_doorbell = true; 209 if (amdgpu_sriov_vf(adev)) { 210 ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1); 211 } else { 212 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i; 213 } 214 sprintf(ring->name, "vcn_dec_%d", i); 215 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 216 AMDGPU_RING_PRIO_DEFAULT, 217 &adev->vcn.inst[i].sched_score); 218 if (r) 219 return r; 220 221 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 222 /* VCN ENC TRAP */ 223 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 224 j + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); 225 if (r) 226 return r; 227 228 ring = &adev->vcn.inst[i].ring_enc[j]; 229 ring->use_doorbell = true; 230 if (amdgpu_sriov_vf(adev)) { 231 ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1) + 1 + j; 232 } else { 233 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + j + 8 * i; 234 } 235 sprintf(ring->name, "vcn_enc_%d.%d", i, j); 236 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 237 AMDGPU_RING_PRIO_DEFAULT, 238 &adev->vcn.inst[i].sched_score); 239 if (r) 240 return r; 241 } 242 243 fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr; 244 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SW_RING_FLAG) | 245 cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG) | 246 cpu_to_le32(AMDGPU_VCN_FW_SHARED_FLAG_0_RB); 247 fw_shared->sw_ring.is_enabled = cpu_to_le32(DEC_SW_RING_ENABLED); 248 } 249 250 if (amdgpu_sriov_vf(adev)) { 251 r = amdgpu_virt_alloc_mm_table(adev); 252 if (r) 253 return r; 254 } 255 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 256 adev->vcn.pause_dpg_mode = vcn_v3_0_pause_dpg_mode; 257 258 return 0; 259 } 260 261 /** 262 * vcn_v3_0_sw_fini - sw fini for VCN block 263 * 264 * @handle: amdgpu_device pointer 265 * 266 * VCN suspend and free up sw allocation 267 */ 268 static int vcn_v3_0_sw_fini(void *handle) 269 { 270 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 271 int i, r; 272 273 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 274 volatile struct amdgpu_fw_shared *fw_shared; 275 276 if (adev->vcn.harvest_config & (1 << i)) 277 continue; 278 fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr; 279 fw_shared->present_flag_0 = 0; 280 fw_shared->sw_ring.is_enabled = false; 281 } 282 283 if (amdgpu_sriov_vf(adev)) 284 amdgpu_virt_free_mm_table(adev); 285 286 r = amdgpu_vcn_suspend(adev); 287 if (r) 288 return r; 289 290 r = amdgpu_vcn_sw_fini(adev); 291 292 return r; 293 } 294 295 /** 296 * vcn_v3_0_hw_init - start and test VCN block 297 * 298 * @handle: amdgpu_device pointer 299 * 300 * Initialize the hardware, boot up the VCPU and do some testing 301 */ 302 static int vcn_v3_0_hw_init(void *handle) 303 { 304 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 305 struct amdgpu_ring *ring; 306 int i, j, r; 307 308 if (amdgpu_sriov_vf(adev)) { 309 r = vcn_v3_0_start_sriov(adev); 310 if (r) 311 goto done; 312 313 /* initialize VCN dec and enc ring buffers */ 314 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 315 if (adev->vcn.harvest_config & (1 << i)) 316 continue; 317 318 ring = &adev->vcn.inst[i].ring_dec; 319 if (ring->sched.ready) { 320 ring->wptr = 0; 321 ring->wptr_old = 0; 322 vcn_v3_0_dec_ring_set_wptr(ring); 323 } 324 325 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 326 ring = &adev->vcn.inst[i].ring_enc[j]; 327 if (ring->sched.ready) { 328 ring->wptr = 0; 329 ring->wptr_old = 0; 330 vcn_v3_0_enc_ring_set_wptr(ring); 331 } 332 } 333 } 334 } else { 335 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 336 if (adev->vcn.harvest_config & (1 << i)) 337 continue; 338 339 ring = &adev->vcn.inst[i].ring_dec; 340 341 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 342 ring->doorbell_index, i); 343 344 r = amdgpu_ring_test_helper(ring); 345 if (r) 346 goto done; 347 348 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 349 ring = &adev->vcn.inst[i].ring_enc[j]; 350 r = amdgpu_ring_test_helper(ring); 351 if (r) 352 goto done; 353 } 354 } 355 } 356 357 done: 358 if (!r) 359 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 360 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 361 362 return r; 363 } 364 365 /** 366 * vcn_v3_0_hw_fini - stop the hardware block 367 * 368 * @handle: amdgpu_device pointer 369 * 370 * Stop the VCN block, mark ring as not ready any more 371 */ 372 static int vcn_v3_0_hw_fini(void *handle) 373 { 374 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 375 struct amdgpu_ring *ring; 376 int i; 377 378 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 379 if (adev->vcn.harvest_config & (1 << i)) 380 continue; 381 382 ring = &adev->vcn.inst[i].ring_dec; 383 384 if (!amdgpu_sriov_vf(adev)) { 385 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 386 (adev->vcn.cur_state != AMD_PG_STATE_GATE && 387 RREG32_SOC15(VCN, i, mmUVD_STATUS))) { 388 vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 389 } 390 } 391 } 392 393 return 0; 394 } 395 396 /** 397 * vcn_v3_0_suspend - suspend VCN block 398 * 399 * @handle: amdgpu_device pointer 400 * 401 * HW fini and suspend VCN block 402 */ 403 static int vcn_v3_0_suspend(void *handle) 404 { 405 int r; 406 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 407 408 r = vcn_v3_0_hw_fini(adev); 409 if (r) 410 return r; 411 412 r = amdgpu_vcn_suspend(adev); 413 414 return r; 415 } 416 417 /** 418 * vcn_v3_0_resume - resume VCN block 419 * 420 * @handle: amdgpu_device pointer 421 * 422 * Resume firmware and hw init VCN block 423 */ 424 static int vcn_v3_0_resume(void *handle) 425 { 426 int r; 427 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 428 429 r = amdgpu_vcn_resume(adev); 430 if (r) 431 return r; 432 433 r = vcn_v3_0_hw_init(adev); 434 435 return r; 436 } 437 438 /** 439 * vcn_v3_0_mc_resume - memory controller programming 440 * 441 * @adev: amdgpu_device pointer 442 * @inst: instance number 443 * 444 * Let the VCN memory controller know it's offsets 445 */ 446 static void vcn_v3_0_mc_resume(struct amdgpu_device *adev, int inst) 447 { 448 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 449 uint32_t offset; 450 451 /* cache window 0: fw */ 452 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 453 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 454 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 455 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 456 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 457 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 0); 458 offset = 0; 459 } else { 460 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 461 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 462 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 463 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 464 offset = size; 465 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 466 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 467 } 468 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE0, size); 469 470 /* cache window 1: stack */ 471 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 472 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 473 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 474 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 475 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET1, 0); 476 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 477 478 /* cache window 2: context */ 479 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 480 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 481 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 482 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 483 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET2, 0); 484 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 485 486 /* non-cache window */ 487 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 488 lower_32_bits(adev->vcn.inst[inst].fw_shared_gpu_addr)); 489 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 490 upper_32_bits(adev->vcn.inst[inst].fw_shared_gpu_addr)); 491 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_OFFSET0, 0); 492 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_SIZE0, 493 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); 494 } 495 496 static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 497 { 498 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 499 uint32_t offset; 500 501 /* cache window 0: fw */ 502 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 503 if (!indirect) { 504 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 505 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 506 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); 507 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 508 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 509 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); 510 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 511 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 512 } else { 513 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 514 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 515 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 516 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 517 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 518 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 519 } 520 offset = 0; 521 } else { 522 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 523 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 524 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 525 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 526 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 527 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 528 offset = size; 529 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 530 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 531 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 532 } 533 534 if (!indirect) 535 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 536 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 537 else 538 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 539 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 540 541 /* cache window 1: stack */ 542 if (!indirect) { 543 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 544 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 545 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 546 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 547 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 548 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 549 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 550 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 551 } else { 552 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 553 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 554 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 555 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 556 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 557 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 558 } 559 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 560 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 561 562 /* cache window 2: context */ 563 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 564 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 565 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 566 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 567 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 568 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 569 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 570 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 571 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 572 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 573 574 /* non-cache window */ 575 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 576 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 577 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect); 578 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 579 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 580 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect); 581 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 582 VCN, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 583 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 584 VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), 585 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); 586 587 /* VCN global tiling registers */ 588 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 589 UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 590 } 591 592 static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int inst) 593 { 594 uint32_t data = 0; 595 596 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 597 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 598 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 599 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 600 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 601 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 602 | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 603 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 604 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 605 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 606 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 607 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 608 | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 609 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 610 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 611 612 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 613 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 614 UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF); 615 } else { 616 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 617 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 618 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 619 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 620 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 621 | 1 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 622 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 623 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 624 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 625 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 626 | 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 627 | 1 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 628 | 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 629 | 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 630 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 631 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 0, 0x3F3FFFFF); 632 } 633 634 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); 635 data &= ~0x103; 636 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 637 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 638 UVD_POWER_STATUS__UVD_PG_EN_MASK; 639 640 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); 641 } 642 643 static void vcn_v3_0_enable_static_power_gating(struct amdgpu_device *adev, int inst) 644 { 645 uint32_t data; 646 647 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 648 /* Before power off, this indicator has to be turned on */ 649 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); 650 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 651 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 652 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); 653 654 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 655 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 656 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 657 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 658 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 659 | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 660 | 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 661 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 662 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 663 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 664 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 665 | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 666 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 667 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 668 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 669 670 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 671 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 672 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 673 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 674 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 675 | 2 << UVD_PGFSM_STATUS__UVDIRL_PWR_STATUS__SHIFT 676 | 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT 677 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 678 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 679 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 680 | 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT 681 | 2 << UVD_PGFSM_STATUS__UVDATD_PWR_STATUS__SHIFT 682 | 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT 683 | 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT); 684 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, data, 0x3F3FFFFF); 685 } 686 } 687 688 /** 689 * vcn_v3_0_disable_clock_gating - disable VCN clock gating 690 * 691 * @adev: amdgpu_device pointer 692 * @inst: instance number 693 * 694 * Disable clock gating for VCN block 695 */ 696 static void vcn_v3_0_disable_clock_gating(struct amdgpu_device *adev, int inst) 697 { 698 uint32_t data; 699 700 /* VCN disable CGC */ 701 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 702 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 703 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 704 else 705 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 706 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 707 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 708 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 709 710 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_GATE); 711 data &= ~(UVD_CGC_GATE__SYS_MASK 712 | UVD_CGC_GATE__UDEC_MASK 713 | UVD_CGC_GATE__MPEG2_MASK 714 | UVD_CGC_GATE__REGS_MASK 715 | UVD_CGC_GATE__RBC_MASK 716 | UVD_CGC_GATE__LMI_MC_MASK 717 | UVD_CGC_GATE__LMI_UMC_MASK 718 | UVD_CGC_GATE__IDCT_MASK 719 | UVD_CGC_GATE__MPRD_MASK 720 | UVD_CGC_GATE__MPC_MASK 721 | UVD_CGC_GATE__LBSI_MASK 722 | UVD_CGC_GATE__LRBBM_MASK 723 | UVD_CGC_GATE__UDEC_RE_MASK 724 | UVD_CGC_GATE__UDEC_CM_MASK 725 | UVD_CGC_GATE__UDEC_IT_MASK 726 | UVD_CGC_GATE__UDEC_DB_MASK 727 | UVD_CGC_GATE__UDEC_MP_MASK 728 | UVD_CGC_GATE__WCB_MASK 729 | UVD_CGC_GATE__VCPU_MASK 730 | UVD_CGC_GATE__MMSCH_MASK); 731 732 WREG32_SOC15(VCN, inst, mmUVD_CGC_GATE, data); 733 734 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); 735 736 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 737 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 738 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 739 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 740 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 741 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 742 | UVD_CGC_CTRL__SYS_MODE_MASK 743 | UVD_CGC_CTRL__UDEC_MODE_MASK 744 | UVD_CGC_CTRL__MPEG2_MODE_MASK 745 | UVD_CGC_CTRL__REGS_MODE_MASK 746 | UVD_CGC_CTRL__RBC_MODE_MASK 747 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 748 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 749 | UVD_CGC_CTRL__IDCT_MODE_MASK 750 | UVD_CGC_CTRL__MPRD_MODE_MASK 751 | UVD_CGC_CTRL__MPC_MODE_MASK 752 | UVD_CGC_CTRL__LBSI_MODE_MASK 753 | UVD_CGC_CTRL__LRBBM_MODE_MASK 754 | UVD_CGC_CTRL__WCB_MODE_MASK 755 | UVD_CGC_CTRL__VCPU_MODE_MASK 756 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 757 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 758 759 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE); 760 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 761 | UVD_SUVD_CGC_GATE__SIT_MASK 762 | UVD_SUVD_CGC_GATE__SMP_MASK 763 | UVD_SUVD_CGC_GATE__SCM_MASK 764 | UVD_SUVD_CGC_GATE__SDB_MASK 765 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 766 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 767 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 768 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 769 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 770 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 771 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 772 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 773 | UVD_SUVD_CGC_GATE__SCLR_MASK 774 | UVD_SUVD_CGC_GATE__ENT_MASK 775 | UVD_SUVD_CGC_GATE__IME_MASK 776 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 777 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 778 | UVD_SUVD_CGC_GATE__SITE_MASK 779 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 780 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 781 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 782 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 783 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK 784 | UVD_SUVD_CGC_GATE__EFC_MASK 785 | UVD_SUVD_CGC_GATE__SAOE_MASK 786 | UVD_SUVD_CGC_GATE__SRE_AV1_MASK 787 | UVD_SUVD_CGC_GATE__FBC_PCLK_MASK 788 | UVD_SUVD_CGC_GATE__FBC_CCLK_MASK 789 | UVD_SUVD_CGC_GATE__SCM_AV1_MASK 790 | UVD_SUVD_CGC_GATE__SMPA_MASK); 791 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE, data); 792 793 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2); 794 data |= (UVD_SUVD_CGC_GATE2__MPBE0_MASK 795 | UVD_SUVD_CGC_GATE2__MPBE1_MASK 796 | UVD_SUVD_CGC_GATE2__SIT_AV1_MASK 797 | UVD_SUVD_CGC_GATE2__SDB_AV1_MASK 798 | UVD_SUVD_CGC_GATE2__MPC1_MASK); 799 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2, data); 800 801 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL); 802 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 803 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 804 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 805 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 806 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 807 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 808 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 809 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 810 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 811 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 812 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK 813 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK 814 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK 815 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK 816 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 817 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 818 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK 819 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK 820 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK); 821 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data); 822 } 823 824 static void vcn_v3_0_clock_gating_dpg_mode(struct amdgpu_device *adev, 825 uint8_t sram_sel, int inst_idx, uint8_t indirect) 826 { 827 uint32_t reg_data = 0; 828 829 /* enable sw clock gating control */ 830 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 831 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 832 else 833 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 834 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 835 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 836 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 837 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 838 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 839 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 840 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 841 UVD_CGC_CTRL__SYS_MODE_MASK | 842 UVD_CGC_CTRL__UDEC_MODE_MASK | 843 UVD_CGC_CTRL__MPEG2_MODE_MASK | 844 UVD_CGC_CTRL__REGS_MODE_MASK | 845 UVD_CGC_CTRL__RBC_MODE_MASK | 846 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 847 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 848 UVD_CGC_CTRL__IDCT_MODE_MASK | 849 UVD_CGC_CTRL__MPRD_MODE_MASK | 850 UVD_CGC_CTRL__MPC_MODE_MASK | 851 UVD_CGC_CTRL__LBSI_MODE_MASK | 852 UVD_CGC_CTRL__LRBBM_MODE_MASK | 853 UVD_CGC_CTRL__WCB_MODE_MASK | 854 UVD_CGC_CTRL__VCPU_MODE_MASK | 855 UVD_CGC_CTRL__MMSCH_MODE_MASK); 856 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 857 VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); 858 859 /* turn off clock gating */ 860 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 861 VCN, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect); 862 863 /* turn on SUVD clock gating */ 864 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 865 VCN, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 866 867 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 868 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 869 VCN, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 870 } 871 872 /** 873 * vcn_v3_0_enable_clock_gating - enable VCN clock gating 874 * 875 * @adev: amdgpu_device pointer 876 * @inst: instance number 877 * 878 * Enable clock gating for VCN block 879 */ 880 static void vcn_v3_0_enable_clock_gating(struct amdgpu_device *adev, int inst) 881 { 882 uint32_t data; 883 884 /* enable VCN CGC */ 885 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 886 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 887 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 888 else 889 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 890 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 891 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 892 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 893 894 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 895 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 896 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 897 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 898 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 899 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 900 | UVD_CGC_CTRL__SYS_MODE_MASK 901 | UVD_CGC_CTRL__UDEC_MODE_MASK 902 | UVD_CGC_CTRL__MPEG2_MODE_MASK 903 | UVD_CGC_CTRL__REGS_MODE_MASK 904 | UVD_CGC_CTRL__RBC_MODE_MASK 905 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 906 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 907 | UVD_CGC_CTRL__IDCT_MODE_MASK 908 | UVD_CGC_CTRL__MPRD_MODE_MASK 909 | UVD_CGC_CTRL__MPC_MODE_MASK 910 | UVD_CGC_CTRL__LBSI_MODE_MASK 911 | UVD_CGC_CTRL__LRBBM_MODE_MASK 912 | UVD_CGC_CTRL__WCB_MODE_MASK 913 | UVD_CGC_CTRL__VCPU_MODE_MASK 914 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 915 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 916 917 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL); 918 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 919 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 920 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 921 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 922 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 923 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 924 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 925 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 926 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 927 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 928 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK 929 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK 930 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK 931 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK 932 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 933 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 934 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK 935 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK 936 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK); 937 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data); 938 } 939 940 static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 941 { 942 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr; 943 struct amdgpu_ring *ring; 944 uint32_t rb_bufsz, tmp; 945 946 /* disable register anti-hang mechanism */ 947 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1, 948 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 949 /* enable dynamic power gating mode */ 950 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS); 951 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 952 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 953 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp); 954 955 if (indirect) 956 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 957 958 /* enable clock gating */ 959 vcn_v3_0_clock_gating_dpg_mode(adev, 0, inst_idx, indirect); 960 961 /* enable VCPU clock */ 962 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 963 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 964 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK; 965 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 966 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 967 968 /* disable master interupt */ 969 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 970 VCN, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect); 971 972 /* setup mmUVD_LMI_CTRL */ 973 tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 974 UVD_LMI_CTRL__REQ_MODE_MASK | 975 UVD_LMI_CTRL__CRC_RESET_MASK | 976 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 977 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 978 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 979 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 980 0x00100000L); 981 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 982 VCN, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect); 983 984 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 985 VCN, inst_idx, mmUVD_MPC_CNTL), 986 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 987 988 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 989 VCN, inst_idx, mmUVD_MPC_SET_MUXA0), 990 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 991 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 992 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 993 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 994 995 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 996 VCN, inst_idx, mmUVD_MPC_SET_MUXB0), 997 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 998 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 999 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1000 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 1001 1002 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1003 VCN, inst_idx, mmUVD_MPC_SET_MUX), 1004 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1005 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1006 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 1007 1008 vcn_v3_0_mc_resume_dpg_mode(adev, inst_idx, indirect); 1009 1010 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1011 VCN, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect); 1012 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1013 VCN, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect); 1014 1015 /* enable LMI MC and UMC channels */ 1016 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1017 VCN, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect); 1018 1019 /* unblock VCPU register access */ 1020 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1021 VCN, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect); 1022 1023 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 1024 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 1025 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1026 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 1027 1028 /* enable master interrupt */ 1029 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1030 VCN, inst_idx, mmUVD_MASTINT_EN), 1031 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 1032 1033 /* add nop to workaround PSP size check */ 1034 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1035 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 1036 1037 if (indirect) 1038 psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, 1039 (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr - 1040 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr)); 1041 1042 ring = &adev->vcn.inst[inst_idx].ring_dec; 1043 /* force RBC into idle state */ 1044 rb_bufsz = order_base_2(ring->ring_size); 1045 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1046 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1047 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1048 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1049 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1050 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp); 1051 1052 /* Stall DPG before WPTR/RPTR reset */ 1053 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1054 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1055 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1056 fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1057 1058 /* set the write pointer delay */ 1059 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0); 1060 1061 /* set the wb address */ 1062 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR, 1063 (upper_32_bits(ring->gpu_addr) >> 2)); 1064 1065 /* programm the RB_BASE for ring buffer */ 1066 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1067 lower_32_bits(ring->gpu_addr)); 1068 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1069 upper_32_bits(ring->gpu_addr)); 1070 1071 /* Initialize the ring buffer's read and write pointers */ 1072 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0); 1073 1074 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0); 1075 1076 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR); 1077 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, 1078 lower_32_bits(ring->wptr)); 1079 1080 /* Reset FW shared memory RBC WPTR/RPTR */ 1081 fw_shared->rb.rptr = 0; 1082 fw_shared->rb.wptr = lower_32_bits(ring->wptr); 1083 1084 /*resetting done, fw can check RB ring */ 1085 fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1086 1087 /* Unstall DPG */ 1088 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1089 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1090 1091 return 0; 1092 } 1093 1094 static int vcn_v3_0_start(struct amdgpu_device *adev) 1095 { 1096 volatile struct amdgpu_fw_shared *fw_shared; 1097 struct amdgpu_ring *ring; 1098 uint32_t rb_bufsz, tmp; 1099 int i, j, k, r; 1100 1101 if (adev->pm.dpm_enabled) 1102 amdgpu_dpm_enable_uvd(adev, true); 1103 1104 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1105 if (adev->vcn.harvest_config & (1 << i)) 1106 continue; 1107 1108 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG){ 1109 r = vcn_v3_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram); 1110 continue; 1111 } 1112 1113 /* disable VCN power gating */ 1114 vcn_v3_0_disable_static_power_gating(adev, i); 1115 1116 /* set VCN status busy */ 1117 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 1118 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp); 1119 1120 /*SW clock gating */ 1121 vcn_v3_0_disable_clock_gating(adev, i); 1122 1123 /* enable VCPU clock */ 1124 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1125 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 1126 1127 /* disable master interrupt */ 1128 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0, 1129 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1130 1131 /* enable LMI MC and UMC channels */ 1132 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0, 1133 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1134 1135 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1136 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1137 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1138 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1139 1140 /* setup mmUVD_LMI_CTRL */ 1141 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL); 1142 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | 1143 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1144 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1145 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1146 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1147 1148 /* setup mmUVD_MPC_CNTL */ 1149 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL); 1150 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1151 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1152 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp); 1153 1154 /* setup UVD_MPC_SET_MUXA0 */ 1155 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0, 1156 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1157 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1158 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1159 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1160 1161 /* setup UVD_MPC_SET_MUXB0 */ 1162 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0, 1163 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1164 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1165 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1166 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1167 1168 /* setup mmUVD_MPC_SET_MUX */ 1169 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX, 1170 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1171 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1172 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1173 1174 vcn_v3_0_mc_resume(adev, i); 1175 1176 /* VCN global tiling registers */ 1177 WREG32_SOC15(VCN, i, mmUVD_GFX10_ADDR_CONFIG, 1178 adev->gfx.config.gb_addr_config); 1179 1180 /* unblock VCPU register access */ 1181 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0, 1182 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1183 1184 /* release VCPU reset to boot */ 1185 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1186 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1187 1188 for (j = 0; j < 10; ++j) { 1189 uint32_t status; 1190 1191 for (k = 0; k < 100; ++k) { 1192 status = RREG32_SOC15(VCN, i, mmUVD_STATUS); 1193 if (status & 2) 1194 break; 1195 mdelay(10); 1196 } 1197 r = 0; 1198 if (status & 2) 1199 break; 1200 1201 DRM_ERROR("VCN[%d] decode not responding, trying to reset the VCPU!!!\n", i); 1202 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1203 UVD_VCPU_CNTL__BLK_RST_MASK, 1204 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1205 mdelay(10); 1206 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1207 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1208 1209 mdelay(10); 1210 r = -1; 1211 } 1212 1213 if (r) { 1214 DRM_ERROR("VCN[%d] decode not responding, giving up!!!\n", i); 1215 return r; 1216 } 1217 1218 /* enable master interrupt */ 1219 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 1220 UVD_MASTINT_EN__VCPU_EN_MASK, 1221 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1222 1223 /* clear the busy bit of VCN_STATUS */ 1224 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0, 1225 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1226 1227 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0); 1228 1229 ring = &adev->vcn.inst[i].ring_dec; 1230 /* force RBC into idle state */ 1231 rb_bufsz = order_base_2(ring->ring_size); 1232 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1233 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1234 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1235 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1236 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1237 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp); 1238 1239 fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr; 1240 fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1241 1242 /* programm the RB_BASE for ring buffer */ 1243 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1244 lower_32_bits(ring->gpu_addr)); 1245 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1246 upper_32_bits(ring->gpu_addr)); 1247 1248 /* Initialize the ring buffer's read and write pointers */ 1249 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0); 1250 1251 WREG32_SOC15(VCN, i, mmUVD_SCRATCH2, 0); 1252 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR); 1253 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR, 1254 lower_32_bits(ring->wptr)); 1255 fw_shared->rb.wptr = lower_32_bits(ring->wptr); 1256 fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1257 1258 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1259 ring = &adev->vcn.inst[i].ring_enc[0]; 1260 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1261 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1262 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr); 1263 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1264 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4); 1265 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1266 1267 fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1268 ring = &adev->vcn.inst[i].ring_enc[1]; 1269 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1270 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1271 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1272 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1273 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4); 1274 fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1275 } 1276 1277 return 0; 1278 } 1279 1280 static int vcn_v3_0_start_sriov(struct amdgpu_device *adev) 1281 { 1282 int i, j; 1283 struct amdgpu_ring *ring; 1284 uint64_t cache_addr; 1285 uint64_t rb_addr; 1286 uint64_t ctx_addr; 1287 uint32_t param, resp, expected; 1288 uint32_t offset, cache_size; 1289 uint32_t tmp, timeout; 1290 uint32_t id; 1291 1292 struct amdgpu_mm_table *table = &adev->virt.mm_table; 1293 uint32_t *table_loc; 1294 uint32_t table_size; 1295 uint32_t size, size_dw; 1296 1297 bool is_vcn_ready; 1298 1299 struct mmsch_v3_0_cmd_direct_write 1300 direct_wt = { {0} }; 1301 struct mmsch_v3_0_cmd_direct_read_modify_write 1302 direct_rd_mod_wt = { {0} }; 1303 struct mmsch_v3_0_cmd_end end = { {0} }; 1304 struct mmsch_v3_0_init_header header; 1305 1306 direct_wt.cmd_header.command_type = 1307 MMSCH_COMMAND__DIRECT_REG_WRITE; 1308 direct_rd_mod_wt.cmd_header.command_type = 1309 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1310 end.cmd_header.command_type = 1311 MMSCH_COMMAND__END; 1312 1313 header.version = MMSCH_VERSION; 1314 header.total_size = sizeof(struct mmsch_v3_0_init_header) >> 2; 1315 for (i = 0; i < AMDGPU_MAX_VCN_INSTANCES; i++) { 1316 header.inst[i].init_status = 0; 1317 header.inst[i].table_offset = 0; 1318 header.inst[i].table_size = 0; 1319 } 1320 1321 table_loc = (uint32_t *)table->cpu_addr; 1322 table_loc += header.total_size; 1323 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1324 if (adev->vcn.harvest_config & (1 << i)) 1325 continue; 1326 1327 table_size = 0; 1328 1329 MMSCH_V3_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i, 1330 mmUVD_STATUS), 1331 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 1332 1333 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 1334 1335 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1336 id = amdgpu_ucode_id_vcns[i]; 1337 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1338 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1339 adev->firmware.ucode[id].tmr_mc_addr_lo); 1340 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1341 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1342 adev->firmware.ucode[id].tmr_mc_addr_hi); 1343 offset = 0; 1344 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1345 mmUVD_VCPU_CACHE_OFFSET0), 1346 0); 1347 } else { 1348 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1349 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1350 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 1351 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1352 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1353 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 1354 offset = cache_size; 1355 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1356 mmUVD_VCPU_CACHE_OFFSET0), 1357 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 1358 } 1359 1360 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1361 mmUVD_VCPU_CACHE_SIZE0), 1362 cache_size); 1363 1364 cache_addr = adev->vcn.inst[i].gpu_addr + offset; 1365 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1366 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 1367 lower_32_bits(cache_addr)); 1368 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1369 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 1370 upper_32_bits(cache_addr)); 1371 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1372 mmUVD_VCPU_CACHE_OFFSET1), 1373 0); 1374 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1375 mmUVD_VCPU_CACHE_SIZE1), 1376 AMDGPU_VCN_STACK_SIZE); 1377 1378 cache_addr = adev->vcn.inst[i].gpu_addr + offset + 1379 AMDGPU_VCN_STACK_SIZE; 1380 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1381 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 1382 lower_32_bits(cache_addr)); 1383 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1384 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 1385 upper_32_bits(cache_addr)); 1386 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1387 mmUVD_VCPU_CACHE_OFFSET2), 1388 0); 1389 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1390 mmUVD_VCPU_CACHE_SIZE2), 1391 AMDGPU_VCN_CONTEXT_SIZE); 1392 1393 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 1394 ring = &adev->vcn.inst[i].ring_enc[j]; 1395 ring->wptr = 0; 1396 rb_addr = ring->gpu_addr; 1397 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1398 mmUVD_RB_BASE_LO), 1399 lower_32_bits(rb_addr)); 1400 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1401 mmUVD_RB_BASE_HI), 1402 upper_32_bits(rb_addr)); 1403 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1404 mmUVD_RB_SIZE), 1405 ring->ring_size / 4); 1406 } 1407 1408 ring = &adev->vcn.inst[i].ring_dec; 1409 ring->wptr = 0; 1410 rb_addr = ring->gpu_addr; 1411 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1412 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW), 1413 lower_32_bits(rb_addr)); 1414 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1415 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH), 1416 upper_32_bits(rb_addr)); 1417 /* force RBC into idle state */ 1418 tmp = order_base_2(ring->ring_size); 1419 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp); 1420 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1421 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1422 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1423 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1424 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1425 mmUVD_RBC_RB_CNTL), 1426 tmp); 1427 1428 /* add end packet */ 1429 MMSCH_V3_0_INSERT_END(); 1430 1431 /* refine header */ 1432 header.inst[i].init_status = 0; 1433 header.inst[i].table_offset = header.total_size; 1434 header.inst[i].table_size = table_size; 1435 header.total_size += table_size; 1436 } 1437 1438 /* Update init table header in memory */ 1439 size = sizeof(struct mmsch_v3_0_init_header); 1440 table_loc = (uint32_t *)table->cpu_addr; 1441 memcpy((void *)table_loc, &header, size); 1442 1443 /* message MMSCH (in VCN[0]) to initialize this client 1444 * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr 1445 * of memory descriptor location 1446 */ 1447 ctx_addr = table->gpu_addr; 1448 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 1449 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 1450 1451 /* 2, update vmid of descriptor */ 1452 tmp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID); 1453 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1454 /* use domain0 for MM scheduler */ 1455 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1456 WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, tmp); 1457 1458 /* 3, notify mmsch about the size of this descriptor */ 1459 size = header.total_size; 1460 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size); 1461 1462 /* 4, set resp to zero */ 1463 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0); 1464 1465 /* 5, kick off the initialization and wait until 1466 * MMSCH_VF_MAILBOX_RESP becomes non-zero 1467 */ 1468 param = 0x10000001; 1469 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, param); 1470 tmp = 0; 1471 timeout = 1000; 1472 resp = 0; 1473 expected = param + 1; 1474 while (resp != expected) { 1475 resp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); 1476 if (resp == expected) 1477 break; 1478 1479 udelay(10); 1480 tmp = tmp + 10; 1481 if (tmp >= timeout) { 1482 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 1483 " waiting for mmMMSCH_VF_MAILBOX_RESP "\ 1484 "(expected=0x%08x, readback=0x%08x)\n", 1485 tmp, expected, resp); 1486 return -EBUSY; 1487 } 1488 } 1489 1490 /* 6, check each VCN's init_status 1491 * if it remains as 0, then this VCN is not assigned to current VF 1492 * do not start ring for this VCN 1493 */ 1494 size = sizeof(struct mmsch_v3_0_init_header); 1495 table_loc = (uint32_t *)table->cpu_addr; 1496 memcpy(&header, (void *)table_loc, size); 1497 1498 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1499 if (adev->vcn.harvest_config & (1 << i)) 1500 continue; 1501 1502 is_vcn_ready = (header.inst[i].init_status == 1); 1503 if (!is_vcn_ready) 1504 DRM_INFO("VCN(%d) engine is disabled by hypervisor\n", i); 1505 1506 ring = &adev->vcn.inst[i].ring_dec; 1507 ring->sched.ready = is_vcn_ready; 1508 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 1509 ring = &adev->vcn.inst[i].ring_enc[j]; 1510 ring->sched.ready = is_vcn_ready; 1511 } 1512 } 1513 1514 return 0; 1515 } 1516 1517 static int vcn_v3_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) 1518 { 1519 uint32_t tmp; 1520 1521 /* Wait for power status to be 1 */ 1522 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1523 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1524 1525 /* wait for read ptr to be equal to write ptr */ 1526 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR); 1527 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1528 1529 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2); 1530 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); 1531 1532 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1533 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); 1534 1535 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1536 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1537 1538 /* disable dynamic power gating mode */ 1539 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0, 1540 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1541 1542 return 0; 1543 } 1544 1545 static int vcn_v3_0_stop(struct amdgpu_device *adev) 1546 { 1547 uint32_t tmp; 1548 int i, r = 0; 1549 1550 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1551 if (adev->vcn.harvest_config & (1 << i)) 1552 continue; 1553 1554 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1555 r = vcn_v3_0_stop_dpg_mode(adev, i); 1556 continue; 1557 } 1558 1559 /* wait for vcn idle */ 1560 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1561 if (r) 1562 return r; 1563 1564 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1565 UVD_LMI_STATUS__READ_CLEAN_MASK | 1566 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1567 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1568 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1569 if (r) 1570 return r; 1571 1572 /* disable LMI UMC channel */ 1573 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2); 1574 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1575 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp); 1576 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK| 1577 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1578 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1579 if (r) 1580 return r; 1581 1582 /* block VCPU register access */ 1583 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 1584 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1585 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1586 1587 /* reset VCPU */ 1588 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1589 UVD_VCPU_CNTL__BLK_RST_MASK, 1590 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1591 1592 /* disable VCPU clock */ 1593 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1594 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1595 1596 /* apply soft reset */ 1597 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1598 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1599 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1600 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1601 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1602 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1603 1604 /* clear status */ 1605 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0); 1606 1607 /* apply HW clock gating */ 1608 vcn_v3_0_enable_clock_gating(adev, i); 1609 1610 /* enable VCN power gating */ 1611 vcn_v3_0_enable_static_power_gating(adev, i); 1612 } 1613 1614 if (adev->pm.dpm_enabled) 1615 amdgpu_dpm_enable_uvd(adev, false); 1616 1617 return 0; 1618 } 1619 1620 static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev, 1621 int inst_idx, struct dpg_pause_state *new_state) 1622 { 1623 volatile struct amdgpu_fw_shared *fw_shared; 1624 struct amdgpu_ring *ring; 1625 uint32_t reg_data = 0; 1626 int ret_code; 1627 1628 /* pause/unpause if state is changed */ 1629 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1630 DRM_DEBUG("dpg pause state changed %d -> %d", 1631 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1632 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) & 1633 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1634 1635 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1636 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, 1637 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1638 1639 if (!ret_code) { 1640 /* pause DPG */ 1641 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1642 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1643 1644 /* wait for ACK */ 1645 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE, 1646 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1647 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1648 1649 /* Stall DPG before WPTR/RPTR reset */ 1650 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1651 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1652 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1653 1654 /* Restore */ 1655 fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr; 1656 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1657 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 1658 ring->wptr = 0; 1659 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr); 1660 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1661 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4); 1662 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1663 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1664 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1665 1666 fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1667 ring = &adev->vcn.inst[inst_idx].ring_enc[1]; 1668 ring->wptr = 0; 1669 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1670 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1671 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4); 1672 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1673 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1674 fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1675 1676 /* restore wptr/rptr with pointers saved in FW shared memory*/ 1677 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, fw_shared->rb.rptr); 1678 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, fw_shared->rb.wptr); 1679 1680 /* Unstall DPG */ 1681 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1682 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1683 1684 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1685 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1686 } 1687 } else { 1688 /* unpause dpg, no need to wait */ 1689 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1690 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1691 } 1692 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1693 } 1694 1695 return 0; 1696 } 1697 1698 /** 1699 * vcn_v3_0_dec_ring_get_rptr - get read pointer 1700 * 1701 * @ring: amdgpu_ring pointer 1702 * 1703 * Returns the current hardware read pointer 1704 */ 1705 static uint64_t vcn_v3_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 1706 { 1707 struct amdgpu_device *adev = ring->adev; 1708 1709 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR); 1710 } 1711 1712 /** 1713 * vcn_v3_0_dec_ring_get_wptr - get write pointer 1714 * 1715 * @ring: amdgpu_ring pointer 1716 * 1717 * Returns the current hardware write pointer 1718 */ 1719 static uint64_t vcn_v3_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 1720 { 1721 struct amdgpu_device *adev = ring->adev; 1722 1723 if (ring->use_doorbell) 1724 return adev->wb.wb[ring->wptr_offs]; 1725 else 1726 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR); 1727 } 1728 1729 /** 1730 * vcn_v3_0_dec_ring_set_wptr - set write pointer 1731 * 1732 * @ring: amdgpu_ring pointer 1733 * 1734 * Commits the write pointer to the hardware 1735 */ 1736 static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 1737 { 1738 struct amdgpu_device *adev = ring->adev; 1739 volatile struct amdgpu_fw_shared *fw_shared; 1740 1741 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1742 /*whenever update RBC_RB_WPTR, we save the wptr in shared rb.wptr and scratch2 */ 1743 fw_shared = adev->vcn.inst[ring->me].fw_shared_cpu_addr; 1744 fw_shared->rb.wptr = lower_32_bits(ring->wptr); 1745 WREG32_SOC15(VCN, ring->me, mmUVD_SCRATCH2, 1746 lower_32_bits(ring->wptr)); 1747 } 1748 1749 if (ring->use_doorbell) { 1750 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 1751 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1752 } else { 1753 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1754 } 1755 } 1756 1757 static void vcn_v3_0_dec_sw_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1758 u64 seq, uint32_t flags) 1759 { 1760 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1761 1762 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_FENCE); 1763 amdgpu_ring_write(ring, addr); 1764 amdgpu_ring_write(ring, upper_32_bits(addr)); 1765 amdgpu_ring_write(ring, seq); 1766 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_TRAP); 1767 } 1768 1769 static void vcn_v3_0_dec_sw_ring_insert_end(struct amdgpu_ring *ring) 1770 { 1771 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END); 1772 } 1773 1774 static void vcn_v3_0_dec_sw_ring_emit_ib(struct amdgpu_ring *ring, 1775 struct amdgpu_job *job, 1776 struct amdgpu_ib *ib, 1777 uint32_t flags) 1778 { 1779 uint32_t vmid = AMDGPU_JOB_GET_VMID(job); 1780 1781 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_IB); 1782 amdgpu_ring_write(ring, vmid); 1783 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1784 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1785 amdgpu_ring_write(ring, ib->length_dw); 1786 } 1787 1788 static void vcn_v3_0_dec_sw_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1789 uint32_t val, uint32_t mask) 1790 { 1791 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WAIT); 1792 amdgpu_ring_write(ring, reg << 2); 1793 amdgpu_ring_write(ring, mask); 1794 amdgpu_ring_write(ring, val); 1795 } 1796 1797 static void vcn_v3_0_dec_sw_ring_emit_vm_flush(struct amdgpu_ring *ring, 1798 uint32_t vmid, uint64_t pd_addr) 1799 { 1800 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1801 uint32_t data0, data1, mask; 1802 1803 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1804 1805 /* wait for register write */ 1806 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance; 1807 data1 = lower_32_bits(pd_addr); 1808 mask = 0xffffffff; 1809 vcn_v3_0_dec_sw_ring_emit_reg_wait(ring, data0, data1, mask); 1810 } 1811 1812 static void vcn_v3_0_dec_sw_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) 1813 { 1814 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WRITE); 1815 amdgpu_ring_write(ring, reg << 2); 1816 amdgpu_ring_write(ring, val); 1817 } 1818 1819 static const struct amdgpu_ring_funcs vcn_v3_0_dec_sw_ring_vm_funcs = { 1820 .type = AMDGPU_RING_TYPE_VCN_DEC, 1821 .align_mask = 0x3f, 1822 .nop = VCN_DEC_SW_CMD_NO_OP, 1823 .vmhub = AMDGPU_MMHUB_0, 1824 .get_rptr = vcn_v3_0_dec_ring_get_rptr, 1825 .get_wptr = vcn_v3_0_dec_ring_get_wptr, 1826 .set_wptr = vcn_v3_0_dec_ring_set_wptr, 1827 .emit_frame_size = 1828 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1829 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1830 4 + /* vcn_v3_0_dec_sw_ring_emit_vm_flush */ 1831 5 + 5 + /* vcn_v3_0_dec_sw_ring_emit_fdec_swe x2 vm fdec_swe */ 1832 1, /* vcn_v3_0_dec_sw_ring_insert_end */ 1833 .emit_ib_size = 5, /* vcn_v3_0_dec_sw_ring_emit_ib */ 1834 .emit_ib = vcn_v3_0_dec_sw_ring_emit_ib, 1835 .emit_fence = vcn_v3_0_dec_sw_ring_emit_fence, 1836 .emit_vm_flush = vcn_v3_0_dec_sw_ring_emit_vm_flush, 1837 .test_ring = amdgpu_vcn_dec_sw_ring_test_ring, 1838 .test_ib = NULL,//amdgpu_vcn_dec_sw_ring_test_ib, 1839 .insert_nop = amdgpu_ring_insert_nop, 1840 .insert_end = vcn_v3_0_dec_sw_ring_insert_end, 1841 .pad_ib = amdgpu_ring_generic_pad_ib, 1842 .begin_use = amdgpu_vcn_ring_begin_use, 1843 .end_use = amdgpu_vcn_ring_end_use, 1844 .emit_wreg = vcn_v3_0_dec_sw_ring_emit_wreg, 1845 .emit_reg_wait = vcn_v3_0_dec_sw_ring_emit_reg_wait, 1846 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1847 }; 1848 1849 static int vcn_v3_0_limit_sched(struct amdgpu_cs_parser *p) 1850 { 1851 struct drm_gpu_scheduler **scheds; 1852 1853 /* The create msg must be in the first IB submitted */ 1854 if (atomic_read(&p->entity->fence_seq)) 1855 return -EINVAL; 1856 1857 scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_DEC] 1858 [AMDGPU_RING_PRIO_DEFAULT].sched; 1859 drm_sched_entity_modify_sched(p->entity, scheds, 1); 1860 return 0; 1861 } 1862 1863 static int vcn_v3_0_dec_msg(struct amdgpu_cs_parser *p, uint64_t addr) 1864 { 1865 struct ttm_operation_ctx ctx = { false, false }; 1866 struct amdgpu_bo_va_mapping *map; 1867 uint32_t *msg, num_buffers; 1868 struct amdgpu_bo *bo; 1869 uint64_t start, end; 1870 unsigned int i; 1871 void * ptr; 1872 int r; 1873 1874 addr &= AMDGPU_GMC_HOLE_MASK; 1875 r = amdgpu_cs_find_mapping(p, addr, &bo, &map); 1876 if (r) { 1877 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 1878 return r; 1879 } 1880 1881 start = map->start * AMDGPU_GPU_PAGE_SIZE; 1882 end = (map->last + 1) * AMDGPU_GPU_PAGE_SIZE; 1883 if (addr & 0x7) { 1884 DRM_ERROR("VCN messages must be 8 byte aligned!\n"); 1885 return -EINVAL; 1886 } 1887 1888 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1889 amdgpu_bo_placement_from_domain(bo, bo->allowed_domains); 1890 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 1891 if (r) { 1892 DRM_ERROR("Failed validating the VCN message BO (%d)!\n", r); 1893 return r; 1894 } 1895 1896 r = amdgpu_bo_kmap(bo, &ptr); 1897 if (r) { 1898 DRM_ERROR("Failed mapping the VCN message (%d)!\n", r); 1899 return r; 1900 } 1901 1902 msg = ptr + addr - start; 1903 1904 /* Check length */ 1905 if (msg[1] > end - addr) { 1906 r = -EINVAL; 1907 goto out; 1908 } 1909 1910 if (msg[3] != RDECODE_MSG_CREATE) 1911 goto out; 1912 1913 num_buffers = msg[2]; 1914 for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) { 1915 uint32_t offset, size, *create; 1916 1917 if (msg[0] != RDECODE_MESSAGE_CREATE) 1918 continue; 1919 1920 offset = msg[1]; 1921 size = msg[2]; 1922 1923 if (offset + size > end) { 1924 r = -EINVAL; 1925 goto out; 1926 } 1927 1928 create = ptr + addr + offset - start; 1929 1930 /* H246, HEVC and VP9 can run on any instance */ 1931 if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11) 1932 continue; 1933 1934 r = vcn_v3_0_limit_sched(p); 1935 if (r) 1936 goto out; 1937 } 1938 1939 out: 1940 amdgpu_bo_kunmap(bo); 1941 return r; 1942 } 1943 1944 static int vcn_v3_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, 1945 uint32_t ib_idx) 1946 { 1947 struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched); 1948 struct amdgpu_ib *ib = &p->job->ibs[ib_idx]; 1949 uint32_t msg_lo = 0, msg_hi = 0; 1950 unsigned i; 1951 int r; 1952 1953 /* The first instance can decode anything */ 1954 if (!ring->me) 1955 return 0; 1956 1957 for (i = 0; i < ib->length_dw; i += 2) { 1958 uint32_t reg = amdgpu_get_ib_value(p, ib_idx, i); 1959 uint32_t val = amdgpu_get_ib_value(p, ib_idx, i + 1); 1960 1961 if (reg == PACKET0(p->adev->vcn.internal.data0, 0)) { 1962 msg_lo = val; 1963 } else if (reg == PACKET0(p->adev->vcn.internal.data1, 0)) { 1964 msg_hi = val; 1965 } else if (reg == PACKET0(p->adev->vcn.internal.cmd, 0) && 1966 val == 0) { 1967 r = vcn_v3_0_dec_msg(p, ((u64)msg_hi) << 32 | msg_lo); 1968 if (r) 1969 return r; 1970 } 1971 } 1972 return 0; 1973 } 1974 1975 static const struct amdgpu_ring_funcs vcn_v3_0_dec_ring_vm_funcs = { 1976 .type = AMDGPU_RING_TYPE_VCN_DEC, 1977 .align_mask = 0xf, 1978 .vmhub = AMDGPU_MMHUB_0, 1979 .get_rptr = vcn_v3_0_dec_ring_get_rptr, 1980 .get_wptr = vcn_v3_0_dec_ring_get_wptr, 1981 .set_wptr = vcn_v3_0_dec_ring_set_wptr, 1982 .patch_cs_in_place = vcn_v3_0_ring_patch_cs_in_place, 1983 .emit_frame_size = 1984 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1985 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1986 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */ 1987 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */ 1988 6, 1989 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */ 1990 .emit_ib = vcn_v2_0_dec_ring_emit_ib, 1991 .emit_fence = vcn_v2_0_dec_ring_emit_fence, 1992 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush, 1993 .test_ring = vcn_v2_0_dec_ring_test_ring, 1994 .test_ib = amdgpu_vcn_dec_ring_test_ib, 1995 .insert_nop = vcn_v2_0_dec_ring_insert_nop, 1996 .insert_start = vcn_v2_0_dec_ring_insert_start, 1997 .insert_end = vcn_v2_0_dec_ring_insert_end, 1998 .pad_ib = amdgpu_ring_generic_pad_ib, 1999 .begin_use = amdgpu_vcn_ring_begin_use, 2000 .end_use = amdgpu_vcn_ring_end_use, 2001 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg, 2002 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait, 2003 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2004 }; 2005 2006 /** 2007 * vcn_v3_0_enc_ring_get_rptr - get enc read pointer 2008 * 2009 * @ring: amdgpu_ring pointer 2010 * 2011 * Returns the current hardware enc read pointer 2012 */ 2013 static uint64_t vcn_v3_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 2014 { 2015 struct amdgpu_device *adev = ring->adev; 2016 2017 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) 2018 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR); 2019 else 2020 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2); 2021 } 2022 2023 /** 2024 * vcn_v3_0_enc_ring_get_wptr - get enc write pointer 2025 * 2026 * @ring: amdgpu_ring pointer 2027 * 2028 * Returns the current hardware enc write pointer 2029 */ 2030 static uint64_t vcn_v3_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 2031 { 2032 struct amdgpu_device *adev = ring->adev; 2033 2034 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 2035 if (ring->use_doorbell) 2036 return adev->wb.wb[ring->wptr_offs]; 2037 else 2038 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR); 2039 } else { 2040 if (ring->use_doorbell) 2041 return adev->wb.wb[ring->wptr_offs]; 2042 else 2043 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2); 2044 } 2045 } 2046 2047 /** 2048 * vcn_v3_0_enc_ring_set_wptr - set enc write pointer 2049 * 2050 * @ring: amdgpu_ring pointer 2051 * 2052 * Commits the enc write pointer to the hardware 2053 */ 2054 static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 2055 { 2056 struct amdgpu_device *adev = ring->adev; 2057 2058 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 2059 if (ring->use_doorbell) { 2060 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 2061 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 2062 } else { 2063 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 2064 } 2065 } else { 2066 if (ring->use_doorbell) { 2067 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 2068 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 2069 } else { 2070 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 2071 } 2072 } 2073 } 2074 2075 static const struct amdgpu_ring_funcs vcn_v3_0_enc_ring_vm_funcs = { 2076 .type = AMDGPU_RING_TYPE_VCN_ENC, 2077 .align_mask = 0x3f, 2078 .nop = VCN_ENC_CMD_NO_OP, 2079 .vmhub = AMDGPU_MMHUB_0, 2080 .get_rptr = vcn_v3_0_enc_ring_get_rptr, 2081 .get_wptr = vcn_v3_0_enc_ring_get_wptr, 2082 .set_wptr = vcn_v3_0_enc_ring_set_wptr, 2083 .emit_frame_size = 2084 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2085 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 2086 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 2087 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 2088 1, /* vcn_v2_0_enc_ring_insert_end */ 2089 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 2090 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 2091 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 2092 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 2093 .test_ring = amdgpu_vcn_enc_ring_test_ring, 2094 .test_ib = amdgpu_vcn_enc_ring_test_ib, 2095 .insert_nop = amdgpu_ring_insert_nop, 2096 .insert_end = vcn_v2_0_enc_ring_insert_end, 2097 .pad_ib = amdgpu_ring_generic_pad_ib, 2098 .begin_use = amdgpu_vcn_ring_begin_use, 2099 .end_use = amdgpu_vcn_ring_end_use, 2100 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 2101 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 2102 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2103 }; 2104 2105 static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev) 2106 { 2107 int i; 2108 2109 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2110 if (adev->vcn.harvest_config & (1 << i)) 2111 continue; 2112 2113 if (!DEC_SW_RING_ENABLED) 2114 adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_ring_vm_funcs; 2115 else 2116 adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_sw_ring_vm_funcs; 2117 adev->vcn.inst[i].ring_dec.me = i; 2118 DRM_INFO("VCN(%d) decode%s is enabled in VM mode\n", i, 2119 DEC_SW_RING_ENABLED?"(Software Ring)":""); 2120 } 2121 } 2122 2123 static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev) 2124 { 2125 int i, j; 2126 2127 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2128 if (adev->vcn.harvest_config & (1 << i)) 2129 continue; 2130 2131 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 2132 adev->vcn.inst[i].ring_enc[j].funcs = &vcn_v3_0_enc_ring_vm_funcs; 2133 adev->vcn.inst[i].ring_enc[j].me = i; 2134 } 2135 DRM_INFO("VCN(%d) encode is enabled in VM mode\n", i); 2136 } 2137 } 2138 2139 static bool vcn_v3_0_is_idle(void *handle) 2140 { 2141 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2142 int i, ret = 1; 2143 2144 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2145 if (adev->vcn.harvest_config & (1 << i)) 2146 continue; 2147 2148 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); 2149 } 2150 2151 return ret; 2152 } 2153 2154 static int vcn_v3_0_wait_for_idle(void *handle) 2155 { 2156 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2157 int i, ret = 0; 2158 2159 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2160 if (adev->vcn.harvest_config & (1 << i)) 2161 continue; 2162 2163 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 2164 UVD_STATUS__IDLE); 2165 if (ret) 2166 return ret; 2167 } 2168 2169 return ret; 2170 } 2171 2172 static int vcn_v3_0_set_clockgating_state(void *handle, 2173 enum amd_clockgating_state state) 2174 { 2175 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2176 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 2177 int i; 2178 2179 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2180 if (adev->vcn.harvest_config & (1 << i)) 2181 continue; 2182 2183 if (enable) { 2184 if (RREG32_SOC15(VCN, i, mmUVD_STATUS) != UVD_STATUS__IDLE) 2185 return -EBUSY; 2186 vcn_v3_0_enable_clock_gating(adev, i); 2187 } else { 2188 vcn_v3_0_disable_clock_gating(adev, i); 2189 } 2190 } 2191 2192 return 0; 2193 } 2194 2195 static int vcn_v3_0_set_powergating_state(void *handle, 2196 enum amd_powergating_state state) 2197 { 2198 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2199 int ret; 2200 2201 /* for SRIOV, guest should not control VCN Power-gating 2202 * MMSCH FW should control Power-gating and clock-gating 2203 * guest should avoid touching CGC and PG 2204 */ 2205 if (amdgpu_sriov_vf(adev)) { 2206 adev->vcn.cur_state = AMD_PG_STATE_UNGATE; 2207 return 0; 2208 } 2209 2210 if(state == adev->vcn.cur_state) 2211 return 0; 2212 2213 if (state == AMD_PG_STATE_GATE) 2214 ret = vcn_v3_0_stop(adev); 2215 else 2216 ret = vcn_v3_0_start(adev); 2217 2218 if(!ret) 2219 adev->vcn.cur_state = state; 2220 2221 return ret; 2222 } 2223 2224 static int vcn_v3_0_set_interrupt_state(struct amdgpu_device *adev, 2225 struct amdgpu_irq_src *source, 2226 unsigned type, 2227 enum amdgpu_interrupt_state state) 2228 { 2229 return 0; 2230 } 2231 2232 static int vcn_v3_0_process_interrupt(struct amdgpu_device *adev, 2233 struct amdgpu_irq_src *source, 2234 struct amdgpu_iv_entry *entry) 2235 { 2236 uint32_t ip_instance; 2237 2238 switch (entry->client_id) { 2239 case SOC15_IH_CLIENTID_VCN: 2240 ip_instance = 0; 2241 break; 2242 case SOC15_IH_CLIENTID_VCN1: 2243 ip_instance = 1; 2244 break; 2245 default: 2246 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 2247 return 0; 2248 } 2249 2250 DRM_DEBUG("IH: VCN TRAP\n"); 2251 2252 switch (entry->src_id) { 2253 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT: 2254 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec); 2255 break; 2256 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 2257 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 2258 break; 2259 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY: 2260 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]); 2261 break; 2262 default: 2263 DRM_ERROR("Unhandled interrupt: %d %d\n", 2264 entry->src_id, entry->src_data[0]); 2265 break; 2266 } 2267 2268 return 0; 2269 } 2270 2271 static const struct amdgpu_irq_src_funcs vcn_v3_0_irq_funcs = { 2272 .set = vcn_v3_0_set_interrupt_state, 2273 .process = vcn_v3_0_process_interrupt, 2274 }; 2275 2276 static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev) 2277 { 2278 int i; 2279 2280 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2281 if (adev->vcn.harvest_config & (1 << i)) 2282 continue; 2283 2284 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1; 2285 adev->vcn.inst[i].irq.funcs = &vcn_v3_0_irq_funcs; 2286 } 2287 } 2288 2289 static const struct amd_ip_funcs vcn_v3_0_ip_funcs = { 2290 .name = "vcn_v3_0", 2291 .early_init = vcn_v3_0_early_init, 2292 .late_init = NULL, 2293 .sw_init = vcn_v3_0_sw_init, 2294 .sw_fini = vcn_v3_0_sw_fini, 2295 .hw_init = vcn_v3_0_hw_init, 2296 .hw_fini = vcn_v3_0_hw_fini, 2297 .suspend = vcn_v3_0_suspend, 2298 .resume = vcn_v3_0_resume, 2299 .is_idle = vcn_v3_0_is_idle, 2300 .wait_for_idle = vcn_v3_0_wait_for_idle, 2301 .check_soft_reset = NULL, 2302 .pre_soft_reset = NULL, 2303 .soft_reset = NULL, 2304 .post_soft_reset = NULL, 2305 .set_clockgating_state = vcn_v3_0_set_clockgating_state, 2306 .set_powergating_state = vcn_v3_0_set_powergating_state, 2307 }; 2308 2309 const struct amdgpu_ip_block_version vcn_v3_0_ip_block = 2310 { 2311 .type = AMD_IP_BLOCK_TYPE_VCN, 2312 .major = 3, 2313 .minor = 0, 2314 .rev = 0, 2315 .funcs = &vcn_v3_0_ip_funcs, 2316 }; 2317