1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_vcn.h" 27 #include "amdgpu_pm.h" 28 #include "soc15.h" 29 #include "soc15d.h" 30 #include "vcn_v2_0.h" 31 #include "mmsch_v3_0.h" 32 33 #include "vcn/vcn_3_0_0_offset.h" 34 #include "vcn/vcn_3_0_0_sh_mask.h" 35 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 36 37 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x27 38 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x0f 39 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x10 40 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x11 41 #define mmUVD_NO_OP_INTERNAL_OFFSET 0x29 42 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x66 43 #define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d 44 45 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x431 46 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x3b4 47 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x3b5 48 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x25c 49 50 #define VCN_INSTANCES_SIENNA_CICHLID 2 51 #define DEC_SW_RING_ENABLED FALSE 52 53 #define RDECODE_MSG_CREATE 0x00000000 54 #define RDECODE_MESSAGE_CREATE 0x00000001 55 56 static int amdgpu_ih_clientid_vcns[] = { 57 SOC15_IH_CLIENTID_VCN, 58 SOC15_IH_CLIENTID_VCN1 59 }; 60 61 static int amdgpu_ucode_id_vcns[] = { 62 AMDGPU_UCODE_ID_VCN, 63 AMDGPU_UCODE_ID_VCN1 64 }; 65 66 static int vcn_v3_0_start_sriov(struct amdgpu_device *adev); 67 static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev); 68 static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev); 69 static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev); 70 static int vcn_v3_0_set_powergating_state(void *handle, 71 enum amd_powergating_state state); 72 static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev, 73 int inst_idx, struct dpg_pause_state *new_state); 74 75 static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring); 76 static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring); 77 78 /** 79 * vcn_v3_0_early_init - set function pointers 80 * 81 * @handle: amdgpu_device pointer 82 * 83 * Set ring and irq function pointers 84 */ 85 static int vcn_v3_0_early_init(void *handle) 86 { 87 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 88 89 if (amdgpu_sriov_vf(adev)) { 90 adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID; 91 adev->vcn.harvest_config = 0; 92 adev->vcn.num_enc_rings = 1; 93 94 } else { 95 if (adev->asic_type == CHIP_SIENNA_CICHLID) { 96 u32 harvest; 97 int i; 98 99 adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID; 100 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 101 harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING); 102 if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK) 103 adev->vcn.harvest_config |= 1 << i; 104 } 105 106 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 | 107 AMDGPU_VCN_HARVEST_VCN1)) 108 /* both instances are harvested, disable the block */ 109 return -ENOENT; 110 } else 111 adev->vcn.num_vcn_inst = 1; 112 113 adev->vcn.num_enc_rings = 2; 114 } 115 116 vcn_v3_0_set_dec_ring_funcs(adev); 117 vcn_v3_0_set_enc_ring_funcs(adev); 118 vcn_v3_0_set_irq_funcs(adev); 119 120 return 0; 121 } 122 123 /** 124 * vcn_v3_0_sw_init - sw init for VCN block 125 * 126 * @handle: amdgpu_device pointer 127 * 128 * Load firmware and sw initialization 129 */ 130 static int vcn_v3_0_sw_init(void *handle) 131 { 132 struct amdgpu_ring *ring; 133 int i, j, r; 134 int vcn_doorbell_index = 0; 135 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 136 137 r = amdgpu_vcn_sw_init(adev); 138 if (r) 139 return r; 140 141 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 142 const struct common_firmware_header *hdr; 143 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 144 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN; 145 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw; 146 adev->firmware.fw_size += 147 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 148 149 if (adev->vcn.num_vcn_inst == VCN_INSTANCES_SIENNA_CICHLID) { 150 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].ucode_id = AMDGPU_UCODE_ID_VCN1; 151 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].fw = adev->vcn.fw; 152 adev->firmware.fw_size += 153 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 154 } 155 DRM_INFO("PSP loading VCN firmware\n"); 156 } 157 158 r = amdgpu_vcn_resume(adev); 159 if (r) 160 return r; 161 162 /* 163 * Note: doorbell assignment is fixed for SRIOV multiple VCN engines 164 * Formula: 165 * vcn_db_base = adev->doorbell_index.vcn.vcn_ring0_1 << 1; 166 * dec_ring_i = vcn_db_base + i * (adev->vcn.num_enc_rings + 1) 167 * enc_ring_i,j = vcn_db_base + i * (adev->vcn.num_enc_rings + 1) + 1 + j 168 */ 169 if (amdgpu_sriov_vf(adev)) { 170 vcn_doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1; 171 /* get DWORD offset */ 172 vcn_doorbell_index = vcn_doorbell_index << 1; 173 } 174 175 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 176 volatile struct amdgpu_fw_shared *fw_shared; 177 178 if (adev->vcn.harvest_config & (1 << i)) 179 continue; 180 181 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; 182 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; 183 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; 184 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; 185 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; 186 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; 187 188 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; 189 adev->vcn.inst[i].external.scratch9 = SOC15_REG_OFFSET(VCN, i, mmUVD_SCRATCH9); 190 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; 191 adev->vcn.inst[i].external.data0 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA0); 192 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; 193 adev->vcn.inst[i].external.data1 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA1); 194 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; 195 adev->vcn.inst[i].external.cmd = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_CMD); 196 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; 197 adev->vcn.inst[i].external.nop = SOC15_REG_OFFSET(VCN, i, mmUVD_NO_OP); 198 199 /* VCN DEC TRAP */ 200 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 201 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[i].irq); 202 if (r) 203 return r; 204 205 atomic_set(&adev->vcn.inst[i].sched_score, 0); 206 207 ring = &adev->vcn.inst[i].ring_dec; 208 ring->use_doorbell = true; 209 if (amdgpu_sriov_vf(adev)) { 210 ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1); 211 } else { 212 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i; 213 } 214 sprintf(ring->name, "vcn_dec_%d", i); 215 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 216 AMDGPU_RING_PRIO_DEFAULT, 217 &adev->vcn.inst[i].sched_score); 218 if (r) 219 return r; 220 221 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 222 /* VCN ENC TRAP */ 223 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 224 j + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); 225 if (r) 226 return r; 227 228 ring = &adev->vcn.inst[i].ring_enc[j]; 229 ring->use_doorbell = true; 230 if (amdgpu_sriov_vf(adev)) { 231 ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1) + 1 + j; 232 } else { 233 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + j + 8 * i; 234 } 235 sprintf(ring->name, "vcn_enc_%d.%d", i, j); 236 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 237 AMDGPU_RING_PRIO_DEFAULT, 238 &adev->vcn.inst[i].sched_score); 239 if (r) 240 return r; 241 } 242 243 fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr; 244 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SW_RING_FLAG) | 245 cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG) | 246 cpu_to_le32(AMDGPU_VCN_FW_SHARED_FLAG_0_RB); 247 fw_shared->sw_ring.is_enabled = cpu_to_le32(DEC_SW_RING_ENABLED); 248 } 249 250 if (amdgpu_sriov_vf(adev)) { 251 r = amdgpu_virt_alloc_mm_table(adev); 252 if (r) 253 return r; 254 } 255 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 256 adev->vcn.pause_dpg_mode = vcn_v3_0_pause_dpg_mode; 257 258 return 0; 259 } 260 261 /** 262 * vcn_v3_0_sw_fini - sw fini for VCN block 263 * 264 * @handle: amdgpu_device pointer 265 * 266 * VCN suspend and free up sw allocation 267 */ 268 static int vcn_v3_0_sw_fini(void *handle) 269 { 270 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 271 int i, r; 272 273 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 274 volatile struct amdgpu_fw_shared *fw_shared; 275 276 if (adev->vcn.harvest_config & (1 << i)) 277 continue; 278 fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr; 279 fw_shared->present_flag_0 = 0; 280 fw_shared->sw_ring.is_enabled = false; 281 } 282 283 if (amdgpu_sriov_vf(adev)) 284 amdgpu_virt_free_mm_table(adev); 285 286 r = amdgpu_vcn_suspend(adev); 287 if (r) 288 return r; 289 290 r = amdgpu_vcn_sw_fini(adev); 291 292 return r; 293 } 294 295 /** 296 * vcn_v3_0_hw_init - start and test VCN block 297 * 298 * @handle: amdgpu_device pointer 299 * 300 * Initialize the hardware, boot up the VCPU and do some testing 301 */ 302 static int vcn_v3_0_hw_init(void *handle) 303 { 304 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 305 struct amdgpu_ring *ring; 306 int i, j, r; 307 308 if (amdgpu_sriov_vf(adev)) { 309 r = vcn_v3_0_start_sriov(adev); 310 if (r) 311 goto done; 312 313 /* initialize VCN dec and enc ring buffers */ 314 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 315 if (adev->vcn.harvest_config & (1 << i)) 316 continue; 317 318 ring = &adev->vcn.inst[i].ring_dec; 319 if (ring->sched.ready) { 320 ring->wptr = 0; 321 ring->wptr_old = 0; 322 vcn_v3_0_dec_ring_set_wptr(ring); 323 } 324 325 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 326 ring = &adev->vcn.inst[i].ring_enc[j]; 327 if (ring->sched.ready) { 328 ring->wptr = 0; 329 ring->wptr_old = 0; 330 vcn_v3_0_enc_ring_set_wptr(ring); 331 } 332 } 333 } 334 } else { 335 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 336 if (adev->vcn.harvest_config & (1 << i)) 337 continue; 338 339 ring = &adev->vcn.inst[i].ring_dec; 340 341 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 342 ring->doorbell_index, i); 343 344 r = amdgpu_ring_test_helper(ring); 345 if (r) 346 goto done; 347 348 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 349 ring = &adev->vcn.inst[i].ring_enc[j]; 350 r = amdgpu_ring_test_helper(ring); 351 if (r) 352 goto done; 353 } 354 } 355 } 356 357 done: 358 if (!r) 359 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 360 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 361 362 return r; 363 } 364 365 /** 366 * vcn_v3_0_hw_fini - stop the hardware block 367 * 368 * @handle: amdgpu_device pointer 369 * 370 * Stop the VCN block, mark ring as not ready any more 371 */ 372 static int vcn_v3_0_hw_fini(void *handle) 373 { 374 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 375 int i; 376 377 cancel_delayed_work_sync(&adev->vcn.idle_work); 378 379 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 380 if (adev->vcn.harvest_config & (1 << i)) 381 continue; 382 383 if (!amdgpu_sriov_vf(adev)) { 384 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 385 (adev->vcn.cur_state != AMD_PG_STATE_GATE && 386 RREG32_SOC15(VCN, i, mmUVD_STATUS))) { 387 vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 388 } 389 } 390 } 391 392 return 0; 393 } 394 395 /** 396 * vcn_v3_0_suspend - suspend VCN block 397 * 398 * @handle: amdgpu_device pointer 399 * 400 * HW fini and suspend VCN block 401 */ 402 static int vcn_v3_0_suspend(void *handle) 403 { 404 int r; 405 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 406 407 r = vcn_v3_0_hw_fini(adev); 408 if (r) 409 return r; 410 411 r = amdgpu_vcn_suspend(adev); 412 413 return r; 414 } 415 416 /** 417 * vcn_v3_0_resume - resume VCN block 418 * 419 * @handle: amdgpu_device pointer 420 * 421 * Resume firmware and hw init VCN block 422 */ 423 static int vcn_v3_0_resume(void *handle) 424 { 425 int r; 426 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 427 428 r = amdgpu_vcn_resume(adev); 429 if (r) 430 return r; 431 432 r = vcn_v3_0_hw_init(adev); 433 434 return r; 435 } 436 437 /** 438 * vcn_v3_0_mc_resume - memory controller programming 439 * 440 * @adev: amdgpu_device pointer 441 * @inst: instance number 442 * 443 * Let the VCN memory controller know it's offsets 444 */ 445 static void vcn_v3_0_mc_resume(struct amdgpu_device *adev, int inst) 446 { 447 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 448 uint32_t offset; 449 450 /* cache window 0: fw */ 451 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 452 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 453 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 454 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 455 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 456 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 0); 457 offset = 0; 458 } else { 459 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 460 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 461 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 462 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 463 offset = size; 464 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 465 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 466 } 467 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE0, size); 468 469 /* cache window 1: stack */ 470 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 471 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 472 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 473 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 474 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET1, 0); 475 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 476 477 /* cache window 2: context */ 478 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 479 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 480 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 481 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 482 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET2, 0); 483 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 484 485 /* non-cache window */ 486 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 487 lower_32_bits(adev->vcn.inst[inst].fw_shared_gpu_addr)); 488 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 489 upper_32_bits(adev->vcn.inst[inst].fw_shared_gpu_addr)); 490 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_OFFSET0, 0); 491 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_SIZE0, 492 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); 493 } 494 495 static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 496 { 497 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 498 uint32_t offset; 499 500 /* cache window 0: fw */ 501 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 502 if (!indirect) { 503 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 504 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 505 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); 506 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 507 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 508 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); 509 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 510 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 511 } else { 512 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 513 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 514 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 515 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 516 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 517 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 518 } 519 offset = 0; 520 } else { 521 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 522 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 523 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 524 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 525 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 526 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 527 offset = size; 528 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 529 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 530 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 531 } 532 533 if (!indirect) 534 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 535 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 536 else 537 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 538 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 539 540 /* cache window 1: stack */ 541 if (!indirect) { 542 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 543 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 544 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 545 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 546 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 547 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 548 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 549 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 550 } else { 551 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 552 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 553 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 554 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 555 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 556 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 557 } 558 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 559 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 560 561 /* cache window 2: context */ 562 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 563 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 564 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 565 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 566 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 567 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 568 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 569 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 570 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 571 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 572 573 /* non-cache window */ 574 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 575 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 576 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect); 577 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 578 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 579 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect); 580 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 581 VCN, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 582 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 583 VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), 584 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); 585 586 /* VCN global tiling registers */ 587 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 588 UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 589 } 590 591 static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int inst) 592 { 593 uint32_t data = 0; 594 595 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 596 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 597 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 598 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 599 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 600 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 601 | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 602 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 603 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 604 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 605 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 606 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 607 | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 608 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 609 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 610 611 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 612 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 613 UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF); 614 } else { 615 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 616 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 617 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 618 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 619 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 620 | 1 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 621 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 622 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 623 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 624 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 625 | 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 626 | 1 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 627 | 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 628 | 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 629 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 630 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 0, 0x3F3FFFFF); 631 } 632 633 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); 634 data &= ~0x103; 635 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 636 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 637 UVD_POWER_STATUS__UVD_PG_EN_MASK; 638 639 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); 640 } 641 642 static void vcn_v3_0_enable_static_power_gating(struct amdgpu_device *adev, int inst) 643 { 644 uint32_t data; 645 646 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 647 /* Before power off, this indicator has to be turned on */ 648 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); 649 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 650 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 651 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); 652 653 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 654 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 655 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 656 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 657 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 658 | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 659 | 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 660 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 661 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 662 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 663 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 664 | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 665 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 666 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 667 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 668 669 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 670 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 671 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 672 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 673 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 674 | 2 << UVD_PGFSM_STATUS__UVDIRL_PWR_STATUS__SHIFT 675 | 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT 676 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 677 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 678 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 679 | 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT 680 | 2 << UVD_PGFSM_STATUS__UVDATD_PWR_STATUS__SHIFT 681 | 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT 682 | 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT); 683 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, data, 0x3F3FFFFF); 684 } 685 } 686 687 /** 688 * vcn_v3_0_disable_clock_gating - disable VCN clock gating 689 * 690 * @adev: amdgpu_device pointer 691 * @inst: instance number 692 * 693 * Disable clock gating for VCN block 694 */ 695 static void vcn_v3_0_disable_clock_gating(struct amdgpu_device *adev, int inst) 696 { 697 uint32_t data; 698 699 /* VCN disable CGC */ 700 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 701 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 702 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 703 else 704 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 705 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 706 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 707 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 708 709 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_GATE); 710 data &= ~(UVD_CGC_GATE__SYS_MASK 711 | UVD_CGC_GATE__UDEC_MASK 712 | UVD_CGC_GATE__MPEG2_MASK 713 | UVD_CGC_GATE__REGS_MASK 714 | UVD_CGC_GATE__RBC_MASK 715 | UVD_CGC_GATE__LMI_MC_MASK 716 | UVD_CGC_GATE__LMI_UMC_MASK 717 | UVD_CGC_GATE__IDCT_MASK 718 | UVD_CGC_GATE__MPRD_MASK 719 | UVD_CGC_GATE__MPC_MASK 720 | UVD_CGC_GATE__LBSI_MASK 721 | UVD_CGC_GATE__LRBBM_MASK 722 | UVD_CGC_GATE__UDEC_RE_MASK 723 | UVD_CGC_GATE__UDEC_CM_MASK 724 | UVD_CGC_GATE__UDEC_IT_MASK 725 | UVD_CGC_GATE__UDEC_DB_MASK 726 | UVD_CGC_GATE__UDEC_MP_MASK 727 | UVD_CGC_GATE__WCB_MASK 728 | UVD_CGC_GATE__VCPU_MASK 729 | UVD_CGC_GATE__MMSCH_MASK); 730 731 WREG32_SOC15(VCN, inst, mmUVD_CGC_GATE, data); 732 733 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); 734 735 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 736 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 737 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 738 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 739 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 740 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 741 | UVD_CGC_CTRL__SYS_MODE_MASK 742 | UVD_CGC_CTRL__UDEC_MODE_MASK 743 | UVD_CGC_CTRL__MPEG2_MODE_MASK 744 | UVD_CGC_CTRL__REGS_MODE_MASK 745 | UVD_CGC_CTRL__RBC_MODE_MASK 746 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 747 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 748 | UVD_CGC_CTRL__IDCT_MODE_MASK 749 | UVD_CGC_CTRL__MPRD_MODE_MASK 750 | UVD_CGC_CTRL__MPC_MODE_MASK 751 | UVD_CGC_CTRL__LBSI_MODE_MASK 752 | UVD_CGC_CTRL__LRBBM_MODE_MASK 753 | UVD_CGC_CTRL__WCB_MODE_MASK 754 | UVD_CGC_CTRL__VCPU_MODE_MASK 755 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 756 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 757 758 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE); 759 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 760 | UVD_SUVD_CGC_GATE__SIT_MASK 761 | UVD_SUVD_CGC_GATE__SMP_MASK 762 | UVD_SUVD_CGC_GATE__SCM_MASK 763 | UVD_SUVD_CGC_GATE__SDB_MASK 764 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 765 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 766 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 767 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 768 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 769 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 770 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 771 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 772 | UVD_SUVD_CGC_GATE__SCLR_MASK 773 | UVD_SUVD_CGC_GATE__ENT_MASK 774 | UVD_SUVD_CGC_GATE__IME_MASK 775 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 776 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 777 | UVD_SUVD_CGC_GATE__SITE_MASK 778 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 779 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 780 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 781 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 782 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK 783 | UVD_SUVD_CGC_GATE__EFC_MASK 784 | UVD_SUVD_CGC_GATE__SAOE_MASK 785 | UVD_SUVD_CGC_GATE__SRE_AV1_MASK 786 | UVD_SUVD_CGC_GATE__FBC_PCLK_MASK 787 | UVD_SUVD_CGC_GATE__FBC_CCLK_MASK 788 | UVD_SUVD_CGC_GATE__SCM_AV1_MASK 789 | UVD_SUVD_CGC_GATE__SMPA_MASK); 790 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE, data); 791 792 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2); 793 data |= (UVD_SUVD_CGC_GATE2__MPBE0_MASK 794 | UVD_SUVD_CGC_GATE2__MPBE1_MASK 795 | UVD_SUVD_CGC_GATE2__SIT_AV1_MASK 796 | UVD_SUVD_CGC_GATE2__SDB_AV1_MASK 797 | UVD_SUVD_CGC_GATE2__MPC1_MASK); 798 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2, data); 799 800 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL); 801 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 802 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 803 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 804 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 805 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 806 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 807 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 808 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 809 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 810 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 811 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK 812 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK 813 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK 814 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK 815 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 816 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 817 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK 818 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK 819 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK); 820 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data); 821 } 822 823 static void vcn_v3_0_clock_gating_dpg_mode(struct amdgpu_device *adev, 824 uint8_t sram_sel, int inst_idx, uint8_t indirect) 825 { 826 uint32_t reg_data = 0; 827 828 /* enable sw clock gating control */ 829 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 830 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 831 else 832 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 833 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 834 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 835 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 836 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 837 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 838 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 839 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 840 UVD_CGC_CTRL__SYS_MODE_MASK | 841 UVD_CGC_CTRL__UDEC_MODE_MASK | 842 UVD_CGC_CTRL__MPEG2_MODE_MASK | 843 UVD_CGC_CTRL__REGS_MODE_MASK | 844 UVD_CGC_CTRL__RBC_MODE_MASK | 845 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 846 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 847 UVD_CGC_CTRL__IDCT_MODE_MASK | 848 UVD_CGC_CTRL__MPRD_MODE_MASK | 849 UVD_CGC_CTRL__MPC_MODE_MASK | 850 UVD_CGC_CTRL__LBSI_MODE_MASK | 851 UVD_CGC_CTRL__LRBBM_MODE_MASK | 852 UVD_CGC_CTRL__WCB_MODE_MASK | 853 UVD_CGC_CTRL__VCPU_MODE_MASK | 854 UVD_CGC_CTRL__MMSCH_MODE_MASK); 855 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 856 VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); 857 858 /* turn off clock gating */ 859 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 860 VCN, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect); 861 862 /* turn on SUVD clock gating */ 863 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 864 VCN, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 865 866 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 867 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 868 VCN, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 869 } 870 871 /** 872 * vcn_v3_0_enable_clock_gating - enable VCN clock gating 873 * 874 * @adev: amdgpu_device pointer 875 * @inst: instance number 876 * 877 * Enable clock gating for VCN block 878 */ 879 static void vcn_v3_0_enable_clock_gating(struct amdgpu_device *adev, int inst) 880 { 881 uint32_t data; 882 883 /* enable VCN CGC */ 884 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 885 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 886 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 887 else 888 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 889 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 890 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 891 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 892 893 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 894 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 895 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 896 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 897 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 898 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 899 | UVD_CGC_CTRL__SYS_MODE_MASK 900 | UVD_CGC_CTRL__UDEC_MODE_MASK 901 | UVD_CGC_CTRL__MPEG2_MODE_MASK 902 | UVD_CGC_CTRL__REGS_MODE_MASK 903 | UVD_CGC_CTRL__RBC_MODE_MASK 904 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 905 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 906 | UVD_CGC_CTRL__IDCT_MODE_MASK 907 | UVD_CGC_CTRL__MPRD_MODE_MASK 908 | UVD_CGC_CTRL__MPC_MODE_MASK 909 | UVD_CGC_CTRL__LBSI_MODE_MASK 910 | UVD_CGC_CTRL__LRBBM_MODE_MASK 911 | UVD_CGC_CTRL__WCB_MODE_MASK 912 | UVD_CGC_CTRL__VCPU_MODE_MASK 913 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 914 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 915 916 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL); 917 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 918 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 919 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 920 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 921 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 922 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 923 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 924 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 925 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 926 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 927 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK 928 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK 929 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK 930 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK 931 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 932 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 933 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK 934 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK 935 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK); 936 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data); 937 } 938 939 static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 940 { 941 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr; 942 struct amdgpu_ring *ring; 943 uint32_t rb_bufsz, tmp; 944 945 /* disable register anti-hang mechanism */ 946 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1, 947 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 948 /* enable dynamic power gating mode */ 949 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS); 950 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 951 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 952 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp); 953 954 if (indirect) 955 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 956 957 /* enable clock gating */ 958 vcn_v3_0_clock_gating_dpg_mode(adev, 0, inst_idx, indirect); 959 960 /* enable VCPU clock */ 961 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 962 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 963 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK; 964 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 965 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 966 967 /* disable master interupt */ 968 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 969 VCN, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect); 970 971 /* setup mmUVD_LMI_CTRL */ 972 tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 973 UVD_LMI_CTRL__REQ_MODE_MASK | 974 UVD_LMI_CTRL__CRC_RESET_MASK | 975 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 976 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 977 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 978 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 979 0x00100000L); 980 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 981 VCN, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect); 982 983 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 984 VCN, inst_idx, mmUVD_MPC_CNTL), 985 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 986 987 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 988 VCN, inst_idx, mmUVD_MPC_SET_MUXA0), 989 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 990 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 991 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 992 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 993 994 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 995 VCN, inst_idx, mmUVD_MPC_SET_MUXB0), 996 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 997 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 998 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 999 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 1000 1001 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1002 VCN, inst_idx, mmUVD_MPC_SET_MUX), 1003 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1004 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1005 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 1006 1007 vcn_v3_0_mc_resume_dpg_mode(adev, inst_idx, indirect); 1008 1009 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1010 VCN, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect); 1011 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1012 VCN, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect); 1013 1014 /* enable LMI MC and UMC channels */ 1015 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1016 VCN, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect); 1017 1018 /* unblock VCPU register access */ 1019 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1020 VCN, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect); 1021 1022 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 1023 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 1024 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1025 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 1026 1027 /* enable master interrupt */ 1028 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1029 VCN, inst_idx, mmUVD_MASTINT_EN), 1030 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 1031 1032 /* add nop to workaround PSP size check */ 1033 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1034 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 1035 1036 if (indirect) 1037 psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, 1038 (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr - 1039 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr)); 1040 1041 ring = &adev->vcn.inst[inst_idx].ring_dec; 1042 /* force RBC into idle state */ 1043 rb_bufsz = order_base_2(ring->ring_size); 1044 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1045 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1046 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1047 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1048 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1049 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp); 1050 1051 /* Stall DPG before WPTR/RPTR reset */ 1052 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1053 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1054 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1055 fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1056 1057 /* set the write pointer delay */ 1058 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0); 1059 1060 /* set the wb address */ 1061 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR, 1062 (upper_32_bits(ring->gpu_addr) >> 2)); 1063 1064 /* programm the RB_BASE for ring buffer */ 1065 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1066 lower_32_bits(ring->gpu_addr)); 1067 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1068 upper_32_bits(ring->gpu_addr)); 1069 1070 /* Initialize the ring buffer's read and write pointers */ 1071 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0); 1072 1073 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0); 1074 1075 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR); 1076 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, 1077 lower_32_bits(ring->wptr)); 1078 1079 /* Reset FW shared memory RBC WPTR/RPTR */ 1080 fw_shared->rb.rptr = 0; 1081 fw_shared->rb.wptr = lower_32_bits(ring->wptr); 1082 1083 /*resetting done, fw can check RB ring */ 1084 fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1085 1086 /* Unstall DPG */ 1087 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1088 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1089 1090 return 0; 1091 } 1092 1093 static int vcn_v3_0_start(struct amdgpu_device *adev) 1094 { 1095 volatile struct amdgpu_fw_shared *fw_shared; 1096 struct amdgpu_ring *ring; 1097 uint32_t rb_bufsz, tmp; 1098 int i, j, k, r; 1099 1100 if (adev->pm.dpm_enabled) 1101 amdgpu_dpm_enable_uvd(adev, true); 1102 1103 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1104 if (adev->vcn.harvest_config & (1 << i)) 1105 continue; 1106 1107 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG){ 1108 r = vcn_v3_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram); 1109 continue; 1110 } 1111 1112 /* disable VCN power gating */ 1113 vcn_v3_0_disable_static_power_gating(adev, i); 1114 1115 /* set VCN status busy */ 1116 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 1117 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp); 1118 1119 /*SW clock gating */ 1120 vcn_v3_0_disable_clock_gating(adev, i); 1121 1122 /* enable VCPU clock */ 1123 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1124 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 1125 1126 /* disable master interrupt */ 1127 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0, 1128 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1129 1130 /* enable LMI MC and UMC channels */ 1131 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0, 1132 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1133 1134 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1135 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1136 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1137 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1138 1139 /* setup mmUVD_LMI_CTRL */ 1140 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL); 1141 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | 1142 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1143 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1144 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1145 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1146 1147 /* setup mmUVD_MPC_CNTL */ 1148 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL); 1149 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1150 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1151 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp); 1152 1153 /* setup UVD_MPC_SET_MUXA0 */ 1154 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0, 1155 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1156 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1157 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1158 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1159 1160 /* setup UVD_MPC_SET_MUXB0 */ 1161 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0, 1162 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1163 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1164 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1165 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1166 1167 /* setup mmUVD_MPC_SET_MUX */ 1168 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX, 1169 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1170 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1171 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1172 1173 vcn_v3_0_mc_resume(adev, i); 1174 1175 /* VCN global tiling registers */ 1176 WREG32_SOC15(VCN, i, mmUVD_GFX10_ADDR_CONFIG, 1177 adev->gfx.config.gb_addr_config); 1178 1179 /* unblock VCPU register access */ 1180 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0, 1181 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1182 1183 /* release VCPU reset to boot */ 1184 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1185 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1186 1187 for (j = 0; j < 10; ++j) { 1188 uint32_t status; 1189 1190 for (k = 0; k < 100; ++k) { 1191 status = RREG32_SOC15(VCN, i, mmUVD_STATUS); 1192 if (status & 2) 1193 break; 1194 mdelay(10); 1195 } 1196 r = 0; 1197 if (status & 2) 1198 break; 1199 1200 DRM_ERROR("VCN[%d] decode not responding, trying to reset the VCPU!!!\n", i); 1201 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1202 UVD_VCPU_CNTL__BLK_RST_MASK, 1203 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1204 mdelay(10); 1205 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1206 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1207 1208 mdelay(10); 1209 r = -1; 1210 } 1211 1212 if (r) { 1213 DRM_ERROR("VCN[%d] decode not responding, giving up!!!\n", i); 1214 return r; 1215 } 1216 1217 /* enable master interrupt */ 1218 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 1219 UVD_MASTINT_EN__VCPU_EN_MASK, 1220 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1221 1222 /* clear the busy bit of VCN_STATUS */ 1223 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0, 1224 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1225 1226 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0); 1227 1228 ring = &adev->vcn.inst[i].ring_dec; 1229 /* force RBC into idle state */ 1230 rb_bufsz = order_base_2(ring->ring_size); 1231 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1232 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1233 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1234 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1235 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1236 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp); 1237 1238 fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr; 1239 fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1240 1241 /* programm the RB_BASE for ring buffer */ 1242 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1243 lower_32_bits(ring->gpu_addr)); 1244 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1245 upper_32_bits(ring->gpu_addr)); 1246 1247 /* Initialize the ring buffer's read and write pointers */ 1248 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0); 1249 1250 WREG32_SOC15(VCN, i, mmUVD_SCRATCH2, 0); 1251 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR); 1252 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR, 1253 lower_32_bits(ring->wptr)); 1254 fw_shared->rb.wptr = lower_32_bits(ring->wptr); 1255 fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1256 1257 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1258 ring = &adev->vcn.inst[i].ring_enc[0]; 1259 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1260 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1261 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr); 1262 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1263 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4); 1264 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1265 1266 fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1267 ring = &adev->vcn.inst[i].ring_enc[1]; 1268 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1269 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1270 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1271 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1272 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4); 1273 fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1274 } 1275 1276 return 0; 1277 } 1278 1279 static int vcn_v3_0_start_sriov(struct amdgpu_device *adev) 1280 { 1281 int i, j; 1282 struct amdgpu_ring *ring; 1283 uint64_t cache_addr; 1284 uint64_t rb_addr; 1285 uint64_t ctx_addr; 1286 uint32_t param, resp, expected; 1287 uint32_t offset, cache_size; 1288 uint32_t tmp, timeout; 1289 uint32_t id; 1290 1291 struct amdgpu_mm_table *table = &adev->virt.mm_table; 1292 uint32_t *table_loc; 1293 uint32_t table_size; 1294 uint32_t size, size_dw; 1295 1296 bool is_vcn_ready; 1297 1298 struct mmsch_v3_0_cmd_direct_write 1299 direct_wt = { {0} }; 1300 struct mmsch_v3_0_cmd_direct_read_modify_write 1301 direct_rd_mod_wt = { {0} }; 1302 struct mmsch_v3_0_cmd_end end = { {0} }; 1303 struct mmsch_v3_0_init_header header; 1304 1305 direct_wt.cmd_header.command_type = 1306 MMSCH_COMMAND__DIRECT_REG_WRITE; 1307 direct_rd_mod_wt.cmd_header.command_type = 1308 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1309 end.cmd_header.command_type = 1310 MMSCH_COMMAND__END; 1311 1312 header.version = MMSCH_VERSION; 1313 header.total_size = sizeof(struct mmsch_v3_0_init_header) >> 2; 1314 for (i = 0; i < AMDGPU_MAX_VCN_INSTANCES; i++) { 1315 header.inst[i].init_status = 0; 1316 header.inst[i].table_offset = 0; 1317 header.inst[i].table_size = 0; 1318 } 1319 1320 table_loc = (uint32_t *)table->cpu_addr; 1321 table_loc += header.total_size; 1322 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1323 if (adev->vcn.harvest_config & (1 << i)) 1324 continue; 1325 1326 table_size = 0; 1327 1328 MMSCH_V3_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i, 1329 mmUVD_STATUS), 1330 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 1331 1332 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 1333 1334 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1335 id = amdgpu_ucode_id_vcns[i]; 1336 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1337 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1338 adev->firmware.ucode[id].tmr_mc_addr_lo); 1339 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1340 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1341 adev->firmware.ucode[id].tmr_mc_addr_hi); 1342 offset = 0; 1343 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1344 mmUVD_VCPU_CACHE_OFFSET0), 1345 0); 1346 } else { 1347 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1348 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1349 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 1350 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1351 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1352 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 1353 offset = cache_size; 1354 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1355 mmUVD_VCPU_CACHE_OFFSET0), 1356 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 1357 } 1358 1359 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1360 mmUVD_VCPU_CACHE_SIZE0), 1361 cache_size); 1362 1363 cache_addr = adev->vcn.inst[i].gpu_addr + offset; 1364 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1365 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 1366 lower_32_bits(cache_addr)); 1367 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1368 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 1369 upper_32_bits(cache_addr)); 1370 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1371 mmUVD_VCPU_CACHE_OFFSET1), 1372 0); 1373 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1374 mmUVD_VCPU_CACHE_SIZE1), 1375 AMDGPU_VCN_STACK_SIZE); 1376 1377 cache_addr = adev->vcn.inst[i].gpu_addr + offset + 1378 AMDGPU_VCN_STACK_SIZE; 1379 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1380 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 1381 lower_32_bits(cache_addr)); 1382 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1383 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 1384 upper_32_bits(cache_addr)); 1385 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1386 mmUVD_VCPU_CACHE_OFFSET2), 1387 0); 1388 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1389 mmUVD_VCPU_CACHE_SIZE2), 1390 AMDGPU_VCN_CONTEXT_SIZE); 1391 1392 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 1393 ring = &adev->vcn.inst[i].ring_enc[j]; 1394 ring->wptr = 0; 1395 rb_addr = ring->gpu_addr; 1396 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1397 mmUVD_RB_BASE_LO), 1398 lower_32_bits(rb_addr)); 1399 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1400 mmUVD_RB_BASE_HI), 1401 upper_32_bits(rb_addr)); 1402 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1403 mmUVD_RB_SIZE), 1404 ring->ring_size / 4); 1405 } 1406 1407 ring = &adev->vcn.inst[i].ring_dec; 1408 ring->wptr = 0; 1409 rb_addr = ring->gpu_addr; 1410 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1411 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW), 1412 lower_32_bits(rb_addr)); 1413 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1414 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH), 1415 upper_32_bits(rb_addr)); 1416 /* force RBC into idle state */ 1417 tmp = order_base_2(ring->ring_size); 1418 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp); 1419 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1420 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1421 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1422 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1423 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1424 mmUVD_RBC_RB_CNTL), 1425 tmp); 1426 1427 /* add end packet */ 1428 MMSCH_V3_0_INSERT_END(); 1429 1430 /* refine header */ 1431 header.inst[i].init_status = 0; 1432 header.inst[i].table_offset = header.total_size; 1433 header.inst[i].table_size = table_size; 1434 header.total_size += table_size; 1435 } 1436 1437 /* Update init table header in memory */ 1438 size = sizeof(struct mmsch_v3_0_init_header); 1439 table_loc = (uint32_t *)table->cpu_addr; 1440 memcpy((void *)table_loc, &header, size); 1441 1442 /* message MMSCH (in VCN[0]) to initialize this client 1443 * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr 1444 * of memory descriptor location 1445 */ 1446 ctx_addr = table->gpu_addr; 1447 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 1448 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 1449 1450 /* 2, update vmid of descriptor */ 1451 tmp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID); 1452 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1453 /* use domain0 for MM scheduler */ 1454 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1455 WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, tmp); 1456 1457 /* 3, notify mmsch about the size of this descriptor */ 1458 size = header.total_size; 1459 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size); 1460 1461 /* 4, set resp to zero */ 1462 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0); 1463 1464 /* 5, kick off the initialization and wait until 1465 * MMSCH_VF_MAILBOX_RESP becomes non-zero 1466 */ 1467 param = 0x10000001; 1468 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, param); 1469 tmp = 0; 1470 timeout = 1000; 1471 resp = 0; 1472 expected = param + 1; 1473 while (resp != expected) { 1474 resp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); 1475 if (resp == expected) 1476 break; 1477 1478 udelay(10); 1479 tmp = tmp + 10; 1480 if (tmp >= timeout) { 1481 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 1482 " waiting for mmMMSCH_VF_MAILBOX_RESP "\ 1483 "(expected=0x%08x, readback=0x%08x)\n", 1484 tmp, expected, resp); 1485 return -EBUSY; 1486 } 1487 } 1488 1489 /* 6, check each VCN's init_status 1490 * if it remains as 0, then this VCN is not assigned to current VF 1491 * do not start ring for this VCN 1492 */ 1493 size = sizeof(struct mmsch_v3_0_init_header); 1494 table_loc = (uint32_t *)table->cpu_addr; 1495 memcpy(&header, (void *)table_loc, size); 1496 1497 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1498 if (adev->vcn.harvest_config & (1 << i)) 1499 continue; 1500 1501 is_vcn_ready = (header.inst[i].init_status == 1); 1502 if (!is_vcn_ready) 1503 DRM_INFO("VCN(%d) engine is disabled by hypervisor\n", i); 1504 1505 ring = &adev->vcn.inst[i].ring_dec; 1506 ring->sched.ready = is_vcn_ready; 1507 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 1508 ring = &adev->vcn.inst[i].ring_enc[j]; 1509 ring->sched.ready = is_vcn_ready; 1510 } 1511 } 1512 1513 return 0; 1514 } 1515 1516 static int vcn_v3_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) 1517 { 1518 uint32_t tmp; 1519 1520 /* Wait for power status to be 1 */ 1521 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1522 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1523 1524 /* wait for read ptr to be equal to write ptr */ 1525 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR); 1526 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1527 1528 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2); 1529 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); 1530 1531 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1532 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); 1533 1534 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1535 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1536 1537 /* disable dynamic power gating mode */ 1538 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0, 1539 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1540 1541 return 0; 1542 } 1543 1544 static int vcn_v3_0_stop(struct amdgpu_device *adev) 1545 { 1546 uint32_t tmp; 1547 int i, r = 0; 1548 1549 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1550 if (adev->vcn.harvest_config & (1 << i)) 1551 continue; 1552 1553 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1554 r = vcn_v3_0_stop_dpg_mode(adev, i); 1555 continue; 1556 } 1557 1558 /* wait for vcn idle */ 1559 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1560 if (r) 1561 return r; 1562 1563 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1564 UVD_LMI_STATUS__READ_CLEAN_MASK | 1565 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1566 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1567 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1568 if (r) 1569 return r; 1570 1571 /* disable LMI UMC channel */ 1572 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2); 1573 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1574 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp); 1575 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK| 1576 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1577 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1578 if (r) 1579 return r; 1580 1581 /* block VCPU register access */ 1582 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 1583 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1584 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1585 1586 /* reset VCPU */ 1587 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1588 UVD_VCPU_CNTL__BLK_RST_MASK, 1589 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1590 1591 /* disable VCPU clock */ 1592 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1593 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1594 1595 /* apply soft reset */ 1596 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1597 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1598 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1599 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1600 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1601 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1602 1603 /* clear status */ 1604 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0); 1605 1606 /* apply HW clock gating */ 1607 vcn_v3_0_enable_clock_gating(adev, i); 1608 1609 /* enable VCN power gating */ 1610 vcn_v3_0_enable_static_power_gating(adev, i); 1611 } 1612 1613 if (adev->pm.dpm_enabled) 1614 amdgpu_dpm_enable_uvd(adev, false); 1615 1616 return 0; 1617 } 1618 1619 static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev, 1620 int inst_idx, struct dpg_pause_state *new_state) 1621 { 1622 volatile struct amdgpu_fw_shared *fw_shared; 1623 struct amdgpu_ring *ring; 1624 uint32_t reg_data = 0; 1625 int ret_code; 1626 1627 /* pause/unpause if state is changed */ 1628 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1629 DRM_DEBUG("dpg pause state changed %d -> %d", 1630 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1631 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) & 1632 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1633 1634 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1635 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, 1636 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1637 1638 if (!ret_code) { 1639 /* pause DPG */ 1640 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1641 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1642 1643 /* wait for ACK */ 1644 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE, 1645 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1646 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1647 1648 /* Stall DPG before WPTR/RPTR reset */ 1649 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1650 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1651 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1652 1653 /* Restore */ 1654 fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr; 1655 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1656 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 1657 ring->wptr = 0; 1658 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr); 1659 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1660 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4); 1661 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1662 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1663 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1664 1665 fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1666 ring = &adev->vcn.inst[inst_idx].ring_enc[1]; 1667 ring->wptr = 0; 1668 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1669 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1670 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4); 1671 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1672 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1673 fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1674 1675 /* restore wptr/rptr with pointers saved in FW shared memory*/ 1676 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, fw_shared->rb.rptr); 1677 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, fw_shared->rb.wptr); 1678 1679 /* Unstall DPG */ 1680 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1681 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1682 1683 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1684 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1685 } 1686 } else { 1687 /* unpause dpg, no need to wait */ 1688 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1689 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1690 } 1691 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1692 } 1693 1694 return 0; 1695 } 1696 1697 /** 1698 * vcn_v3_0_dec_ring_get_rptr - get read pointer 1699 * 1700 * @ring: amdgpu_ring pointer 1701 * 1702 * Returns the current hardware read pointer 1703 */ 1704 static uint64_t vcn_v3_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 1705 { 1706 struct amdgpu_device *adev = ring->adev; 1707 1708 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR); 1709 } 1710 1711 /** 1712 * vcn_v3_0_dec_ring_get_wptr - get write pointer 1713 * 1714 * @ring: amdgpu_ring pointer 1715 * 1716 * Returns the current hardware write pointer 1717 */ 1718 static uint64_t vcn_v3_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 1719 { 1720 struct amdgpu_device *adev = ring->adev; 1721 1722 if (ring->use_doorbell) 1723 return adev->wb.wb[ring->wptr_offs]; 1724 else 1725 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR); 1726 } 1727 1728 /** 1729 * vcn_v3_0_dec_ring_set_wptr - set write pointer 1730 * 1731 * @ring: amdgpu_ring pointer 1732 * 1733 * Commits the write pointer to the hardware 1734 */ 1735 static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 1736 { 1737 struct amdgpu_device *adev = ring->adev; 1738 volatile struct amdgpu_fw_shared *fw_shared; 1739 1740 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1741 /*whenever update RBC_RB_WPTR, we save the wptr in shared rb.wptr and scratch2 */ 1742 fw_shared = adev->vcn.inst[ring->me].fw_shared_cpu_addr; 1743 fw_shared->rb.wptr = lower_32_bits(ring->wptr); 1744 WREG32_SOC15(VCN, ring->me, mmUVD_SCRATCH2, 1745 lower_32_bits(ring->wptr)); 1746 } 1747 1748 if (ring->use_doorbell) { 1749 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 1750 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1751 } else { 1752 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1753 } 1754 } 1755 1756 static void vcn_v3_0_dec_sw_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1757 u64 seq, uint32_t flags) 1758 { 1759 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1760 1761 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_FENCE); 1762 amdgpu_ring_write(ring, addr); 1763 amdgpu_ring_write(ring, upper_32_bits(addr)); 1764 amdgpu_ring_write(ring, seq); 1765 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_TRAP); 1766 } 1767 1768 static void vcn_v3_0_dec_sw_ring_insert_end(struct amdgpu_ring *ring) 1769 { 1770 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END); 1771 } 1772 1773 static void vcn_v3_0_dec_sw_ring_emit_ib(struct amdgpu_ring *ring, 1774 struct amdgpu_job *job, 1775 struct amdgpu_ib *ib, 1776 uint32_t flags) 1777 { 1778 uint32_t vmid = AMDGPU_JOB_GET_VMID(job); 1779 1780 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_IB); 1781 amdgpu_ring_write(ring, vmid); 1782 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1783 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1784 amdgpu_ring_write(ring, ib->length_dw); 1785 } 1786 1787 static void vcn_v3_0_dec_sw_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1788 uint32_t val, uint32_t mask) 1789 { 1790 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WAIT); 1791 amdgpu_ring_write(ring, reg << 2); 1792 amdgpu_ring_write(ring, mask); 1793 amdgpu_ring_write(ring, val); 1794 } 1795 1796 static void vcn_v3_0_dec_sw_ring_emit_vm_flush(struct amdgpu_ring *ring, 1797 uint32_t vmid, uint64_t pd_addr) 1798 { 1799 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1800 uint32_t data0, data1, mask; 1801 1802 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1803 1804 /* wait for register write */ 1805 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance; 1806 data1 = lower_32_bits(pd_addr); 1807 mask = 0xffffffff; 1808 vcn_v3_0_dec_sw_ring_emit_reg_wait(ring, data0, data1, mask); 1809 } 1810 1811 static void vcn_v3_0_dec_sw_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) 1812 { 1813 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WRITE); 1814 amdgpu_ring_write(ring, reg << 2); 1815 amdgpu_ring_write(ring, val); 1816 } 1817 1818 static const struct amdgpu_ring_funcs vcn_v3_0_dec_sw_ring_vm_funcs = { 1819 .type = AMDGPU_RING_TYPE_VCN_DEC, 1820 .align_mask = 0x3f, 1821 .nop = VCN_DEC_SW_CMD_NO_OP, 1822 .vmhub = AMDGPU_MMHUB_0, 1823 .get_rptr = vcn_v3_0_dec_ring_get_rptr, 1824 .get_wptr = vcn_v3_0_dec_ring_get_wptr, 1825 .set_wptr = vcn_v3_0_dec_ring_set_wptr, 1826 .emit_frame_size = 1827 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1828 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1829 4 + /* vcn_v3_0_dec_sw_ring_emit_vm_flush */ 1830 5 + 5 + /* vcn_v3_0_dec_sw_ring_emit_fdec_swe x2 vm fdec_swe */ 1831 1, /* vcn_v3_0_dec_sw_ring_insert_end */ 1832 .emit_ib_size = 5, /* vcn_v3_0_dec_sw_ring_emit_ib */ 1833 .emit_ib = vcn_v3_0_dec_sw_ring_emit_ib, 1834 .emit_fence = vcn_v3_0_dec_sw_ring_emit_fence, 1835 .emit_vm_flush = vcn_v3_0_dec_sw_ring_emit_vm_flush, 1836 .test_ring = amdgpu_vcn_dec_sw_ring_test_ring, 1837 .test_ib = NULL,//amdgpu_vcn_dec_sw_ring_test_ib, 1838 .insert_nop = amdgpu_ring_insert_nop, 1839 .insert_end = vcn_v3_0_dec_sw_ring_insert_end, 1840 .pad_ib = amdgpu_ring_generic_pad_ib, 1841 .begin_use = amdgpu_vcn_ring_begin_use, 1842 .end_use = amdgpu_vcn_ring_end_use, 1843 .emit_wreg = vcn_v3_0_dec_sw_ring_emit_wreg, 1844 .emit_reg_wait = vcn_v3_0_dec_sw_ring_emit_reg_wait, 1845 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1846 }; 1847 1848 static int vcn_v3_0_limit_sched(struct amdgpu_cs_parser *p) 1849 { 1850 struct drm_gpu_scheduler **scheds; 1851 1852 /* The create msg must be in the first IB submitted */ 1853 if (atomic_read(&p->entity->fence_seq)) 1854 return -EINVAL; 1855 1856 scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_DEC] 1857 [AMDGPU_RING_PRIO_DEFAULT].sched; 1858 drm_sched_entity_modify_sched(p->entity, scheds, 1); 1859 return 0; 1860 } 1861 1862 static int vcn_v3_0_dec_msg(struct amdgpu_cs_parser *p, uint64_t addr) 1863 { 1864 struct ttm_operation_ctx ctx = { false, false }; 1865 struct amdgpu_bo_va_mapping *map; 1866 uint32_t *msg, num_buffers; 1867 struct amdgpu_bo *bo; 1868 uint64_t start, end; 1869 unsigned int i; 1870 void * ptr; 1871 int r; 1872 1873 addr &= AMDGPU_GMC_HOLE_MASK; 1874 r = amdgpu_cs_find_mapping(p, addr, &bo, &map); 1875 if (r) { 1876 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 1877 return r; 1878 } 1879 1880 start = map->start * AMDGPU_GPU_PAGE_SIZE; 1881 end = (map->last + 1) * AMDGPU_GPU_PAGE_SIZE; 1882 if (addr & 0x7) { 1883 DRM_ERROR("VCN messages must be 8 byte aligned!\n"); 1884 return -EINVAL; 1885 } 1886 1887 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1888 amdgpu_bo_placement_from_domain(bo, bo->allowed_domains); 1889 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 1890 if (r) { 1891 DRM_ERROR("Failed validating the VCN message BO (%d)!\n", r); 1892 return r; 1893 } 1894 1895 r = amdgpu_bo_kmap(bo, &ptr); 1896 if (r) { 1897 DRM_ERROR("Failed mapping the VCN message (%d)!\n", r); 1898 return r; 1899 } 1900 1901 msg = ptr + addr - start; 1902 1903 /* Check length */ 1904 if (msg[1] > end - addr) { 1905 r = -EINVAL; 1906 goto out; 1907 } 1908 1909 if (msg[3] != RDECODE_MSG_CREATE) 1910 goto out; 1911 1912 num_buffers = msg[2]; 1913 for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) { 1914 uint32_t offset, size, *create; 1915 1916 if (msg[0] != RDECODE_MESSAGE_CREATE) 1917 continue; 1918 1919 offset = msg[1]; 1920 size = msg[2]; 1921 1922 if (offset + size > end) { 1923 r = -EINVAL; 1924 goto out; 1925 } 1926 1927 create = ptr + addr + offset - start; 1928 1929 /* H246, HEVC and VP9 can run on any instance */ 1930 if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11) 1931 continue; 1932 1933 r = vcn_v3_0_limit_sched(p); 1934 if (r) 1935 goto out; 1936 } 1937 1938 out: 1939 amdgpu_bo_kunmap(bo); 1940 return r; 1941 } 1942 1943 static int vcn_v3_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, 1944 uint32_t ib_idx) 1945 { 1946 struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched); 1947 struct amdgpu_ib *ib = &p->job->ibs[ib_idx]; 1948 uint32_t msg_lo = 0, msg_hi = 0; 1949 unsigned i; 1950 int r; 1951 1952 /* The first instance can decode anything */ 1953 if (!ring->me) 1954 return 0; 1955 1956 for (i = 0; i < ib->length_dw; i += 2) { 1957 uint32_t reg = amdgpu_get_ib_value(p, ib_idx, i); 1958 uint32_t val = amdgpu_get_ib_value(p, ib_idx, i + 1); 1959 1960 if (reg == PACKET0(p->adev->vcn.internal.data0, 0)) { 1961 msg_lo = val; 1962 } else if (reg == PACKET0(p->adev->vcn.internal.data1, 0)) { 1963 msg_hi = val; 1964 } else if (reg == PACKET0(p->adev->vcn.internal.cmd, 0) && 1965 val == 0) { 1966 r = vcn_v3_0_dec_msg(p, ((u64)msg_hi) << 32 | msg_lo); 1967 if (r) 1968 return r; 1969 } 1970 } 1971 return 0; 1972 } 1973 1974 static const struct amdgpu_ring_funcs vcn_v3_0_dec_ring_vm_funcs = { 1975 .type = AMDGPU_RING_TYPE_VCN_DEC, 1976 .align_mask = 0xf, 1977 .vmhub = AMDGPU_MMHUB_0, 1978 .get_rptr = vcn_v3_0_dec_ring_get_rptr, 1979 .get_wptr = vcn_v3_0_dec_ring_get_wptr, 1980 .set_wptr = vcn_v3_0_dec_ring_set_wptr, 1981 .patch_cs_in_place = vcn_v3_0_ring_patch_cs_in_place, 1982 .emit_frame_size = 1983 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1984 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1985 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */ 1986 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */ 1987 6, 1988 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */ 1989 .emit_ib = vcn_v2_0_dec_ring_emit_ib, 1990 .emit_fence = vcn_v2_0_dec_ring_emit_fence, 1991 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush, 1992 .test_ring = vcn_v2_0_dec_ring_test_ring, 1993 .test_ib = amdgpu_vcn_dec_ring_test_ib, 1994 .insert_nop = vcn_v2_0_dec_ring_insert_nop, 1995 .insert_start = vcn_v2_0_dec_ring_insert_start, 1996 .insert_end = vcn_v2_0_dec_ring_insert_end, 1997 .pad_ib = amdgpu_ring_generic_pad_ib, 1998 .begin_use = amdgpu_vcn_ring_begin_use, 1999 .end_use = amdgpu_vcn_ring_end_use, 2000 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg, 2001 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait, 2002 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2003 }; 2004 2005 /** 2006 * vcn_v3_0_enc_ring_get_rptr - get enc read pointer 2007 * 2008 * @ring: amdgpu_ring pointer 2009 * 2010 * Returns the current hardware enc read pointer 2011 */ 2012 static uint64_t vcn_v3_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 2013 { 2014 struct amdgpu_device *adev = ring->adev; 2015 2016 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) 2017 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR); 2018 else 2019 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2); 2020 } 2021 2022 /** 2023 * vcn_v3_0_enc_ring_get_wptr - get enc write pointer 2024 * 2025 * @ring: amdgpu_ring pointer 2026 * 2027 * Returns the current hardware enc write pointer 2028 */ 2029 static uint64_t vcn_v3_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 2030 { 2031 struct amdgpu_device *adev = ring->adev; 2032 2033 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 2034 if (ring->use_doorbell) 2035 return adev->wb.wb[ring->wptr_offs]; 2036 else 2037 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR); 2038 } else { 2039 if (ring->use_doorbell) 2040 return adev->wb.wb[ring->wptr_offs]; 2041 else 2042 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2); 2043 } 2044 } 2045 2046 /** 2047 * vcn_v3_0_enc_ring_set_wptr - set enc write pointer 2048 * 2049 * @ring: amdgpu_ring pointer 2050 * 2051 * Commits the enc write pointer to the hardware 2052 */ 2053 static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 2054 { 2055 struct amdgpu_device *adev = ring->adev; 2056 2057 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 2058 if (ring->use_doorbell) { 2059 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 2060 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 2061 } else { 2062 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 2063 } 2064 } else { 2065 if (ring->use_doorbell) { 2066 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 2067 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 2068 } else { 2069 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 2070 } 2071 } 2072 } 2073 2074 static const struct amdgpu_ring_funcs vcn_v3_0_enc_ring_vm_funcs = { 2075 .type = AMDGPU_RING_TYPE_VCN_ENC, 2076 .align_mask = 0x3f, 2077 .nop = VCN_ENC_CMD_NO_OP, 2078 .vmhub = AMDGPU_MMHUB_0, 2079 .get_rptr = vcn_v3_0_enc_ring_get_rptr, 2080 .get_wptr = vcn_v3_0_enc_ring_get_wptr, 2081 .set_wptr = vcn_v3_0_enc_ring_set_wptr, 2082 .emit_frame_size = 2083 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2084 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 2085 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 2086 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 2087 1, /* vcn_v2_0_enc_ring_insert_end */ 2088 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 2089 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 2090 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 2091 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 2092 .test_ring = amdgpu_vcn_enc_ring_test_ring, 2093 .test_ib = amdgpu_vcn_enc_ring_test_ib, 2094 .insert_nop = amdgpu_ring_insert_nop, 2095 .insert_end = vcn_v2_0_enc_ring_insert_end, 2096 .pad_ib = amdgpu_ring_generic_pad_ib, 2097 .begin_use = amdgpu_vcn_ring_begin_use, 2098 .end_use = amdgpu_vcn_ring_end_use, 2099 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 2100 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 2101 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2102 }; 2103 2104 static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev) 2105 { 2106 int i; 2107 2108 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2109 if (adev->vcn.harvest_config & (1 << i)) 2110 continue; 2111 2112 if (!DEC_SW_RING_ENABLED) 2113 adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_ring_vm_funcs; 2114 else 2115 adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_sw_ring_vm_funcs; 2116 adev->vcn.inst[i].ring_dec.me = i; 2117 DRM_INFO("VCN(%d) decode%s is enabled in VM mode\n", i, 2118 DEC_SW_RING_ENABLED?"(Software Ring)":""); 2119 } 2120 } 2121 2122 static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev) 2123 { 2124 int i, j; 2125 2126 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2127 if (adev->vcn.harvest_config & (1 << i)) 2128 continue; 2129 2130 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 2131 adev->vcn.inst[i].ring_enc[j].funcs = &vcn_v3_0_enc_ring_vm_funcs; 2132 adev->vcn.inst[i].ring_enc[j].me = i; 2133 } 2134 DRM_INFO("VCN(%d) encode is enabled in VM mode\n", i); 2135 } 2136 } 2137 2138 static bool vcn_v3_0_is_idle(void *handle) 2139 { 2140 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2141 int i, ret = 1; 2142 2143 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2144 if (adev->vcn.harvest_config & (1 << i)) 2145 continue; 2146 2147 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); 2148 } 2149 2150 return ret; 2151 } 2152 2153 static int vcn_v3_0_wait_for_idle(void *handle) 2154 { 2155 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2156 int i, ret = 0; 2157 2158 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2159 if (adev->vcn.harvest_config & (1 << i)) 2160 continue; 2161 2162 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 2163 UVD_STATUS__IDLE); 2164 if (ret) 2165 return ret; 2166 } 2167 2168 return ret; 2169 } 2170 2171 static int vcn_v3_0_set_clockgating_state(void *handle, 2172 enum amd_clockgating_state state) 2173 { 2174 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2175 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 2176 int i; 2177 2178 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2179 if (adev->vcn.harvest_config & (1 << i)) 2180 continue; 2181 2182 if (enable) { 2183 if (RREG32_SOC15(VCN, i, mmUVD_STATUS) != UVD_STATUS__IDLE) 2184 return -EBUSY; 2185 vcn_v3_0_enable_clock_gating(adev, i); 2186 } else { 2187 vcn_v3_0_disable_clock_gating(adev, i); 2188 } 2189 } 2190 2191 return 0; 2192 } 2193 2194 static int vcn_v3_0_set_powergating_state(void *handle, 2195 enum amd_powergating_state state) 2196 { 2197 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2198 int ret; 2199 2200 /* for SRIOV, guest should not control VCN Power-gating 2201 * MMSCH FW should control Power-gating and clock-gating 2202 * guest should avoid touching CGC and PG 2203 */ 2204 if (amdgpu_sriov_vf(adev)) { 2205 adev->vcn.cur_state = AMD_PG_STATE_UNGATE; 2206 return 0; 2207 } 2208 2209 if(state == adev->vcn.cur_state) 2210 return 0; 2211 2212 if (state == AMD_PG_STATE_GATE) 2213 ret = vcn_v3_0_stop(adev); 2214 else 2215 ret = vcn_v3_0_start(adev); 2216 2217 if(!ret) 2218 adev->vcn.cur_state = state; 2219 2220 return ret; 2221 } 2222 2223 static int vcn_v3_0_set_interrupt_state(struct amdgpu_device *adev, 2224 struct amdgpu_irq_src *source, 2225 unsigned type, 2226 enum amdgpu_interrupt_state state) 2227 { 2228 return 0; 2229 } 2230 2231 static int vcn_v3_0_process_interrupt(struct amdgpu_device *adev, 2232 struct amdgpu_irq_src *source, 2233 struct amdgpu_iv_entry *entry) 2234 { 2235 uint32_t ip_instance; 2236 2237 switch (entry->client_id) { 2238 case SOC15_IH_CLIENTID_VCN: 2239 ip_instance = 0; 2240 break; 2241 case SOC15_IH_CLIENTID_VCN1: 2242 ip_instance = 1; 2243 break; 2244 default: 2245 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 2246 return 0; 2247 } 2248 2249 DRM_DEBUG("IH: VCN TRAP\n"); 2250 2251 switch (entry->src_id) { 2252 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT: 2253 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec); 2254 break; 2255 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 2256 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 2257 break; 2258 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY: 2259 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]); 2260 break; 2261 default: 2262 DRM_ERROR("Unhandled interrupt: %d %d\n", 2263 entry->src_id, entry->src_data[0]); 2264 break; 2265 } 2266 2267 return 0; 2268 } 2269 2270 static const struct amdgpu_irq_src_funcs vcn_v3_0_irq_funcs = { 2271 .set = vcn_v3_0_set_interrupt_state, 2272 .process = vcn_v3_0_process_interrupt, 2273 }; 2274 2275 static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev) 2276 { 2277 int i; 2278 2279 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2280 if (adev->vcn.harvest_config & (1 << i)) 2281 continue; 2282 2283 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1; 2284 adev->vcn.inst[i].irq.funcs = &vcn_v3_0_irq_funcs; 2285 } 2286 } 2287 2288 static const struct amd_ip_funcs vcn_v3_0_ip_funcs = { 2289 .name = "vcn_v3_0", 2290 .early_init = vcn_v3_0_early_init, 2291 .late_init = NULL, 2292 .sw_init = vcn_v3_0_sw_init, 2293 .sw_fini = vcn_v3_0_sw_fini, 2294 .hw_init = vcn_v3_0_hw_init, 2295 .hw_fini = vcn_v3_0_hw_fini, 2296 .suspend = vcn_v3_0_suspend, 2297 .resume = vcn_v3_0_resume, 2298 .is_idle = vcn_v3_0_is_idle, 2299 .wait_for_idle = vcn_v3_0_wait_for_idle, 2300 .check_soft_reset = NULL, 2301 .pre_soft_reset = NULL, 2302 .soft_reset = NULL, 2303 .post_soft_reset = NULL, 2304 .set_clockgating_state = vcn_v3_0_set_clockgating_state, 2305 .set_powergating_state = vcn_v3_0_set_powergating_state, 2306 }; 2307 2308 const struct amdgpu_ip_block_version vcn_v3_0_ip_block = 2309 { 2310 .type = AMD_IP_BLOCK_TYPE_VCN, 2311 .major = 3, 2312 .minor = 0, 2313 .rev = 0, 2314 .funcs = &vcn_v3_0_ip_funcs, 2315 }; 2316