1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_vcn.h" 27 #include "amdgpu_pm.h" 28 #include "soc15.h" 29 #include "soc15d.h" 30 #include "vcn_v2_0.h" 31 #include "mmsch_v3_0.h" 32 33 #include "vcn/vcn_3_0_0_offset.h" 34 #include "vcn/vcn_3_0_0_sh_mask.h" 35 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 36 37 #include <drm/drm_drv.h> 38 39 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x27 40 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x0f 41 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x10 42 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x11 43 #define mmUVD_NO_OP_INTERNAL_OFFSET 0x29 44 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x66 45 #define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d 46 47 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x431 48 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x3b4 49 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x3b5 50 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x25c 51 52 #define VCN_INSTANCES_SIENNA_CICHLID 2 53 #define DEC_SW_RING_ENABLED FALSE 54 55 #define RDECODE_MSG_CREATE 0x00000000 56 #define RDECODE_MESSAGE_CREATE 0x00000001 57 58 static int amdgpu_ih_clientid_vcns[] = { 59 SOC15_IH_CLIENTID_VCN, 60 SOC15_IH_CLIENTID_VCN1 61 }; 62 63 static int amdgpu_ucode_id_vcns[] = { 64 AMDGPU_UCODE_ID_VCN, 65 AMDGPU_UCODE_ID_VCN1 66 }; 67 68 static int vcn_v3_0_start_sriov(struct amdgpu_device *adev); 69 static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev); 70 static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev); 71 static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev); 72 static int vcn_v3_0_set_powergating_state(void *handle, 73 enum amd_powergating_state state); 74 static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev, 75 int inst_idx, struct dpg_pause_state *new_state); 76 77 static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring); 78 static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring); 79 80 /** 81 * vcn_v3_0_early_init - set function pointers 82 * 83 * @handle: amdgpu_device pointer 84 * 85 * Set ring and irq function pointers 86 */ 87 static int vcn_v3_0_early_init(void *handle) 88 { 89 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 90 91 if (amdgpu_sriov_vf(adev)) { 92 adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID; 93 adev->vcn.harvest_config = 0; 94 adev->vcn.num_enc_rings = 1; 95 96 if (adev->asic_type == CHIP_BEIGE_GOBY) { 97 adev->vcn.num_vcn_inst = 1; 98 adev->vcn.num_enc_rings = 0; 99 } 100 101 } else { 102 if (adev->asic_type == CHIP_SIENNA_CICHLID) { 103 u32 harvest; 104 int i; 105 106 adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID; 107 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 108 harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING); 109 if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK) 110 adev->vcn.harvest_config |= 1 << i; 111 } 112 113 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 | 114 AMDGPU_VCN_HARVEST_VCN1)) 115 /* both instances are harvested, disable the block */ 116 return -ENOENT; 117 } else 118 adev->vcn.num_vcn_inst = 1; 119 120 if (adev->asic_type == CHIP_BEIGE_GOBY) 121 adev->vcn.num_enc_rings = 0; 122 else 123 adev->vcn.num_enc_rings = 2; 124 } 125 126 vcn_v3_0_set_dec_ring_funcs(adev); 127 vcn_v3_0_set_enc_ring_funcs(adev); 128 vcn_v3_0_set_irq_funcs(adev); 129 130 return 0; 131 } 132 133 /** 134 * vcn_v3_0_sw_init - sw init for VCN block 135 * 136 * @handle: amdgpu_device pointer 137 * 138 * Load firmware and sw initialization 139 */ 140 static int vcn_v3_0_sw_init(void *handle) 141 { 142 struct amdgpu_ring *ring; 143 int i, j, r; 144 int vcn_doorbell_index = 0; 145 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 146 147 r = amdgpu_vcn_sw_init(adev); 148 if (r) 149 return r; 150 151 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 152 const struct common_firmware_header *hdr; 153 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 154 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN; 155 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw; 156 adev->firmware.fw_size += 157 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 158 159 if (adev->vcn.num_vcn_inst == VCN_INSTANCES_SIENNA_CICHLID) { 160 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].ucode_id = AMDGPU_UCODE_ID_VCN1; 161 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].fw = adev->vcn.fw; 162 adev->firmware.fw_size += 163 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 164 } 165 DRM_INFO("PSP loading VCN firmware\n"); 166 } 167 168 r = amdgpu_vcn_resume(adev); 169 if (r) 170 return r; 171 172 /* 173 * Note: doorbell assignment is fixed for SRIOV multiple VCN engines 174 * Formula: 175 * vcn_db_base = adev->doorbell_index.vcn.vcn_ring0_1 << 1; 176 * dec_ring_i = vcn_db_base + i * (adev->vcn.num_enc_rings + 1) 177 * enc_ring_i,j = vcn_db_base + i * (adev->vcn.num_enc_rings + 1) + 1 + j 178 */ 179 if (amdgpu_sriov_vf(adev)) { 180 vcn_doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1; 181 /* get DWORD offset */ 182 vcn_doorbell_index = vcn_doorbell_index << 1; 183 } 184 185 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 186 volatile struct amdgpu_fw_shared *fw_shared; 187 188 if (adev->vcn.harvest_config & (1 << i)) 189 continue; 190 191 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; 192 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; 193 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; 194 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; 195 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; 196 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; 197 198 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; 199 adev->vcn.inst[i].external.scratch9 = SOC15_REG_OFFSET(VCN, i, mmUVD_SCRATCH9); 200 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; 201 adev->vcn.inst[i].external.data0 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA0); 202 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; 203 adev->vcn.inst[i].external.data1 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA1); 204 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; 205 adev->vcn.inst[i].external.cmd = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_CMD); 206 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; 207 adev->vcn.inst[i].external.nop = SOC15_REG_OFFSET(VCN, i, mmUVD_NO_OP); 208 209 /* VCN DEC TRAP */ 210 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 211 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[i].irq); 212 if (r) 213 return r; 214 215 atomic_set(&adev->vcn.inst[i].sched_score, 0); 216 217 ring = &adev->vcn.inst[i].ring_dec; 218 ring->use_doorbell = true; 219 if (amdgpu_sriov_vf(adev)) { 220 ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1); 221 } else { 222 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i; 223 } 224 sprintf(ring->name, "vcn_dec_%d", i); 225 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 226 AMDGPU_RING_PRIO_DEFAULT, 227 &adev->vcn.inst[i].sched_score); 228 if (r) 229 return r; 230 231 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 232 /* VCN ENC TRAP */ 233 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 234 j + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); 235 if (r) 236 return r; 237 238 ring = &adev->vcn.inst[i].ring_enc[j]; 239 ring->use_doorbell = true; 240 if (amdgpu_sriov_vf(adev)) { 241 ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1) + 1 + j; 242 } else { 243 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + j + 8 * i; 244 } 245 sprintf(ring->name, "vcn_enc_%d.%d", i, j); 246 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 247 AMDGPU_RING_PRIO_DEFAULT, 248 &adev->vcn.inst[i].sched_score); 249 if (r) 250 return r; 251 } 252 253 fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr; 254 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SW_RING_FLAG) | 255 cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG) | 256 cpu_to_le32(AMDGPU_VCN_FW_SHARED_FLAG_0_RB); 257 fw_shared->sw_ring.is_enabled = cpu_to_le32(DEC_SW_RING_ENABLED); 258 } 259 260 if (amdgpu_sriov_vf(adev)) { 261 r = amdgpu_virt_alloc_mm_table(adev); 262 if (r) 263 return r; 264 } 265 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 266 adev->vcn.pause_dpg_mode = vcn_v3_0_pause_dpg_mode; 267 268 return 0; 269 } 270 271 /** 272 * vcn_v3_0_sw_fini - sw fini for VCN block 273 * 274 * @handle: amdgpu_device pointer 275 * 276 * VCN suspend and free up sw allocation 277 */ 278 static int vcn_v3_0_sw_fini(void *handle) 279 { 280 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 281 int i, r, idx; 282 283 if (drm_dev_enter(&adev->ddev, &idx)) { 284 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 285 volatile struct amdgpu_fw_shared *fw_shared; 286 287 if (adev->vcn.harvest_config & (1 << i)) 288 continue; 289 fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr; 290 fw_shared->present_flag_0 = 0; 291 fw_shared->sw_ring.is_enabled = false; 292 } 293 294 drm_dev_exit(idx); 295 } 296 297 if (amdgpu_sriov_vf(adev)) 298 amdgpu_virt_free_mm_table(adev); 299 300 r = amdgpu_vcn_suspend(adev); 301 if (r) 302 return r; 303 304 r = amdgpu_vcn_sw_fini(adev); 305 306 return r; 307 } 308 309 /** 310 * vcn_v3_0_hw_init - start and test VCN block 311 * 312 * @handle: amdgpu_device pointer 313 * 314 * Initialize the hardware, boot up the VCPU and do some testing 315 */ 316 static int vcn_v3_0_hw_init(void *handle) 317 { 318 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 319 struct amdgpu_ring *ring; 320 int i, j, r; 321 322 if (amdgpu_sriov_vf(adev)) { 323 r = vcn_v3_0_start_sriov(adev); 324 if (r) 325 goto done; 326 327 /* initialize VCN dec and enc ring buffers */ 328 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 329 if (adev->vcn.harvest_config & (1 << i)) 330 continue; 331 332 ring = &adev->vcn.inst[i].ring_dec; 333 if (ring->sched.ready) { 334 ring->wptr = 0; 335 ring->wptr_old = 0; 336 vcn_v3_0_dec_ring_set_wptr(ring); 337 } 338 339 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 340 ring = &adev->vcn.inst[i].ring_enc[j]; 341 if (ring->sched.ready) { 342 ring->wptr = 0; 343 ring->wptr_old = 0; 344 vcn_v3_0_enc_ring_set_wptr(ring); 345 } 346 } 347 } 348 } else { 349 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 350 if (adev->vcn.harvest_config & (1 << i)) 351 continue; 352 353 ring = &adev->vcn.inst[i].ring_dec; 354 355 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 356 ring->doorbell_index, i); 357 358 r = amdgpu_ring_test_helper(ring); 359 if (r) 360 goto done; 361 362 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 363 ring = &adev->vcn.inst[i].ring_enc[j]; 364 r = amdgpu_ring_test_helper(ring); 365 if (r) 366 goto done; 367 } 368 } 369 } 370 371 done: 372 if (!r) 373 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 374 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 375 376 return r; 377 } 378 379 /** 380 * vcn_v3_0_hw_fini - stop the hardware block 381 * 382 * @handle: amdgpu_device pointer 383 * 384 * Stop the VCN block, mark ring as not ready any more 385 */ 386 static int vcn_v3_0_hw_fini(void *handle) 387 { 388 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 389 int i; 390 391 cancel_delayed_work_sync(&adev->vcn.idle_work); 392 393 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 394 if (adev->vcn.harvest_config & (1 << i)) 395 continue; 396 397 if (!amdgpu_sriov_vf(adev)) { 398 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 399 (adev->vcn.cur_state != AMD_PG_STATE_GATE && 400 RREG32_SOC15(VCN, i, mmUVD_STATUS))) { 401 vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 402 } 403 } 404 } 405 406 return 0; 407 } 408 409 /** 410 * vcn_v3_0_suspend - suspend VCN block 411 * 412 * @handle: amdgpu_device pointer 413 * 414 * HW fini and suspend VCN block 415 */ 416 static int vcn_v3_0_suspend(void *handle) 417 { 418 int r; 419 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 420 421 r = vcn_v3_0_hw_fini(adev); 422 if (r) 423 return r; 424 425 r = amdgpu_vcn_suspend(adev); 426 427 return r; 428 } 429 430 /** 431 * vcn_v3_0_resume - resume VCN block 432 * 433 * @handle: amdgpu_device pointer 434 * 435 * Resume firmware and hw init VCN block 436 */ 437 static int vcn_v3_0_resume(void *handle) 438 { 439 int r; 440 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 441 442 r = amdgpu_vcn_resume(adev); 443 if (r) 444 return r; 445 446 r = vcn_v3_0_hw_init(adev); 447 448 return r; 449 } 450 451 /** 452 * vcn_v3_0_mc_resume - memory controller programming 453 * 454 * @adev: amdgpu_device pointer 455 * @inst: instance number 456 * 457 * Let the VCN memory controller know it's offsets 458 */ 459 static void vcn_v3_0_mc_resume(struct amdgpu_device *adev, int inst) 460 { 461 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 462 uint32_t offset; 463 464 /* cache window 0: fw */ 465 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 466 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 467 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 468 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 469 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 470 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 0); 471 offset = 0; 472 } else { 473 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 474 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 475 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 476 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 477 offset = size; 478 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 479 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 480 } 481 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE0, size); 482 483 /* cache window 1: stack */ 484 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 485 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 486 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 487 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 488 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET1, 0); 489 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 490 491 /* cache window 2: context */ 492 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 493 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 494 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 495 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 496 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET2, 0); 497 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 498 499 /* non-cache window */ 500 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 501 lower_32_bits(adev->vcn.inst[inst].fw_shared_gpu_addr)); 502 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 503 upper_32_bits(adev->vcn.inst[inst].fw_shared_gpu_addr)); 504 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_OFFSET0, 0); 505 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_SIZE0, 506 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); 507 } 508 509 static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 510 { 511 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 512 uint32_t offset; 513 514 /* cache window 0: fw */ 515 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 516 if (!indirect) { 517 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 518 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 519 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); 520 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 521 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 522 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); 523 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 524 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 525 } else { 526 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 527 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 528 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 529 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 530 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 531 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 532 } 533 offset = 0; 534 } else { 535 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 536 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 537 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 538 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 539 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 540 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 541 offset = size; 542 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 543 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 544 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 545 } 546 547 if (!indirect) 548 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 549 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 550 else 551 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 552 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 553 554 /* cache window 1: stack */ 555 if (!indirect) { 556 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 557 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 558 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 559 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 560 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 561 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 562 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 563 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 564 } else { 565 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 566 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 567 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 568 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 569 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 570 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 571 } 572 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 573 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 574 575 /* cache window 2: context */ 576 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 577 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 578 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 579 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 580 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 581 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 582 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 583 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 584 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 585 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 586 587 /* non-cache window */ 588 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 589 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 590 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect); 591 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 592 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 593 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect); 594 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 595 VCN, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 596 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 597 VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), 598 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); 599 600 /* VCN global tiling registers */ 601 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 602 UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 603 } 604 605 static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int inst) 606 { 607 uint32_t data = 0; 608 609 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 610 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 611 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 612 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 613 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 614 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 615 | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 616 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 617 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 618 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 619 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 620 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 621 | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 622 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 623 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 624 625 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 626 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 627 UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF); 628 } else { 629 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 630 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 631 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 632 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 633 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 634 | 1 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 635 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 636 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 637 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 638 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 639 | 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 640 | 1 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 641 | 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 642 | 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 643 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 644 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 0, 0x3F3FFFFF); 645 } 646 647 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); 648 data &= ~0x103; 649 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 650 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 651 UVD_POWER_STATUS__UVD_PG_EN_MASK; 652 653 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); 654 } 655 656 static void vcn_v3_0_enable_static_power_gating(struct amdgpu_device *adev, int inst) 657 { 658 uint32_t data; 659 660 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 661 /* Before power off, this indicator has to be turned on */ 662 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); 663 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 664 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 665 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); 666 667 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 668 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 669 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 670 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 671 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 672 | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 673 | 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 674 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 675 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 676 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 677 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 678 | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 679 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 680 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 681 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 682 683 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 684 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 685 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 686 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 687 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 688 | 2 << UVD_PGFSM_STATUS__UVDIRL_PWR_STATUS__SHIFT 689 | 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT 690 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 691 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 692 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 693 | 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT 694 | 2 << UVD_PGFSM_STATUS__UVDATD_PWR_STATUS__SHIFT 695 | 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT 696 | 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT); 697 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, data, 0x3F3FFFFF); 698 } 699 } 700 701 /** 702 * vcn_v3_0_disable_clock_gating - disable VCN clock gating 703 * 704 * @adev: amdgpu_device pointer 705 * @inst: instance number 706 * 707 * Disable clock gating for VCN block 708 */ 709 static void vcn_v3_0_disable_clock_gating(struct amdgpu_device *adev, int inst) 710 { 711 uint32_t data; 712 713 /* VCN disable CGC */ 714 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 715 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 716 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 717 else 718 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 719 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 720 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 721 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 722 723 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_GATE); 724 data &= ~(UVD_CGC_GATE__SYS_MASK 725 | UVD_CGC_GATE__UDEC_MASK 726 | UVD_CGC_GATE__MPEG2_MASK 727 | UVD_CGC_GATE__REGS_MASK 728 | UVD_CGC_GATE__RBC_MASK 729 | UVD_CGC_GATE__LMI_MC_MASK 730 | UVD_CGC_GATE__LMI_UMC_MASK 731 | UVD_CGC_GATE__IDCT_MASK 732 | UVD_CGC_GATE__MPRD_MASK 733 | UVD_CGC_GATE__MPC_MASK 734 | UVD_CGC_GATE__LBSI_MASK 735 | UVD_CGC_GATE__LRBBM_MASK 736 | UVD_CGC_GATE__UDEC_RE_MASK 737 | UVD_CGC_GATE__UDEC_CM_MASK 738 | UVD_CGC_GATE__UDEC_IT_MASK 739 | UVD_CGC_GATE__UDEC_DB_MASK 740 | UVD_CGC_GATE__UDEC_MP_MASK 741 | UVD_CGC_GATE__WCB_MASK 742 | UVD_CGC_GATE__VCPU_MASK 743 | UVD_CGC_GATE__MMSCH_MASK); 744 745 WREG32_SOC15(VCN, inst, mmUVD_CGC_GATE, data); 746 747 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); 748 749 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 750 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 751 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 752 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 753 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 754 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 755 | UVD_CGC_CTRL__SYS_MODE_MASK 756 | UVD_CGC_CTRL__UDEC_MODE_MASK 757 | UVD_CGC_CTRL__MPEG2_MODE_MASK 758 | UVD_CGC_CTRL__REGS_MODE_MASK 759 | UVD_CGC_CTRL__RBC_MODE_MASK 760 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 761 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 762 | UVD_CGC_CTRL__IDCT_MODE_MASK 763 | UVD_CGC_CTRL__MPRD_MODE_MASK 764 | UVD_CGC_CTRL__MPC_MODE_MASK 765 | UVD_CGC_CTRL__LBSI_MODE_MASK 766 | UVD_CGC_CTRL__LRBBM_MODE_MASK 767 | UVD_CGC_CTRL__WCB_MODE_MASK 768 | UVD_CGC_CTRL__VCPU_MODE_MASK 769 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 770 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 771 772 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE); 773 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 774 | UVD_SUVD_CGC_GATE__SIT_MASK 775 | UVD_SUVD_CGC_GATE__SMP_MASK 776 | UVD_SUVD_CGC_GATE__SCM_MASK 777 | UVD_SUVD_CGC_GATE__SDB_MASK 778 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 779 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 780 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 781 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 782 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 783 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 784 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 785 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 786 | UVD_SUVD_CGC_GATE__SCLR_MASK 787 | UVD_SUVD_CGC_GATE__ENT_MASK 788 | UVD_SUVD_CGC_GATE__IME_MASK 789 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 790 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 791 | UVD_SUVD_CGC_GATE__SITE_MASK 792 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 793 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 794 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 795 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 796 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK 797 | UVD_SUVD_CGC_GATE__EFC_MASK 798 | UVD_SUVD_CGC_GATE__SAOE_MASK 799 | UVD_SUVD_CGC_GATE__SRE_AV1_MASK 800 | UVD_SUVD_CGC_GATE__FBC_PCLK_MASK 801 | UVD_SUVD_CGC_GATE__FBC_CCLK_MASK 802 | UVD_SUVD_CGC_GATE__SCM_AV1_MASK 803 | UVD_SUVD_CGC_GATE__SMPA_MASK); 804 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE, data); 805 806 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2); 807 data |= (UVD_SUVD_CGC_GATE2__MPBE0_MASK 808 | UVD_SUVD_CGC_GATE2__MPBE1_MASK 809 | UVD_SUVD_CGC_GATE2__SIT_AV1_MASK 810 | UVD_SUVD_CGC_GATE2__SDB_AV1_MASK 811 | UVD_SUVD_CGC_GATE2__MPC1_MASK); 812 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2, data); 813 814 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL); 815 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 816 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 817 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 818 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 819 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 820 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 821 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 822 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 823 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 824 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 825 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK 826 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK 827 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK 828 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK 829 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 830 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 831 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK 832 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK 833 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK); 834 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data); 835 } 836 837 static void vcn_v3_0_clock_gating_dpg_mode(struct amdgpu_device *adev, 838 uint8_t sram_sel, int inst_idx, uint8_t indirect) 839 { 840 uint32_t reg_data = 0; 841 842 /* enable sw clock gating control */ 843 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 844 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 845 else 846 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 847 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 848 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 849 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 850 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 851 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 852 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 853 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 854 UVD_CGC_CTRL__SYS_MODE_MASK | 855 UVD_CGC_CTRL__UDEC_MODE_MASK | 856 UVD_CGC_CTRL__MPEG2_MODE_MASK | 857 UVD_CGC_CTRL__REGS_MODE_MASK | 858 UVD_CGC_CTRL__RBC_MODE_MASK | 859 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 860 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 861 UVD_CGC_CTRL__IDCT_MODE_MASK | 862 UVD_CGC_CTRL__MPRD_MODE_MASK | 863 UVD_CGC_CTRL__MPC_MODE_MASK | 864 UVD_CGC_CTRL__LBSI_MODE_MASK | 865 UVD_CGC_CTRL__LRBBM_MODE_MASK | 866 UVD_CGC_CTRL__WCB_MODE_MASK | 867 UVD_CGC_CTRL__VCPU_MODE_MASK | 868 UVD_CGC_CTRL__MMSCH_MODE_MASK); 869 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 870 VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); 871 872 /* turn off clock gating */ 873 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 874 VCN, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect); 875 876 /* turn on SUVD clock gating */ 877 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 878 VCN, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 879 880 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 881 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 882 VCN, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 883 } 884 885 /** 886 * vcn_v3_0_enable_clock_gating - enable VCN clock gating 887 * 888 * @adev: amdgpu_device pointer 889 * @inst: instance number 890 * 891 * Enable clock gating for VCN block 892 */ 893 static void vcn_v3_0_enable_clock_gating(struct amdgpu_device *adev, int inst) 894 { 895 uint32_t data; 896 897 /* enable VCN CGC */ 898 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 899 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 900 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 901 else 902 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 903 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 904 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 905 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 906 907 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 908 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 909 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 910 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 911 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 912 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 913 | UVD_CGC_CTRL__SYS_MODE_MASK 914 | UVD_CGC_CTRL__UDEC_MODE_MASK 915 | UVD_CGC_CTRL__MPEG2_MODE_MASK 916 | UVD_CGC_CTRL__REGS_MODE_MASK 917 | UVD_CGC_CTRL__RBC_MODE_MASK 918 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 919 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 920 | UVD_CGC_CTRL__IDCT_MODE_MASK 921 | UVD_CGC_CTRL__MPRD_MODE_MASK 922 | UVD_CGC_CTRL__MPC_MODE_MASK 923 | UVD_CGC_CTRL__LBSI_MODE_MASK 924 | UVD_CGC_CTRL__LRBBM_MODE_MASK 925 | UVD_CGC_CTRL__WCB_MODE_MASK 926 | UVD_CGC_CTRL__VCPU_MODE_MASK 927 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 928 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 929 930 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL); 931 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 932 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 933 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 934 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 935 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 936 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 937 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 938 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 939 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 940 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 941 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK 942 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK 943 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK 944 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK 945 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 946 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 947 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK 948 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK 949 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK); 950 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data); 951 } 952 953 static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 954 { 955 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr; 956 struct amdgpu_ring *ring; 957 uint32_t rb_bufsz, tmp; 958 959 /* disable register anti-hang mechanism */ 960 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1, 961 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 962 /* enable dynamic power gating mode */ 963 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS); 964 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 965 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 966 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp); 967 968 if (indirect) 969 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 970 971 /* enable clock gating */ 972 vcn_v3_0_clock_gating_dpg_mode(adev, 0, inst_idx, indirect); 973 974 /* enable VCPU clock */ 975 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 976 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 977 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK; 978 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 979 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 980 981 /* disable master interupt */ 982 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 983 VCN, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect); 984 985 /* setup mmUVD_LMI_CTRL */ 986 tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 987 UVD_LMI_CTRL__REQ_MODE_MASK | 988 UVD_LMI_CTRL__CRC_RESET_MASK | 989 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 990 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 991 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 992 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 993 0x00100000L); 994 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 995 VCN, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect); 996 997 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 998 VCN, inst_idx, mmUVD_MPC_CNTL), 999 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 1000 1001 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1002 VCN, inst_idx, mmUVD_MPC_SET_MUXA0), 1003 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1004 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1005 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1006 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 1007 1008 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1009 VCN, inst_idx, mmUVD_MPC_SET_MUXB0), 1010 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1011 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1012 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1013 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 1014 1015 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1016 VCN, inst_idx, mmUVD_MPC_SET_MUX), 1017 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1018 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1019 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 1020 1021 vcn_v3_0_mc_resume_dpg_mode(adev, inst_idx, indirect); 1022 1023 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1024 VCN, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect); 1025 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1026 VCN, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect); 1027 1028 /* enable LMI MC and UMC channels */ 1029 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1030 VCN, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect); 1031 1032 /* unblock VCPU register access */ 1033 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1034 VCN, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect); 1035 1036 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 1037 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 1038 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1039 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 1040 1041 /* enable master interrupt */ 1042 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1043 VCN, inst_idx, mmUVD_MASTINT_EN), 1044 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 1045 1046 /* add nop to workaround PSP size check */ 1047 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1048 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 1049 1050 if (indirect) 1051 psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, 1052 (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr - 1053 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr)); 1054 1055 ring = &adev->vcn.inst[inst_idx].ring_dec; 1056 /* force RBC into idle state */ 1057 rb_bufsz = order_base_2(ring->ring_size); 1058 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1059 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1060 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1061 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1062 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1063 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp); 1064 1065 /* Stall DPG before WPTR/RPTR reset */ 1066 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1067 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1068 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1069 fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1070 1071 /* set the write pointer delay */ 1072 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0); 1073 1074 /* set the wb address */ 1075 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR, 1076 (upper_32_bits(ring->gpu_addr) >> 2)); 1077 1078 /* programm the RB_BASE for ring buffer */ 1079 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1080 lower_32_bits(ring->gpu_addr)); 1081 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1082 upper_32_bits(ring->gpu_addr)); 1083 1084 /* Initialize the ring buffer's read and write pointers */ 1085 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0); 1086 1087 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0); 1088 1089 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR); 1090 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, 1091 lower_32_bits(ring->wptr)); 1092 1093 /* Reset FW shared memory RBC WPTR/RPTR */ 1094 fw_shared->rb.rptr = 0; 1095 fw_shared->rb.wptr = lower_32_bits(ring->wptr); 1096 1097 /*resetting done, fw can check RB ring */ 1098 fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1099 1100 /* Unstall DPG */ 1101 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1102 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1103 1104 return 0; 1105 } 1106 1107 static int vcn_v3_0_start(struct amdgpu_device *adev) 1108 { 1109 volatile struct amdgpu_fw_shared *fw_shared; 1110 struct amdgpu_ring *ring; 1111 uint32_t rb_bufsz, tmp; 1112 int i, j, k, r; 1113 1114 if (adev->pm.dpm_enabled) 1115 amdgpu_dpm_enable_uvd(adev, true); 1116 1117 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1118 if (adev->vcn.harvest_config & (1 << i)) 1119 continue; 1120 1121 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG){ 1122 r = vcn_v3_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram); 1123 continue; 1124 } 1125 1126 /* disable VCN power gating */ 1127 vcn_v3_0_disable_static_power_gating(adev, i); 1128 1129 /* set VCN status busy */ 1130 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 1131 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp); 1132 1133 /*SW clock gating */ 1134 vcn_v3_0_disable_clock_gating(adev, i); 1135 1136 /* enable VCPU clock */ 1137 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1138 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 1139 1140 /* disable master interrupt */ 1141 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0, 1142 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1143 1144 /* enable LMI MC and UMC channels */ 1145 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0, 1146 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1147 1148 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1149 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1150 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1151 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1152 1153 /* setup mmUVD_LMI_CTRL */ 1154 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL); 1155 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | 1156 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1157 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1158 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1159 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1160 1161 /* setup mmUVD_MPC_CNTL */ 1162 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL); 1163 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1164 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1165 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp); 1166 1167 /* setup UVD_MPC_SET_MUXA0 */ 1168 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0, 1169 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1170 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1171 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1172 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1173 1174 /* setup UVD_MPC_SET_MUXB0 */ 1175 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0, 1176 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1177 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1178 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1179 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1180 1181 /* setup mmUVD_MPC_SET_MUX */ 1182 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX, 1183 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1184 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1185 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1186 1187 vcn_v3_0_mc_resume(adev, i); 1188 1189 /* VCN global tiling registers */ 1190 WREG32_SOC15(VCN, i, mmUVD_GFX10_ADDR_CONFIG, 1191 adev->gfx.config.gb_addr_config); 1192 1193 /* unblock VCPU register access */ 1194 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0, 1195 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1196 1197 /* release VCPU reset to boot */ 1198 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1199 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1200 1201 for (j = 0; j < 10; ++j) { 1202 uint32_t status; 1203 1204 for (k = 0; k < 100; ++k) { 1205 status = RREG32_SOC15(VCN, i, mmUVD_STATUS); 1206 if (status & 2) 1207 break; 1208 mdelay(10); 1209 } 1210 r = 0; 1211 if (status & 2) 1212 break; 1213 1214 DRM_ERROR("VCN[%d] decode not responding, trying to reset the VCPU!!!\n", i); 1215 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1216 UVD_VCPU_CNTL__BLK_RST_MASK, 1217 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1218 mdelay(10); 1219 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1220 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1221 1222 mdelay(10); 1223 r = -1; 1224 } 1225 1226 if (r) { 1227 DRM_ERROR("VCN[%d] decode not responding, giving up!!!\n", i); 1228 return r; 1229 } 1230 1231 /* enable master interrupt */ 1232 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 1233 UVD_MASTINT_EN__VCPU_EN_MASK, 1234 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1235 1236 /* clear the busy bit of VCN_STATUS */ 1237 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0, 1238 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1239 1240 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0); 1241 1242 ring = &adev->vcn.inst[i].ring_dec; 1243 /* force RBC into idle state */ 1244 rb_bufsz = order_base_2(ring->ring_size); 1245 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1246 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1247 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1248 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1249 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1250 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp); 1251 1252 fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr; 1253 fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1254 1255 /* programm the RB_BASE for ring buffer */ 1256 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1257 lower_32_bits(ring->gpu_addr)); 1258 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1259 upper_32_bits(ring->gpu_addr)); 1260 1261 /* Initialize the ring buffer's read and write pointers */ 1262 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0); 1263 1264 WREG32_SOC15(VCN, i, mmUVD_SCRATCH2, 0); 1265 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR); 1266 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR, 1267 lower_32_bits(ring->wptr)); 1268 fw_shared->rb.wptr = lower_32_bits(ring->wptr); 1269 fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1270 1271 if (adev->asic_type != CHIP_BEIGE_GOBY) { 1272 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1273 ring = &adev->vcn.inst[i].ring_enc[0]; 1274 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1275 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1276 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr); 1277 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1278 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4); 1279 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1280 1281 fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1282 ring = &adev->vcn.inst[i].ring_enc[1]; 1283 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1284 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1285 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1286 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1287 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4); 1288 fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1289 } 1290 } 1291 1292 return 0; 1293 } 1294 1295 static int vcn_v3_0_start_sriov(struct amdgpu_device *adev) 1296 { 1297 int i, j; 1298 struct amdgpu_ring *ring; 1299 uint64_t cache_addr; 1300 uint64_t rb_addr; 1301 uint64_t ctx_addr; 1302 uint32_t param, resp, expected; 1303 uint32_t offset, cache_size; 1304 uint32_t tmp, timeout; 1305 uint32_t id; 1306 1307 struct amdgpu_mm_table *table = &adev->virt.mm_table; 1308 uint32_t *table_loc; 1309 uint32_t table_size; 1310 uint32_t size, size_dw; 1311 1312 bool is_vcn_ready; 1313 1314 struct mmsch_v3_0_cmd_direct_write 1315 direct_wt = { {0} }; 1316 struct mmsch_v3_0_cmd_direct_read_modify_write 1317 direct_rd_mod_wt = { {0} }; 1318 struct mmsch_v3_0_cmd_end end = { {0} }; 1319 struct mmsch_v3_0_init_header header; 1320 1321 direct_wt.cmd_header.command_type = 1322 MMSCH_COMMAND__DIRECT_REG_WRITE; 1323 direct_rd_mod_wt.cmd_header.command_type = 1324 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1325 end.cmd_header.command_type = 1326 MMSCH_COMMAND__END; 1327 1328 header.version = MMSCH_VERSION; 1329 header.total_size = sizeof(struct mmsch_v3_0_init_header) >> 2; 1330 for (i = 0; i < AMDGPU_MAX_VCN_INSTANCES; i++) { 1331 header.inst[i].init_status = 0; 1332 header.inst[i].table_offset = 0; 1333 header.inst[i].table_size = 0; 1334 } 1335 1336 table_loc = (uint32_t *)table->cpu_addr; 1337 table_loc += header.total_size; 1338 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1339 if (adev->vcn.harvest_config & (1 << i)) 1340 continue; 1341 1342 table_size = 0; 1343 1344 MMSCH_V3_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i, 1345 mmUVD_STATUS), 1346 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 1347 1348 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 1349 1350 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1351 id = amdgpu_ucode_id_vcns[i]; 1352 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1353 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1354 adev->firmware.ucode[id].tmr_mc_addr_lo); 1355 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1356 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1357 adev->firmware.ucode[id].tmr_mc_addr_hi); 1358 offset = 0; 1359 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1360 mmUVD_VCPU_CACHE_OFFSET0), 1361 0); 1362 } else { 1363 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1364 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1365 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 1366 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1367 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1368 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 1369 offset = cache_size; 1370 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1371 mmUVD_VCPU_CACHE_OFFSET0), 1372 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 1373 } 1374 1375 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1376 mmUVD_VCPU_CACHE_SIZE0), 1377 cache_size); 1378 1379 cache_addr = adev->vcn.inst[i].gpu_addr + offset; 1380 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1381 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 1382 lower_32_bits(cache_addr)); 1383 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1384 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 1385 upper_32_bits(cache_addr)); 1386 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1387 mmUVD_VCPU_CACHE_OFFSET1), 1388 0); 1389 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1390 mmUVD_VCPU_CACHE_SIZE1), 1391 AMDGPU_VCN_STACK_SIZE); 1392 1393 cache_addr = adev->vcn.inst[i].gpu_addr + offset + 1394 AMDGPU_VCN_STACK_SIZE; 1395 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1396 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 1397 lower_32_bits(cache_addr)); 1398 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1399 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 1400 upper_32_bits(cache_addr)); 1401 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1402 mmUVD_VCPU_CACHE_OFFSET2), 1403 0); 1404 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1405 mmUVD_VCPU_CACHE_SIZE2), 1406 AMDGPU_VCN_CONTEXT_SIZE); 1407 1408 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 1409 ring = &adev->vcn.inst[i].ring_enc[j]; 1410 ring->wptr = 0; 1411 rb_addr = ring->gpu_addr; 1412 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1413 mmUVD_RB_BASE_LO), 1414 lower_32_bits(rb_addr)); 1415 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1416 mmUVD_RB_BASE_HI), 1417 upper_32_bits(rb_addr)); 1418 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1419 mmUVD_RB_SIZE), 1420 ring->ring_size / 4); 1421 } 1422 1423 ring = &adev->vcn.inst[i].ring_dec; 1424 ring->wptr = 0; 1425 rb_addr = ring->gpu_addr; 1426 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1427 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW), 1428 lower_32_bits(rb_addr)); 1429 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1430 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH), 1431 upper_32_bits(rb_addr)); 1432 /* force RBC into idle state */ 1433 tmp = order_base_2(ring->ring_size); 1434 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp); 1435 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1436 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1437 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1438 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1439 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1440 mmUVD_RBC_RB_CNTL), 1441 tmp); 1442 1443 /* add end packet */ 1444 MMSCH_V3_0_INSERT_END(); 1445 1446 /* refine header */ 1447 header.inst[i].init_status = 0; 1448 header.inst[i].table_offset = header.total_size; 1449 header.inst[i].table_size = table_size; 1450 header.total_size += table_size; 1451 } 1452 1453 /* Update init table header in memory */ 1454 size = sizeof(struct mmsch_v3_0_init_header); 1455 table_loc = (uint32_t *)table->cpu_addr; 1456 memcpy((void *)table_loc, &header, size); 1457 1458 /* message MMSCH (in VCN[0]) to initialize this client 1459 * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr 1460 * of memory descriptor location 1461 */ 1462 ctx_addr = table->gpu_addr; 1463 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 1464 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 1465 1466 /* 2, update vmid of descriptor */ 1467 tmp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID); 1468 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1469 /* use domain0 for MM scheduler */ 1470 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1471 WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, tmp); 1472 1473 /* 3, notify mmsch about the size of this descriptor */ 1474 size = header.total_size; 1475 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size); 1476 1477 /* 4, set resp to zero */ 1478 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0); 1479 1480 /* 5, kick off the initialization and wait until 1481 * MMSCH_VF_MAILBOX_RESP becomes non-zero 1482 */ 1483 param = 0x10000001; 1484 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, param); 1485 tmp = 0; 1486 timeout = 1000; 1487 resp = 0; 1488 expected = param + 1; 1489 while (resp != expected) { 1490 resp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); 1491 if (resp == expected) 1492 break; 1493 1494 udelay(10); 1495 tmp = tmp + 10; 1496 if (tmp >= timeout) { 1497 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 1498 " waiting for mmMMSCH_VF_MAILBOX_RESP "\ 1499 "(expected=0x%08x, readback=0x%08x)\n", 1500 tmp, expected, resp); 1501 return -EBUSY; 1502 } 1503 } 1504 1505 /* 6, check each VCN's init_status 1506 * if it remains as 0, then this VCN is not assigned to current VF 1507 * do not start ring for this VCN 1508 */ 1509 size = sizeof(struct mmsch_v3_0_init_header); 1510 table_loc = (uint32_t *)table->cpu_addr; 1511 memcpy(&header, (void *)table_loc, size); 1512 1513 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1514 if (adev->vcn.harvest_config & (1 << i)) 1515 continue; 1516 1517 is_vcn_ready = (header.inst[i].init_status == 1); 1518 if (!is_vcn_ready) 1519 DRM_INFO("VCN(%d) engine is disabled by hypervisor\n", i); 1520 1521 ring = &adev->vcn.inst[i].ring_dec; 1522 ring->sched.ready = is_vcn_ready; 1523 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 1524 ring = &adev->vcn.inst[i].ring_enc[j]; 1525 ring->sched.ready = is_vcn_ready; 1526 } 1527 } 1528 1529 return 0; 1530 } 1531 1532 static int vcn_v3_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) 1533 { 1534 uint32_t tmp; 1535 1536 /* Wait for power status to be 1 */ 1537 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1538 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1539 1540 /* wait for read ptr to be equal to write ptr */ 1541 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR); 1542 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1543 1544 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2); 1545 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); 1546 1547 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1548 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); 1549 1550 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1551 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1552 1553 /* disable dynamic power gating mode */ 1554 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0, 1555 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1556 1557 return 0; 1558 } 1559 1560 static int vcn_v3_0_stop(struct amdgpu_device *adev) 1561 { 1562 uint32_t tmp; 1563 int i, r = 0; 1564 1565 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1566 if (adev->vcn.harvest_config & (1 << i)) 1567 continue; 1568 1569 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1570 r = vcn_v3_0_stop_dpg_mode(adev, i); 1571 continue; 1572 } 1573 1574 /* wait for vcn idle */ 1575 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1576 if (r) 1577 return r; 1578 1579 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1580 UVD_LMI_STATUS__READ_CLEAN_MASK | 1581 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1582 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1583 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1584 if (r) 1585 return r; 1586 1587 /* disable LMI UMC channel */ 1588 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2); 1589 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1590 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp); 1591 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK| 1592 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1593 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1594 if (r) 1595 return r; 1596 1597 /* block VCPU register access */ 1598 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 1599 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1600 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1601 1602 /* reset VCPU */ 1603 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1604 UVD_VCPU_CNTL__BLK_RST_MASK, 1605 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1606 1607 /* disable VCPU clock */ 1608 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1609 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1610 1611 /* apply soft reset */ 1612 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1613 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1614 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1615 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1616 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1617 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1618 1619 /* clear status */ 1620 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0); 1621 1622 /* apply HW clock gating */ 1623 vcn_v3_0_enable_clock_gating(adev, i); 1624 1625 /* enable VCN power gating */ 1626 vcn_v3_0_enable_static_power_gating(adev, i); 1627 } 1628 1629 if (adev->pm.dpm_enabled) 1630 amdgpu_dpm_enable_uvd(adev, false); 1631 1632 return 0; 1633 } 1634 1635 static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev, 1636 int inst_idx, struct dpg_pause_state *new_state) 1637 { 1638 volatile struct amdgpu_fw_shared *fw_shared; 1639 struct amdgpu_ring *ring; 1640 uint32_t reg_data = 0; 1641 int ret_code; 1642 1643 /* pause/unpause if state is changed */ 1644 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1645 DRM_DEBUG("dpg pause state changed %d -> %d", 1646 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1647 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) & 1648 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1649 1650 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1651 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, 1652 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1653 1654 if (!ret_code) { 1655 /* pause DPG */ 1656 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1657 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1658 1659 /* wait for ACK */ 1660 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE, 1661 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1662 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1663 1664 /* Stall DPG before WPTR/RPTR reset */ 1665 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1666 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1667 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1668 1669 if (adev->asic_type != CHIP_BEIGE_GOBY) { 1670 /* Restore */ 1671 fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr; 1672 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1673 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 1674 ring->wptr = 0; 1675 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr); 1676 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1677 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4); 1678 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1679 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1680 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1681 1682 fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1683 ring = &adev->vcn.inst[inst_idx].ring_enc[1]; 1684 ring->wptr = 0; 1685 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1686 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1687 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4); 1688 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1689 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1690 fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1691 1692 /* restore wptr/rptr with pointers saved in FW shared memory*/ 1693 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, fw_shared->rb.rptr); 1694 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, fw_shared->rb.wptr); 1695 } 1696 1697 /* Unstall DPG */ 1698 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1699 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1700 1701 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1702 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1703 } 1704 } else { 1705 /* unpause dpg, no need to wait */ 1706 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1707 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1708 } 1709 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1710 } 1711 1712 return 0; 1713 } 1714 1715 /** 1716 * vcn_v3_0_dec_ring_get_rptr - get read pointer 1717 * 1718 * @ring: amdgpu_ring pointer 1719 * 1720 * Returns the current hardware read pointer 1721 */ 1722 static uint64_t vcn_v3_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 1723 { 1724 struct amdgpu_device *adev = ring->adev; 1725 1726 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR); 1727 } 1728 1729 /** 1730 * vcn_v3_0_dec_ring_get_wptr - get write pointer 1731 * 1732 * @ring: amdgpu_ring pointer 1733 * 1734 * Returns the current hardware write pointer 1735 */ 1736 static uint64_t vcn_v3_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 1737 { 1738 struct amdgpu_device *adev = ring->adev; 1739 1740 if (ring->use_doorbell) 1741 return adev->wb.wb[ring->wptr_offs]; 1742 else 1743 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR); 1744 } 1745 1746 /** 1747 * vcn_v3_0_dec_ring_set_wptr - set write pointer 1748 * 1749 * @ring: amdgpu_ring pointer 1750 * 1751 * Commits the write pointer to the hardware 1752 */ 1753 static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 1754 { 1755 struct amdgpu_device *adev = ring->adev; 1756 volatile struct amdgpu_fw_shared *fw_shared; 1757 1758 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1759 /*whenever update RBC_RB_WPTR, we save the wptr in shared rb.wptr and scratch2 */ 1760 fw_shared = adev->vcn.inst[ring->me].fw_shared_cpu_addr; 1761 fw_shared->rb.wptr = lower_32_bits(ring->wptr); 1762 WREG32_SOC15(VCN, ring->me, mmUVD_SCRATCH2, 1763 lower_32_bits(ring->wptr)); 1764 } 1765 1766 if (ring->use_doorbell) { 1767 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 1768 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1769 } else { 1770 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1771 } 1772 } 1773 1774 static void vcn_v3_0_dec_sw_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1775 u64 seq, uint32_t flags) 1776 { 1777 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1778 1779 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_FENCE); 1780 amdgpu_ring_write(ring, addr); 1781 amdgpu_ring_write(ring, upper_32_bits(addr)); 1782 amdgpu_ring_write(ring, seq); 1783 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_TRAP); 1784 } 1785 1786 static void vcn_v3_0_dec_sw_ring_insert_end(struct amdgpu_ring *ring) 1787 { 1788 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END); 1789 } 1790 1791 static void vcn_v3_0_dec_sw_ring_emit_ib(struct amdgpu_ring *ring, 1792 struct amdgpu_job *job, 1793 struct amdgpu_ib *ib, 1794 uint32_t flags) 1795 { 1796 uint32_t vmid = AMDGPU_JOB_GET_VMID(job); 1797 1798 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_IB); 1799 amdgpu_ring_write(ring, vmid); 1800 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1801 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1802 amdgpu_ring_write(ring, ib->length_dw); 1803 } 1804 1805 static void vcn_v3_0_dec_sw_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1806 uint32_t val, uint32_t mask) 1807 { 1808 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WAIT); 1809 amdgpu_ring_write(ring, reg << 2); 1810 amdgpu_ring_write(ring, mask); 1811 amdgpu_ring_write(ring, val); 1812 } 1813 1814 static void vcn_v3_0_dec_sw_ring_emit_vm_flush(struct amdgpu_ring *ring, 1815 uint32_t vmid, uint64_t pd_addr) 1816 { 1817 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1818 uint32_t data0, data1, mask; 1819 1820 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1821 1822 /* wait for register write */ 1823 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance; 1824 data1 = lower_32_bits(pd_addr); 1825 mask = 0xffffffff; 1826 vcn_v3_0_dec_sw_ring_emit_reg_wait(ring, data0, data1, mask); 1827 } 1828 1829 static void vcn_v3_0_dec_sw_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) 1830 { 1831 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WRITE); 1832 amdgpu_ring_write(ring, reg << 2); 1833 amdgpu_ring_write(ring, val); 1834 } 1835 1836 static const struct amdgpu_ring_funcs vcn_v3_0_dec_sw_ring_vm_funcs = { 1837 .type = AMDGPU_RING_TYPE_VCN_DEC, 1838 .align_mask = 0x3f, 1839 .nop = VCN_DEC_SW_CMD_NO_OP, 1840 .vmhub = AMDGPU_MMHUB_0, 1841 .get_rptr = vcn_v3_0_dec_ring_get_rptr, 1842 .get_wptr = vcn_v3_0_dec_ring_get_wptr, 1843 .set_wptr = vcn_v3_0_dec_ring_set_wptr, 1844 .emit_frame_size = 1845 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1846 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1847 4 + /* vcn_v3_0_dec_sw_ring_emit_vm_flush */ 1848 5 + 5 + /* vcn_v3_0_dec_sw_ring_emit_fdec_swe x2 vm fdec_swe */ 1849 1, /* vcn_v3_0_dec_sw_ring_insert_end */ 1850 .emit_ib_size = 5, /* vcn_v3_0_dec_sw_ring_emit_ib */ 1851 .emit_ib = vcn_v3_0_dec_sw_ring_emit_ib, 1852 .emit_fence = vcn_v3_0_dec_sw_ring_emit_fence, 1853 .emit_vm_flush = vcn_v3_0_dec_sw_ring_emit_vm_flush, 1854 .test_ring = amdgpu_vcn_dec_sw_ring_test_ring, 1855 .test_ib = NULL,//amdgpu_vcn_dec_sw_ring_test_ib, 1856 .insert_nop = amdgpu_ring_insert_nop, 1857 .insert_end = vcn_v3_0_dec_sw_ring_insert_end, 1858 .pad_ib = amdgpu_ring_generic_pad_ib, 1859 .begin_use = amdgpu_vcn_ring_begin_use, 1860 .end_use = amdgpu_vcn_ring_end_use, 1861 .emit_wreg = vcn_v3_0_dec_sw_ring_emit_wreg, 1862 .emit_reg_wait = vcn_v3_0_dec_sw_ring_emit_reg_wait, 1863 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1864 }; 1865 1866 static int vcn_v3_0_limit_sched(struct amdgpu_cs_parser *p) 1867 { 1868 struct drm_gpu_scheduler **scheds; 1869 1870 /* The create msg must be in the first IB submitted */ 1871 if (atomic_read(&p->entity->fence_seq)) 1872 return -EINVAL; 1873 1874 scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_DEC] 1875 [AMDGPU_RING_PRIO_DEFAULT].sched; 1876 drm_sched_entity_modify_sched(p->entity, scheds, 1); 1877 return 0; 1878 } 1879 1880 static int vcn_v3_0_dec_msg(struct amdgpu_cs_parser *p, uint64_t addr) 1881 { 1882 struct ttm_operation_ctx ctx = { false, false }; 1883 struct amdgpu_bo_va_mapping *map; 1884 uint32_t *msg, num_buffers; 1885 struct amdgpu_bo *bo; 1886 uint64_t start, end; 1887 unsigned int i; 1888 void * ptr; 1889 int r; 1890 1891 addr &= AMDGPU_GMC_HOLE_MASK; 1892 r = amdgpu_cs_find_mapping(p, addr, &bo, &map); 1893 if (r) { 1894 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 1895 return r; 1896 } 1897 1898 start = map->start * AMDGPU_GPU_PAGE_SIZE; 1899 end = (map->last + 1) * AMDGPU_GPU_PAGE_SIZE; 1900 if (addr & 0x7) { 1901 DRM_ERROR("VCN messages must be 8 byte aligned!\n"); 1902 return -EINVAL; 1903 } 1904 1905 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1906 amdgpu_bo_placement_from_domain(bo, bo->allowed_domains); 1907 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 1908 if (r) { 1909 DRM_ERROR("Failed validating the VCN message BO (%d)!\n", r); 1910 return r; 1911 } 1912 1913 r = amdgpu_bo_kmap(bo, &ptr); 1914 if (r) { 1915 DRM_ERROR("Failed mapping the VCN message (%d)!\n", r); 1916 return r; 1917 } 1918 1919 msg = ptr + addr - start; 1920 1921 /* Check length */ 1922 if (msg[1] > end - addr) { 1923 r = -EINVAL; 1924 goto out; 1925 } 1926 1927 if (msg[3] != RDECODE_MSG_CREATE) 1928 goto out; 1929 1930 num_buffers = msg[2]; 1931 for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) { 1932 uint32_t offset, size, *create; 1933 1934 if (msg[0] != RDECODE_MESSAGE_CREATE) 1935 continue; 1936 1937 offset = msg[1]; 1938 size = msg[2]; 1939 1940 if (offset + size > end) { 1941 r = -EINVAL; 1942 goto out; 1943 } 1944 1945 create = ptr + addr + offset - start; 1946 1947 /* H246, HEVC and VP9 can run on any instance */ 1948 if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11) 1949 continue; 1950 1951 r = vcn_v3_0_limit_sched(p); 1952 if (r) 1953 goto out; 1954 } 1955 1956 out: 1957 amdgpu_bo_kunmap(bo); 1958 return r; 1959 } 1960 1961 static int vcn_v3_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, 1962 uint32_t ib_idx) 1963 { 1964 struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched); 1965 struct amdgpu_ib *ib = &p->job->ibs[ib_idx]; 1966 uint32_t msg_lo = 0, msg_hi = 0; 1967 unsigned i; 1968 int r; 1969 1970 /* The first instance can decode anything */ 1971 if (!ring->me) 1972 return 0; 1973 1974 for (i = 0; i < ib->length_dw; i += 2) { 1975 uint32_t reg = amdgpu_get_ib_value(p, ib_idx, i); 1976 uint32_t val = amdgpu_get_ib_value(p, ib_idx, i + 1); 1977 1978 if (reg == PACKET0(p->adev->vcn.internal.data0, 0)) { 1979 msg_lo = val; 1980 } else if (reg == PACKET0(p->adev->vcn.internal.data1, 0)) { 1981 msg_hi = val; 1982 } else if (reg == PACKET0(p->adev->vcn.internal.cmd, 0) && 1983 val == 0) { 1984 r = vcn_v3_0_dec_msg(p, ((u64)msg_hi) << 32 | msg_lo); 1985 if (r) 1986 return r; 1987 } 1988 } 1989 return 0; 1990 } 1991 1992 static const struct amdgpu_ring_funcs vcn_v3_0_dec_ring_vm_funcs = { 1993 .type = AMDGPU_RING_TYPE_VCN_DEC, 1994 .align_mask = 0xf, 1995 .vmhub = AMDGPU_MMHUB_0, 1996 .get_rptr = vcn_v3_0_dec_ring_get_rptr, 1997 .get_wptr = vcn_v3_0_dec_ring_get_wptr, 1998 .set_wptr = vcn_v3_0_dec_ring_set_wptr, 1999 .patch_cs_in_place = vcn_v3_0_ring_patch_cs_in_place, 2000 .emit_frame_size = 2001 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 2002 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 2003 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */ 2004 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */ 2005 6, 2006 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */ 2007 .emit_ib = vcn_v2_0_dec_ring_emit_ib, 2008 .emit_fence = vcn_v2_0_dec_ring_emit_fence, 2009 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush, 2010 .test_ring = vcn_v2_0_dec_ring_test_ring, 2011 .test_ib = amdgpu_vcn_dec_ring_test_ib, 2012 .insert_nop = vcn_v2_0_dec_ring_insert_nop, 2013 .insert_start = vcn_v2_0_dec_ring_insert_start, 2014 .insert_end = vcn_v2_0_dec_ring_insert_end, 2015 .pad_ib = amdgpu_ring_generic_pad_ib, 2016 .begin_use = amdgpu_vcn_ring_begin_use, 2017 .end_use = amdgpu_vcn_ring_end_use, 2018 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg, 2019 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait, 2020 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2021 }; 2022 2023 /** 2024 * vcn_v3_0_enc_ring_get_rptr - get enc read pointer 2025 * 2026 * @ring: amdgpu_ring pointer 2027 * 2028 * Returns the current hardware enc read pointer 2029 */ 2030 static uint64_t vcn_v3_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 2031 { 2032 struct amdgpu_device *adev = ring->adev; 2033 2034 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) 2035 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR); 2036 else 2037 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2); 2038 } 2039 2040 /** 2041 * vcn_v3_0_enc_ring_get_wptr - get enc write pointer 2042 * 2043 * @ring: amdgpu_ring pointer 2044 * 2045 * Returns the current hardware enc write pointer 2046 */ 2047 static uint64_t vcn_v3_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 2048 { 2049 struct amdgpu_device *adev = ring->adev; 2050 2051 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 2052 if (ring->use_doorbell) 2053 return adev->wb.wb[ring->wptr_offs]; 2054 else 2055 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR); 2056 } else { 2057 if (ring->use_doorbell) 2058 return adev->wb.wb[ring->wptr_offs]; 2059 else 2060 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2); 2061 } 2062 } 2063 2064 /** 2065 * vcn_v3_0_enc_ring_set_wptr - set enc write pointer 2066 * 2067 * @ring: amdgpu_ring pointer 2068 * 2069 * Commits the enc write pointer to the hardware 2070 */ 2071 static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 2072 { 2073 struct amdgpu_device *adev = ring->adev; 2074 2075 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 2076 if (ring->use_doorbell) { 2077 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 2078 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 2079 } else { 2080 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 2081 } 2082 } else { 2083 if (ring->use_doorbell) { 2084 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 2085 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 2086 } else { 2087 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 2088 } 2089 } 2090 } 2091 2092 static const struct amdgpu_ring_funcs vcn_v3_0_enc_ring_vm_funcs = { 2093 .type = AMDGPU_RING_TYPE_VCN_ENC, 2094 .align_mask = 0x3f, 2095 .nop = VCN_ENC_CMD_NO_OP, 2096 .vmhub = AMDGPU_MMHUB_0, 2097 .get_rptr = vcn_v3_0_enc_ring_get_rptr, 2098 .get_wptr = vcn_v3_0_enc_ring_get_wptr, 2099 .set_wptr = vcn_v3_0_enc_ring_set_wptr, 2100 .emit_frame_size = 2101 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2102 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 2103 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 2104 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 2105 1, /* vcn_v2_0_enc_ring_insert_end */ 2106 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 2107 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 2108 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 2109 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 2110 .test_ring = amdgpu_vcn_enc_ring_test_ring, 2111 .test_ib = amdgpu_vcn_enc_ring_test_ib, 2112 .insert_nop = amdgpu_ring_insert_nop, 2113 .insert_end = vcn_v2_0_enc_ring_insert_end, 2114 .pad_ib = amdgpu_ring_generic_pad_ib, 2115 .begin_use = amdgpu_vcn_ring_begin_use, 2116 .end_use = amdgpu_vcn_ring_end_use, 2117 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 2118 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 2119 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2120 }; 2121 2122 static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev) 2123 { 2124 int i; 2125 2126 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2127 if (adev->vcn.harvest_config & (1 << i)) 2128 continue; 2129 2130 if (!DEC_SW_RING_ENABLED) 2131 adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_ring_vm_funcs; 2132 else 2133 adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_sw_ring_vm_funcs; 2134 adev->vcn.inst[i].ring_dec.me = i; 2135 DRM_INFO("VCN(%d) decode%s is enabled in VM mode\n", i, 2136 DEC_SW_RING_ENABLED?"(Software Ring)":""); 2137 } 2138 } 2139 2140 static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev) 2141 { 2142 int i, j; 2143 2144 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2145 if (adev->vcn.harvest_config & (1 << i)) 2146 continue; 2147 2148 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 2149 adev->vcn.inst[i].ring_enc[j].funcs = &vcn_v3_0_enc_ring_vm_funcs; 2150 adev->vcn.inst[i].ring_enc[j].me = i; 2151 } 2152 if (adev->vcn.num_enc_rings > 0) 2153 DRM_INFO("VCN(%d) encode is enabled in VM mode\n", i); 2154 } 2155 } 2156 2157 static bool vcn_v3_0_is_idle(void *handle) 2158 { 2159 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2160 int i, ret = 1; 2161 2162 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2163 if (adev->vcn.harvest_config & (1 << i)) 2164 continue; 2165 2166 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); 2167 } 2168 2169 return ret; 2170 } 2171 2172 static int vcn_v3_0_wait_for_idle(void *handle) 2173 { 2174 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2175 int i, ret = 0; 2176 2177 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2178 if (adev->vcn.harvest_config & (1 << i)) 2179 continue; 2180 2181 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 2182 UVD_STATUS__IDLE); 2183 if (ret) 2184 return ret; 2185 } 2186 2187 return ret; 2188 } 2189 2190 static int vcn_v3_0_set_clockgating_state(void *handle, 2191 enum amd_clockgating_state state) 2192 { 2193 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2194 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 2195 int i; 2196 2197 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2198 if (adev->vcn.harvest_config & (1 << i)) 2199 continue; 2200 2201 if (enable) { 2202 if (RREG32_SOC15(VCN, i, mmUVD_STATUS) != UVD_STATUS__IDLE) 2203 return -EBUSY; 2204 vcn_v3_0_enable_clock_gating(adev, i); 2205 } else { 2206 vcn_v3_0_disable_clock_gating(adev, i); 2207 } 2208 } 2209 2210 return 0; 2211 } 2212 2213 static int vcn_v3_0_set_powergating_state(void *handle, 2214 enum amd_powergating_state state) 2215 { 2216 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2217 int ret; 2218 2219 /* for SRIOV, guest should not control VCN Power-gating 2220 * MMSCH FW should control Power-gating and clock-gating 2221 * guest should avoid touching CGC and PG 2222 */ 2223 if (amdgpu_sriov_vf(adev)) { 2224 adev->vcn.cur_state = AMD_PG_STATE_UNGATE; 2225 return 0; 2226 } 2227 2228 if(state == adev->vcn.cur_state) 2229 return 0; 2230 2231 if (state == AMD_PG_STATE_GATE) 2232 ret = vcn_v3_0_stop(adev); 2233 else 2234 ret = vcn_v3_0_start(adev); 2235 2236 if(!ret) 2237 adev->vcn.cur_state = state; 2238 2239 return ret; 2240 } 2241 2242 static int vcn_v3_0_set_interrupt_state(struct amdgpu_device *adev, 2243 struct amdgpu_irq_src *source, 2244 unsigned type, 2245 enum amdgpu_interrupt_state state) 2246 { 2247 return 0; 2248 } 2249 2250 static int vcn_v3_0_process_interrupt(struct amdgpu_device *adev, 2251 struct amdgpu_irq_src *source, 2252 struct amdgpu_iv_entry *entry) 2253 { 2254 uint32_t ip_instance; 2255 2256 switch (entry->client_id) { 2257 case SOC15_IH_CLIENTID_VCN: 2258 ip_instance = 0; 2259 break; 2260 case SOC15_IH_CLIENTID_VCN1: 2261 ip_instance = 1; 2262 break; 2263 default: 2264 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 2265 return 0; 2266 } 2267 2268 DRM_DEBUG("IH: VCN TRAP\n"); 2269 2270 switch (entry->src_id) { 2271 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT: 2272 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec); 2273 break; 2274 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 2275 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 2276 break; 2277 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY: 2278 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]); 2279 break; 2280 default: 2281 DRM_ERROR("Unhandled interrupt: %d %d\n", 2282 entry->src_id, entry->src_data[0]); 2283 break; 2284 } 2285 2286 return 0; 2287 } 2288 2289 static const struct amdgpu_irq_src_funcs vcn_v3_0_irq_funcs = { 2290 .set = vcn_v3_0_set_interrupt_state, 2291 .process = vcn_v3_0_process_interrupt, 2292 }; 2293 2294 static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev) 2295 { 2296 int i; 2297 2298 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2299 if (adev->vcn.harvest_config & (1 << i)) 2300 continue; 2301 2302 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1; 2303 adev->vcn.inst[i].irq.funcs = &vcn_v3_0_irq_funcs; 2304 } 2305 } 2306 2307 static const struct amd_ip_funcs vcn_v3_0_ip_funcs = { 2308 .name = "vcn_v3_0", 2309 .early_init = vcn_v3_0_early_init, 2310 .late_init = NULL, 2311 .sw_init = vcn_v3_0_sw_init, 2312 .sw_fini = vcn_v3_0_sw_fini, 2313 .hw_init = vcn_v3_0_hw_init, 2314 .hw_fini = vcn_v3_0_hw_fini, 2315 .suspend = vcn_v3_0_suspend, 2316 .resume = vcn_v3_0_resume, 2317 .is_idle = vcn_v3_0_is_idle, 2318 .wait_for_idle = vcn_v3_0_wait_for_idle, 2319 .check_soft_reset = NULL, 2320 .pre_soft_reset = NULL, 2321 .soft_reset = NULL, 2322 .post_soft_reset = NULL, 2323 .set_clockgating_state = vcn_v3_0_set_clockgating_state, 2324 .set_powergating_state = vcn_v3_0_set_powergating_state, 2325 }; 2326 2327 const struct amdgpu_ip_block_version vcn_v3_0_ip_block = 2328 { 2329 .type = AMD_IP_BLOCK_TYPE_VCN, 2330 .major = 3, 2331 .minor = 0, 2332 .rev = 0, 2333 .funcs = &vcn_v3_0_ip_funcs, 2334 }; 2335