1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_vcn.h" 27 #include "amdgpu_pm.h" 28 #include "soc15.h" 29 #include "soc15d.h" 30 #include "vcn_v2_0.h" 31 #include "mmsch_v3_0.h" 32 33 #include "vcn/vcn_3_0_0_offset.h" 34 #include "vcn/vcn_3_0_0_sh_mask.h" 35 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 36 37 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x27 38 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x0f 39 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x10 40 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x11 41 #define mmUVD_NO_OP_INTERNAL_OFFSET 0x29 42 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x66 43 #define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d 44 45 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x431 46 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x3b4 47 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x3b5 48 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x25c 49 50 #define VCN_INSTANCES_SIENNA_CICHLID 2 51 52 static int amdgpu_ih_clientid_vcns[] = { 53 SOC15_IH_CLIENTID_VCN, 54 SOC15_IH_CLIENTID_VCN1 55 }; 56 57 static int amdgpu_ucode_id_vcns[] = { 58 AMDGPU_UCODE_ID_VCN, 59 AMDGPU_UCODE_ID_VCN1 60 }; 61 62 static int vcn_v3_0_start_sriov(struct amdgpu_device *adev); 63 static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev); 64 static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev); 65 static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev); 66 static int vcn_v3_0_set_powergating_state(void *handle, 67 enum amd_powergating_state state); 68 static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev, 69 int inst_idx, struct dpg_pause_state *new_state); 70 71 static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring); 72 static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring); 73 74 /** 75 * vcn_v3_0_early_init - set function pointers 76 * 77 * @handle: amdgpu_device pointer 78 * 79 * Set ring and irq function pointers 80 */ 81 static int vcn_v3_0_early_init(void *handle) 82 { 83 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 84 85 if (amdgpu_sriov_vf(adev)) { 86 adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID; 87 adev->vcn.harvest_config = 0; 88 adev->vcn.num_enc_rings = 1; 89 90 } else { 91 if (adev->asic_type == CHIP_SIENNA_CICHLID) { 92 u32 harvest; 93 int i; 94 95 adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID; 96 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 97 harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING); 98 if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK) 99 adev->vcn.harvest_config |= 1 << i; 100 } 101 102 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 | 103 AMDGPU_VCN_HARVEST_VCN1)) 104 /* both instances are harvested, disable the block */ 105 return -ENOENT; 106 } else 107 adev->vcn.num_vcn_inst = 1; 108 109 adev->vcn.num_enc_rings = 2; 110 } 111 112 vcn_v3_0_set_dec_ring_funcs(adev); 113 vcn_v3_0_set_enc_ring_funcs(adev); 114 vcn_v3_0_set_irq_funcs(adev); 115 116 return 0; 117 } 118 119 /** 120 * vcn_v3_0_sw_init - sw init for VCN block 121 * 122 * @handle: amdgpu_device pointer 123 * 124 * Load firmware and sw initialization 125 */ 126 static int vcn_v3_0_sw_init(void *handle) 127 { 128 struct amdgpu_ring *ring; 129 int i, j, r; 130 int vcn_doorbell_index = 0; 131 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 132 133 r = amdgpu_vcn_sw_init(adev); 134 if (r) 135 return r; 136 137 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 138 const struct common_firmware_header *hdr; 139 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 140 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN; 141 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw; 142 adev->firmware.fw_size += 143 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 144 145 if (adev->vcn.num_vcn_inst == VCN_INSTANCES_SIENNA_CICHLID) { 146 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].ucode_id = AMDGPU_UCODE_ID_VCN1; 147 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].fw = adev->vcn.fw; 148 adev->firmware.fw_size += 149 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 150 } 151 DRM_INFO("PSP loading VCN firmware\n"); 152 } 153 154 r = amdgpu_vcn_resume(adev); 155 if (r) 156 return r; 157 158 if (amdgpu_sriov_vf(adev)) { 159 vcn_doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1; 160 /* get DWORD offset */ 161 vcn_doorbell_index = vcn_doorbell_index << 1; 162 } 163 164 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 165 if (adev->vcn.harvest_config & (1 << i)) 166 continue; 167 168 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; 169 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; 170 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; 171 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; 172 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; 173 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; 174 175 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; 176 adev->vcn.inst[i].external.scratch9 = SOC15_REG_OFFSET(VCN, i, mmUVD_SCRATCH9); 177 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; 178 adev->vcn.inst[i].external.data0 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA0); 179 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; 180 adev->vcn.inst[i].external.data1 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA1); 181 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; 182 adev->vcn.inst[i].external.cmd = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_CMD); 183 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; 184 adev->vcn.inst[i].external.nop = SOC15_REG_OFFSET(VCN, i, mmUVD_NO_OP); 185 186 /* VCN DEC TRAP */ 187 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 188 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[i].irq); 189 if (r) 190 return r; 191 192 ring = &adev->vcn.inst[i].ring_dec; 193 ring->use_doorbell = true; 194 if (amdgpu_sriov_vf(adev)) { 195 ring->doorbell_index = vcn_doorbell_index; 196 /* NOTE: increment so next VCN engine use next DOORBELL DWORD */ 197 vcn_doorbell_index++; 198 } else { 199 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i; 200 } 201 if (adev->asic_type == CHIP_SIENNA_CICHLID && i != 0) 202 ring->no_scheduler = true; 203 sprintf(ring->name, "vcn_dec_%d", i); 204 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 205 AMDGPU_RING_PRIO_DEFAULT); 206 if (r) 207 return r; 208 209 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 210 /* VCN ENC TRAP */ 211 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 212 j + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); 213 if (r) 214 return r; 215 216 ring = &adev->vcn.inst[i].ring_enc[j]; 217 ring->use_doorbell = true; 218 if (amdgpu_sriov_vf(adev)) { 219 ring->doorbell_index = vcn_doorbell_index; 220 /* NOTE: increment so next VCN engine use next DOORBELL DWORD */ 221 vcn_doorbell_index++; 222 } else { 223 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + j + 8 * i; 224 } 225 if (adev->asic_type == CHIP_SIENNA_CICHLID && i != 1) 226 ring->no_scheduler = true; 227 sprintf(ring->name, "vcn_enc_%d.%d", i, j); 228 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 229 AMDGPU_RING_PRIO_DEFAULT); 230 if (r) 231 return r; 232 } 233 } 234 235 if (amdgpu_sriov_vf(adev)) { 236 r = amdgpu_virt_alloc_mm_table(adev); 237 if (r) 238 return r; 239 } 240 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 241 adev->vcn.pause_dpg_mode = vcn_v3_0_pause_dpg_mode; 242 243 return 0; 244 } 245 246 /** 247 * vcn_v3_0_sw_fini - sw fini for VCN block 248 * 249 * @handle: amdgpu_device pointer 250 * 251 * VCN suspend and free up sw allocation 252 */ 253 static int vcn_v3_0_sw_fini(void *handle) 254 { 255 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 256 int r; 257 258 if (amdgpu_sriov_vf(adev)) 259 amdgpu_virt_free_mm_table(adev); 260 261 r = amdgpu_vcn_suspend(adev); 262 if (r) 263 return r; 264 265 r = amdgpu_vcn_sw_fini(adev); 266 267 return r; 268 } 269 270 /** 271 * vcn_v3_0_hw_init - start and test VCN block 272 * 273 * @handle: amdgpu_device pointer 274 * 275 * Initialize the hardware, boot up the VCPU and do some testing 276 */ 277 static int vcn_v3_0_hw_init(void *handle) 278 { 279 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 280 struct amdgpu_ring *ring; 281 int i, j, r; 282 283 if (amdgpu_sriov_vf(adev)) { 284 r = vcn_v3_0_start_sriov(adev); 285 if (r) 286 goto done; 287 288 /* initialize VCN dec and enc ring buffers */ 289 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 290 if (adev->vcn.harvest_config & (1 << i)) 291 continue; 292 293 ring = &adev->vcn.inst[i].ring_dec; 294 ring->wptr = 0; 295 ring->wptr_old = 0; 296 vcn_v3_0_dec_ring_set_wptr(ring); 297 ring->sched.ready = true; 298 299 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 300 ring = &adev->vcn.inst[i].ring_enc[j]; 301 ring->wptr = 0; 302 ring->wptr_old = 0; 303 vcn_v3_0_enc_ring_set_wptr(ring); 304 ring->sched.ready = true; 305 } 306 } 307 } else { 308 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 309 if (adev->vcn.harvest_config & (1 << i)) 310 continue; 311 312 ring = &adev->vcn.inst[i].ring_dec; 313 314 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 315 ring->doorbell_index, i); 316 317 r = amdgpu_ring_test_helper(ring); 318 if (r) 319 goto done; 320 321 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 322 ring = &adev->vcn.inst[i].ring_enc[j]; 323 r = amdgpu_ring_test_helper(ring); 324 if (r) 325 goto done; 326 } 327 } 328 } 329 330 done: 331 if (!r) 332 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 333 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 334 335 return r; 336 } 337 338 /** 339 * vcn_v3_0_hw_fini - stop the hardware block 340 * 341 * @handle: amdgpu_device pointer 342 * 343 * Stop the VCN block, mark ring as not ready any more 344 */ 345 static int vcn_v3_0_hw_fini(void *handle) 346 { 347 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 348 struct amdgpu_ring *ring; 349 int i, j; 350 351 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 352 if (adev->vcn.harvest_config & (1 << i)) 353 continue; 354 355 ring = &adev->vcn.inst[i].ring_dec; 356 357 if (!amdgpu_sriov_vf(adev)) { 358 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 359 (adev->vcn.cur_state != AMD_PG_STATE_GATE && 360 RREG32_SOC15(VCN, i, mmUVD_STATUS))) { 361 vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 362 } 363 } 364 ring->sched.ready = false; 365 366 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 367 ring = &adev->vcn.inst[i].ring_enc[j]; 368 ring->sched.ready = false; 369 } 370 } 371 372 return 0; 373 } 374 375 /** 376 * vcn_v3_0_suspend - suspend VCN block 377 * 378 * @handle: amdgpu_device pointer 379 * 380 * HW fini and suspend VCN block 381 */ 382 static int vcn_v3_0_suspend(void *handle) 383 { 384 int r; 385 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 386 387 r = vcn_v3_0_hw_fini(adev); 388 if (r) 389 return r; 390 391 r = amdgpu_vcn_suspend(adev); 392 393 return r; 394 } 395 396 /** 397 * vcn_v3_0_resume - resume VCN block 398 * 399 * @handle: amdgpu_device pointer 400 * 401 * Resume firmware and hw init VCN block 402 */ 403 static int vcn_v3_0_resume(void *handle) 404 { 405 int r; 406 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 407 408 r = amdgpu_vcn_resume(adev); 409 if (r) 410 return r; 411 412 r = vcn_v3_0_hw_init(adev); 413 414 return r; 415 } 416 417 /** 418 * vcn_v3_0_mc_resume - memory controller programming 419 * 420 * @adev: amdgpu_device pointer 421 * @inst: instance number 422 * 423 * Let the VCN memory controller know it's offsets 424 */ 425 static void vcn_v3_0_mc_resume(struct amdgpu_device *adev, int inst) 426 { 427 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 428 uint32_t offset; 429 430 /* cache window 0: fw */ 431 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 432 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 433 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 434 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 435 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 436 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 0); 437 offset = 0; 438 } else { 439 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 440 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 441 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 442 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 443 offset = size; 444 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 445 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 446 } 447 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE0, size); 448 449 /* cache window 1: stack */ 450 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 451 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 452 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 453 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 454 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET1, 0); 455 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 456 457 /* cache window 2: context */ 458 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 459 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 460 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 461 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 462 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET2, 0); 463 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 464 } 465 466 static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 467 { 468 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 469 uint32_t offset; 470 471 /* cache window 0: fw */ 472 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 473 if (!indirect) { 474 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 475 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 476 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); 477 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 478 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 479 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); 480 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 481 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 482 } else { 483 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 484 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 485 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 486 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 487 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 488 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 489 } 490 offset = 0; 491 } else { 492 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 493 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 494 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 495 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 496 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 497 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 498 offset = size; 499 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 500 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 501 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 502 } 503 504 if (!indirect) 505 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 506 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 507 else 508 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 509 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 510 511 /* cache window 1: stack */ 512 if (!indirect) { 513 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 514 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 515 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 516 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 517 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 518 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 519 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 520 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 521 } else { 522 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 523 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 524 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 525 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 526 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 527 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 528 } 529 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 530 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 531 532 /* cache window 2: context */ 533 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 534 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 535 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 536 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 537 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 538 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 539 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 540 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 541 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 542 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 543 544 /* non-cache window */ 545 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 546 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect); 547 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 548 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect); 549 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 550 VCN, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 551 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 552 VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect); 553 } 554 555 static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int inst) 556 { 557 uint32_t data = 0; 558 559 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 560 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 561 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 562 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 563 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 564 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 565 | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 566 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 567 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 568 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 569 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 570 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 571 | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 572 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 573 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 574 575 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 576 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 577 UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF); 578 } else { 579 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 580 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 581 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 582 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 583 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 584 | 1 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 585 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 586 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 587 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 588 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 589 | 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 590 | 1 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 591 | 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 592 | 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 593 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 594 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 0, 0x3F3FFFFF); 595 } 596 597 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); 598 data &= ~0x103; 599 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 600 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 601 UVD_POWER_STATUS__UVD_PG_EN_MASK; 602 603 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); 604 } 605 606 static void vcn_v3_0_enable_static_power_gating(struct amdgpu_device *adev, int inst) 607 { 608 uint32_t data; 609 610 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 611 /* Before power off, this indicator has to be turned on */ 612 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); 613 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 614 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 615 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); 616 617 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 618 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 619 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 620 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 621 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 622 | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 623 | 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 624 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 625 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 626 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 627 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 628 | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 629 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 630 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 631 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 632 633 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 634 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 635 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 636 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 637 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 638 | 2 << UVD_PGFSM_STATUS__UVDIRL_PWR_STATUS__SHIFT 639 | 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT 640 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 641 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 642 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 643 | 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT 644 | 2 << UVD_PGFSM_STATUS__UVDATD_PWR_STATUS__SHIFT 645 | 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT 646 | 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT); 647 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, data, 0x3F3FFFFF); 648 } 649 } 650 651 /** 652 * vcn_v3_0_disable_clock_gating - disable VCN clock gating 653 * 654 * @adev: amdgpu_device pointer 655 * @inst: instance number 656 * 657 * Disable clock gating for VCN block 658 */ 659 static void vcn_v3_0_disable_clock_gating(struct amdgpu_device *adev, int inst) 660 { 661 uint32_t data; 662 663 /* VCN disable CGC */ 664 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 665 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 666 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 667 else 668 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 669 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 670 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 671 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 672 673 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_GATE); 674 data &= ~(UVD_CGC_GATE__SYS_MASK 675 | UVD_CGC_GATE__UDEC_MASK 676 | UVD_CGC_GATE__MPEG2_MASK 677 | UVD_CGC_GATE__REGS_MASK 678 | UVD_CGC_GATE__RBC_MASK 679 | UVD_CGC_GATE__LMI_MC_MASK 680 | UVD_CGC_GATE__LMI_UMC_MASK 681 | UVD_CGC_GATE__IDCT_MASK 682 | UVD_CGC_GATE__MPRD_MASK 683 | UVD_CGC_GATE__MPC_MASK 684 | UVD_CGC_GATE__LBSI_MASK 685 | UVD_CGC_GATE__LRBBM_MASK 686 | UVD_CGC_GATE__UDEC_RE_MASK 687 | UVD_CGC_GATE__UDEC_CM_MASK 688 | UVD_CGC_GATE__UDEC_IT_MASK 689 | UVD_CGC_GATE__UDEC_DB_MASK 690 | UVD_CGC_GATE__UDEC_MP_MASK 691 | UVD_CGC_GATE__WCB_MASK 692 | UVD_CGC_GATE__VCPU_MASK 693 | UVD_CGC_GATE__MMSCH_MASK); 694 695 WREG32_SOC15(VCN, inst, mmUVD_CGC_GATE, data); 696 697 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); 698 699 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 700 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 701 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 702 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 703 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 704 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 705 | UVD_CGC_CTRL__SYS_MODE_MASK 706 | UVD_CGC_CTRL__UDEC_MODE_MASK 707 | UVD_CGC_CTRL__MPEG2_MODE_MASK 708 | UVD_CGC_CTRL__REGS_MODE_MASK 709 | UVD_CGC_CTRL__RBC_MODE_MASK 710 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 711 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 712 | UVD_CGC_CTRL__IDCT_MODE_MASK 713 | UVD_CGC_CTRL__MPRD_MODE_MASK 714 | UVD_CGC_CTRL__MPC_MODE_MASK 715 | UVD_CGC_CTRL__LBSI_MODE_MASK 716 | UVD_CGC_CTRL__LRBBM_MODE_MASK 717 | UVD_CGC_CTRL__WCB_MODE_MASK 718 | UVD_CGC_CTRL__VCPU_MODE_MASK 719 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 720 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 721 722 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE); 723 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 724 | UVD_SUVD_CGC_GATE__SIT_MASK 725 | UVD_SUVD_CGC_GATE__SMP_MASK 726 | UVD_SUVD_CGC_GATE__SCM_MASK 727 | UVD_SUVD_CGC_GATE__SDB_MASK 728 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 729 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 730 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 731 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 732 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 733 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 734 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 735 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 736 | UVD_SUVD_CGC_GATE__SCLR_MASK 737 | UVD_SUVD_CGC_GATE__ENT_MASK 738 | UVD_SUVD_CGC_GATE__IME_MASK 739 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 740 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 741 | UVD_SUVD_CGC_GATE__SITE_MASK 742 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 743 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 744 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 745 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 746 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK 747 | UVD_SUVD_CGC_GATE__EFC_MASK 748 | UVD_SUVD_CGC_GATE__SAOE_MASK 749 | UVD_SUVD_CGC_GATE__SRE_AV1_MASK 750 | UVD_SUVD_CGC_GATE__FBC_PCLK_MASK 751 | UVD_SUVD_CGC_GATE__FBC_CCLK_MASK 752 | UVD_SUVD_CGC_GATE__SCM_AV1_MASK 753 | UVD_SUVD_CGC_GATE__SMPA_MASK); 754 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE, data); 755 756 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2); 757 data |= (UVD_SUVD_CGC_GATE2__MPBE0_MASK 758 | UVD_SUVD_CGC_GATE2__MPBE1_MASK 759 | UVD_SUVD_CGC_GATE2__SIT_AV1_MASK 760 | UVD_SUVD_CGC_GATE2__SDB_AV1_MASK 761 | UVD_SUVD_CGC_GATE2__MPC1_MASK); 762 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2, data); 763 764 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL); 765 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 766 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 767 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 768 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 769 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 770 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 771 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 772 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 773 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 774 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 775 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK 776 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK 777 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK 778 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK 779 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 780 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 781 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK 782 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK 783 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK); 784 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data); 785 } 786 787 static void vcn_v3_0_clock_gating_dpg_mode(struct amdgpu_device *adev, 788 uint8_t sram_sel, int inst_idx, uint8_t indirect) 789 { 790 uint32_t reg_data = 0; 791 792 /* enable sw clock gating control */ 793 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 794 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 795 else 796 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 797 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 798 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 799 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 800 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 801 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 802 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 803 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 804 UVD_CGC_CTRL__SYS_MODE_MASK | 805 UVD_CGC_CTRL__UDEC_MODE_MASK | 806 UVD_CGC_CTRL__MPEG2_MODE_MASK | 807 UVD_CGC_CTRL__REGS_MODE_MASK | 808 UVD_CGC_CTRL__RBC_MODE_MASK | 809 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 810 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 811 UVD_CGC_CTRL__IDCT_MODE_MASK | 812 UVD_CGC_CTRL__MPRD_MODE_MASK | 813 UVD_CGC_CTRL__MPC_MODE_MASK | 814 UVD_CGC_CTRL__LBSI_MODE_MASK | 815 UVD_CGC_CTRL__LRBBM_MODE_MASK | 816 UVD_CGC_CTRL__WCB_MODE_MASK | 817 UVD_CGC_CTRL__VCPU_MODE_MASK | 818 UVD_CGC_CTRL__MMSCH_MODE_MASK); 819 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 820 VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); 821 822 /* turn off clock gating */ 823 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 824 VCN, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect); 825 826 /* turn on SUVD clock gating */ 827 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 828 VCN, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 829 830 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 831 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 832 VCN, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 833 } 834 835 /** 836 * vcn_v3_0_enable_clock_gating - enable VCN clock gating 837 * 838 * @adev: amdgpu_device pointer 839 * @inst: instance number 840 * 841 * Enable clock gating for VCN block 842 */ 843 static void vcn_v3_0_enable_clock_gating(struct amdgpu_device *adev, int inst) 844 { 845 uint32_t data; 846 847 /* enable VCN CGC */ 848 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 849 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 850 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 851 else 852 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 853 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 854 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 855 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 856 857 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 858 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 859 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 860 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 861 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 862 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 863 | UVD_CGC_CTRL__SYS_MODE_MASK 864 | UVD_CGC_CTRL__UDEC_MODE_MASK 865 | UVD_CGC_CTRL__MPEG2_MODE_MASK 866 | UVD_CGC_CTRL__REGS_MODE_MASK 867 | UVD_CGC_CTRL__RBC_MODE_MASK 868 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 869 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 870 | UVD_CGC_CTRL__IDCT_MODE_MASK 871 | UVD_CGC_CTRL__MPRD_MODE_MASK 872 | UVD_CGC_CTRL__MPC_MODE_MASK 873 | UVD_CGC_CTRL__LBSI_MODE_MASK 874 | UVD_CGC_CTRL__LRBBM_MODE_MASK 875 | UVD_CGC_CTRL__WCB_MODE_MASK 876 | UVD_CGC_CTRL__VCPU_MODE_MASK 877 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 878 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 879 880 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL); 881 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 882 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 883 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 884 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 885 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 886 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 887 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 888 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 889 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 890 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 891 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK 892 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK 893 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK 894 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK 895 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 896 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 897 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK 898 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK 899 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK); 900 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data); 901 } 902 903 static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 904 { 905 struct amdgpu_ring *ring; 906 uint32_t rb_bufsz, tmp; 907 908 /* disable register anti-hang mechanism */ 909 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1, 910 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 911 /* enable dynamic power gating mode */ 912 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS); 913 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 914 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 915 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp); 916 917 if (indirect) 918 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t*)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 919 920 /* enable clock gating */ 921 vcn_v3_0_clock_gating_dpg_mode(adev, 0, inst_idx, indirect); 922 923 /* enable VCPU clock */ 924 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 925 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 926 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK; 927 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 928 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 929 930 /* disable master interupt */ 931 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 932 VCN, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect); 933 934 /* setup mmUVD_LMI_CTRL */ 935 tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 936 UVD_LMI_CTRL__REQ_MODE_MASK | 937 UVD_LMI_CTRL__CRC_RESET_MASK | 938 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 939 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 940 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 941 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 942 0x00100000L); 943 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 944 VCN, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect); 945 946 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 947 VCN, inst_idx, mmUVD_MPC_CNTL), 948 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 949 950 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 951 VCN, inst_idx, mmUVD_MPC_SET_MUXA0), 952 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 953 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 954 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 955 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 956 957 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 958 VCN, inst_idx, mmUVD_MPC_SET_MUXB0), 959 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 960 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 961 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 962 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 963 964 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 965 VCN, inst_idx, mmUVD_MPC_SET_MUX), 966 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 967 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 968 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 969 970 vcn_v3_0_mc_resume_dpg_mode(adev, inst_idx, indirect); 971 972 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 973 VCN, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect); 974 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 975 VCN, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect); 976 977 /* enable LMI MC and UMC channels */ 978 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 979 VCN, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect); 980 981 /* unblock VCPU register access */ 982 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 983 VCN, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect); 984 985 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 986 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 987 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 988 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 989 990 /* enable master interrupt */ 991 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 992 VCN, inst_idx, mmUVD_MASTINT_EN), 993 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 994 995 /* add nop to workaround PSP size check */ 996 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 997 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 998 999 if (indirect) 1000 psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, 1001 (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr - 1002 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr)); 1003 1004 ring = &adev->vcn.inst[inst_idx].ring_dec; 1005 /* force RBC into idle state */ 1006 rb_bufsz = order_base_2(ring->ring_size); 1007 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1008 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1009 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1010 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1011 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1012 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp); 1013 1014 /* Stall DPG before WPTR/RPTR reset */ 1015 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1016 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1017 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1018 1019 /* set the write pointer delay */ 1020 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0); 1021 1022 /* set the wb address */ 1023 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR, 1024 (upper_32_bits(ring->gpu_addr) >> 2)); 1025 1026 /* programm the RB_BASE for ring buffer */ 1027 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1028 lower_32_bits(ring->gpu_addr)); 1029 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1030 upper_32_bits(ring->gpu_addr)); 1031 1032 /* Initialize the ring buffer's read and write pointers */ 1033 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0); 1034 1035 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0); 1036 1037 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR); 1038 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, 1039 lower_32_bits(ring->wptr)); 1040 1041 /* Unstall DPG */ 1042 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1043 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1044 1045 return 0; 1046 } 1047 1048 static int vcn_v3_0_start(struct amdgpu_device *adev) 1049 { 1050 struct amdgpu_ring *ring; 1051 uint32_t rb_bufsz, tmp; 1052 int i, j, k, r; 1053 1054 if (adev->pm.dpm_enabled) 1055 amdgpu_dpm_enable_uvd(adev, true); 1056 1057 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1058 if (adev->vcn.harvest_config & (1 << i)) 1059 continue; 1060 1061 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG){ 1062 r = vcn_v3_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram); 1063 continue; 1064 } 1065 1066 /* disable VCN power gating */ 1067 vcn_v3_0_disable_static_power_gating(adev, i); 1068 1069 /* set VCN status busy */ 1070 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 1071 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp); 1072 1073 /*SW clock gating */ 1074 vcn_v3_0_disable_clock_gating(adev, i); 1075 1076 /* enable VCPU clock */ 1077 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1078 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 1079 1080 /* disable master interrupt */ 1081 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0, 1082 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1083 1084 /* enable LMI MC and UMC channels */ 1085 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0, 1086 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1087 1088 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1089 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1090 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1091 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1092 1093 /* setup mmUVD_LMI_CTRL */ 1094 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL); 1095 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | 1096 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1097 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1098 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1099 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1100 1101 /* setup mmUVD_MPC_CNTL */ 1102 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL); 1103 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1104 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1105 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp); 1106 1107 /* setup UVD_MPC_SET_MUXA0 */ 1108 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0, 1109 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1110 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1111 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1112 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1113 1114 /* setup UVD_MPC_SET_MUXB0 */ 1115 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0, 1116 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1117 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1118 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1119 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1120 1121 /* setup mmUVD_MPC_SET_MUX */ 1122 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX, 1123 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1124 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1125 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1126 1127 vcn_v3_0_mc_resume(adev, i); 1128 1129 /* VCN global tiling registers */ 1130 WREG32_SOC15(VCN, i, mmUVD_GFX10_ADDR_CONFIG, 1131 adev->gfx.config.gb_addr_config); 1132 1133 /* unblock VCPU register access */ 1134 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0, 1135 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1136 1137 /* release VCPU reset to boot */ 1138 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1139 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1140 1141 for (j = 0; j < 10; ++j) { 1142 uint32_t status; 1143 1144 for (k = 0; k < 100; ++k) { 1145 status = RREG32_SOC15(VCN, i, mmUVD_STATUS); 1146 if (status & 2) 1147 break; 1148 mdelay(10); 1149 } 1150 r = 0; 1151 if (status & 2) 1152 break; 1153 1154 DRM_ERROR("VCN[%d] decode not responding, trying to reset the VCPU!!!\n", i); 1155 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1156 UVD_VCPU_CNTL__BLK_RST_MASK, 1157 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1158 mdelay(10); 1159 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1160 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1161 1162 mdelay(10); 1163 r = -1; 1164 } 1165 1166 if (r) { 1167 DRM_ERROR("VCN[%d] decode not responding, giving up!!!\n", i); 1168 return r; 1169 } 1170 1171 /* enable master interrupt */ 1172 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 1173 UVD_MASTINT_EN__VCPU_EN_MASK, 1174 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1175 1176 /* clear the busy bit of VCN_STATUS */ 1177 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0, 1178 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1179 1180 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0); 1181 1182 ring = &adev->vcn.inst[i].ring_dec; 1183 /* force RBC into idle state */ 1184 rb_bufsz = order_base_2(ring->ring_size); 1185 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1186 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1187 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1188 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1189 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1190 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp); 1191 1192 /* programm the RB_BASE for ring buffer */ 1193 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1194 lower_32_bits(ring->gpu_addr)); 1195 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1196 upper_32_bits(ring->gpu_addr)); 1197 1198 /* Initialize the ring buffer's read and write pointers */ 1199 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0); 1200 1201 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR); 1202 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR, 1203 lower_32_bits(ring->wptr)); 1204 ring = &adev->vcn.inst[i].ring_enc[0]; 1205 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1206 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1207 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr); 1208 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1209 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4); 1210 1211 ring = &adev->vcn.inst[i].ring_enc[1]; 1212 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1213 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1214 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1215 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1216 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4); 1217 } 1218 1219 return 0; 1220 } 1221 1222 static int vcn_v3_0_start_sriov(struct amdgpu_device *adev) 1223 { 1224 int i, j; 1225 struct amdgpu_ring *ring; 1226 uint64_t cache_addr; 1227 uint64_t rb_addr; 1228 uint64_t ctx_addr; 1229 uint32_t param, resp, expected; 1230 uint32_t offset, cache_size; 1231 uint32_t tmp, timeout; 1232 uint32_t id; 1233 1234 struct amdgpu_mm_table *table = &adev->virt.mm_table; 1235 uint32_t *table_loc; 1236 uint32_t table_size; 1237 uint32_t size, size_dw; 1238 1239 struct mmsch_v3_0_cmd_direct_write 1240 direct_wt = { {0} }; 1241 struct mmsch_v3_0_cmd_direct_read_modify_write 1242 direct_rd_mod_wt = { {0} }; 1243 struct mmsch_v3_0_cmd_direct_polling 1244 direct_poll = { {0} }; 1245 struct mmsch_v3_0_cmd_end end = { {0} }; 1246 struct mmsch_v3_0_init_header header; 1247 1248 direct_wt.cmd_header.command_type = 1249 MMSCH_COMMAND__DIRECT_REG_WRITE; 1250 direct_rd_mod_wt.cmd_header.command_type = 1251 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1252 direct_poll.cmd_header.command_type = 1253 MMSCH_COMMAND__DIRECT_REG_POLLING; 1254 end.cmd_header.command_type = 1255 MMSCH_COMMAND__END; 1256 1257 header.version = MMSCH_VERSION; 1258 header.total_size = sizeof(struct mmsch_v3_0_init_header) >> 2; 1259 for (i = 0; i < AMDGPU_MAX_VCN_INSTANCES; i++) { 1260 header.inst[i].init_status = 0; 1261 header.inst[i].table_offset = 0; 1262 header.inst[i].table_size = 0; 1263 } 1264 1265 table_loc = (uint32_t *)table->cpu_addr; 1266 table_loc += header.total_size; 1267 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1268 if (adev->vcn.harvest_config & (1 << i)) 1269 continue; 1270 1271 table_size = 0; 1272 1273 MMSCH_V3_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i, 1274 mmUVD_STATUS), 1275 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 1276 1277 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 1278 1279 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1280 id = amdgpu_ucode_id_vcns[i]; 1281 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1282 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1283 adev->firmware.ucode[id].tmr_mc_addr_lo); 1284 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1285 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1286 adev->firmware.ucode[id].tmr_mc_addr_hi); 1287 offset = 0; 1288 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1289 mmUVD_VCPU_CACHE_OFFSET0), 1290 0); 1291 } else { 1292 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1293 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1294 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 1295 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1296 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1297 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 1298 offset = cache_size; 1299 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1300 mmUVD_VCPU_CACHE_OFFSET0), 1301 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 1302 } 1303 1304 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1305 mmUVD_VCPU_CACHE_SIZE0), 1306 cache_size); 1307 1308 cache_addr = adev->vcn.inst[i].gpu_addr + offset; 1309 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1310 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 1311 lower_32_bits(cache_addr)); 1312 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1313 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 1314 upper_32_bits(cache_addr)); 1315 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1316 mmUVD_VCPU_CACHE_OFFSET1), 1317 0); 1318 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1319 mmUVD_VCPU_CACHE_SIZE1), 1320 AMDGPU_VCN_STACK_SIZE); 1321 1322 cache_addr = adev->vcn.inst[i].gpu_addr + offset + 1323 AMDGPU_VCN_STACK_SIZE; 1324 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1325 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 1326 lower_32_bits(cache_addr)); 1327 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1328 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 1329 upper_32_bits(cache_addr)); 1330 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1331 mmUVD_VCPU_CACHE_OFFSET2), 1332 0); 1333 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1334 mmUVD_VCPU_CACHE_SIZE2), 1335 AMDGPU_VCN_CONTEXT_SIZE); 1336 1337 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 1338 ring = &adev->vcn.inst[i].ring_enc[j]; 1339 ring->wptr = 0; 1340 rb_addr = ring->gpu_addr; 1341 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1342 mmUVD_RB_BASE_LO), 1343 lower_32_bits(rb_addr)); 1344 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1345 mmUVD_RB_BASE_HI), 1346 upper_32_bits(rb_addr)); 1347 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1348 mmUVD_RB_SIZE), 1349 ring->ring_size / 4); 1350 } 1351 1352 ring = &adev->vcn.inst[i].ring_dec; 1353 ring->wptr = 0; 1354 rb_addr = ring->gpu_addr; 1355 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1356 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW), 1357 lower_32_bits(rb_addr)); 1358 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1359 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH), 1360 upper_32_bits(rb_addr)); 1361 /* force RBC into idle state */ 1362 tmp = order_base_2(ring->ring_size); 1363 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp); 1364 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1365 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1366 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1367 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1368 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1369 mmUVD_RBC_RB_CNTL), 1370 tmp); 1371 1372 /* add end packet */ 1373 MMSCH_V3_0_INSERT_END(); 1374 1375 /* refine header */ 1376 header.inst[i].init_status = 1; 1377 header.inst[i].table_offset = header.total_size; 1378 header.inst[i].table_size = table_size; 1379 header.total_size += table_size; 1380 } 1381 1382 /* Update init table header in memory */ 1383 size = sizeof(struct mmsch_v3_0_init_header); 1384 table_loc = (uint32_t *)table->cpu_addr; 1385 memcpy((void *)table_loc, &header, size); 1386 1387 /* message MMSCH (in VCN[0]) to initialize this client 1388 * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr 1389 * of memory descriptor location 1390 */ 1391 ctx_addr = table->gpu_addr; 1392 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 1393 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 1394 1395 /* 2, update vmid of descriptor */ 1396 tmp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID); 1397 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1398 /* use domain0 for MM scheduler */ 1399 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1400 WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, tmp); 1401 1402 /* 3, notify mmsch about the size of this descriptor */ 1403 size = header.total_size; 1404 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size); 1405 1406 /* 4, set resp to zero */ 1407 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0); 1408 1409 /* 5, kick off the initialization and wait until 1410 * MMSCH_VF_MAILBOX_RESP becomes non-zero 1411 */ 1412 param = 0x10000001; 1413 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, param); 1414 tmp = 0; 1415 timeout = 1000; 1416 resp = 0; 1417 expected = param + 1; 1418 while (resp != expected) { 1419 resp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); 1420 if (resp == expected) 1421 break; 1422 1423 udelay(10); 1424 tmp = tmp + 10; 1425 if (tmp >= timeout) { 1426 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 1427 " waiting for mmMMSCH_VF_MAILBOX_RESP "\ 1428 "(expected=0x%08x, readback=0x%08x)\n", 1429 tmp, expected, resp); 1430 return -EBUSY; 1431 } 1432 } 1433 1434 return 0; 1435 } 1436 1437 static int vcn_v3_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) 1438 { 1439 uint32_t tmp; 1440 1441 /* Wait for power status to be 1 */ 1442 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1443 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1444 1445 /* wait for read ptr to be equal to write ptr */ 1446 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR); 1447 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1448 1449 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2); 1450 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); 1451 1452 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1453 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); 1454 1455 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1456 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1457 1458 /* disable dynamic power gating mode */ 1459 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0, 1460 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1461 1462 return 0; 1463 } 1464 1465 static int vcn_v3_0_stop(struct amdgpu_device *adev) 1466 { 1467 uint32_t tmp; 1468 int i, r = 0; 1469 1470 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1471 if (adev->vcn.harvest_config & (1 << i)) 1472 continue; 1473 1474 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1475 r = vcn_v3_0_stop_dpg_mode(adev, i); 1476 continue; 1477 } 1478 1479 /* wait for vcn idle */ 1480 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1481 if (r) 1482 return r; 1483 1484 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1485 UVD_LMI_STATUS__READ_CLEAN_MASK | 1486 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1487 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1488 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1489 if (r) 1490 return r; 1491 1492 /* disable LMI UMC channel */ 1493 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2); 1494 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1495 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp); 1496 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK| 1497 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1498 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1499 if (r) 1500 return r; 1501 1502 /* block VCPU register access */ 1503 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 1504 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1505 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1506 1507 /* reset VCPU */ 1508 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1509 UVD_VCPU_CNTL__BLK_RST_MASK, 1510 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1511 1512 /* disable VCPU clock */ 1513 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1514 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1515 1516 /* apply soft reset */ 1517 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1518 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1519 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1520 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1521 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1522 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1523 1524 /* clear status */ 1525 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0); 1526 1527 /* apply HW clock gating */ 1528 vcn_v3_0_enable_clock_gating(adev, i); 1529 1530 /* enable VCN power gating */ 1531 vcn_v3_0_enable_static_power_gating(adev, i); 1532 } 1533 1534 if (adev->pm.dpm_enabled) 1535 amdgpu_dpm_enable_uvd(adev, false); 1536 1537 return 0; 1538 } 1539 1540 static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev, 1541 int inst_idx, struct dpg_pause_state *new_state) 1542 { 1543 struct amdgpu_ring *ring; 1544 uint32_t reg_data = 0; 1545 int ret_code; 1546 1547 /* pause/unpause if state is changed */ 1548 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1549 DRM_DEBUG("dpg pause state changed %d -> %d", 1550 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1551 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) & 1552 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1553 1554 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1555 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, 1556 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1557 1558 if (!ret_code) { 1559 /* pause DPG */ 1560 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1561 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1562 1563 /* wait for ACK */ 1564 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE, 1565 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1566 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1567 1568 /* Stall DPG before WPTR/RPTR reset */ 1569 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1570 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1571 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1572 1573 /* Restore */ 1574 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 1575 ring->wptr = 0; 1576 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr); 1577 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1578 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4); 1579 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1580 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1581 1582 ring = &adev->vcn.inst[inst_idx].ring_enc[1]; 1583 ring->wptr = 0; 1584 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1585 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1586 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4); 1587 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1588 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1589 1590 /* Unstall DPG */ 1591 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1592 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1593 1594 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1595 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1596 } 1597 } else { 1598 /* unpause dpg, no need to wait */ 1599 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1600 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1601 } 1602 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1603 } 1604 1605 return 0; 1606 } 1607 1608 /** 1609 * vcn_v3_0_dec_ring_get_rptr - get read pointer 1610 * 1611 * @ring: amdgpu_ring pointer 1612 * 1613 * Returns the current hardware read pointer 1614 */ 1615 static uint64_t vcn_v3_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 1616 { 1617 struct amdgpu_device *adev = ring->adev; 1618 1619 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR); 1620 } 1621 1622 /** 1623 * vcn_v3_0_dec_ring_get_wptr - get write pointer 1624 * 1625 * @ring: amdgpu_ring pointer 1626 * 1627 * Returns the current hardware write pointer 1628 */ 1629 static uint64_t vcn_v3_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 1630 { 1631 struct amdgpu_device *adev = ring->adev; 1632 1633 if (ring->use_doorbell) 1634 return adev->wb.wb[ring->wptr_offs]; 1635 else 1636 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR); 1637 } 1638 1639 /** 1640 * vcn_v3_0_dec_ring_set_wptr - set write pointer 1641 * 1642 * @ring: amdgpu_ring pointer 1643 * 1644 * Commits the write pointer to the hardware 1645 */ 1646 static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 1647 { 1648 struct amdgpu_device *adev = ring->adev; 1649 1650 if (ring->use_doorbell) { 1651 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 1652 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1653 } else { 1654 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1655 } 1656 } 1657 1658 static const struct amdgpu_ring_funcs vcn_v3_0_dec_ring_vm_funcs = { 1659 .type = AMDGPU_RING_TYPE_VCN_DEC, 1660 .align_mask = 0xf, 1661 .vmhub = AMDGPU_MMHUB_0, 1662 .get_rptr = vcn_v3_0_dec_ring_get_rptr, 1663 .get_wptr = vcn_v3_0_dec_ring_get_wptr, 1664 .set_wptr = vcn_v3_0_dec_ring_set_wptr, 1665 .emit_frame_size = 1666 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1667 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1668 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */ 1669 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */ 1670 6, 1671 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */ 1672 .emit_ib = vcn_v2_0_dec_ring_emit_ib, 1673 .emit_fence = vcn_v2_0_dec_ring_emit_fence, 1674 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush, 1675 .test_ring = vcn_v2_0_dec_ring_test_ring, 1676 .test_ib = amdgpu_vcn_dec_ring_test_ib, 1677 .insert_nop = vcn_v2_0_dec_ring_insert_nop, 1678 .insert_start = vcn_v2_0_dec_ring_insert_start, 1679 .insert_end = vcn_v2_0_dec_ring_insert_end, 1680 .pad_ib = amdgpu_ring_generic_pad_ib, 1681 .begin_use = amdgpu_vcn_ring_begin_use, 1682 .end_use = amdgpu_vcn_ring_end_use, 1683 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg, 1684 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait, 1685 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1686 }; 1687 1688 /** 1689 * vcn_v3_0_enc_ring_get_rptr - get enc read pointer 1690 * 1691 * @ring: amdgpu_ring pointer 1692 * 1693 * Returns the current hardware enc read pointer 1694 */ 1695 static uint64_t vcn_v3_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 1696 { 1697 struct amdgpu_device *adev = ring->adev; 1698 1699 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) 1700 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR); 1701 else 1702 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2); 1703 } 1704 1705 /** 1706 * vcn_v3_0_enc_ring_get_wptr - get enc write pointer 1707 * 1708 * @ring: amdgpu_ring pointer 1709 * 1710 * Returns the current hardware enc write pointer 1711 */ 1712 static uint64_t vcn_v3_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 1713 { 1714 struct amdgpu_device *adev = ring->adev; 1715 1716 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 1717 if (ring->use_doorbell) 1718 return adev->wb.wb[ring->wptr_offs]; 1719 else 1720 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR); 1721 } else { 1722 if (ring->use_doorbell) 1723 return adev->wb.wb[ring->wptr_offs]; 1724 else 1725 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2); 1726 } 1727 } 1728 1729 /** 1730 * vcn_v3_0_enc_ring_set_wptr - set enc write pointer 1731 * 1732 * @ring: amdgpu_ring pointer 1733 * 1734 * Commits the enc write pointer to the hardware 1735 */ 1736 static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 1737 { 1738 struct amdgpu_device *adev = ring->adev; 1739 1740 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 1741 if (ring->use_doorbell) { 1742 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 1743 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1744 } else { 1745 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1746 } 1747 } else { 1748 if (ring->use_doorbell) { 1749 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 1750 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1751 } else { 1752 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1753 } 1754 } 1755 } 1756 1757 static const struct amdgpu_ring_funcs vcn_v3_0_enc_ring_vm_funcs = { 1758 .type = AMDGPU_RING_TYPE_VCN_ENC, 1759 .align_mask = 0x3f, 1760 .nop = VCN_ENC_CMD_NO_OP, 1761 .vmhub = AMDGPU_MMHUB_0, 1762 .get_rptr = vcn_v3_0_enc_ring_get_rptr, 1763 .get_wptr = vcn_v3_0_enc_ring_get_wptr, 1764 .set_wptr = vcn_v3_0_enc_ring_set_wptr, 1765 .emit_frame_size = 1766 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1767 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1768 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1769 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1770 1, /* vcn_v2_0_enc_ring_insert_end */ 1771 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1772 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1773 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1774 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 1775 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1776 .test_ib = amdgpu_vcn_enc_ring_test_ib, 1777 .insert_nop = amdgpu_ring_insert_nop, 1778 .insert_end = vcn_v2_0_enc_ring_insert_end, 1779 .pad_ib = amdgpu_ring_generic_pad_ib, 1780 .begin_use = amdgpu_vcn_ring_begin_use, 1781 .end_use = amdgpu_vcn_ring_end_use, 1782 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 1783 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 1784 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1785 }; 1786 1787 static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev) 1788 { 1789 int i; 1790 1791 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1792 if (adev->vcn.harvest_config & (1 << i)) 1793 continue; 1794 1795 adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_ring_vm_funcs; 1796 adev->vcn.inst[i].ring_dec.me = i; 1797 DRM_INFO("VCN(%d) decode is enabled in VM mode\n", i); 1798 } 1799 } 1800 1801 static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev) 1802 { 1803 int i, j; 1804 1805 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1806 if (adev->vcn.harvest_config & (1 << i)) 1807 continue; 1808 1809 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 1810 adev->vcn.inst[i].ring_enc[j].funcs = &vcn_v3_0_enc_ring_vm_funcs; 1811 adev->vcn.inst[i].ring_enc[j].me = i; 1812 } 1813 DRM_INFO("VCN(%d) encode is enabled in VM mode\n", i); 1814 } 1815 } 1816 1817 static bool vcn_v3_0_is_idle(void *handle) 1818 { 1819 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1820 int i, ret = 1; 1821 1822 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1823 if (adev->vcn.harvest_config & (1 << i)) 1824 continue; 1825 1826 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); 1827 } 1828 1829 return ret; 1830 } 1831 1832 static int vcn_v3_0_wait_for_idle(void *handle) 1833 { 1834 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1835 int i, ret = 0; 1836 1837 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1838 if (adev->vcn.harvest_config & (1 << i)) 1839 continue; 1840 1841 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 1842 UVD_STATUS__IDLE); 1843 if (ret) 1844 return ret; 1845 } 1846 1847 return ret; 1848 } 1849 1850 static int vcn_v3_0_set_clockgating_state(void *handle, 1851 enum amd_clockgating_state state) 1852 { 1853 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1854 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 1855 int i; 1856 1857 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1858 if (adev->vcn.harvest_config & (1 << i)) 1859 continue; 1860 1861 if (enable) { 1862 if (RREG32_SOC15(VCN, i, mmUVD_STATUS) != UVD_STATUS__IDLE) 1863 return -EBUSY; 1864 vcn_v3_0_enable_clock_gating(adev, i); 1865 } else { 1866 vcn_v3_0_disable_clock_gating(adev, i); 1867 } 1868 } 1869 1870 return 0; 1871 } 1872 1873 static int vcn_v3_0_set_powergating_state(void *handle, 1874 enum amd_powergating_state state) 1875 { 1876 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1877 int ret; 1878 1879 /* for SRIOV, guest should not control VCN Power-gating 1880 * MMSCH FW should control Power-gating and clock-gating 1881 * guest should avoid touching CGC and PG 1882 */ 1883 if (amdgpu_sriov_vf(adev)) { 1884 adev->vcn.cur_state = AMD_PG_STATE_UNGATE; 1885 return 0; 1886 } 1887 1888 if(state == adev->vcn.cur_state) 1889 return 0; 1890 1891 if (state == AMD_PG_STATE_GATE) 1892 ret = vcn_v3_0_stop(adev); 1893 else 1894 ret = vcn_v3_0_start(adev); 1895 1896 if(!ret) 1897 adev->vcn.cur_state = state; 1898 1899 return ret; 1900 } 1901 1902 static int vcn_v3_0_set_interrupt_state(struct amdgpu_device *adev, 1903 struct amdgpu_irq_src *source, 1904 unsigned type, 1905 enum amdgpu_interrupt_state state) 1906 { 1907 return 0; 1908 } 1909 1910 static int vcn_v3_0_process_interrupt(struct amdgpu_device *adev, 1911 struct amdgpu_irq_src *source, 1912 struct amdgpu_iv_entry *entry) 1913 { 1914 uint32_t ip_instance; 1915 1916 switch (entry->client_id) { 1917 case SOC15_IH_CLIENTID_VCN: 1918 ip_instance = 0; 1919 break; 1920 case SOC15_IH_CLIENTID_VCN1: 1921 ip_instance = 1; 1922 break; 1923 default: 1924 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 1925 return 0; 1926 } 1927 1928 DRM_DEBUG("IH: VCN TRAP\n"); 1929 1930 switch (entry->src_id) { 1931 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT: 1932 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec); 1933 break; 1934 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1935 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 1936 break; 1937 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY: 1938 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]); 1939 break; 1940 default: 1941 DRM_ERROR("Unhandled interrupt: %d %d\n", 1942 entry->src_id, entry->src_data[0]); 1943 break; 1944 } 1945 1946 return 0; 1947 } 1948 1949 static const struct amdgpu_irq_src_funcs vcn_v3_0_irq_funcs = { 1950 .set = vcn_v3_0_set_interrupt_state, 1951 .process = vcn_v3_0_process_interrupt, 1952 }; 1953 1954 static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev) 1955 { 1956 int i; 1957 1958 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1959 if (adev->vcn.harvest_config & (1 << i)) 1960 continue; 1961 1962 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1; 1963 adev->vcn.inst[i].irq.funcs = &vcn_v3_0_irq_funcs; 1964 } 1965 } 1966 1967 static const struct amd_ip_funcs vcn_v3_0_ip_funcs = { 1968 .name = "vcn_v3_0", 1969 .early_init = vcn_v3_0_early_init, 1970 .late_init = NULL, 1971 .sw_init = vcn_v3_0_sw_init, 1972 .sw_fini = vcn_v3_0_sw_fini, 1973 .hw_init = vcn_v3_0_hw_init, 1974 .hw_fini = vcn_v3_0_hw_fini, 1975 .suspend = vcn_v3_0_suspend, 1976 .resume = vcn_v3_0_resume, 1977 .is_idle = vcn_v3_0_is_idle, 1978 .wait_for_idle = vcn_v3_0_wait_for_idle, 1979 .check_soft_reset = NULL, 1980 .pre_soft_reset = NULL, 1981 .soft_reset = NULL, 1982 .post_soft_reset = NULL, 1983 .set_clockgating_state = vcn_v3_0_set_clockgating_state, 1984 .set_powergating_state = vcn_v3_0_set_powergating_state, 1985 }; 1986 1987 const struct amdgpu_ip_block_version vcn_v3_0_ip_block = 1988 { 1989 .type = AMD_IP_BLOCK_TYPE_VCN, 1990 .major = 3, 1991 .minor = 0, 1992 .rev = 0, 1993 .funcs = &vcn_v3_0_ip_funcs, 1994 }; 1995