1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_vcn.h" 27 #include "amdgpu_pm.h" 28 #include "soc15.h" 29 #include "soc15d.h" 30 #include "vcn_v2_0.h" 31 #include "mmsch_v3_0.h" 32 33 #include "vcn/vcn_3_0_0_offset.h" 34 #include "vcn/vcn_3_0_0_sh_mask.h" 35 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 36 37 #include <drm/drm_drv.h> 38 39 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x27 40 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x0f 41 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x10 42 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x11 43 #define mmUVD_NO_OP_INTERNAL_OFFSET 0x29 44 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x66 45 #define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d 46 47 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x431 48 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x3b4 49 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x3b5 50 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x25c 51 52 #define VCN_INSTANCES_SIENNA_CICHLID 2 53 #define DEC_SW_RING_ENABLED FALSE 54 55 #define RDECODE_MSG_CREATE 0x00000000 56 #define RDECODE_MESSAGE_CREATE 0x00000001 57 58 static int amdgpu_ih_clientid_vcns[] = { 59 SOC15_IH_CLIENTID_VCN, 60 SOC15_IH_CLIENTID_VCN1 61 }; 62 63 static int amdgpu_ucode_id_vcns[] = { 64 AMDGPU_UCODE_ID_VCN, 65 AMDGPU_UCODE_ID_VCN1 66 }; 67 68 static int vcn_v3_0_start_sriov(struct amdgpu_device *adev); 69 static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev); 70 static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev); 71 static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev); 72 static int vcn_v3_0_set_powergating_state(void *handle, 73 enum amd_powergating_state state); 74 static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev, 75 int inst_idx, struct dpg_pause_state *new_state); 76 77 static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring); 78 static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring); 79 80 /** 81 * vcn_v3_0_early_init - set function pointers 82 * 83 * @handle: amdgpu_device pointer 84 * 85 * Set ring and irq function pointers 86 */ 87 static int vcn_v3_0_early_init(void *handle) 88 { 89 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 90 int i; 91 92 if (amdgpu_sriov_vf(adev)) { 93 adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID; 94 adev->vcn.harvest_config = 0; 95 adev->vcn.num_enc_rings = 1; 96 97 } else { 98 if (adev->asic_type == CHIP_SIENNA_CICHLID) { 99 u32 harvest; 100 101 adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID; 102 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 103 harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING); 104 if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK) 105 adev->vcn.harvest_config |= 1 << i; 106 } 107 108 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 | 109 AMDGPU_VCN_HARVEST_VCN1)) 110 /* both instances are harvested, disable the block */ 111 return -ENOENT; 112 } else 113 adev->vcn.num_vcn_inst = 1; 114 115 if (adev->asic_type == CHIP_BEIGE_GOBY) 116 adev->vcn.num_enc_rings = 0; 117 else 118 adev->vcn.num_enc_rings = 2; 119 } 120 121 vcn_v3_0_set_dec_ring_funcs(adev); 122 vcn_v3_0_set_enc_ring_funcs(adev); 123 vcn_v3_0_set_irq_funcs(adev); 124 125 return 0; 126 } 127 128 /** 129 * vcn_v3_0_sw_init - sw init for VCN block 130 * 131 * @handle: amdgpu_device pointer 132 * 133 * Load firmware and sw initialization 134 */ 135 static int vcn_v3_0_sw_init(void *handle) 136 { 137 struct amdgpu_ring *ring; 138 int i, j, r; 139 int vcn_doorbell_index = 0; 140 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 141 142 r = amdgpu_vcn_sw_init(adev); 143 if (r) 144 return r; 145 146 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 147 const struct common_firmware_header *hdr; 148 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 149 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN; 150 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw; 151 adev->firmware.fw_size += 152 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 153 154 if (adev->vcn.num_vcn_inst == VCN_INSTANCES_SIENNA_CICHLID) { 155 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].ucode_id = AMDGPU_UCODE_ID_VCN1; 156 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].fw = adev->vcn.fw; 157 adev->firmware.fw_size += 158 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 159 } 160 dev_info(adev->dev, "Will use PSP to load VCN firmware\n"); 161 } 162 163 r = amdgpu_vcn_resume(adev); 164 if (r) 165 return r; 166 167 /* 168 * Note: doorbell assignment is fixed for SRIOV multiple VCN engines 169 * Formula: 170 * vcn_db_base = adev->doorbell_index.vcn.vcn_ring0_1 << 1; 171 * dec_ring_i = vcn_db_base + i * (adev->vcn.num_enc_rings + 1) 172 * enc_ring_i,j = vcn_db_base + i * (adev->vcn.num_enc_rings + 1) + 1 + j 173 */ 174 if (amdgpu_sriov_vf(adev)) { 175 vcn_doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1; 176 /* get DWORD offset */ 177 vcn_doorbell_index = vcn_doorbell_index << 1; 178 } 179 180 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 181 volatile struct amdgpu_fw_shared *fw_shared; 182 183 if (adev->vcn.harvest_config & (1 << i)) 184 continue; 185 186 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; 187 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; 188 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; 189 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; 190 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; 191 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; 192 193 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; 194 adev->vcn.inst[i].external.scratch9 = SOC15_REG_OFFSET(VCN, i, mmUVD_SCRATCH9); 195 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; 196 adev->vcn.inst[i].external.data0 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA0); 197 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; 198 adev->vcn.inst[i].external.data1 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA1); 199 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; 200 adev->vcn.inst[i].external.cmd = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_CMD); 201 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; 202 adev->vcn.inst[i].external.nop = SOC15_REG_OFFSET(VCN, i, mmUVD_NO_OP); 203 204 /* VCN DEC TRAP */ 205 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 206 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[i].irq); 207 if (r) 208 return r; 209 210 atomic_set(&adev->vcn.inst[i].sched_score, 0); 211 212 ring = &adev->vcn.inst[i].ring_dec; 213 ring->use_doorbell = true; 214 if (amdgpu_sriov_vf(adev)) { 215 ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1); 216 } else { 217 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i; 218 } 219 sprintf(ring->name, "vcn_dec_%d", i); 220 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 221 AMDGPU_RING_PRIO_DEFAULT, 222 &adev->vcn.inst[i].sched_score); 223 if (r) 224 return r; 225 226 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 227 enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(j); 228 229 /* VCN ENC TRAP */ 230 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 231 j + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); 232 if (r) 233 return r; 234 235 ring = &adev->vcn.inst[i].ring_enc[j]; 236 ring->use_doorbell = true; 237 if (amdgpu_sriov_vf(adev)) { 238 ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1) + 1 + j; 239 } else { 240 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + j + 8 * i; 241 } 242 sprintf(ring->name, "vcn_enc_%d.%d", i, j); 243 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 244 hw_prio, &adev->vcn.inst[i].sched_score); 245 if (r) 246 return r; 247 } 248 249 fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr; 250 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SW_RING_FLAG) | 251 cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG) | 252 cpu_to_le32(AMDGPU_VCN_FW_SHARED_FLAG_0_RB); 253 fw_shared->sw_ring.is_enabled = cpu_to_le32(DEC_SW_RING_ENABLED); 254 } 255 256 if (amdgpu_sriov_vf(adev)) { 257 r = amdgpu_virt_alloc_mm_table(adev); 258 if (r) 259 return r; 260 } 261 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 262 adev->vcn.pause_dpg_mode = vcn_v3_0_pause_dpg_mode; 263 264 return 0; 265 } 266 267 /** 268 * vcn_v3_0_sw_fini - sw fini for VCN block 269 * 270 * @handle: amdgpu_device pointer 271 * 272 * VCN suspend and free up sw allocation 273 */ 274 static int vcn_v3_0_sw_fini(void *handle) 275 { 276 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 277 int i, r, idx; 278 279 if (drm_dev_enter(&adev->ddev, &idx)) { 280 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 281 volatile struct amdgpu_fw_shared *fw_shared; 282 283 if (adev->vcn.harvest_config & (1 << i)) 284 continue; 285 fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr; 286 fw_shared->present_flag_0 = 0; 287 fw_shared->sw_ring.is_enabled = false; 288 } 289 290 drm_dev_exit(idx); 291 } 292 293 if (amdgpu_sriov_vf(adev)) 294 amdgpu_virt_free_mm_table(adev); 295 296 r = amdgpu_vcn_suspend(adev); 297 if (r) 298 return r; 299 300 r = amdgpu_vcn_sw_fini(adev); 301 302 return r; 303 } 304 305 /** 306 * vcn_v3_0_hw_init - start and test VCN block 307 * 308 * @handle: amdgpu_device pointer 309 * 310 * Initialize the hardware, boot up the VCPU and do some testing 311 */ 312 static int vcn_v3_0_hw_init(void *handle) 313 { 314 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 315 struct amdgpu_ring *ring; 316 int i, j, r; 317 318 if (amdgpu_sriov_vf(adev)) { 319 r = vcn_v3_0_start_sriov(adev); 320 if (r) 321 goto done; 322 323 /* initialize VCN dec and enc ring buffers */ 324 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 325 if (adev->vcn.harvest_config & (1 << i)) 326 continue; 327 328 ring = &adev->vcn.inst[i].ring_dec; 329 if (amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, i)) { 330 ring->sched.ready = false; 331 dev_info(adev->dev, "ring %s is disabled by hypervisor\n", ring->name); 332 } else { 333 ring->wptr = 0; 334 ring->wptr_old = 0; 335 vcn_v3_0_dec_ring_set_wptr(ring); 336 ring->sched.ready = true; 337 } 338 339 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 340 ring = &adev->vcn.inst[i].ring_enc[j]; 341 if (amdgpu_vcn_is_disabled_vcn(adev, VCN_ENCODE_RING, i)) { 342 ring->sched.ready = false; 343 dev_info(adev->dev, "ring %s is disabled by hypervisor\n", ring->name); 344 } else { 345 ring->wptr = 0; 346 ring->wptr_old = 0; 347 vcn_v3_0_enc_ring_set_wptr(ring); 348 ring->sched.ready = true; 349 } 350 } 351 } 352 } else { 353 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 354 if (adev->vcn.harvest_config & (1 << i)) 355 continue; 356 357 ring = &adev->vcn.inst[i].ring_dec; 358 359 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 360 ring->doorbell_index, i); 361 362 r = amdgpu_ring_test_helper(ring); 363 if (r) 364 goto done; 365 366 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 367 ring = &adev->vcn.inst[i].ring_enc[j]; 368 r = amdgpu_ring_test_helper(ring); 369 if (r) 370 goto done; 371 } 372 } 373 } 374 375 done: 376 if (!r) 377 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 378 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 379 380 return r; 381 } 382 383 /** 384 * vcn_v3_0_hw_fini - stop the hardware block 385 * 386 * @handle: amdgpu_device pointer 387 * 388 * Stop the VCN block, mark ring as not ready any more 389 */ 390 static int vcn_v3_0_hw_fini(void *handle) 391 { 392 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 393 int i; 394 395 cancel_delayed_work_sync(&adev->vcn.idle_work); 396 397 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 398 if (adev->vcn.harvest_config & (1 << i)) 399 continue; 400 401 if (!amdgpu_sriov_vf(adev)) { 402 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 403 (adev->vcn.cur_state != AMD_PG_STATE_GATE && 404 RREG32_SOC15(VCN, i, mmUVD_STATUS))) { 405 vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 406 } 407 } 408 } 409 410 return 0; 411 } 412 413 /** 414 * vcn_v3_0_suspend - suspend VCN block 415 * 416 * @handle: amdgpu_device pointer 417 * 418 * HW fini and suspend VCN block 419 */ 420 static int vcn_v3_0_suspend(void *handle) 421 { 422 int r; 423 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 424 425 r = vcn_v3_0_hw_fini(adev); 426 if (r) 427 return r; 428 429 r = amdgpu_vcn_suspend(adev); 430 431 return r; 432 } 433 434 /** 435 * vcn_v3_0_resume - resume VCN block 436 * 437 * @handle: amdgpu_device pointer 438 * 439 * Resume firmware and hw init VCN block 440 */ 441 static int vcn_v3_0_resume(void *handle) 442 { 443 int r; 444 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 445 446 r = amdgpu_vcn_resume(adev); 447 if (r) 448 return r; 449 450 r = vcn_v3_0_hw_init(adev); 451 452 return r; 453 } 454 455 /** 456 * vcn_v3_0_mc_resume - memory controller programming 457 * 458 * @adev: amdgpu_device pointer 459 * @inst: instance number 460 * 461 * Let the VCN memory controller know it's offsets 462 */ 463 static void vcn_v3_0_mc_resume(struct amdgpu_device *adev, int inst) 464 { 465 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 466 uint32_t offset; 467 468 /* cache window 0: fw */ 469 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 470 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 471 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 472 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 473 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 474 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 0); 475 offset = 0; 476 } else { 477 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 478 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 479 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 480 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 481 offset = size; 482 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 483 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 484 } 485 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE0, size); 486 487 /* cache window 1: stack */ 488 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 489 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 490 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 491 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 492 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET1, 0); 493 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 494 495 /* cache window 2: context */ 496 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 497 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 498 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 499 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 500 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET2, 0); 501 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 502 503 /* non-cache window */ 504 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 505 lower_32_bits(adev->vcn.inst[inst].fw_shared_gpu_addr)); 506 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 507 upper_32_bits(adev->vcn.inst[inst].fw_shared_gpu_addr)); 508 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_OFFSET0, 0); 509 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_SIZE0, 510 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); 511 } 512 513 static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 514 { 515 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 516 uint32_t offset; 517 518 /* cache window 0: fw */ 519 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 520 if (!indirect) { 521 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 522 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 523 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); 524 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 525 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 526 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); 527 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 528 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 529 } else { 530 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 531 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 532 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 533 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 534 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 535 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 536 } 537 offset = 0; 538 } else { 539 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 540 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 541 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 542 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 543 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 544 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 545 offset = size; 546 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 547 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 548 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 549 } 550 551 if (!indirect) 552 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 553 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 554 else 555 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 556 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 557 558 /* cache window 1: stack */ 559 if (!indirect) { 560 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 561 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 562 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 563 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 564 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 565 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 566 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 567 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 568 } else { 569 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 570 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 571 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 572 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 573 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 574 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 575 } 576 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 577 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 578 579 /* cache window 2: context */ 580 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 581 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 582 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 583 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 584 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 585 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 586 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 587 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 588 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 589 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 590 591 /* non-cache window */ 592 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 593 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 594 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect); 595 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 596 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 597 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect); 598 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 599 VCN, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 600 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 601 VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), 602 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); 603 604 /* VCN global tiling registers */ 605 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 606 UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 607 } 608 609 static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int inst) 610 { 611 uint32_t data = 0; 612 613 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 614 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 615 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 616 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 617 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 618 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 619 | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 620 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 621 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 622 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 623 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 624 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 625 | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 626 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 627 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 628 629 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 630 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 631 UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF); 632 } else { 633 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 634 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 635 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 636 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 637 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 638 | 1 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 639 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 640 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 641 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 642 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 643 | 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 644 | 1 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 645 | 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 646 | 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 647 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 648 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 0, 0x3F3FFFFF); 649 } 650 651 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); 652 data &= ~0x103; 653 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 654 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 655 UVD_POWER_STATUS__UVD_PG_EN_MASK; 656 657 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); 658 } 659 660 static void vcn_v3_0_enable_static_power_gating(struct amdgpu_device *adev, int inst) 661 { 662 uint32_t data; 663 664 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 665 /* Before power off, this indicator has to be turned on */ 666 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); 667 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 668 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 669 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); 670 671 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 672 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 673 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 674 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 675 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 676 | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 677 | 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 678 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 679 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 680 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 681 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 682 | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 683 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 684 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 685 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 686 687 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 688 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 689 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 690 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 691 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 692 | 2 << UVD_PGFSM_STATUS__UVDIRL_PWR_STATUS__SHIFT 693 | 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT 694 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 695 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 696 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 697 | 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT 698 | 2 << UVD_PGFSM_STATUS__UVDATD_PWR_STATUS__SHIFT 699 | 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT 700 | 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT); 701 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, data, 0x3F3FFFFF); 702 } 703 } 704 705 /** 706 * vcn_v3_0_disable_clock_gating - disable VCN clock gating 707 * 708 * @adev: amdgpu_device pointer 709 * @inst: instance number 710 * 711 * Disable clock gating for VCN block 712 */ 713 static void vcn_v3_0_disable_clock_gating(struct amdgpu_device *adev, int inst) 714 { 715 uint32_t data; 716 717 /* VCN disable CGC */ 718 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 719 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 720 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 721 else 722 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 723 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 724 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 725 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 726 727 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_GATE); 728 data &= ~(UVD_CGC_GATE__SYS_MASK 729 | UVD_CGC_GATE__UDEC_MASK 730 | UVD_CGC_GATE__MPEG2_MASK 731 | UVD_CGC_GATE__REGS_MASK 732 | UVD_CGC_GATE__RBC_MASK 733 | UVD_CGC_GATE__LMI_MC_MASK 734 | UVD_CGC_GATE__LMI_UMC_MASK 735 | UVD_CGC_GATE__IDCT_MASK 736 | UVD_CGC_GATE__MPRD_MASK 737 | UVD_CGC_GATE__MPC_MASK 738 | UVD_CGC_GATE__LBSI_MASK 739 | UVD_CGC_GATE__LRBBM_MASK 740 | UVD_CGC_GATE__UDEC_RE_MASK 741 | UVD_CGC_GATE__UDEC_CM_MASK 742 | UVD_CGC_GATE__UDEC_IT_MASK 743 | UVD_CGC_GATE__UDEC_DB_MASK 744 | UVD_CGC_GATE__UDEC_MP_MASK 745 | UVD_CGC_GATE__WCB_MASK 746 | UVD_CGC_GATE__VCPU_MASK 747 | UVD_CGC_GATE__MMSCH_MASK); 748 749 WREG32_SOC15(VCN, inst, mmUVD_CGC_GATE, data); 750 751 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); 752 753 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 754 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 755 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 756 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 757 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 758 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 759 | UVD_CGC_CTRL__SYS_MODE_MASK 760 | UVD_CGC_CTRL__UDEC_MODE_MASK 761 | UVD_CGC_CTRL__MPEG2_MODE_MASK 762 | UVD_CGC_CTRL__REGS_MODE_MASK 763 | UVD_CGC_CTRL__RBC_MODE_MASK 764 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 765 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 766 | UVD_CGC_CTRL__IDCT_MODE_MASK 767 | UVD_CGC_CTRL__MPRD_MODE_MASK 768 | UVD_CGC_CTRL__MPC_MODE_MASK 769 | UVD_CGC_CTRL__LBSI_MODE_MASK 770 | UVD_CGC_CTRL__LRBBM_MODE_MASK 771 | UVD_CGC_CTRL__WCB_MODE_MASK 772 | UVD_CGC_CTRL__VCPU_MODE_MASK 773 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 774 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 775 776 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE); 777 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 778 | UVD_SUVD_CGC_GATE__SIT_MASK 779 | UVD_SUVD_CGC_GATE__SMP_MASK 780 | UVD_SUVD_CGC_GATE__SCM_MASK 781 | UVD_SUVD_CGC_GATE__SDB_MASK 782 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 783 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 784 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 785 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 786 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 787 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 788 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 789 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 790 | UVD_SUVD_CGC_GATE__SCLR_MASK 791 | UVD_SUVD_CGC_GATE__ENT_MASK 792 | UVD_SUVD_CGC_GATE__IME_MASK 793 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 794 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 795 | UVD_SUVD_CGC_GATE__SITE_MASK 796 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 797 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 798 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 799 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 800 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK 801 | UVD_SUVD_CGC_GATE__EFC_MASK 802 | UVD_SUVD_CGC_GATE__SAOE_MASK 803 | UVD_SUVD_CGC_GATE__SRE_AV1_MASK 804 | UVD_SUVD_CGC_GATE__FBC_PCLK_MASK 805 | UVD_SUVD_CGC_GATE__FBC_CCLK_MASK 806 | UVD_SUVD_CGC_GATE__SCM_AV1_MASK 807 | UVD_SUVD_CGC_GATE__SMPA_MASK); 808 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE, data); 809 810 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2); 811 data |= (UVD_SUVD_CGC_GATE2__MPBE0_MASK 812 | UVD_SUVD_CGC_GATE2__MPBE1_MASK 813 | UVD_SUVD_CGC_GATE2__SIT_AV1_MASK 814 | UVD_SUVD_CGC_GATE2__SDB_AV1_MASK 815 | UVD_SUVD_CGC_GATE2__MPC1_MASK); 816 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2, data); 817 818 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL); 819 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 820 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 821 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 822 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 823 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 824 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 825 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 826 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 827 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 828 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 829 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK 830 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK 831 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK 832 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK 833 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 834 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 835 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK 836 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK 837 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK); 838 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data); 839 } 840 841 static void vcn_v3_0_clock_gating_dpg_mode(struct amdgpu_device *adev, 842 uint8_t sram_sel, int inst_idx, uint8_t indirect) 843 { 844 uint32_t reg_data = 0; 845 846 /* enable sw clock gating control */ 847 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 848 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 849 else 850 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 851 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 852 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 853 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 854 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 855 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 856 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 857 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 858 UVD_CGC_CTRL__SYS_MODE_MASK | 859 UVD_CGC_CTRL__UDEC_MODE_MASK | 860 UVD_CGC_CTRL__MPEG2_MODE_MASK | 861 UVD_CGC_CTRL__REGS_MODE_MASK | 862 UVD_CGC_CTRL__RBC_MODE_MASK | 863 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 864 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 865 UVD_CGC_CTRL__IDCT_MODE_MASK | 866 UVD_CGC_CTRL__MPRD_MODE_MASK | 867 UVD_CGC_CTRL__MPC_MODE_MASK | 868 UVD_CGC_CTRL__LBSI_MODE_MASK | 869 UVD_CGC_CTRL__LRBBM_MODE_MASK | 870 UVD_CGC_CTRL__WCB_MODE_MASK | 871 UVD_CGC_CTRL__VCPU_MODE_MASK | 872 UVD_CGC_CTRL__MMSCH_MODE_MASK); 873 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 874 VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); 875 876 /* turn off clock gating */ 877 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 878 VCN, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect); 879 880 /* turn on SUVD clock gating */ 881 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 882 VCN, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 883 884 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 885 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 886 VCN, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 887 } 888 889 /** 890 * vcn_v3_0_enable_clock_gating - enable VCN clock gating 891 * 892 * @adev: amdgpu_device pointer 893 * @inst: instance number 894 * 895 * Enable clock gating for VCN block 896 */ 897 static void vcn_v3_0_enable_clock_gating(struct amdgpu_device *adev, int inst) 898 { 899 uint32_t data; 900 901 /* enable VCN CGC */ 902 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 903 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 904 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 905 else 906 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 907 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 908 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 909 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 910 911 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 912 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 913 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 914 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 915 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 916 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 917 | UVD_CGC_CTRL__SYS_MODE_MASK 918 | UVD_CGC_CTRL__UDEC_MODE_MASK 919 | UVD_CGC_CTRL__MPEG2_MODE_MASK 920 | UVD_CGC_CTRL__REGS_MODE_MASK 921 | UVD_CGC_CTRL__RBC_MODE_MASK 922 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 923 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 924 | UVD_CGC_CTRL__IDCT_MODE_MASK 925 | UVD_CGC_CTRL__MPRD_MODE_MASK 926 | UVD_CGC_CTRL__MPC_MODE_MASK 927 | UVD_CGC_CTRL__LBSI_MODE_MASK 928 | UVD_CGC_CTRL__LRBBM_MODE_MASK 929 | UVD_CGC_CTRL__WCB_MODE_MASK 930 | UVD_CGC_CTRL__VCPU_MODE_MASK 931 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 932 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 933 934 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL); 935 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 936 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 937 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 938 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 939 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 940 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 941 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 942 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 943 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 944 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 945 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK 946 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK 947 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK 948 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK 949 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 950 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 951 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK 952 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK 953 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK); 954 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data); 955 } 956 957 static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 958 { 959 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr; 960 struct amdgpu_ring *ring; 961 uint32_t rb_bufsz, tmp; 962 963 /* disable register anti-hang mechanism */ 964 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1, 965 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 966 /* enable dynamic power gating mode */ 967 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS); 968 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 969 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 970 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp); 971 972 if (indirect) 973 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 974 975 /* enable clock gating */ 976 vcn_v3_0_clock_gating_dpg_mode(adev, 0, inst_idx, indirect); 977 978 /* enable VCPU clock */ 979 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 980 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 981 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK; 982 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 983 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 984 985 /* disable master interupt */ 986 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 987 VCN, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect); 988 989 /* setup mmUVD_LMI_CTRL */ 990 tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 991 UVD_LMI_CTRL__REQ_MODE_MASK | 992 UVD_LMI_CTRL__CRC_RESET_MASK | 993 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 994 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 995 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 996 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 997 0x00100000L); 998 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 999 VCN, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect); 1000 1001 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1002 VCN, inst_idx, mmUVD_MPC_CNTL), 1003 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 1004 1005 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1006 VCN, inst_idx, mmUVD_MPC_SET_MUXA0), 1007 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1008 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1009 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1010 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 1011 1012 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1013 VCN, inst_idx, mmUVD_MPC_SET_MUXB0), 1014 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1015 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1016 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1017 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 1018 1019 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1020 VCN, inst_idx, mmUVD_MPC_SET_MUX), 1021 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1022 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1023 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 1024 1025 vcn_v3_0_mc_resume_dpg_mode(adev, inst_idx, indirect); 1026 1027 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1028 VCN, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect); 1029 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1030 VCN, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect); 1031 1032 /* enable LMI MC and UMC channels */ 1033 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1034 VCN, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect); 1035 1036 /* unblock VCPU register access */ 1037 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1038 VCN, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect); 1039 1040 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 1041 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 1042 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1043 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 1044 1045 /* enable master interrupt */ 1046 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1047 VCN, inst_idx, mmUVD_MASTINT_EN), 1048 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 1049 1050 /* add nop to workaround PSP size check */ 1051 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1052 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 1053 1054 if (indirect) 1055 psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, 1056 (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr - 1057 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr)); 1058 1059 ring = &adev->vcn.inst[inst_idx].ring_dec; 1060 /* force RBC into idle state */ 1061 rb_bufsz = order_base_2(ring->ring_size); 1062 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1063 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1064 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1065 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1066 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1067 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp); 1068 1069 /* Stall DPG before WPTR/RPTR reset */ 1070 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1071 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1072 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1073 fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1074 1075 /* set the write pointer delay */ 1076 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0); 1077 1078 /* set the wb address */ 1079 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR, 1080 (upper_32_bits(ring->gpu_addr) >> 2)); 1081 1082 /* programm the RB_BASE for ring buffer */ 1083 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1084 lower_32_bits(ring->gpu_addr)); 1085 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1086 upper_32_bits(ring->gpu_addr)); 1087 1088 /* Initialize the ring buffer's read and write pointers */ 1089 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0); 1090 1091 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0); 1092 1093 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR); 1094 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, 1095 lower_32_bits(ring->wptr)); 1096 1097 /* Reset FW shared memory RBC WPTR/RPTR */ 1098 fw_shared->rb.rptr = 0; 1099 fw_shared->rb.wptr = lower_32_bits(ring->wptr); 1100 1101 /*resetting done, fw can check RB ring */ 1102 fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1103 1104 /* Unstall DPG */ 1105 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1106 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1107 1108 return 0; 1109 } 1110 1111 static int vcn_v3_0_start(struct amdgpu_device *adev) 1112 { 1113 volatile struct amdgpu_fw_shared *fw_shared; 1114 struct amdgpu_ring *ring; 1115 uint32_t rb_bufsz, tmp; 1116 int i, j, k, r; 1117 1118 if (adev->pm.dpm_enabled) 1119 amdgpu_dpm_enable_uvd(adev, true); 1120 1121 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1122 if (adev->vcn.harvest_config & (1 << i)) 1123 continue; 1124 1125 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG){ 1126 r = vcn_v3_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram); 1127 continue; 1128 } 1129 1130 /* disable VCN power gating */ 1131 vcn_v3_0_disable_static_power_gating(adev, i); 1132 1133 /* set VCN status busy */ 1134 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 1135 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp); 1136 1137 /*SW clock gating */ 1138 vcn_v3_0_disable_clock_gating(adev, i); 1139 1140 /* enable VCPU clock */ 1141 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1142 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 1143 1144 /* disable master interrupt */ 1145 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0, 1146 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1147 1148 /* enable LMI MC and UMC channels */ 1149 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0, 1150 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1151 1152 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1153 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1154 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1155 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1156 1157 /* setup mmUVD_LMI_CTRL */ 1158 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL); 1159 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | 1160 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1161 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1162 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1163 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1164 1165 /* setup mmUVD_MPC_CNTL */ 1166 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL); 1167 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1168 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1169 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp); 1170 1171 /* setup UVD_MPC_SET_MUXA0 */ 1172 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0, 1173 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1174 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1175 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1176 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1177 1178 /* setup UVD_MPC_SET_MUXB0 */ 1179 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0, 1180 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1181 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1182 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1183 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1184 1185 /* setup mmUVD_MPC_SET_MUX */ 1186 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX, 1187 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1188 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1189 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1190 1191 vcn_v3_0_mc_resume(adev, i); 1192 1193 /* VCN global tiling registers */ 1194 WREG32_SOC15(VCN, i, mmUVD_GFX10_ADDR_CONFIG, 1195 adev->gfx.config.gb_addr_config); 1196 1197 /* unblock VCPU register access */ 1198 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0, 1199 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1200 1201 /* release VCPU reset to boot */ 1202 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1203 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1204 1205 for (j = 0; j < 10; ++j) { 1206 uint32_t status; 1207 1208 for (k = 0; k < 100; ++k) { 1209 status = RREG32_SOC15(VCN, i, mmUVD_STATUS); 1210 if (status & 2) 1211 break; 1212 mdelay(10); 1213 } 1214 r = 0; 1215 if (status & 2) 1216 break; 1217 1218 DRM_ERROR("VCN[%d] decode not responding, trying to reset the VCPU!!!\n", i); 1219 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1220 UVD_VCPU_CNTL__BLK_RST_MASK, 1221 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1222 mdelay(10); 1223 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1224 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1225 1226 mdelay(10); 1227 r = -1; 1228 } 1229 1230 if (r) { 1231 DRM_ERROR("VCN[%d] decode not responding, giving up!!!\n", i); 1232 return r; 1233 } 1234 1235 /* enable master interrupt */ 1236 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 1237 UVD_MASTINT_EN__VCPU_EN_MASK, 1238 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1239 1240 /* clear the busy bit of VCN_STATUS */ 1241 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0, 1242 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1243 1244 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0); 1245 1246 ring = &adev->vcn.inst[i].ring_dec; 1247 /* force RBC into idle state */ 1248 rb_bufsz = order_base_2(ring->ring_size); 1249 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1250 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1251 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1252 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1253 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1254 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp); 1255 1256 fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr; 1257 fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1258 1259 /* programm the RB_BASE for ring buffer */ 1260 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1261 lower_32_bits(ring->gpu_addr)); 1262 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1263 upper_32_bits(ring->gpu_addr)); 1264 1265 /* Initialize the ring buffer's read and write pointers */ 1266 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0); 1267 1268 WREG32_SOC15(VCN, i, mmUVD_SCRATCH2, 0); 1269 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR); 1270 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR, 1271 lower_32_bits(ring->wptr)); 1272 fw_shared->rb.wptr = lower_32_bits(ring->wptr); 1273 fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1274 1275 if (adev->asic_type != CHIP_BEIGE_GOBY) { 1276 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1277 ring = &adev->vcn.inst[i].ring_enc[0]; 1278 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1279 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1280 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr); 1281 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1282 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4); 1283 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1284 1285 fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1286 ring = &adev->vcn.inst[i].ring_enc[1]; 1287 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1288 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1289 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1290 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1291 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4); 1292 fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1293 } 1294 } 1295 1296 return 0; 1297 } 1298 1299 static int vcn_v3_0_start_sriov(struct amdgpu_device *adev) 1300 { 1301 int i, j; 1302 struct amdgpu_ring *ring; 1303 uint64_t cache_addr; 1304 uint64_t rb_addr; 1305 uint64_t ctx_addr; 1306 uint32_t param, resp, expected; 1307 uint32_t offset, cache_size; 1308 uint32_t tmp, timeout; 1309 uint32_t id; 1310 1311 struct amdgpu_mm_table *table = &adev->virt.mm_table; 1312 uint32_t *table_loc; 1313 uint32_t table_size; 1314 uint32_t size, size_dw; 1315 1316 struct mmsch_v3_0_cmd_direct_write 1317 direct_wt = { {0} }; 1318 struct mmsch_v3_0_cmd_direct_read_modify_write 1319 direct_rd_mod_wt = { {0} }; 1320 struct mmsch_v3_0_cmd_end end = { {0} }; 1321 struct mmsch_v3_0_init_header header; 1322 1323 direct_wt.cmd_header.command_type = 1324 MMSCH_COMMAND__DIRECT_REG_WRITE; 1325 direct_rd_mod_wt.cmd_header.command_type = 1326 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1327 end.cmd_header.command_type = 1328 MMSCH_COMMAND__END; 1329 1330 header.version = MMSCH_VERSION; 1331 header.total_size = sizeof(struct mmsch_v3_0_init_header) >> 2; 1332 for (i = 0; i < AMDGPU_MAX_VCN_INSTANCES; i++) { 1333 header.inst[i].init_status = 0; 1334 header.inst[i].table_offset = 0; 1335 header.inst[i].table_size = 0; 1336 } 1337 1338 table_loc = (uint32_t *)table->cpu_addr; 1339 table_loc += header.total_size; 1340 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1341 if (adev->vcn.harvest_config & (1 << i)) 1342 continue; 1343 1344 table_size = 0; 1345 1346 MMSCH_V3_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i, 1347 mmUVD_STATUS), 1348 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 1349 1350 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 1351 1352 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1353 id = amdgpu_ucode_id_vcns[i]; 1354 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1355 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1356 adev->firmware.ucode[id].tmr_mc_addr_lo); 1357 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1358 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1359 adev->firmware.ucode[id].tmr_mc_addr_hi); 1360 offset = 0; 1361 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1362 mmUVD_VCPU_CACHE_OFFSET0), 1363 0); 1364 } else { 1365 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1366 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1367 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 1368 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1369 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1370 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 1371 offset = cache_size; 1372 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1373 mmUVD_VCPU_CACHE_OFFSET0), 1374 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 1375 } 1376 1377 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1378 mmUVD_VCPU_CACHE_SIZE0), 1379 cache_size); 1380 1381 cache_addr = adev->vcn.inst[i].gpu_addr + offset; 1382 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1383 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 1384 lower_32_bits(cache_addr)); 1385 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1386 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 1387 upper_32_bits(cache_addr)); 1388 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1389 mmUVD_VCPU_CACHE_OFFSET1), 1390 0); 1391 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1392 mmUVD_VCPU_CACHE_SIZE1), 1393 AMDGPU_VCN_STACK_SIZE); 1394 1395 cache_addr = adev->vcn.inst[i].gpu_addr + offset + 1396 AMDGPU_VCN_STACK_SIZE; 1397 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1398 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 1399 lower_32_bits(cache_addr)); 1400 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1401 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 1402 upper_32_bits(cache_addr)); 1403 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1404 mmUVD_VCPU_CACHE_OFFSET2), 1405 0); 1406 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1407 mmUVD_VCPU_CACHE_SIZE2), 1408 AMDGPU_VCN_CONTEXT_SIZE); 1409 1410 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 1411 ring = &adev->vcn.inst[i].ring_enc[j]; 1412 ring->wptr = 0; 1413 rb_addr = ring->gpu_addr; 1414 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1415 mmUVD_RB_BASE_LO), 1416 lower_32_bits(rb_addr)); 1417 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1418 mmUVD_RB_BASE_HI), 1419 upper_32_bits(rb_addr)); 1420 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1421 mmUVD_RB_SIZE), 1422 ring->ring_size / 4); 1423 } 1424 1425 ring = &adev->vcn.inst[i].ring_dec; 1426 ring->wptr = 0; 1427 rb_addr = ring->gpu_addr; 1428 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1429 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW), 1430 lower_32_bits(rb_addr)); 1431 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1432 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH), 1433 upper_32_bits(rb_addr)); 1434 /* force RBC into idle state */ 1435 tmp = order_base_2(ring->ring_size); 1436 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp); 1437 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1438 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1439 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1440 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1441 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1442 mmUVD_RBC_RB_CNTL), 1443 tmp); 1444 1445 /* add end packet */ 1446 MMSCH_V3_0_INSERT_END(); 1447 1448 /* refine header */ 1449 header.inst[i].init_status = 0; 1450 header.inst[i].table_offset = header.total_size; 1451 header.inst[i].table_size = table_size; 1452 header.total_size += table_size; 1453 } 1454 1455 /* Update init table header in memory */ 1456 size = sizeof(struct mmsch_v3_0_init_header); 1457 table_loc = (uint32_t *)table->cpu_addr; 1458 memcpy((void *)table_loc, &header, size); 1459 1460 /* message MMSCH (in VCN[0]) to initialize this client 1461 * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr 1462 * of memory descriptor location 1463 */ 1464 ctx_addr = table->gpu_addr; 1465 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 1466 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 1467 1468 /* 2, update vmid of descriptor */ 1469 tmp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID); 1470 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1471 /* use domain0 for MM scheduler */ 1472 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1473 WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, tmp); 1474 1475 /* 3, notify mmsch about the size of this descriptor */ 1476 size = header.total_size; 1477 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size); 1478 1479 /* 4, set resp to zero */ 1480 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0); 1481 1482 /* 5, kick off the initialization and wait until 1483 * MMSCH_VF_MAILBOX_RESP becomes non-zero 1484 */ 1485 param = 0x10000001; 1486 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, param); 1487 tmp = 0; 1488 timeout = 1000; 1489 resp = 0; 1490 expected = param + 1; 1491 while (resp != expected) { 1492 resp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); 1493 if (resp == expected) 1494 break; 1495 1496 udelay(10); 1497 tmp = tmp + 10; 1498 if (tmp >= timeout) { 1499 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 1500 " waiting for mmMMSCH_VF_MAILBOX_RESP "\ 1501 "(expected=0x%08x, readback=0x%08x)\n", 1502 tmp, expected, resp); 1503 return -EBUSY; 1504 } 1505 } 1506 1507 return 0; 1508 } 1509 1510 static int vcn_v3_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) 1511 { 1512 uint32_t tmp; 1513 1514 /* Wait for power status to be 1 */ 1515 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1516 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1517 1518 /* wait for read ptr to be equal to write ptr */ 1519 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR); 1520 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1521 1522 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2); 1523 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); 1524 1525 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1526 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); 1527 1528 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1529 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1530 1531 /* disable dynamic power gating mode */ 1532 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0, 1533 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1534 1535 return 0; 1536 } 1537 1538 static int vcn_v3_0_stop(struct amdgpu_device *adev) 1539 { 1540 uint32_t tmp; 1541 int i, r = 0; 1542 1543 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1544 if (adev->vcn.harvest_config & (1 << i)) 1545 continue; 1546 1547 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1548 r = vcn_v3_0_stop_dpg_mode(adev, i); 1549 continue; 1550 } 1551 1552 /* wait for vcn idle */ 1553 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1554 if (r) 1555 return r; 1556 1557 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1558 UVD_LMI_STATUS__READ_CLEAN_MASK | 1559 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1560 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1561 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1562 if (r) 1563 return r; 1564 1565 /* disable LMI UMC channel */ 1566 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2); 1567 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1568 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp); 1569 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK| 1570 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1571 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1572 if (r) 1573 return r; 1574 1575 /* block VCPU register access */ 1576 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 1577 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1578 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1579 1580 /* reset VCPU */ 1581 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1582 UVD_VCPU_CNTL__BLK_RST_MASK, 1583 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1584 1585 /* disable VCPU clock */ 1586 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1587 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1588 1589 /* apply soft reset */ 1590 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1591 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1592 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1593 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1594 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1595 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1596 1597 /* clear status */ 1598 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0); 1599 1600 /* apply HW clock gating */ 1601 vcn_v3_0_enable_clock_gating(adev, i); 1602 1603 /* enable VCN power gating */ 1604 vcn_v3_0_enable_static_power_gating(adev, i); 1605 } 1606 1607 if (adev->pm.dpm_enabled) 1608 amdgpu_dpm_enable_uvd(adev, false); 1609 1610 return 0; 1611 } 1612 1613 static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev, 1614 int inst_idx, struct dpg_pause_state *new_state) 1615 { 1616 volatile struct amdgpu_fw_shared *fw_shared; 1617 struct amdgpu_ring *ring; 1618 uint32_t reg_data = 0; 1619 int ret_code; 1620 1621 /* pause/unpause if state is changed */ 1622 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1623 DRM_DEBUG("dpg pause state changed %d -> %d", 1624 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1625 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) & 1626 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1627 1628 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1629 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, 1630 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1631 1632 if (!ret_code) { 1633 /* pause DPG */ 1634 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1635 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1636 1637 /* wait for ACK */ 1638 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE, 1639 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1640 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1641 1642 /* Stall DPG before WPTR/RPTR reset */ 1643 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1644 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1645 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1646 1647 if (adev->asic_type != CHIP_BEIGE_GOBY) { 1648 /* Restore */ 1649 fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr; 1650 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1651 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 1652 ring->wptr = 0; 1653 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr); 1654 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1655 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4); 1656 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1657 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1658 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1659 1660 fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1661 ring = &adev->vcn.inst[inst_idx].ring_enc[1]; 1662 ring->wptr = 0; 1663 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1664 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1665 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4); 1666 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1667 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1668 fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1669 1670 /* restore wptr/rptr with pointers saved in FW shared memory*/ 1671 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, fw_shared->rb.rptr); 1672 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, fw_shared->rb.wptr); 1673 } 1674 1675 /* Unstall DPG */ 1676 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1677 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1678 1679 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1680 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1681 } 1682 } else { 1683 /* unpause dpg, no need to wait */ 1684 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1685 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1686 } 1687 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1688 } 1689 1690 return 0; 1691 } 1692 1693 /** 1694 * vcn_v3_0_dec_ring_get_rptr - get read pointer 1695 * 1696 * @ring: amdgpu_ring pointer 1697 * 1698 * Returns the current hardware read pointer 1699 */ 1700 static uint64_t vcn_v3_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 1701 { 1702 struct amdgpu_device *adev = ring->adev; 1703 1704 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR); 1705 } 1706 1707 /** 1708 * vcn_v3_0_dec_ring_get_wptr - get write pointer 1709 * 1710 * @ring: amdgpu_ring pointer 1711 * 1712 * Returns the current hardware write pointer 1713 */ 1714 static uint64_t vcn_v3_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 1715 { 1716 struct amdgpu_device *adev = ring->adev; 1717 1718 if (ring->use_doorbell) 1719 return adev->wb.wb[ring->wptr_offs]; 1720 else 1721 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR); 1722 } 1723 1724 /** 1725 * vcn_v3_0_dec_ring_set_wptr - set write pointer 1726 * 1727 * @ring: amdgpu_ring pointer 1728 * 1729 * Commits the write pointer to the hardware 1730 */ 1731 static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 1732 { 1733 struct amdgpu_device *adev = ring->adev; 1734 volatile struct amdgpu_fw_shared *fw_shared; 1735 1736 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1737 /*whenever update RBC_RB_WPTR, we save the wptr in shared rb.wptr and scratch2 */ 1738 fw_shared = adev->vcn.inst[ring->me].fw_shared_cpu_addr; 1739 fw_shared->rb.wptr = lower_32_bits(ring->wptr); 1740 WREG32_SOC15(VCN, ring->me, mmUVD_SCRATCH2, 1741 lower_32_bits(ring->wptr)); 1742 } 1743 1744 if (ring->use_doorbell) { 1745 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 1746 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1747 } else { 1748 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1749 } 1750 } 1751 1752 static void vcn_v3_0_dec_sw_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1753 u64 seq, uint32_t flags) 1754 { 1755 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1756 1757 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_FENCE); 1758 amdgpu_ring_write(ring, addr); 1759 amdgpu_ring_write(ring, upper_32_bits(addr)); 1760 amdgpu_ring_write(ring, seq); 1761 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_TRAP); 1762 } 1763 1764 static void vcn_v3_0_dec_sw_ring_insert_end(struct amdgpu_ring *ring) 1765 { 1766 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END); 1767 } 1768 1769 static void vcn_v3_0_dec_sw_ring_emit_ib(struct amdgpu_ring *ring, 1770 struct amdgpu_job *job, 1771 struct amdgpu_ib *ib, 1772 uint32_t flags) 1773 { 1774 uint32_t vmid = AMDGPU_JOB_GET_VMID(job); 1775 1776 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_IB); 1777 amdgpu_ring_write(ring, vmid); 1778 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1779 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1780 amdgpu_ring_write(ring, ib->length_dw); 1781 } 1782 1783 static void vcn_v3_0_dec_sw_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1784 uint32_t val, uint32_t mask) 1785 { 1786 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WAIT); 1787 amdgpu_ring_write(ring, reg << 2); 1788 amdgpu_ring_write(ring, mask); 1789 amdgpu_ring_write(ring, val); 1790 } 1791 1792 static void vcn_v3_0_dec_sw_ring_emit_vm_flush(struct amdgpu_ring *ring, 1793 uint32_t vmid, uint64_t pd_addr) 1794 { 1795 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1796 uint32_t data0, data1, mask; 1797 1798 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1799 1800 /* wait for register write */ 1801 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance; 1802 data1 = lower_32_bits(pd_addr); 1803 mask = 0xffffffff; 1804 vcn_v3_0_dec_sw_ring_emit_reg_wait(ring, data0, data1, mask); 1805 } 1806 1807 static void vcn_v3_0_dec_sw_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) 1808 { 1809 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WRITE); 1810 amdgpu_ring_write(ring, reg << 2); 1811 amdgpu_ring_write(ring, val); 1812 } 1813 1814 static const struct amdgpu_ring_funcs vcn_v3_0_dec_sw_ring_vm_funcs = { 1815 .type = AMDGPU_RING_TYPE_VCN_DEC, 1816 .align_mask = 0x3f, 1817 .nop = VCN_DEC_SW_CMD_NO_OP, 1818 .vmhub = AMDGPU_MMHUB_0, 1819 .get_rptr = vcn_v3_0_dec_ring_get_rptr, 1820 .get_wptr = vcn_v3_0_dec_ring_get_wptr, 1821 .set_wptr = vcn_v3_0_dec_ring_set_wptr, 1822 .emit_frame_size = 1823 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1824 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1825 4 + /* vcn_v3_0_dec_sw_ring_emit_vm_flush */ 1826 5 + 5 + /* vcn_v3_0_dec_sw_ring_emit_fdec_swe x2 vm fdec_swe */ 1827 1, /* vcn_v3_0_dec_sw_ring_insert_end */ 1828 .emit_ib_size = 5, /* vcn_v3_0_dec_sw_ring_emit_ib */ 1829 .emit_ib = vcn_v3_0_dec_sw_ring_emit_ib, 1830 .emit_fence = vcn_v3_0_dec_sw_ring_emit_fence, 1831 .emit_vm_flush = vcn_v3_0_dec_sw_ring_emit_vm_flush, 1832 .test_ring = amdgpu_vcn_dec_sw_ring_test_ring, 1833 .test_ib = NULL,//amdgpu_vcn_dec_sw_ring_test_ib, 1834 .insert_nop = amdgpu_ring_insert_nop, 1835 .insert_end = vcn_v3_0_dec_sw_ring_insert_end, 1836 .pad_ib = amdgpu_ring_generic_pad_ib, 1837 .begin_use = amdgpu_vcn_ring_begin_use, 1838 .end_use = amdgpu_vcn_ring_end_use, 1839 .emit_wreg = vcn_v3_0_dec_sw_ring_emit_wreg, 1840 .emit_reg_wait = vcn_v3_0_dec_sw_ring_emit_reg_wait, 1841 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1842 }; 1843 1844 static int vcn_v3_0_limit_sched(struct amdgpu_cs_parser *p) 1845 { 1846 struct drm_gpu_scheduler **scheds; 1847 1848 /* The create msg must be in the first IB submitted */ 1849 if (atomic_read(&p->entity->fence_seq)) 1850 return -EINVAL; 1851 1852 scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_DEC] 1853 [AMDGPU_RING_PRIO_DEFAULT].sched; 1854 drm_sched_entity_modify_sched(p->entity, scheds, 1); 1855 return 0; 1856 } 1857 1858 static int vcn_v3_0_dec_msg(struct amdgpu_cs_parser *p, uint64_t addr) 1859 { 1860 struct ttm_operation_ctx ctx = { false, false }; 1861 struct amdgpu_bo_va_mapping *map; 1862 uint32_t *msg, num_buffers; 1863 struct amdgpu_bo *bo; 1864 uint64_t start, end; 1865 unsigned int i; 1866 void * ptr; 1867 int r; 1868 1869 addr &= AMDGPU_GMC_HOLE_MASK; 1870 r = amdgpu_cs_find_mapping(p, addr, &bo, &map); 1871 if (r) { 1872 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 1873 return r; 1874 } 1875 1876 start = map->start * AMDGPU_GPU_PAGE_SIZE; 1877 end = (map->last + 1) * AMDGPU_GPU_PAGE_SIZE; 1878 if (addr & 0x7) { 1879 DRM_ERROR("VCN messages must be 8 byte aligned!\n"); 1880 return -EINVAL; 1881 } 1882 1883 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1884 amdgpu_bo_placement_from_domain(bo, bo->allowed_domains); 1885 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 1886 if (r) { 1887 DRM_ERROR("Failed validating the VCN message BO (%d)!\n", r); 1888 return r; 1889 } 1890 1891 r = amdgpu_bo_kmap(bo, &ptr); 1892 if (r) { 1893 DRM_ERROR("Failed mapping the VCN message (%d)!\n", r); 1894 return r; 1895 } 1896 1897 msg = ptr + addr - start; 1898 1899 /* Check length */ 1900 if (msg[1] > end - addr) { 1901 r = -EINVAL; 1902 goto out; 1903 } 1904 1905 if (msg[3] != RDECODE_MSG_CREATE) 1906 goto out; 1907 1908 num_buffers = msg[2]; 1909 for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) { 1910 uint32_t offset, size, *create; 1911 1912 if (msg[0] != RDECODE_MESSAGE_CREATE) 1913 continue; 1914 1915 offset = msg[1]; 1916 size = msg[2]; 1917 1918 if (offset + size > end) { 1919 r = -EINVAL; 1920 goto out; 1921 } 1922 1923 create = ptr + addr + offset - start; 1924 1925 /* H246, HEVC and VP9 can run on any instance */ 1926 if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11) 1927 continue; 1928 1929 r = vcn_v3_0_limit_sched(p); 1930 if (r) 1931 goto out; 1932 } 1933 1934 out: 1935 amdgpu_bo_kunmap(bo); 1936 return r; 1937 } 1938 1939 static int vcn_v3_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, 1940 uint32_t ib_idx) 1941 { 1942 struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched); 1943 struct amdgpu_ib *ib = &p->job->ibs[ib_idx]; 1944 uint32_t msg_lo = 0, msg_hi = 0; 1945 unsigned i; 1946 int r; 1947 1948 /* The first instance can decode anything */ 1949 if (!ring->me) 1950 return 0; 1951 1952 for (i = 0; i < ib->length_dw; i += 2) { 1953 uint32_t reg = amdgpu_get_ib_value(p, ib_idx, i); 1954 uint32_t val = amdgpu_get_ib_value(p, ib_idx, i + 1); 1955 1956 if (reg == PACKET0(p->adev->vcn.internal.data0, 0)) { 1957 msg_lo = val; 1958 } else if (reg == PACKET0(p->adev->vcn.internal.data1, 0)) { 1959 msg_hi = val; 1960 } else if (reg == PACKET0(p->adev->vcn.internal.cmd, 0) && 1961 val == 0) { 1962 r = vcn_v3_0_dec_msg(p, ((u64)msg_hi) << 32 | msg_lo); 1963 if (r) 1964 return r; 1965 } 1966 } 1967 return 0; 1968 } 1969 1970 static const struct amdgpu_ring_funcs vcn_v3_0_dec_ring_vm_funcs = { 1971 .type = AMDGPU_RING_TYPE_VCN_DEC, 1972 .align_mask = 0xf, 1973 .vmhub = AMDGPU_MMHUB_0, 1974 .get_rptr = vcn_v3_0_dec_ring_get_rptr, 1975 .get_wptr = vcn_v3_0_dec_ring_get_wptr, 1976 .set_wptr = vcn_v3_0_dec_ring_set_wptr, 1977 .patch_cs_in_place = vcn_v3_0_ring_patch_cs_in_place, 1978 .emit_frame_size = 1979 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1980 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1981 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */ 1982 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */ 1983 6, 1984 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */ 1985 .emit_ib = vcn_v2_0_dec_ring_emit_ib, 1986 .emit_fence = vcn_v2_0_dec_ring_emit_fence, 1987 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush, 1988 .test_ring = vcn_v2_0_dec_ring_test_ring, 1989 .test_ib = amdgpu_vcn_dec_ring_test_ib, 1990 .insert_nop = vcn_v2_0_dec_ring_insert_nop, 1991 .insert_start = vcn_v2_0_dec_ring_insert_start, 1992 .insert_end = vcn_v2_0_dec_ring_insert_end, 1993 .pad_ib = amdgpu_ring_generic_pad_ib, 1994 .begin_use = amdgpu_vcn_ring_begin_use, 1995 .end_use = amdgpu_vcn_ring_end_use, 1996 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg, 1997 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait, 1998 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1999 }; 2000 2001 /** 2002 * vcn_v3_0_enc_ring_get_rptr - get enc read pointer 2003 * 2004 * @ring: amdgpu_ring pointer 2005 * 2006 * Returns the current hardware enc read pointer 2007 */ 2008 static uint64_t vcn_v3_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 2009 { 2010 struct amdgpu_device *adev = ring->adev; 2011 2012 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) 2013 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR); 2014 else 2015 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2); 2016 } 2017 2018 /** 2019 * vcn_v3_0_enc_ring_get_wptr - get enc write pointer 2020 * 2021 * @ring: amdgpu_ring pointer 2022 * 2023 * Returns the current hardware enc write pointer 2024 */ 2025 static uint64_t vcn_v3_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 2026 { 2027 struct amdgpu_device *adev = ring->adev; 2028 2029 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 2030 if (ring->use_doorbell) 2031 return adev->wb.wb[ring->wptr_offs]; 2032 else 2033 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR); 2034 } else { 2035 if (ring->use_doorbell) 2036 return adev->wb.wb[ring->wptr_offs]; 2037 else 2038 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2); 2039 } 2040 } 2041 2042 /** 2043 * vcn_v3_0_enc_ring_set_wptr - set enc write pointer 2044 * 2045 * @ring: amdgpu_ring pointer 2046 * 2047 * Commits the enc write pointer to the hardware 2048 */ 2049 static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 2050 { 2051 struct amdgpu_device *adev = ring->adev; 2052 2053 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 2054 if (ring->use_doorbell) { 2055 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 2056 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 2057 } else { 2058 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 2059 } 2060 } else { 2061 if (ring->use_doorbell) { 2062 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 2063 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 2064 } else { 2065 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 2066 } 2067 } 2068 } 2069 2070 static const struct amdgpu_ring_funcs vcn_v3_0_enc_ring_vm_funcs = { 2071 .type = AMDGPU_RING_TYPE_VCN_ENC, 2072 .align_mask = 0x3f, 2073 .nop = VCN_ENC_CMD_NO_OP, 2074 .vmhub = AMDGPU_MMHUB_0, 2075 .get_rptr = vcn_v3_0_enc_ring_get_rptr, 2076 .get_wptr = vcn_v3_0_enc_ring_get_wptr, 2077 .set_wptr = vcn_v3_0_enc_ring_set_wptr, 2078 .emit_frame_size = 2079 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2080 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 2081 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 2082 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 2083 1, /* vcn_v2_0_enc_ring_insert_end */ 2084 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 2085 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 2086 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 2087 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 2088 .test_ring = amdgpu_vcn_enc_ring_test_ring, 2089 .test_ib = amdgpu_vcn_enc_ring_test_ib, 2090 .insert_nop = amdgpu_ring_insert_nop, 2091 .insert_end = vcn_v2_0_enc_ring_insert_end, 2092 .pad_ib = amdgpu_ring_generic_pad_ib, 2093 .begin_use = amdgpu_vcn_ring_begin_use, 2094 .end_use = amdgpu_vcn_ring_end_use, 2095 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 2096 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 2097 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2098 }; 2099 2100 static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev) 2101 { 2102 int i; 2103 2104 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2105 if (adev->vcn.harvest_config & (1 << i)) 2106 continue; 2107 2108 if (!DEC_SW_RING_ENABLED) 2109 adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_ring_vm_funcs; 2110 else 2111 adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_sw_ring_vm_funcs; 2112 adev->vcn.inst[i].ring_dec.me = i; 2113 DRM_INFO("VCN(%d) decode%s is enabled in VM mode\n", i, 2114 DEC_SW_RING_ENABLED?"(Software Ring)":""); 2115 } 2116 } 2117 2118 static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev) 2119 { 2120 int i, j; 2121 2122 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2123 if (adev->vcn.harvest_config & (1 << i)) 2124 continue; 2125 2126 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 2127 adev->vcn.inst[i].ring_enc[j].funcs = &vcn_v3_0_enc_ring_vm_funcs; 2128 adev->vcn.inst[i].ring_enc[j].me = i; 2129 } 2130 if (adev->vcn.num_enc_rings > 0) 2131 DRM_INFO("VCN(%d) encode is enabled in VM mode\n", i); 2132 } 2133 } 2134 2135 static bool vcn_v3_0_is_idle(void *handle) 2136 { 2137 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2138 int i, ret = 1; 2139 2140 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2141 if (adev->vcn.harvest_config & (1 << i)) 2142 continue; 2143 2144 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); 2145 } 2146 2147 return ret; 2148 } 2149 2150 static int vcn_v3_0_wait_for_idle(void *handle) 2151 { 2152 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2153 int i, ret = 0; 2154 2155 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2156 if (adev->vcn.harvest_config & (1 << i)) 2157 continue; 2158 2159 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 2160 UVD_STATUS__IDLE); 2161 if (ret) 2162 return ret; 2163 } 2164 2165 return ret; 2166 } 2167 2168 static int vcn_v3_0_set_clockgating_state(void *handle, 2169 enum amd_clockgating_state state) 2170 { 2171 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2172 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 2173 int i; 2174 2175 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2176 if (adev->vcn.harvest_config & (1 << i)) 2177 continue; 2178 2179 if (enable) { 2180 if (RREG32_SOC15(VCN, i, mmUVD_STATUS) != UVD_STATUS__IDLE) 2181 return -EBUSY; 2182 vcn_v3_0_enable_clock_gating(adev, i); 2183 } else { 2184 vcn_v3_0_disable_clock_gating(adev, i); 2185 } 2186 } 2187 2188 return 0; 2189 } 2190 2191 static int vcn_v3_0_set_powergating_state(void *handle, 2192 enum amd_powergating_state state) 2193 { 2194 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2195 int ret; 2196 2197 /* for SRIOV, guest should not control VCN Power-gating 2198 * MMSCH FW should control Power-gating and clock-gating 2199 * guest should avoid touching CGC and PG 2200 */ 2201 if (amdgpu_sriov_vf(adev)) { 2202 adev->vcn.cur_state = AMD_PG_STATE_UNGATE; 2203 return 0; 2204 } 2205 2206 if(state == adev->vcn.cur_state) 2207 return 0; 2208 2209 if (state == AMD_PG_STATE_GATE) 2210 ret = vcn_v3_0_stop(adev); 2211 else 2212 ret = vcn_v3_0_start(adev); 2213 2214 if(!ret) 2215 adev->vcn.cur_state = state; 2216 2217 return ret; 2218 } 2219 2220 static int vcn_v3_0_set_interrupt_state(struct amdgpu_device *adev, 2221 struct amdgpu_irq_src *source, 2222 unsigned type, 2223 enum amdgpu_interrupt_state state) 2224 { 2225 return 0; 2226 } 2227 2228 static int vcn_v3_0_process_interrupt(struct amdgpu_device *adev, 2229 struct amdgpu_irq_src *source, 2230 struct amdgpu_iv_entry *entry) 2231 { 2232 uint32_t ip_instance; 2233 2234 switch (entry->client_id) { 2235 case SOC15_IH_CLIENTID_VCN: 2236 ip_instance = 0; 2237 break; 2238 case SOC15_IH_CLIENTID_VCN1: 2239 ip_instance = 1; 2240 break; 2241 default: 2242 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 2243 return 0; 2244 } 2245 2246 DRM_DEBUG("IH: VCN TRAP\n"); 2247 2248 switch (entry->src_id) { 2249 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT: 2250 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec); 2251 break; 2252 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 2253 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 2254 break; 2255 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY: 2256 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]); 2257 break; 2258 default: 2259 DRM_ERROR("Unhandled interrupt: %d %d\n", 2260 entry->src_id, entry->src_data[0]); 2261 break; 2262 } 2263 2264 return 0; 2265 } 2266 2267 static const struct amdgpu_irq_src_funcs vcn_v3_0_irq_funcs = { 2268 .set = vcn_v3_0_set_interrupt_state, 2269 .process = vcn_v3_0_process_interrupt, 2270 }; 2271 2272 static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev) 2273 { 2274 int i; 2275 2276 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2277 if (adev->vcn.harvest_config & (1 << i)) 2278 continue; 2279 2280 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1; 2281 adev->vcn.inst[i].irq.funcs = &vcn_v3_0_irq_funcs; 2282 } 2283 } 2284 2285 static const struct amd_ip_funcs vcn_v3_0_ip_funcs = { 2286 .name = "vcn_v3_0", 2287 .early_init = vcn_v3_0_early_init, 2288 .late_init = NULL, 2289 .sw_init = vcn_v3_0_sw_init, 2290 .sw_fini = vcn_v3_0_sw_fini, 2291 .hw_init = vcn_v3_0_hw_init, 2292 .hw_fini = vcn_v3_0_hw_fini, 2293 .suspend = vcn_v3_0_suspend, 2294 .resume = vcn_v3_0_resume, 2295 .is_idle = vcn_v3_0_is_idle, 2296 .wait_for_idle = vcn_v3_0_wait_for_idle, 2297 .check_soft_reset = NULL, 2298 .pre_soft_reset = NULL, 2299 .soft_reset = NULL, 2300 .post_soft_reset = NULL, 2301 .set_clockgating_state = vcn_v3_0_set_clockgating_state, 2302 .set_powergating_state = vcn_v3_0_set_powergating_state, 2303 }; 2304 2305 const struct amdgpu_ip_block_version vcn_v3_0_ip_block = 2306 { 2307 .type = AMD_IP_BLOCK_TYPE_VCN, 2308 .major = 3, 2309 .minor = 0, 2310 .rev = 0, 2311 .funcs = &vcn_v3_0_ip_funcs, 2312 }; 2313