1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_vcn.h" 27 #include "amdgpu_pm.h" 28 #include "soc15.h" 29 #include "soc15d.h" 30 #include "vcn_v2_0.h" 31 #include "mmsch_v3_0.h" 32 33 #include "vcn/vcn_3_0_0_offset.h" 34 #include "vcn/vcn_3_0_0_sh_mask.h" 35 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 36 37 #include <drm/drm_drv.h> 38 39 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x27 40 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x0f 41 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x10 42 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x11 43 #define mmUVD_NO_OP_INTERNAL_OFFSET 0x29 44 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x66 45 #define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d 46 47 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x431 48 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x3b4 49 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x3b5 50 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x25c 51 52 #define VCN_INSTANCES_SIENNA_CICHLID 2 53 #define DEC_SW_RING_ENABLED FALSE 54 55 #define RDECODE_MSG_CREATE 0x00000000 56 #define RDECODE_MESSAGE_CREATE 0x00000001 57 58 static int amdgpu_ih_clientid_vcns[] = { 59 SOC15_IH_CLIENTID_VCN, 60 SOC15_IH_CLIENTID_VCN1 61 }; 62 63 static int amdgpu_ucode_id_vcns[] = { 64 AMDGPU_UCODE_ID_VCN, 65 AMDGPU_UCODE_ID_VCN1 66 }; 67 68 static int vcn_v3_0_start_sriov(struct amdgpu_device *adev); 69 static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev); 70 static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev); 71 static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev); 72 static int vcn_v3_0_set_powergating_state(void *handle, 73 enum amd_powergating_state state); 74 static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev, 75 int inst_idx, struct dpg_pause_state *new_state); 76 77 static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring); 78 static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring); 79 80 /** 81 * vcn_v3_0_early_init - set function pointers 82 * 83 * @handle: amdgpu_device pointer 84 * 85 * Set ring and irq function pointers 86 */ 87 static int vcn_v3_0_early_init(void *handle) 88 { 89 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 90 91 if (amdgpu_sriov_vf(adev)) { 92 adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID; 93 adev->vcn.harvest_config = 0; 94 adev->vcn.num_enc_rings = 1; 95 96 } else { 97 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 | 98 AMDGPU_VCN_HARVEST_VCN1)) 99 /* both instances are harvested, disable the block */ 100 return -ENOENT; 101 102 if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(3, 0, 33)) 103 adev->vcn.num_enc_rings = 0; 104 else 105 adev->vcn.num_enc_rings = 2; 106 } 107 108 vcn_v3_0_set_dec_ring_funcs(adev); 109 vcn_v3_0_set_enc_ring_funcs(adev); 110 vcn_v3_0_set_irq_funcs(adev); 111 112 return 0; 113 } 114 115 /** 116 * vcn_v3_0_sw_init - sw init for VCN block 117 * 118 * @handle: amdgpu_device pointer 119 * 120 * Load firmware and sw initialization 121 */ 122 static int vcn_v3_0_sw_init(void *handle) 123 { 124 struct amdgpu_ring *ring; 125 int i, j, r; 126 int vcn_doorbell_index = 0; 127 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 128 129 r = amdgpu_vcn_sw_init(adev); 130 if (r) 131 return r; 132 133 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 134 const struct common_firmware_header *hdr; 135 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 136 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN; 137 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw; 138 adev->firmware.fw_size += 139 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 140 141 if (adev->vcn.num_vcn_inst == VCN_INSTANCES_SIENNA_CICHLID) { 142 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].ucode_id = AMDGPU_UCODE_ID_VCN1; 143 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].fw = adev->vcn.fw; 144 adev->firmware.fw_size += 145 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 146 } 147 dev_info(adev->dev, "Will use PSP to load VCN firmware\n"); 148 } 149 150 r = amdgpu_vcn_resume(adev); 151 if (r) 152 return r; 153 154 /* 155 * Note: doorbell assignment is fixed for SRIOV multiple VCN engines 156 * Formula: 157 * vcn_db_base = adev->doorbell_index.vcn.vcn_ring0_1 << 1; 158 * dec_ring_i = vcn_db_base + i * (adev->vcn.num_enc_rings + 1) 159 * enc_ring_i,j = vcn_db_base + i * (adev->vcn.num_enc_rings + 1) + 1 + j 160 */ 161 if (amdgpu_sriov_vf(adev)) { 162 vcn_doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1; 163 /* get DWORD offset */ 164 vcn_doorbell_index = vcn_doorbell_index << 1; 165 } 166 167 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 168 volatile struct amdgpu_fw_shared *fw_shared; 169 170 if (adev->vcn.harvest_config & (1 << i)) 171 continue; 172 173 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; 174 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; 175 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; 176 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; 177 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; 178 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; 179 180 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; 181 adev->vcn.inst[i].external.scratch9 = SOC15_REG_OFFSET(VCN, i, mmUVD_SCRATCH9); 182 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; 183 adev->vcn.inst[i].external.data0 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA0); 184 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; 185 adev->vcn.inst[i].external.data1 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA1); 186 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; 187 adev->vcn.inst[i].external.cmd = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_CMD); 188 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; 189 adev->vcn.inst[i].external.nop = SOC15_REG_OFFSET(VCN, i, mmUVD_NO_OP); 190 191 /* VCN DEC TRAP */ 192 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 193 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[i].irq); 194 if (r) 195 return r; 196 197 atomic_set(&adev->vcn.inst[i].sched_score, 0); 198 199 ring = &adev->vcn.inst[i].ring_dec; 200 ring->use_doorbell = true; 201 if (amdgpu_sriov_vf(adev)) { 202 ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1); 203 } else { 204 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i; 205 } 206 sprintf(ring->name, "vcn_dec_%d", i); 207 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 208 AMDGPU_RING_PRIO_DEFAULT, 209 &adev->vcn.inst[i].sched_score); 210 if (r) 211 return r; 212 213 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 214 enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(j); 215 216 /* VCN ENC TRAP */ 217 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 218 j + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); 219 if (r) 220 return r; 221 222 ring = &adev->vcn.inst[i].ring_enc[j]; 223 ring->use_doorbell = true; 224 if (amdgpu_sriov_vf(adev)) { 225 ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1) + 1 + j; 226 } else { 227 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + j + 8 * i; 228 } 229 sprintf(ring->name, "vcn_enc_%d.%d", i, j); 230 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 231 hw_prio, &adev->vcn.inst[i].sched_score); 232 if (r) 233 return r; 234 } 235 236 fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr; 237 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SW_RING_FLAG) | 238 cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG) | 239 cpu_to_le32(AMDGPU_VCN_FW_SHARED_FLAG_0_RB); 240 fw_shared->sw_ring.is_enabled = cpu_to_le32(DEC_SW_RING_ENABLED); 241 } 242 243 if (amdgpu_sriov_vf(adev)) { 244 r = amdgpu_virt_alloc_mm_table(adev); 245 if (r) 246 return r; 247 } 248 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 249 adev->vcn.pause_dpg_mode = vcn_v3_0_pause_dpg_mode; 250 251 return 0; 252 } 253 254 /** 255 * vcn_v3_0_sw_fini - sw fini for VCN block 256 * 257 * @handle: amdgpu_device pointer 258 * 259 * VCN suspend and free up sw allocation 260 */ 261 static int vcn_v3_0_sw_fini(void *handle) 262 { 263 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 264 int i, r, idx; 265 266 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 267 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 268 volatile struct amdgpu_fw_shared *fw_shared; 269 270 if (adev->vcn.harvest_config & (1 << i)) 271 continue; 272 fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr; 273 fw_shared->present_flag_0 = 0; 274 fw_shared->sw_ring.is_enabled = false; 275 } 276 277 drm_dev_exit(idx); 278 } 279 280 if (amdgpu_sriov_vf(adev)) 281 amdgpu_virt_free_mm_table(adev); 282 283 r = amdgpu_vcn_suspend(adev); 284 if (r) 285 return r; 286 287 r = amdgpu_vcn_sw_fini(adev); 288 289 return r; 290 } 291 292 /** 293 * vcn_v3_0_hw_init - start and test VCN block 294 * 295 * @handle: amdgpu_device pointer 296 * 297 * Initialize the hardware, boot up the VCPU and do some testing 298 */ 299 static int vcn_v3_0_hw_init(void *handle) 300 { 301 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 302 struct amdgpu_ring *ring; 303 int i, j, r; 304 305 if (amdgpu_sriov_vf(adev)) { 306 r = vcn_v3_0_start_sriov(adev); 307 if (r) 308 goto done; 309 310 /* initialize VCN dec and enc ring buffers */ 311 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 312 if (adev->vcn.harvest_config & (1 << i)) 313 continue; 314 315 ring = &adev->vcn.inst[i].ring_dec; 316 if (amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, i)) { 317 ring->sched.ready = false; 318 dev_info(adev->dev, "ring %s is disabled by hypervisor\n", ring->name); 319 } else { 320 ring->wptr = 0; 321 ring->wptr_old = 0; 322 vcn_v3_0_dec_ring_set_wptr(ring); 323 ring->sched.ready = true; 324 } 325 326 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 327 ring = &adev->vcn.inst[i].ring_enc[j]; 328 if (amdgpu_vcn_is_disabled_vcn(adev, VCN_ENCODE_RING, i)) { 329 ring->sched.ready = false; 330 dev_info(adev->dev, "ring %s is disabled by hypervisor\n", ring->name); 331 } else { 332 ring->wptr = 0; 333 ring->wptr_old = 0; 334 vcn_v3_0_enc_ring_set_wptr(ring); 335 ring->sched.ready = true; 336 } 337 } 338 } 339 } else { 340 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 341 if (adev->vcn.harvest_config & (1 << i)) 342 continue; 343 344 ring = &adev->vcn.inst[i].ring_dec; 345 346 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 347 ring->doorbell_index, i); 348 349 r = amdgpu_ring_test_helper(ring); 350 if (r) 351 goto done; 352 353 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 354 ring = &adev->vcn.inst[i].ring_enc[j]; 355 r = amdgpu_ring_test_helper(ring); 356 if (r) 357 goto done; 358 } 359 } 360 } 361 362 done: 363 if (!r) 364 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 365 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 366 367 return r; 368 } 369 370 /** 371 * vcn_v3_0_hw_fini - stop the hardware block 372 * 373 * @handle: amdgpu_device pointer 374 * 375 * Stop the VCN block, mark ring as not ready any more 376 */ 377 static int vcn_v3_0_hw_fini(void *handle) 378 { 379 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 380 int i; 381 382 cancel_delayed_work_sync(&adev->vcn.idle_work); 383 384 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 385 if (adev->vcn.harvest_config & (1 << i)) 386 continue; 387 388 if (!amdgpu_sriov_vf(adev)) { 389 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 390 (adev->vcn.cur_state != AMD_PG_STATE_GATE && 391 RREG32_SOC15(VCN, i, mmUVD_STATUS))) { 392 vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 393 } 394 } 395 } 396 397 return 0; 398 } 399 400 /** 401 * vcn_v3_0_suspend - suspend VCN block 402 * 403 * @handle: amdgpu_device pointer 404 * 405 * HW fini and suspend VCN block 406 */ 407 static int vcn_v3_0_suspend(void *handle) 408 { 409 int r; 410 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 411 412 r = vcn_v3_0_hw_fini(adev); 413 if (r) 414 return r; 415 416 r = amdgpu_vcn_suspend(adev); 417 418 return r; 419 } 420 421 /** 422 * vcn_v3_0_resume - resume VCN block 423 * 424 * @handle: amdgpu_device pointer 425 * 426 * Resume firmware and hw init VCN block 427 */ 428 static int vcn_v3_0_resume(void *handle) 429 { 430 int r; 431 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 432 433 r = amdgpu_vcn_resume(adev); 434 if (r) 435 return r; 436 437 r = vcn_v3_0_hw_init(adev); 438 439 return r; 440 } 441 442 /** 443 * vcn_v3_0_mc_resume - memory controller programming 444 * 445 * @adev: amdgpu_device pointer 446 * @inst: instance number 447 * 448 * Let the VCN memory controller know it's offsets 449 */ 450 static void vcn_v3_0_mc_resume(struct amdgpu_device *adev, int inst) 451 { 452 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 453 uint32_t offset; 454 455 /* cache window 0: fw */ 456 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 457 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 458 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 459 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 460 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 461 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 0); 462 offset = 0; 463 } else { 464 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 465 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 466 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 467 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 468 offset = size; 469 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 470 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 471 } 472 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE0, size); 473 474 /* cache window 1: stack */ 475 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 476 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 477 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 478 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 479 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET1, 0); 480 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 481 482 /* cache window 2: context */ 483 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 484 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 485 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 486 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 487 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET2, 0); 488 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 489 490 /* non-cache window */ 491 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 492 lower_32_bits(adev->vcn.inst[inst].fw_shared_gpu_addr)); 493 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 494 upper_32_bits(adev->vcn.inst[inst].fw_shared_gpu_addr)); 495 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_OFFSET0, 0); 496 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_SIZE0, 497 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); 498 } 499 500 static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 501 { 502 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 503 uint32_t offset; 504 505 /* cache window 0: fw */ 506 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 507 if (!indirect) { 508 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 509 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 510 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); 511 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 512 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 513 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); 514 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 515 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 516 } else { 517 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 518 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 519 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 520 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 521 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 522 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 523 } 524 offset = 0; 525 } else { 526 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 527 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 528 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 529 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 530 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 531 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 532 offset = size; 533 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 534 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 535 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 536 } 537 538 if (!indirect) 539 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 540 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 541 else 542 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 543 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 544 545 /* cache window 1: stack */ 546 if (!indirect) { 547 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 548 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 549 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 550 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 551 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 552 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 553 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 554 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 555 } else { 556 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 557 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 558 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 559 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 560 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 561 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 562 } 563 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 564 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 565 566 /* cache window 2: context */ 567 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 568 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 569 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 570 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 571 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 572 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 573 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 574 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 575 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 576 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 577 578 /* non-cache window */ 579 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 580 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 581 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect); 582 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 583 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 584 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect); 585 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 586 VCN, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 587 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 588 VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), 589 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); 590 591 /* VCN global tiling registers */ 592 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 593 UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 594 } 595 596 static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int inst) 597 { 598 uint32_t data = 0; 599 600 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 601 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 602 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 603 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 604 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 605 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 606 | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 607 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 608 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 609 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 610 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 611 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 612 | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 613 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 614 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 615 616 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 617 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 618 UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF); 619 } else { 620 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 621 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 622 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 623 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 624 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 625 | 1 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 626 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 627 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 628 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 629 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 630 | 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 631 | 1 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 632 | 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 633 | 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 634 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 635 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 0, 0x3F3FFFFF); 636 } 637 638 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); 639 data &= ~0x103; 640 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 641 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 642 UVD_POWER_STATUS__UVD_PG_EN_MASK; 643 644 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); 645 } 646 647 static void vcn_v3_0_enable_static_power_gating(struct amdgpu_device *adev, int inst) 648 { 649 uint32_t data; 650 651 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 652 /* Before power off, this indicator has to be turned on */ 653 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); 654 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 655 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 656 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); 657 658 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 659 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 660 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 661 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 662 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 663 | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 664 | 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 665 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 666 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 667 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 668 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 669 | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 670 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 671 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 672 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 673 674 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 675 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 676 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 677 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 678 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 679 | 2 << UVD_PGFSM_STATUS__UVDIRL_PWR_STATUS__SHIFT 680 | 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT 681 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 682 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 683 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 684 | 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT 685 | 2 << UVD_PGFSM_STATUS__UVDATD_PWR_STATUS__SHIFT 686 | 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT 687 | 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT); 688 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, data, 0x3F3FFFFF); 689 } 690 } 691 692 /** 693 * vcn_v3_0_disable_clock_gating - disable VCN clock gating 694 * 695 * @adev: amdgpu_device pointer 696 * @inst: instance number 697 * 698 * Disable clock gating for VCN block 699 */ 700 static void vcn_v3_0_disable_clock_gating(struct amdgpu_device *adev, int inst) 701 { 702 uint32_t data; 703 704 /* VCN disable CGC */ 705 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 706 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 707 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 708 else 709 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 710 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 711 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 712 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 713 714 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_GATE); 715 data &= ~(UVD_CGC_GATE__SYS_MASK 716 | UVD_CGC_GATE__UDEC_MASK 717 | UVD_CGC_GATE__MPEG2_MASK 718 | UVD_CGC_GATE__REGS_MASK 719 | UVD_CGC_GATE__RBC_MASK 720 | UVD_CGC_GATE__LMI_MC_MASK 721 | UVD_CGC_GATE__LMI_UMC_MASK 722 | UVD_CGC_GATE__IDCT_MASK 723 | UVD_CGC_GATE__MPRD_MASK 724 | UVD_CGC_GATE__MPC_MASK 725 | UVD_CGC_GATE__LBSI_MASK 726 | UVD_CGC_GATE__LRBBM_MASK 727 | UVD_CGC_GATE__UDEC_RE_MASK 728 | UVD_CGC_GATE__UDEC_CM_MASK 729 | UVD_CGC_GATE__UDEC_IT_MASK 730 | UVD_CGC_GATE__UDEC_DB_MASK 731 | UVD_CGC_GATE__UDEC_MP_MASK 732 | UVD_CGC_GATE__WCB_MASK 733 | UVD_CGC_GATE__VCPU_MASK 734 | UVD_CGC_GATE__MMSCH_MASK); 735 736 WREG32_SOC15(VCN, inst, mmUVD_CGC_GATE, data); 737 738 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); 739 740 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 741 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 742 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 743 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 744 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 745 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 746 | UVD_CGC_CTRL__SYS_MODE_MASK 747 | UVD_CGC_CTRL__UDEC_MODE_MASK 748 | UVD_CGC_CTRL__MPEG2_MODE_MASK 749 | UVD_CGC_CTRL__REGS_MODE_MASK 750 | UVD_CGC_CTRL__RBC_MODE_MASK 751 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 752 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 753 | UVD_CGC_CTRL__IDCT_MODE_MASK 754 | UVD_CGC_CTRL__MPRD_MODE_MASK 755 | UVD_CGC_CTRL__MPC_MODE_MASK 756 | UVD_CGC_CTRL__LBSI_MODE_MASK 757 | UVD_CGC_CTRL__LRBBM_MODE_MASK 758 | UVD_CGC_CTRL__WCB_MODE_MASK 759 | UVD_CGC_CTRL__VCPU_MODE_MASK 760 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 761 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 762 763 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE); 764 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 765 | UVD_SUVD_CGC_GATE__SIT_MASK 766 | UVD_SUVD_CGC_GATE__SMP_MASK 767 | UVD_SUVD_CGC_GATE__SCM_MASK 768 | UVD_SUVD_CGC_GATE__SDB_MASK 769 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 770 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 771 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 772 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 773 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 774 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 775 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 776 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 777 | UVD_SUVD_CGC_GATE__SCLR_MASK 778 | UVD_SUVD_CGC_GATE__ENT_MASK 779 | UVD_SUVD_CGC_GATE__IME_MASK 780 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 781 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 782 | UVD_SUVD_CGC_GATE__SITE_MASK 783 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 784 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 785 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 786 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 787 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK 788 | UVD_SUVD_CGC_GATE__EFC_MASK 789 | UVD_SUVD_CGC_GATE__SAOE_MASK 790 | UVD_SUVD_CGC_GATE__SRE_AV1_MASK 791 | UVD_SUVD_CGC_GATE__FBC_PCLK_MASK 792 | UVD_SUVD_CGC_GATE__FBC_CCLK_MASK 793 | UVD_SUVD_CGC_GATE__SCM_AV1_MASK 794 | UVD_SUVD_CGC_GATE__SMPA_MASK); 795 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE, data); 796 797 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2); 798 data |= (UVD_SUVD_CGC_GATE2__MPBE0_MASK 799 | UVD_SUVD_CGC_GATE2__MPBE1_MASK 800 | UVD_SUVD_CGC_GATE2__SIT_AV1_MASK 801 | UVD_SUVD_CGC_GATE2__SDB_AV1_MASK 802 | UVD_SUVD_CGC_GATE2__MPC1_MASK); 803 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2, data); 804 805 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL); 806 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 807 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 808 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 809 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 810 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 811 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 812 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 813 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 814 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 815 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 816 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK 817 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK 818 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK 819 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK 820 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 821 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 822 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK 823 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK 824 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK); 825 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data); 826 } 827 828 static void vcn_v3_0_clock_gating_dpg_mode(struct amdgpu_device *adev, 829 uint8_t sram_sel, int inst_idx, uint8_t indirect) 830 { 831 uint32_t reg_data = 0; 832 833 /* enable sw clock gating control */ 834 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 835 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 836 else 837 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 838 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 839 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 840 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 841 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 842 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 843 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 844 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 845 UVD_CGC_CTRL__SYS_MODE_MASK | 846 UVD_CGC_CTRL__UDEC_MODE_MASK | 847 UVD_CGC_CTRL__MPEG2_MODE_MASK | 848 UVD_CGC_CTRL__REGS_MODE_MASK | 849 UVD_CGC_CTRL__RBC_MODE_MASK | 850 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 851 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 852 UVD_CGC_CTRL__IDCT_MODE_MASK | 853 UVD_CGC_CTRL__MPRD_MODE_MASK | 854 UVD_CGC_CTRL__MPC_MODE_MASK | 855 UVD_CGC_CTRL__LBSI_MODE_MASK | 856 UVD_CGC_CTRL__LRBBM_MODE_MASK | 857 UVD_CGC_CTRL__WCB_MODE_MASK | 858 UVD_CGC_CTRL__VCPU_MODE_MASK | 859 UVD_CGC_CTRL__MMSCH_MODE_MASK); 860 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 861 VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); 862 863 /* turn off clock gating */ 864 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 865 VCN, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect); 866 867 /* turn on SUVD clock gating */ 868 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 869 VCN, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 870 871 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 872 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 873 VCN, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 874 } 875 876 /** 877 * vcn_v3_0_enable_clock_gating - enable VCN clock gating 878 * 879 * @adev: amdgpu_device pointer 880 * @inst: instance number 881 * 882 * Enable clock gating for VCN block 883 */ 884 static void vcn_v3_0_enable_clock_gating(struct amdgpu_device *adev, int inst) 885 { 886 uint32_t data; 887 888 /* enable VCN CGC */ 889 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 890 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 891 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 892 else 893 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 894 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 895 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 896 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 897 898 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 899 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 900 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 901 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 902 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 903 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 904 | UVD_CGC_CTRL__SYS_MODE_MASK 905 | UVD_CGC_CTRL__UDEC_MODE_MASK 906 | UVD_CGC_CTRL__MPEG2_MODE_MASK 907 | UVD_CGC_CTRL__REGS_MODE_MASK 908 | UVD_CGC_CTRL__RBC_MODE_MASK 909 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 910 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 911 | UVD_CGC_CTRL__IDCT_MODE_MASK 912 | UVD_CGC_CTRL__MPRD_MODE_MASK 913 | UVD_CGC_CTRL__MPC_MODE_MASK 914 | UVD_CGC_CTRL__LBSI_MODE_MASK 915 | UVD_CGC_CTRL__LRBBM_MODE_MASK 916 | UVD_CGC_CTRL__WCB_MODE_MASK 917 | UVD_CGC_CTRL__VCPU_MODE_MASK 918 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 919 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 920 921 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL); 922 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 923 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 924 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 925 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 926 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 927 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 928 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 929 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 930 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 931 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 932 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK 933 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK 934 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK 935 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK 936 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 937 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 938 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK 939 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK 940 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK); 941 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data); 942 } 943 944 static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 945 { 946 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr; 947 struct amdgpu_ring *ring; 948 uint32_t rb_bufsz, tmp; 949 950 /* disable register anti-hang mechanism */ 951 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1, 952 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 953 /* enable dynamic power gating mode */ 954 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS); 955 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 956 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 957 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp); 958 959 if (indirect) 960 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 961 962 /* enable clock gating */ 963 vcn_v3_0_clock_gating_dpg_mode(adev, 0, inst_idx, indirect); 964 965 /* enable VCPU clock */ 966 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 967 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 968 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK; 969 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 970 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 971 972 /* disable master interupt */ 973 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 974 VCN, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect); 975 976 /* setup mmUVD_LMI_CTRL */ 977 tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 978 UVD_LMI_CTRL__REQ_MODE_MASK | 979 UVD_LMI_CTRL__CRC_RESET_MASK | 980 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 981 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 982 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 983 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 984 0x00100000L); 985 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 986 VCN, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect); 987 988 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 989 VCN, inst_idx, mmUVD_MPC_CNTL), 990 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 991 992 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 993 VCN, inst_idx, mmUVD_MPC_SET_MUXA0), 994 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 995 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 996 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 997 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 998 999 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1000 VCN, inst_idx, mmUVD_MPC_SET_MUXB0), 1001 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1002 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1003 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1004 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 1005 1006 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1007 VCN, inst_idx, mmUVD_MPC_SET_MUX), 1008 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1009 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1010 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 1011 1012 vcn_v3_0_mc_resume_dpg_mode(adev, inst_idx, indirect); 1013 1014 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1015 VCN, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect); 1016 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1017 VCN, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect); 1018 1019 /* enable LMI MC and UMC channels */ 1020 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1021 VCN, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect); 1022 1023 /* unblock VCPU register access */ 1024 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1025 VCN, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect); 1026 1027 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 1028 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 1029 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1030 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 1031 1032 /* enable master interrupt */ 1033 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1034 VCN, inst_idx, mmUVD_MASTINT_EN), 1035 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 1036 1037 /* add nop to workaround PSP size check */ 1038 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1039 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 1040 1041 if (indirect) 1042 psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, 1043 (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr - 1044 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr)); 1045 1046 ring = &adev->vcn.inst[inst_idx].ring_dec; 1047 /* force RBC into idle state */ 1048 rb_bufsz = order_base_2(ring->ring_size); 1049 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1050 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1051 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1052 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1053 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1054 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp); 1055 1056 /* Stall DPG before WPTR/RPTR reset */ 1057 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1058 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1059 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1060 fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1061 1062 /* set the write pointer delay */ 1063 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0); 1064 1065 /* set the wb address */ 1066 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR, 1067 (upper_32_bits(ring->gpu_addr) >> 2)); 1068 1069 /* programm the RB_BASE for ring buffer */ 1070 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1071 lower_32_bits(ring->gpu_addr)); 1072 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1073 upper_32_bits(ring->gpu_addr)); 1074 1075 /* Initialize the ring buffer's read and write pointers */ 1076 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0); 1077 1078 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0); 1079 1080 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR); 1081 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, 1082 lower_32_bits(ring->wptr)); 1083 1084 /* Reset FW shared memory RBC WPTR/RPTR */ 1085 fw_shared->rb.rptr = 0; 1086 fw_shared->rb.wptr = lower_32_bits(ring->wptr); 1087 1088 /*resetting done, fw can check RB ring */ 1089 fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1090 1091 /* Unstall DPG */ 1092 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1093 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1094 1095 return 0; 1096 } 1097 1098 static int vcn_v3_0_start(struct amdgpu_device *adev) 1099 { 1100 volatile struct amdgpu_fw_shared *fw_shared; 1101 struct amdgpu_ring *ring; 1102 uint32_t rb_bufsz, tmp; 1103 int i, j, k, r; 1104 1105 if (adev->pm.dpm_enabled) 1106 amdgpu_dpm_enable_uvd(adev, true); 1107 1108 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1109 if (adev->vcn.harvest_config & (1 << i)) 1110 continue; 1111 1112 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG){ 1113 r = vcn_v3_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram); 1114 continue; 1115 } 1116 1117 /* disable VCN power gating */ 1118 vcn_v3_0_disable_static_power_gating(adev, i); 1119 1120 /* set VCN status busy */ 1121 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 1122 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp); 1123 1124 /*SW clock gating */ 1125 vcn_v3_0_disable_clock_gating(adev, i); 1126 1127 /* enable VCPU clock */ 1128 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1129 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 1130 1131 /* disable master interrupt */ 1132 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0, 1133 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1134 1135 /* enable LMI MC and UMC channels */ 1136 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0, 1137 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1138 1139 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1140 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1141 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1142 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1143 1144 /* setup mmUVD_LMI_CTRL */ 1145 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL); 1146 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | 1147 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1148 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1149 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1150 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1151 1152 /* setup mmUVD_MPC_CNTL */ 1153 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL); 1154 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1155 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1156 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp); 1157 1158 /* setup UVD_MPC_SET_MUXA0 */ 1159 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0, 1160 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1161 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1162 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1163 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1164 1165 /* setup UVD_MPC_SET_MUXB0 */ 1166 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0, 1167 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1168 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1169 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1170 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1171 1172 /* setup mmUVD_MPC_SET_MUX */ 1173 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX, 1174 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1175 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1176 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1177 1178 vcn_v3_0_mc_resume(adev, i); 1179 1180 /* VCN global tiling registers */ 1181 WREG32_SOC15(VCN, i, mmUVD_GFX10_ADDR_CONFIG, 1182 adev->gfx.config.gb_addr_config); 1183 1184 /* unblock VCPU register access */ 1185 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0, 1186 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1187 1188 /* release VCPU reset to boot */ 1189 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1190 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1191 1192 for (j = 0; j < 10; ++j) { 1193 uint32_t status; 1194 1195 for (k = 0; k < 100; ++k) { 1196 status = RREG32_SOC15(VCN, i, mmUVD_STATUS); 1197 if (status & 2) 1198 break; 1199 mdelay(10); 1200 } 1201 r = 0; 1202 if (status & 2) 1203 break; 1204 1205 DRM_ERROR("VCN[%d] decode not responding, trying to reset the VCPU!!!\n", i); 1206 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1207 UVD_VCPU_CNTL__BLK_RST_MASK, 1208 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1209 mdelay(10); 1210 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1211 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1212 1213 mdelay(10); 1214 r = -1; 1215 } 1216 1217 if (r) { 1218 DRM_ERROR("VCN[%d] decode not responding, giving up!!!\n", i); 1219 return r; 1220 } 1221 1222 /* enable master interrupt */ 1223 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 1224 UVD_MASTINT_EN__VCPU_EN_MASK, 1225 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1226 1227 /* clear the busy bit of VCN_STATUS */ 1228 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0, 1229 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1230 1231 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0); 1232 1233 ring = &adev->vcn.inst[i].ring_dec; 1234 /* force RBC into idle state */ 1235 rb_bufsz = order_base_2(ring->ring_size); 1236 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1237 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1238 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1239 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1240 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1241 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp); 1242 1243 fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr; 1244 fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1245 1246 /* programm the RB_BASE for ring buffer */ 1247 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1248 lower_32_bits(ring->gpu_addr)); 1249 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1250 upper_32_bits(ring->gpu_addr)); 1251 1252 /* Initialize the ring buffer's read and write pointers */ 1253 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0); 1254 1255 WREG32_SOC15(VCN, i, mmUVD_SCRATCH2, 0); 1256 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR); 1257 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR, 1258 lower_32_bits(ring->wptr)); 1259 fw_shared->rb.wptr = lower_32_bits(ring->wptr); 1260 fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1261 1262 if (adev->ip_versions[UVD_HWIP][0] != IP_VERSION(3, 0, 33)) { 1263 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1264 ring = &adev->vcn.inst[i].ring_enc[0]; 1265 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1266 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1267 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr); 1268 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1269 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4); 1270 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1271 1272 fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1273 ring = &adev->vcn.inst[i].ring_enc[1]; 1274 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1275 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1276 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1277 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1278 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4); 1279 fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1280 } 1281 } 1282 1283 return 0; 1284 } 1285 1286 static int vcn_v3_0_start_sriov(struct amdgpu_device *adev) 1287 { 1288 int i, j; 1289 struct amdgpu_ring *ring; 1290 uint64_t cache_addr; 1291 uint64_t rb_addr; 1292 uint64_t ctx_addr; 1293 uint32_t param, resp, expected; 1294 uint32_t offset, cache_size; 1295 uint32_t tmp, timeout; 1296 uint32_t id; 1297 1298 struct amdgpu_mm_table *table = &adev->virt.mm_table; 1299 uint32_t *table_loc; 1300 uint32_t table_size; 1301 uint32_t size, size_dw; 1302 1303 struct mmsch_v3_0_cmd_direct_write 1304 direct_wt = { {0} }; 1305 struct mmsch_v3_0_cmd_direct_read_modify_write 1306 direct_rd_mod_wt = { {0} }; 1307 struct mmsch_v3_0_cmd_end end = { {0} }; 1308 struct mmsch_v3_0_init_header header; 1309 1310 direct_wt.cmd_header.command_type = 1311 MMSCH_COMMAND__DIRECT_REG_WRITE; 1312 direct_rd_mod_wt.cmd_header.command_type = 1313 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1314 end.cmd_header.command_type = 1315 MMSCH_COMMAND__END; 1316 1317 header.version = MMSCH_VERSION; 1318 header.total_size = sizeof(struct mmsch_v3_0_init_header) >> 2; 1319 for (i = 0; i < AMDGPU_MAX_VCN_INSTANCES; i++) { 1320 header.inst[i].init_status = 0; 1321 header.inst[i].table_offset = 0; 1322 header.inst[i].table_size = 0; 1323 } 1324 1325 table_loc = (uint32_t *)table->cpu_addr; 1326 table_loc += header.total_size; 1327 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1328 if (adev->vcn.harvest_config & (1 << i)) 1329 continue; 1330 1331 table_size = 0; 1332 1333 MMSCH_V3_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i, 1334 mmUVD_STATUS), 1335 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 1336 1337 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 1338 1339 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1340 id = amdgpu_ucode_id_vcns[i]; 1341 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1342 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1343 adev->firmware.ucode[id].tmr_mc_addr_lo); 1344 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1345 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1346 adev->firmware.ucode[id].tmr_mc_addr_hi); 1347 offset = 0; 1348 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1349 mmUVD_VCPU_CACHE_OFFSET0), 1350 0); 1351 } else { 1352 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1353 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1354 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 1355 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1356 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1357 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 1358 offset = cache_size; 1359 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1360 mmUVD_VCPU_CACHE_OFFSET0), 1361 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 1362 } 1363 1364 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1365 mmUVD_VCPU_CACHE_SIZE0), 1366 cache_size); 1367 1368 cache_addr = adev->vcn.inst[i].gpu_addr + offset; 1369 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1370 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 1371 lower_32_bits(cache_addr)); 1372 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1373 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 1374 upper_32_bits(cache_addr)); 1375 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1376 mmUVD_VCPU_CACHE_OFFSET1), 1377 0); 1378 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1379 mmUVD_VCPU_CACHE_SIZE1), 1380 AMDGPU_VCN_STACK_SIZE); 1381 1382 cache_addr = adev->vcn.inst[i].gpu_addr + offset + 1383 AMDGPU_VCN_STACK_SIZE; 1384 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1385 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 1386 lower_32_bits(cache_addr)); 1387 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1388 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 1389 upper_32_bits(cache_addr)); 1390 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1391 mmUVD_VCPU_CACHE_OFFSET2), 1392 0); 1393 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1394 mmUVD_VCPU_CACHE_SIZE2), 1395 AMDGPU_VCN_CONTEXT_SIZE); 1396 1397 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 1398 ring = &adev->vcn.inst[i].ring_enc[j]; 1399 ring->wptr = 0; 1400 rb_addr = ring->gpu_addr; 1401 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1402 mmUVD_RB_BASE_LO), 1403 lower_32_bits(rb_addr)); 1404 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1405 mmUVD_RB_BASE_HI), 1406 upper_32_bits(rb_addr)); 1407 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1408 mmUVD_RB_SIZE), 1409 ring->ring_size / 4); 1410 } 1411 1412 ring = &adev->vcn.inst[i].ring_dec; 1413 ring->wptr = 0; 1414 rb_addr = ring->gpu_addr; 1415 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1416 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW), 1417 lower_32_bits(rb_addr)); 1418 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1419 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH), 1420 upper_32_bits(rb_addr)); 1421 /* force RBC into idle state */ 1422 tmp = order_base_2(ring->ring_size); 1423 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp); 1424 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1425 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1426 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1427 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1428 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1429 mmUVD_RBC_RB_CNTL), 1430 tmp); 1431 1432 /* add end packet */ 1433 MMSCH_V3_0_INSERT_END(); 1434 1435 /* refine header */ 1436 header.inst[i].init_status = 0; 1437 header.inst[i].table_offset = header.total_size; 1438 header.inst[i].table_size = table_size; 1439 header.total_size += table_size; 1440 } 1441 1442 /* Update init table header in memory */ 1443 size = sizeof(struct mmsch_v3_0_init_header); 1444 table_loc = (uint32_t *)table->cpu_addr; 1445 memcpy((void *)table_loc, &header, size); 1446 1447 /* message MMSCH (in VCN[0]) to initialize this client 1448 * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr 1449 * of memory descriptor location 1450 */ 1451 ctx_addr = table->gpu_addr; 1452 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 1453 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 1454 1455 /* 2, update vmid of descriptor */ 1456 tmp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID); 1457 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1458 /* use domain0 for MM scheduler */ 1459 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1460 WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, tmp); 1461 1462 /* 3, notify mmsch about the size of this descriptor */ 1463 size = header.total_size; 1464 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size); 1465 1466 /* 4, set resp to zero */ 1467 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0); 1468 1469 /* 5, kick off the initialization and wait until 1470 * MMSCH_VF_MAILBOX_RESP becomes non-zero 1471 */ 1472 param = 0x10000001; 1473 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, param); 1474 tmp = 0; 1475 timeout = 1000; 1476 resp = 0; 1477 expected = param + 1; 1478 while (resp != expected) { 1479 resp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); 1480 if (resp == expected) 1481 break; 1482 1483 udelay(10); 1484 tmp = tmp + 10; 1485 if (tmp >= timeout) { 1486 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 1487 " waiting for mmMMSCH_VF_MAILBOX_RESP "\ 1488 "(expected=0x%08x, readback=0x%08x)\n", 1489 tmp, expected, resp); 1490 return -EBUSY; 1491 } 1492 } 1493 1494 return 0; 1495 } 1496 1497 static int vcn_v3_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) 1498 { 1499 uint32_t tmp; 1500 1501 /* Wait for power status to be 1 */ 1502 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1503 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1504 1505 /* wait for read ptr to be equal to write ptr */ 1506 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR); 1507 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1508 1509 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2); 1510 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); 1511 1512 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1513 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); 1514 1515 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1516 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1517 1518 /* disable dynamic power gating mode */ 1519 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0, 1520 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1521 1522 return 0; 1523 } 1524 1525 static int vcn_v3_0_stop(struct amdgpu_device *adev) 1526 { 1527 uint32_t tmp; 1528 int i, r = 0; 1529 1530 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1531 if (adev->vcn.harvest_config & (1 << i)) 1532 continue; 1533 1534 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1535 r = vcn_v3_0_stop_dpg_mode(adev, i); 1536 continue; 1537 } 1538 1539 /* wait for vcn idle */ 1540 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1541 if (r) 1542 return r; 1543 1544 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1545 UVD_LMI_STATUS__READ_CLEAN_MASK | 1546 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1547 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1548 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1549 if (r) 1550 return r; 1551 1552 /* disable LMI UMC channel */ 1553 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2); 1554 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1555 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp); 1556 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK| 1557 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1558 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1559 if (r) 1560 return r; 1561 1562 /* block VCPU register access */ 1563 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 1564 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1565 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1566 1567 /* reset VCPU */ 1568 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1569 UVD_VCPU_CNTL__BLK_RST_MASK, 1570 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1571 1572 /* disable VCPU clock */ 1573 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1574 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1575 1576 /* apply soft reset */ 1577 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1578 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1579 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1580 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1581 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1582 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1583 1584 /* clear status */ 1585 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0); 1586 1587 /* apply HW clock gating */ 1588 vcn_v3_0_enable_clock_gating(adev, i); 1589 1590 /* enable VCN power gating */ 1591 vcn_v3_0_enable_static_power_gating(adev, i); 1592 } 1593 1594 if (adev->pm.dpm_enabled) 1595 amdgpu_dpm_enable_uvd(adev, false); 1596 1597 return 0; 1598 } 1599 1600 static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev, 1601 int inst_idx, struct dpg_pause_state *new_state) 1602 { 1603 volatile struct amdgpu_fw_shared *fw_shared; 1604 struct amdgpu_ring *ring; 1605 uint32_t reg_data = 0; 1606 int ret_code; 1607 1608 /* pause/unpause if state is changed */ 1609 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1610 DRM_DEBUG("dpg pause state changed %d -> %d", 1611 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1612 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) & 1613 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1614 1615 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1616 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, 1617 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1618 1619 if (!ret_code) { 1620 /* pause DPG */ 1621 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1622 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1623 1624 /* wait for ACK */ 1625 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE, 1626 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1627 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1628 1629 /* Stall DPG before WPTR/RPTR reset */ 1630 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1631 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1632 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1633 1634 if (adev->ip_versions[UVD_HWIP][0] != IP_VERSION(3, 0, 33)) { 1635 /* Restore */ 1636 fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr; 1637 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1638 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 1639 ring->wptr = 0; 1640 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr); 1641 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1642 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4); 1643 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1644 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1645 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1646 1647 fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1648 ring = &adev->vcn.inst[inst_idx].ring_enc[1]; 1649 ring->wptr = 0; 1650 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1651 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1652 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4); 1653 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1654 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1655 fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1656 1657 /* restore wptr/rptr with pointers saved in FW shared memory*/ 1658 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, fw_shared->rb.rptr); 1659 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, fw_shared->rb.wptr); 1660 } 1661 1662 /* Unstall DPG */ 1663 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1664 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1665 1666 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1667 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1668 } 1669 } else { 1670 /* unpause dpg, no need to wait */ 1671 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1672 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1673 } 1674 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1675 } 1676 1677 return 0; 1678 } 1679 1680 /** 1681 * vcn_v3_0_dec_ring_get_rptr - get read pointer 1682 * 1683 * @ring: amdgpu_ring pointer 1684 * 1685 * Returns the current hardware read pointer 1686 */ 1687 static uint64_t vcn_v3_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 1688 { 1689 struct amdgpu_device *adev = ring->adev; 1690 1691 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR); 1692 } 1693 1694 /** 1695 * vcn_v3_0_dec_ring_get_wptr - get write pointer 1696 * 1697 * @ring: amdgpu_ring pointer 1698 * 1699 * Returns the current hardware write pointer 1700 */ 1701 static uint64_t vcn_v3_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 1702 { 1703 struct amdgpu_device *adev = ring->adev; 1704 1705 if (ring->use_doorbell) 1706 return adev->wb.wb[ring->wptr_offs]; 1707 else 1708 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR); 1709 } 1710 1711 /** 1712 * vcn_v3_0_dec_ring_set_wptr - set write pointer 1713 * 1714 * @ring: amdgpu_ring pointer 1715 * 1716 * Commits the write pointer to the hardware 1717 */ 1718 static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 1719 { 1720 struct amdgpu_device *adev = ring->adev; 1721 volatile struct amdgpu_fw_shared *fw_shared; 1722 1723 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1724 /*whenever update RBC_RB_WPTR, we save the wptr in shared rb.wptr and scratch2 */ 1725 fw_shared = adev->vcn.inst[ring->me].fw_shared_cpu_addr; 1726 fw_shared->rb.wptr = lower_32_bits(ring->wptr); 1727 WREG32_SOC15(VCN, ring->me, mmUVD_SCRATCH2, 1728 lower_32_bits(ring->wptr)); 1729 } 1730 1731 if (ring->use_doorbell) { 1732 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 1733 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1734 } else { 1735 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1736 } 1737 } 1738 1739 static void vcn_v3_0_dec_sw_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1740 u64 seq, uint32_t flags) 1741 { 1742 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1743 1744 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_FENCE); 1745 amdgpu_ring_write(ring, addr); 1746 amdgpu_ring_write(ring, upper_32_bits(addr)); 1747 amdgpu_ring_write(ring, seq); 1748 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_TRAP); 1749 } 1750 1751 static void vcn_v3_0_dec_sw_ring_insert_end(struct amdgpu_ring *ring) 1752 { 1753 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END); 1754 } 1755 1756 static void vcn_v3_0_dec_sw_ring_emit_ib(struct amdgpu_ring *ring, 1757 struct amdgpu_job *job, 1758 struct amdgpu_ib *ib, 1759 uint32_t flags) 1760 { 1761 uint32_t vmid = AMDGPU_JOB_GET_VMID(job); 1762 1763 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_IB); 1764 amdgpu_ring_write(ring, vmid); 1765 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1766 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1767 amdgpu_ring_write(ring, ib->length_dw); 1768 } 1769 1770 static void vcn_v3_0_dec_sw_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1771 uint32_t val, uint32_t mask) 1772 { 1773 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WAIT); 1774 amdgpu_ring_write(ring, reg << 2); 1775 amdgpu_ring_write(ring, mask); 1776 amdgpu_ring_write(ring, val); 1777 } 1778 1779 static void vcn_v3_0_dec_sw_ring_emit_vm_flush(struct amdgpu_ring *ring, 1780 uint32_t vmid, uint64_t pd_addr) 1781 { 1782 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1783 uint32_t data0, data1, mask; 1784 1785 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1786 1787 /* wait for register write */ 1788 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance; 1789 data1 = lower_32_bits(pd_addr); 1790 mask = 0xffffffff; 1791 vcn_v3_0_dec_sw_ring_emit_reg_wait(ring, data0, data1, mask); 1792 } 1793 1794 static void vcn_v3_0_dec_sw_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) 1795 { 1796 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WRITE); 1797 amdgpu_ring_write(ring, reg << 2); 1798 amdgpu_ring_write(ring, val); 1799 } 1800 1801 static const struct amdgpu_ring_funcs vcn_v3_0_dec_sw_ring_vm_funcs = { 1802 .type = AMDGPU_RING_TYPE_VCN_DEC, 1803 .align_mask = 0x3f, 1804 .nop = VCN_DEC_SW_CMD_NO_OP, 1805 .vmhub = AMDGPU_MMHUB_0, 1806 .get_rptr = vcn_v3_0_dec_ring_get_rptr, 1807 .get_wptr = vcn_v3_0_dec_ring_get_wptr, 1808 .set_wptr = vcn_v3_0_dec_ring_set_wptr, 1809 .emit_frame_size = 1810 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1811 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1812 4 + /* vcn_v3_0_dec_sw_ring_emit_vm_flush */ 1813 5 + 5 + /* vcn_v3_0_dec_sw_ring_emit_fdec_swe x2 vm fdec_swe */ 1814 1, /* vcn_v3_0_dec_sw_ring_insert_end */ 1815 .emit_ib_size = 5, /* vcn_v3_0_dec_sw_ring_emit_ib */ 1816 .emit_ib = vcn_v3_0_dec_sw_ring_emit_ib, 1817 .emit_fence = vcn_v3_0_dec_sw_ring_emit_fence, 1818 .emit_vm_flush = vcn_v3_0_dec_sw_ring_emit_vm_flush, 1819 .test_ring = amdgpu_vcn_dec_sw_ring_test_ring, 1820 .test_ib = NULL,//amdgpu_vcn_dec_sw_ring_test_ib, 1821 .insert_nop = amdgpu_ring_insert_nop, 1822 .insert_end = vcn_v3_0_dec_sw_ring_insert_end, 1823 .pad_ib = amdgpu_ring_generic_pad_ib, 1824 .begin_use = amdgpu_vcn_ring_begin_use, 1825 .end_use = amdgpu_vcn_ring_end_use, 1826 .emit_wreg = vcn_v3_0_dec_sw_ring_emit_wreg, 1827 .emit_reg_wait = vcn_v3_0_dec_sw_ring_emit_reg_wait, 1828 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1829 }; 1830 1831 static int vcn_v3_0_limit_sched(struct amdgpu_cs_parser *p) 1832 { 1833 struct drm_gpu_scheduler **scheds; 1834 1835 /* The create msg must be in the first IB submitted */ 1836 if (atomic_read(&p->entity->fence_seq)) 1837 return -EINVAL; 1838 1839 scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_DEC] 1840 [AMDGPU_RING_PRIO_DEFAULT].sched; 1841 drm_sched_entity_modify_sched(p->entity, scheds, 1); 1842 return 0; 1843 } 1844 1845 static int vcn_v3_0_dec_msg(struct amdgpu_cs_parser *p, uint64_t addr) 1846 { 1847 struct ttm_operation_ctx ctx = { false, false }; 1848 struct amdgpu_bo_va_mapping *map; 1849 uint32_t *msg, num_buffers; 1850 struct amdgpu_bo *bo; 1851 uint64_t start, end; 1852 unsigned int i; 1853 void * ptr; 1854 int r; 1855 1856 addr &= AMDGPU_GMC_HOLE_MASK; 1857 r = amdgpu_cs_find_mapping(p, addr, &bo, &map); 1858 if (r) { 1859 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 1860 return r; 1861 } 1862 1863 start = map->start * AMDGPU_GPU_PAGE_SIZE; 1864 end = (map->last + 1) * AMDGPU_GPU_PAGE_SIZE; 1865 if (addr & 0x7) { 1866 DRM_ERROR("VCN messages must be 8 byte aligned!\n"); 1867 return -EINVAL; 1868 } 1869 1870 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1871 amdgpu_bo_placement_from_domain(bo, bo->allowed_domains); 1872 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 1873 if (r) { 1874 DRM_ERROR("Failed validating the VCN message BO (%d)!\n", r); 1875 return r; 1876 } 1877 1878 r = amdgpu_bo_kmap(bo, &ptr); 1879 if (r) { 1880 DRM_ERROR("Failed mapping the VCN message (%d)!\n", r); 1881 return r; 1882 } 1883 1884 msg = ptr + addr - start; 1885 1886 /* Check length */ 1887 if (msg[1] > end - addr) { 1888 r = -EINVAL; 1889 goto out; 1890 } 1891 1892 if (msg[3] != RDECODE_MSG_CREATE) 1893 goto out; 1894 1895 num_buffers = msg[2]; 1896 for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) { 1897 uint32_t offset, size, *create; 1898 1899 if (msg[0] != RDECODE_MESSAGE_CREATE) 1900 continue; 1901 1902 offset = msg[1]; 1903 size = msg[2]; 1904 1905 if (offset + size > end) { 1906 r = -EINVAL; 1907 goto out; 1908 } 1909 1910 create = ptr + addr + offset - start; 1911 1912 /* H246, HEVC and VP9 can run on any instance */ 1913 if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11) 1914 continue; 1915 1916 r = vcn_v3_0_limit_sched(p); 1917 if (r) 1918 goto out; 1919 } 1920 1921 out: 1922 amdgpu_bo_kunmap(bo); 1923 return r; 1924 } 1925 1926 static int vcn_v3_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, 1927 uint32_t ib_idx) 1928 { 1929 struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched); 1930 struct amdgpu_ib *ib = &p->job->ibs[ib_idx]; 1931 uint32_t msg_lo = 0, msg_hi = 0; 1932 unsigned i; 1933 int r; 1934 1935 /* The first instance can decode anything */ 1936 if (!ring->me) 1937 return 0; 1938 1939 for (i = 0; i < ib->length_dw; i += 2) { 1940 uint32_t reg = amdgpu_get_ib_value(p, ib_idx, i); 1941 uint32_t val = amdgpu_get_ib_value(p, ib_idx, i + 1); 1942 1943 if (reg == PACKET0(p->adev->vcn.internal.data0, 0)) { 1944 msg_lo = val; 1945 } else if (reg == PACKET0(p->adev->vcn.internal.data1, 0)) { 1946 msg_hi = val; 1947 } else if (reg == PACKET0(p->adev->vcn.internal.cmd, 0) && 1948 val == 0) { 1949 r = vcn_v3_0_dec_msg(p, ((u64)msg_hi) << 32 | msg_lo); 1950 if (r) 1951 return r; 1952 } 1953 } 1954 return 0; 1955 } 1956 1957 static const struct amdgpu_ring_funcs vcn_v3_0_dec_ring_vm_funcs = { 1958 .type = AMDGPU_RING_TYPE_VCN_DEC, 1959 .align_mask = 0xf, 1960 .vmhub = AMDGPU_MMHUB_0, 1961 .get_rptr = vcn_v3_0_dec_ring_get_rptr, 1962 .get_wptr = vcn_v3_0_dec_ring_get_wptr, 1963 .set_wptr = vcn_v3_0_dec_ring_set_wptr, 1964 .patch_cs_in_place = vcn_v3_0_ring_patch_cs_in_place, 1965 .emit_frame_size = 1966 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1967 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1968 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */ 1969 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */ 1970 6, 1971 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */ 1972 .emit_ib = vcn_v2_0_dec_ring_emit_ib, 1973 .emit_fence = vcn_v2_0_dec_ring_emit_fence, 1974 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush, 1975 .test_ring = vcn_v2_0_dec_ring_test_ring, 1976 .test_ib = amdgpu_vcn_dec_ring_test_ib, 1977 .insert_nop = vcn_v2_0_dec_ring_insert_nop, 1978 .insert_start = vcn_v2_0_dec_ring_insert_start, 1979 .insert_end = vcn_v2_0_dec_ring_insert_end, 1980 .pad_ib = amdgpu_ring_generic_pad_ib, 1981 .begin_use = amdgpu_vcn_ring_begin_use, 1982 .end_use = amdgpu_vcn_ring_end_use, 1983 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg, 1984 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait, 1985 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1986 }; 1987 1988 /** 1989 * vcn_v3_0_enc_ring_get_rptr - get enc read pointer 1990 * 1991 * @ring: amdgpu_ring pointer 1992 * 1993 * Returns the current hardware enc read pointer 1994 */ 1995 static uint64_t vcn_v3_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 1996 { 1997 struct amdgpu_device *adev = ring->adev; 1998 1999 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) 2000 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR); 2001 else 2002 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2); 2003 } 2004 2005 /** 2006 * vcn_v3_0_enc_ring_get_wptr - get enc write pointer 2007 * 2008 * @ring: amdgpu_ring pointer 2009 * 2010 * Returns the current hardware enc write pointer 2011 */ 2012 static uint64_t vcn_v3_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 2013 { 2014 struct amdgpu_device *adev = ring->adev; 2015 2016 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 2017 if (ring->use_doorbell) 2018 return adev->wb.wb[ring->wptr_offs]; 2019 else 2020 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR); 2021 } else { 2022 if (ring->use_doorbell) 2023 return adev->wb.wb[ring->wptr_offs]; 2024 else 2025 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2); 2026 } 2027 } 2028 2029 /** 2030 * vcn_v3_0_enc_ring_set_wptr - set enc write pointer 2031 * 2032 * @ring: amdgpu_ring pointer 2033 * 2034 * Commits the enc write pointer to the hardware 2035 */ 2036 static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 2037 { 2038 struct amdgpu_device *adev = ring->adev; 2039 2040 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 2041 if (ring->use_doorbell) { 2042 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 2043 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 2044 } else { 2045 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 2046 } 2047 } else { 2048 if (ring->use_doorbell) { 2049 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 2050 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 2051 } else { 2052 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 2053 } 2054 } 2055 } 2056 2057 static const struct amdgpu_ring_funcs vcn_v3_0_enc_ring_vm_funcs = { 2058 .type = AMDGPU_RING_TYPE_VCN_ENC, 2059 .align_mask = 0x3f, 2060 .nop = VCN_ENC_CMD_NO_OP, 2061 .vmhub = AMDGPU_MMHUB_0, 2062 .get_rptr = vcn_v3_0_enc_ring_get_rptr, 2063 .get_wptr = vcn_v3_0_enc_ring_get_wptr, 2064 .set_wptr = vcn_v3_0_enc_ring_set_wptr, 2065 .emit_frame_size = 2066 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2067 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 2068 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 2069 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 2070 1, /* vcn_v2_0_enc_ring_insert_end */ 2071 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 2072 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 2073 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 2074 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 2075 .test_ring = amdgpu_vcn_enc_ring_test_ring, 2076 .test_ib = amdgpu_vcn_enc_ring_test_ib, 2077 .insert_nop = amdgpu_ring_insert_nop, 2078 .insert_end = vcn_v2_0_enc_ring_insert_end, 2079 .pad_ib = amdgpu_ring_generic_pad_ib, 2080 .begin_use = amdgpu_vcn_ring_begin_use, 2081 .end_use = amdgpu_vcn_ring_end_use, 2082 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 2083 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 2084 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2085 }; 2086 2087 static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev) 2088 { 2089 int i; 2090 2091 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2092 if (adev->vcn.harvest_config & (1 << i)) 2093 continue; 2094 2095 if (!DEC_SW_RING_ENABLED) 2096 adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_ring_vm_funcs; 2097 else 2098 adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_sw_ring_vm_funcs; 2099 adev->vcn.inst[i].ring_dec.me = i; 2100 DRM_INFO("VCN(%d) decode%s is enabled in VM mode\n", i, 2101 DEC_SW_RING_ENABLED?"(Software Ring)":""); 2102 } 2103 } 2104 2105 static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev) 2106 { 2107 int i, j; 2108 2109 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2110 if (adev->vcn.harvest_config & (1 << i)) 2111 continue; 2112 2113 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 2114 adev->vcn.inst[i].ring_enc[j].funcs = &vcn_v3_0_enc_ring_vm_funcs; 2115 adev->vcn.inst[i].ring_enc[j].me = i; 2116 } 2117 if (adev->vcn.num_enc_rings > 0) 2118 DRM_INFO("VCN(%d) encode is enabled in VM mode\n", i); 2119 } 2120 } 2121 2122 static bool vcn_v3_0_is_idle(void *handle) 2123 { 2124 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2125 int i, ret = 1; 2126 2127 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2128 if (adev->vcn.harvest_config & (1 << i)) 2129 continue; 2130 2131 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); 2132 } 2133 2134 return ret; 2135 } 2136 2137 static int vcn_v3_0_wait_for_idle(void *handle) 2138 { 2139 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2140 int i, ret = 0; 2141 2142 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2143 if (adev->vcn.harvest_config & (1 << i)) 2144 continue; 2145 2146 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 2147 UVD_STATUS__IDLE); 2148 if (ret) 2149 return ret; 2150 } 2151 2152 return ret; 2153 } 2154 2155 static int vcn_v3_0_set_clockgating_state(void *handle, 2156 enum amd_clockgating_state state) 2157 { 2158 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2159 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 2160 int i; 2161 2162 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2163 if (adev->vcn.harvest_config & (1 << i)) 2164 continue; 2165 2166 if (enable) { 2167 if (RREG32_SOC15(VCN, i, mmUVD_STATUS) != UVD_STATUS__IDLE) 2168 return -EBUSY; 2169 vcn_v3_0_enable_clock_gating(adev, i); 2170 } else { 2171 vcn_v3_0_disable_clock_gating(adev, i); 2172 } 2173 } 2174 2175 return 0; 2176 } 2177 2178 static int vcn_v3_0_set_powergating_state(void *handle, 2179 enum amd_powergating_state state) 2180 { 2181 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2182 int ret; 2183 2184 /* for SRIOV, guest should not control VCN Power-gating 2185 * MMSCH FW should control Power-gating and clock-gating 2186 * guest should avoid touching CGC and PG 2187 */ 2188 if (amdgpu_sriov_vf(adev)) { 2189 adev->vcn.cur_state = AMD_PG_STATE_UNGATE; 2190 return 0; 2191 } 2192 2193 if(state == adev->vcn.cur_state) 2194 return 0; 2195 2196 if (state == AMD_PG_STATE_GATE) 2197 ret = vcn_v3_0_stop(adev); 2198 else 2199 ret = vcn_v3_0_start(adev); 2200 2201 if(!ret) 2202 adev->vcn.cur_state = state; 2203 2204 return ret; 2205 } 2206 2207 static int vcn_v3_0_set_interrupt_state(struct amdgpu_device *adev, 2208 struct amdgpu_irq_src *source, 2209 unsigned type, 2210 enum amdgpu_interrupt_state state) 2211 { 2212 return 0; 2213 } 2214 2215 static int vcn_v3_0_process_interrupt(struct amdgpu_device *adev, 2216 struct amdgpu_irq_src *source, 2217 struct amdgpu_iv_entry *entry) 2218 { 2219 uint32_t ip_instance; 2220 2221 switch (entry->client_id) { 2222 case SOC15_IH_CLIENTID_VCN: 2223 ip_instance = 0; 2224 break; 2225 case SOC15_IH_CLIENTID_VCN1: 2226 ip_instance = 1; 2227 break; 2228 default: 2229 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 2230 return 0; 2231 } 2232 2233 DRM_DEBUG("IH: VCN TRAP\n"); 2234 2235 switch (entry->src_id) { 2236 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT: 2237 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec); 2238 break; 2239 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 2240 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 2241 break; 2242 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY: 2243 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]); 2244 break; 2245 default: 2246 DRM_ERROR("Unhandled interrupt: %d %d\n", 2247 entry->src_id, entry->src_data[0]); 2248 break; 2249 } 2250 2251 return 0; 2252 } 2253 2254 static const struct amdgpu_irq_src_funcs vcn_v3_0_irq_funcs = { 2255 .set = vcn_v3_0_set_interrupt_state, 2256 .process = vcn_v3_0_process_interrupt, 2257 }; 2258 2259 static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev) 2260 { 2261 int i; 2262 2263 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2264 if (adev->vcn.harvest_config & (1 << i)) 2265 continue; 2266 2267 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1; 2268 adev->vcn.inst[i].irq.funcs = &vcn_v3_0_irq_funcs; 2269 } 2270 } 2271 2272 static const struct amd_ip_funcs vcn_v3_0_ip_funcs = { 2273 .name = "vcn_v3_0", 2274 .early_init = vcn_v3_0_early_init, 2275 .late_init = NULL, 2276 .sw_init = vcn_v3_0_sw_init, 2277 .sw_fini = vcn_v3_0_sw_fini, 2278 .hw_init = vcn_v3_0_hw_init, 2279 .hw_fini = vcn_v3_0_hw_fini, 2280 .suspend = vcn_v3_0_suspend, 2281 .resume = vcn_v3_0_resume, 2282 .is_idle = vcn_v3_0_is_idle, 2283 .wait_for_idle = vcn_v3_0_wait_for_idle, 2284 .check_soft_reset = NULL, 2285 .pre_soft_reset = NULL, 2286 .soft_reset = NULL, 2287 .post_soft_reset = NULL, 2288 .set_clockgating_state = vcn_v3_0_set_clockgating_state, 2289 .set_powergating_state = vcn_v3_0_set_powergating_state, 2290 }; 2291 2292 const struct amdgpu_ip_block_version vcn_v3_0_ip_block = 2293 { 2294 .type = AMD_IP_BLOCK_TYPE_VCN, 2295 .major = 3, 2296 .minor = 0, 2297 .rev = 0, 2298 .funcs = &vcn_v3_0_ip_funcs, 2299 }; 2300