1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_vcn.h" 27 #include "amdgpu_pm.h" 28 #include "soc15.h" 29 #include "soc15d.h" 30 #include "vcn_v2_0.h" 31 #include "mmsch_v3_0.h" 32 33 #include "vcn/vcn_3_0_0_offset.h" 34 #include "vcn/vcn_3_0_0_sh_mask.h" 35 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 36 37 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x27 38 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x0f 39 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x10 40 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x11 41 #define mmUVD_NO_OP_INTERNAL_OFFSET 0x29 42 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x66 43 #define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d 44 45 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x431 46 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x3b4 47 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x3b5 48 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x25c 49 50 #define VCN_INSTANCES_SIENNA_CICHLID 2 51 #define DEC_SW_RING_ENABLED FALSE 52 53 static int amdgpu_ih_clientid_vcns[] = { 54 SOC15_IH_CLIENTID_VCN, 55 SOC15_IH_CLIENTID_VCN1 56 }; 57 58 static int amdgpu_ucode_id_vcns[] = { 59 AMDGPU_UCODE_ID_VCN, 60 AMDGPU_UCODE_ID_VCN1 61 }; 62 63 static int vcn_v3_0_start_sriov(struct amdgpu_device *adev); 64 static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev); 65 static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev); 66 static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev); 67 static int vcn_v3_0_set_powergating_state(void *handle, 68 enum amd_powergating_state state); 69 static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev, 70 int inst_idx, struct dpg_pause_state *new_state); 71 72 static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring); 73 static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring); 74 75 /** 76 * vcn_v3_0_early_init - set function pointers 77 * 78 * @handle: amdgpu_device pointer 79 * 80 * Set ring and irq function pointers 81 */ 82 static int vcn_v3_0_early_init(void *handle) 83 { 84 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 85 86 if (amdgpu_sriov_vf(adev)) { 87 adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID; 88 adev->vcn.harvest_config = 0; 89 adev->vcn.num_enc_rings = 1; 90 91 } else { 92 if (adev->asic_type == CHIP_SIENNA_CICHLID) { 93 u32 harvest; 94 int i; 95 96 adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID; 97 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 98 harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING); 99 if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK) 100 adev->vcn.harvest_config |= 1 << i; 101 } 102 103 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 | 104 AMDGPU_VCN_HARVEST_VCN1)) 105 /* both instances are harvested, disable the block */ 106 return -ENOENT; 107 } else 108 adev->vcn.num_vcn_inst = 1; 109 110 adev->vcn.num_enc_rings = 2; 111 } 112 113 vcn_v3_0_set_dec_ring_funcs(adev); 114 vcn_v3_0_set_enc_ring_funcs(adev); 115 vcn_v3_0_set_irq_funcs(adev); 116 117 return 0; 118 } 119 120 /** 121 * vcn_v3_0_sw_init - sw init for VCN block 122 * 123 * @handle: amdgpu_device pointer 124 * 125 * Load firmware and sw initialization 126 */ 127 static int vcn_v3_0_sw_init(void *handle) 128 { 129 struct amdgpu_ring *ring; 130 int i, j, r; 131 int vcn_doorbell_index = 0; 132 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 133 134 r = amdgpu_vcn_sw_init(adev); 135 if (r) 136 return r; 137 138 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 139 const struct common_firmware_header *hdr; 140 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 141 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN; 142 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw; 143 adev->firmware.fw_size += 144 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 145 146 if (adev->vcn.num_vcn_inst == VCN_INSTANCES_SIENNA_CICHLID) { 147 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].ucode_id = AMDGPU_UCODE_ID_VCN1; 148 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].fw = adev->vcn.fw; 149 adev->firmware.fw_size += 150 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 151 } 152 DRM_INFO("PSP loading VCN firmware\n"); 153 } 154 155 r = amdgpu_vcn_resume(adev); 156 if (r) 157 return r; 158 159 /* 160 * Note: doorbell assignment is fixed for SRIOV multiple VCN engines 161 * Formula: 162 * vcn_db_base = adev->doorbell_index.vcn.vcn_ring0_1 << 1; 163 * dec_ring_i = vcn_db_base + i * (adev->vcn.num_enc_rings + 1) 164 * enc_ring_i,j = vcn_db_base + i * (adev->vcn.num_enc_rings + 1) + 1 + j 165 */ 166 if (amdgpu_sriov_vf(adev)) { 167 vcn_doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1; 168 /* get DWORD offset */ 169 vcn_doorbell_index = vcn_doorbell_index << 1; 170 } 171 172 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 173 volatile struct amdgpu_fw_shared *fw_shared; 174 if (adev->vcn.harvest_config & (1 << i)) 175 continue; 176 177 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; 178 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; 179 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; 180 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; 181 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; 182 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; 183 184 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; 185 adev->vcn.inst[i].external.scratch9 = SOC15_REG_OFFSET(VCN, i, mmUVD_SCRATCH9); 186 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; 187 adev->vcn.inst[i].external.data0 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA0); 188 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; 189 adev->vcn.inst[i].external.data1 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA1); 190 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; 191 adev->vcn.inst[i].external.cmd = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_CMD); 192 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; 193 adev->vcn.inst[i].external.nop = SOC15_REG_OFFSET(VCN, i, mmUVD_NO_OP); 194 195 /* VCN DEC TRAP */ 196 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 197 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[i].irq); 198 if (r) 199 return r; 200 201 ring = &adev->vcn.inst[i].ring_dec; 202 ring->use_doorbell = true; 203 if (amdgpu_sriov_vf(adev)) { 204 ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1); 205 } else { 206 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i; 207 } 208 if (adev->asic_type == CHIP_SIENNA_CICHLID && i != 0) 209 ring->no_scheduler = true; 210 sprintf(ring->name, "vcn_dec_%d", i); 211 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 212 AMDGPU_RING_PRIO_DEFAULT); 213 if (r) 214 return r; 215 216 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 217 /* VCN ENC TRAP */ 218 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 219 j + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); 220 if (r) 221 return r; 222 223 ring = &adev->vcn.inst[i].ring_enc[j]; 224 ring->use_doorbell = true; 225 if (amdgpu_sriov_vf(adev)) { 226 ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1) + 1 + j; 227 } else { 228 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + j + 8 * i; 229 } 230 if (adev->asic_type == CHIP_SIENNA_CICHLID && i != 1) 231 ring->no_scheduler = true; 232 sprintf(ring->name, "vcn_enc_%d.%d", i, j); 233 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 234 AMDGPU_RING_PRIO_DEFAULT); 235 if (r) 236 return r; 237 } 238 239 fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr; 240 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SW_RING_FLAG) | 241 cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG) | 242 cpu_to_le32(AMDGPU_VCN_FW_SHARED_FLAG_0_RB); 243 fw_shared->sw_ring.is_enabled = cpu_to_le32(DEC_SW_RING_ENABLED); 244 } 245 246 if (amdgpu_sriov_vf(adev)) { 247 r = amdgpu_virt_alloc_mm_table(adev); 248 if (r) 249 return r; 250 } 251 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 252 adev->vcn.pause_dpg_mode = vcn_v3_0_pause_dpg_mode; 253 254 return 0; 255 } 256 257 /** 258 * vcn_v3_0_sw_fini - sw fini for VCN block 259 * 260 * @handle: amdgpu_device pointer 261 * 262 * VCN suspend and free up sw allocation 263 */ 264 static int vcn_v3_0_sw_fini(void *handle) 265 { 266 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 267 int i, r; 268 269 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 270 volatile struct amdgpu_fw_shared *fw_shared; 271 272 if (adev->vcn.harvest_config & (1 << i)) 273 continue; 274 fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr; 275 fw_shared->present_flag_0 = 0; 276 fw_shared->sw_ring.is_enabled = false; 277 } 278 279 if (amdgpu_sriov_vf(adev)) 280 amdgpu_virt_free_mm_table(adev); 281 282 r = amdgpu_vcn_suspend(adev); 283 if (r) 284 return r; 285 286 r = amdgpu_vcn_sw_fini(adev); 287 288 return r; 289 } 290 291 /** 292 * vcn_v3_0_hw_init - start and test VCN block 293 * 294 * @handle: amdgpu_device pointer 295 * 296 * Initialize the hardware, boot up the VCPU and do some testing 297 */ 298 static int vcn_v3_0_hw_init(void *handle) 299 { 300 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 301 struct amdgpu_ring *ring; 302 int i, j, r; 303 304 if (amdgpu_sriov_vf(adev)) { 305 r = vcn_v3_0_start_sriov(adev); 306 if (r) 307 goto done; 308 309 /* initialize VCN dec and enc ring buffers */ 310 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 311 if (adev->vcn.harvest_config & (1 << i)) 312 continue; 313 314 ring = &adev->vcn.inst[i].ring_dec; 315 if (ring->sched.ready) { 316 ring->wptr = 0; 317 ring->wptr_old = 0; 318 vcn_v3_0_dec_ring_set_wptr(ring); 319 } 320 321 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 322 ring = &adev->vcn.inst[i].ring_enc[j]; 323 if (ring->sched.ready) { 324 ring->wptr = 0; 325 ring->wptr_old = 0; 326 vcn_v3_0_enc_ring_set_wptr(ring); 327 } 328 } 329 } 330 } else { 331 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 332 if (adev->vcn.harvest_config & (1 << i)) 333 continue; 334 335 ring = &adev->vcn.inst[i].ring_dec; 336 337 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 338 ring->doorbell_index, i); 339 340 r = amdgpu_ring_test_helper(ring); 341 if (r) 342 goto done; 343 344 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 345 ring = &adev->vcn.inst[i].ring_enc[j]; 346 r = amdgpu_ring_test_helper(ring); 347 if (r) 348 goto done; 349 } 350 } 351 } 352 353 done: 354 if (!r) 355 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 356 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 357 358 return r; 359 } 360 361 /** 362 * vcn_v3_0_hw_fini - stop the hardware block 363 * 364 * @handle: amdgpu_device pointer 365 * 366 * Stop the VCN block, mark ring as not ready any more 367 */ 368 static int vcn_v3_0_hw_fini(void *handle) 369 { 370 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 371 struct amdgpu_ring *ring; 372 int i, j; 373 374 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 375 if (adev->vcn.harvest_config & (1 << i)) 376 continue; 377 378 ring = &adev->vcn.inst[i].ring_dec; 379 380 if (!amdgpu_sriov_vf(adev)) { 381 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 382 (adev->vcn.cur_state != AMD_PG_STATE_GATE && 383 RREG32_SOC15(VCN, i, mmUVD_STATUS))) { 384 vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 385 } 386 } 387 ring->sched.ready = false; 388 389 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 390 ring = &adev->vcn.inst[i].ring_enc[j]; 391 ring->sched.ready = false; 392 } 393 } 394 395 return 0; 396 } 397 398 /** 399 * vcn_v3_0_suspend - suspend VCN block 400 * 401 * @handle: amdgpu_device pointer 402 * 403 * HW fini and suspend VCN block 404 */ 405 static int vcn_v3_0_suspend(void *handle) 406 { 407 int r; 408 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 409 410 r = vcn_v3_0_hw_fini(adev); 411 if (r) 412 return r; 413 414 r = amdgpu_vcn_suspend(adev); 415 416 return r; 417 } 418 419 /** 420 * vcn_v3_0_resume - resume VCN block 421 * 422 * @handle: amdgpu_device pointer 423 * 424 * Resume firmware and hw init VCN block 425 */ 426 static int vcn_v3_0_resume(void *handle) 427 { 428 int r; 429 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 430 431 r = amdgpu_vcn_resume(adev); 432 if (r) 433 return r; 434 435 r = vcn_v3_0_hw_init(adev); 436 437 return r; 438 } 439 440 /** 441 * vcn_v3_0_mc_resume - memory controller programming 442 * 443 * @adev: amdgpu_device pointer 444 * @inst: instance number 445 * 446 * Let the VCN memory controller know it's offsets 447 */ 448 static void vcn_v3_0_mc_resume(struct amdgpu_device *adev, int inst) 449 { 450 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 451 uint32_t offset; 452 453 /* cache window 0: fw */ 454 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 455 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 456 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 457 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 458 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 459 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 0); 460 offset = 0; 461 } else { 462 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 463 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 464 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 465 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 466 offset = size; 467 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 468 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 469 } 470 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE0, size); 471 472 /* cache window 1: stack */ 473 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 474 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 475 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 476 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 477 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET1, 0); 478 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 479 480 /* cache window 2: context */ 481 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 482 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 483 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 484 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 485 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET2, 0); 486 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 487 488 /* non-cache window */ 489 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 490 lower_32_bits(adev->vcn.inst[inst].fw_shared_gpu_addr)); 491 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 492 upper_32_bits(adev->vcn.inst[inst].fw_shared_gpu_addr)); 493 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_OFFSET0, 0); 494 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_SIZE0, 495 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); 496 } 497 498 static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 499 { 500 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 501 uint32_t offset; 502 503 /* cache window 0: fw */ 504 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 505 if (!indirect) { 506 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 507 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 508 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); 509 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 510 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 511 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); 512 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 513 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 514 } else { 515 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 516 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 517 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 518 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 519 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 520 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 521 } 522 offset = 0; 523 } else { 524 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 525 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 526 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 527 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 528 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 529 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 530 offset = size; 531 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 532 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 533 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 534 } 535 536 if (!indirect) 537 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 538 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 539 else 540 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 541 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 542 543 /* cache window 1: stack */ 544 if (!indirect) { 545 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 546 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 547 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 548 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 549 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 550 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 551 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 552 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 553 } else { 554 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 555 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 556 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 557 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 558 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 559 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 560 } 561 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 562 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 563 564 /* cache window 2: context */ 565 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 566 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 567 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 568 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 569 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 570 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 571 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 572 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 573 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 574 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 575 576 /* non-cache window */ 577 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 578 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 579 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect); 580 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 581 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 582 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect); 583 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 584 VCN, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 585 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 586 VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), 587 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); 588 } 589 590 static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int inst) 591 { 592 uint32_t data = 0; 593 594 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 595 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 596 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 597 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 598 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 599 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 600 | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 601 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 602 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 603 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 604 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 605 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 606 | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 607 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 608 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 609 610 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 611 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 612 UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF); 613 } else { 614 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 615 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 616 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 617 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 618 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 619 | 1 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 620 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 621 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 622 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 623 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 624 | 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 625 | 1 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 626 | 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 627 | 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 628 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 629 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 0, 0x3F3FFFFF); 630 } 631 632 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); 633 data &= ~0x103; 634 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 635 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 636 UVD_POWER_STATUS__UVD_PG_EN_MASK; 637 638 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); 639 } 640 641 static void vcn_v3_0_enable_static_power_gating(struct amdgpu_device *adev, int inst) 642 { 643 uint32_t data; 644 645 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 646 /* Before power off, this indicator has to be turned on */ 647 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); 648 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 649 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 650 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); 651 652 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 653 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 654 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 655 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 656 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 657 | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 658 | 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 659 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 660 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 661 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 662 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 663 | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 664 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 665 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 666 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 667 668 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 669 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 670 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 671 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 672 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 673 | 2 << UVD_PGFSM_STATUS__UVDIRL_PWR_STATUS__SHIFT 674 | 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT 675 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 676 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 677 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 678 | 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT 679 | 2 << UVD_PGFSM_STATUS__UVDATD_PWR_STATUS__SHIFT 680 | 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT 681 | 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT); 682 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, data, 0x3F3FFFFF); 683 } 684 } 685 686 /** 687 * vcn_v3_0_disable_clock_gating - disable VCN clock gating 688 * 689 * @adev: amdgpu_device pointer 690 * @inst: instance number 691 * 692 * Disable clock gating for VCN block 693 */ 694 static void vcn_v3_0_disable_clock_gating(struct amdgpu_device *adev, int inst) 695 { 696 uint32_t data; 697 698 /* VCN disable CGC */ 699 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 700 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 701 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 702 else 703 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 704 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 705 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 706 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 707 708 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_GATE); 709 data &= ~(UVD_CGC_GATE__SYS_MASK 710 | UVD_CGC_GATE__UDEC_MASK 711 | UVD_CGC_GATE__MPEG2_MASK 712 | UVD_CGC_GATE__REGS_MASK 713 | UVD_CGC_GATE__RBC_MASK 714 | UVD_CGC_GATE__LMI_MC_MASK 715 | UVD_CGC_GATE__LMI_UMC_MASK 716 | UVD_CGC_GATE__IDCT_MASK 717 | UVD_CGC_GATE__MPRD_MASK 718 | UVD_CGC_GATE__MPC_MASK 719 | UVD_CGC_GATE__LBSI_MASK 720 | UVD_CGC_GATE__LRBBM_MASK 721 | UVD_CGC_GATE__UDEC_RE_MASK 722 | UVD_CGC_GATE__UDEC_CM_MASK 723 | UVD_CGC_GATE__UDEC_IT_MASK 724 | UVD_CGC_GATE__UDEC_DB_MASK 725 | UVD_CGC_GATE__UDEC_MP_MASK 726 | UVD_CGC_GATE__WCB_MASK 727 | UVD_CGC_GATE__VCPU_MASK 728 | UVD_CGC_GATE__MMSCH_MASK); 729 730 WREG32_SOC15(VCN, inst, mmUVD_CGC_GATE, data); 731 732 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); 733 734 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 735 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 736 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 737 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 738 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 739 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 740 | UVD_CGC_CTRL__SYS_MODE_MASK 741 | UVD_CGC_CTRL__UDEC_MODE_MASK 742 | UVD_CGC_CTRL__MPEG2_MODE_MASK 743 | UVD_CGC_CTRL__REGS_MODE_MASK 744 | UVD_CGC_CTRL__RBC_MODE_MASK 745 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 746 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 747 | UVD_CGC_CTRL__IDCT_MODE_MASK 748 | UVD_CGC_CTRL__MPRD_MODE_MASK 749 | UVD_CGC_CTRL__MPC_MODE_MASK 750 | UVD_CGC_CTRL__LBSI_MODE_MASK 751 | UVD_CGC_CTRL__LRBBM_MODE_MASK 752 | UVD_CGC_CTRL__WCB_MODE_MASK 753 | UVD_CGC_CTRL__VCPU_MODE_MASK 754 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 755 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 756 757 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE); 758 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 759 | UVD_SUVD_CGC_GATE__SIT_MASK 760 | UVD_SUVD_CGC_GATE__SMP_MASK 761 | UVD_SUVD_CGC_GATE__SCM_MASK 762 | UVD_SUVD_CGC_GATE__SDB_MASK 763 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 764 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 765 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 766 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 767 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 768 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 769 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 770 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 771 | UVD_SUVD_CGC_GATE__SCLR_MASK 772 | UVD_SUVD_CGC_GATE__ENT_MASK 773 | UVD_SUVD_CGC_GATE__IME_MASK 774 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 775 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 776 | UVD_SUVD_CGC_GATE__SITE_MASK 777 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 778 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 779 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 780 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 781 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK 782 | UVD_SUVD_CGC_GATE__EFC_MASK 783 | UVD_SUVD_CGC_GATE__SAOE_MASK 784 | UVD_SUVD_CGC_GATE__SRE_AV1_MASK 785 | UVD_SUVD_CGC_GATE__FBC_PCLK_MASK 786 | UVD_SUVD_CGC_GATE__FBC_CCLK_MASK 787 | UVD_SUVD_CGC_GATE__SCM_AV1_MASK 788 | UVD_SUVD_CGC_GATE__SMPA_MASK); 789 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE, data); 790 791 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2); 792 data |= (UVD_SUVD_CGC_GATE2__MPBE0_MASK 793 | UVD_SUVD_CGC_GATE2__MPBE1_MASK 794 | UVD_SUVD_CGC_GATE2__SIT_AV1_MASK 795 | UVD_SUVD_CGC_GATE2__SDB_AV1_MASK 796 | UVD_SUVD_CGC_GATE2__MPC1_MASK); 797 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2, data); 798 799 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL); 800 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 801 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 802 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 803 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 804 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 805 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 806 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 807 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 808 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 809 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 810 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK 811 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK 812 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK 813 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK 814 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 815 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 816 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK 817 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK 818 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK); 819 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data); 820 } 821 822 static void vcn_v3_0_clock_gating_dpg_mode(struct amdgpu_device *adev, 823 uint8_t sram_sel, int inst_idx, uint8_t indirect) 824 { 825 uint32_t reg_data = 0; 826 827 /* enable sw clock gating control */ 828 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 829 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 830 else 831 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 832 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 833 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 834 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 835 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 836 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 837 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 838 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 839 UVD_CGC_CTRL__SYS_MODE_MASK | 840 UVD_CGC_CTRL__UDEC_MODE_MASK | 841 UVD_CGC_CTRL__MPEG2_MODE_MASK | 842 UVD_CGC_CTRL__REGS_MODE_MASK | 843 UVD_CGC_CTRL__RBC_MODE_MASK | 844 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 845 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 846 UVD_CGC_CTRL__IDCT_MODE_MASK | 847 UVD_CGC_CTRL__MPRD_MODE_MASK | 848 UVD_CGC_CTRL__MPC_MODE_MASK | 849 UVD_CGC_CTRL__LBSI_MODE_MASK | 850 UVD_CGC_CTRL__LRBBM_MODE_MASK | 851 UVD_CGC_CTRL__WCB_MODE_MASK | 852 UVD_CGC_CTRL__VCPU_MODE_MASK | 853 UVD_CGC_CTRL__MMSCH_MODE_MASK); 854 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 855 VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); 856 857 /* turn off clock gating */ 858 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 859 VCN, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect); 860 861 /* turn on SUVD clock gating */ 862 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 863 VCN, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 864 865 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 866 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 867 VCN, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 868 } 869 870 /** 871 * vcn_v3_0_enable_clock_gating - enable VCN clock gating 872 * 873 * @adev: amdgpu_device pointer 874 * @inst: instance number 875 * 876 * Enable clock gating for VCN block 877 */ 878 static void vcn_v3_0_enable_clock_gating(struct amdgpu_device *adev, int inst) 879 { 880 uint32_t data; 881 882 /* enable VCN CGC */ 883 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 884 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 885 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 886 else 887 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 888 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 889 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 890 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 891 892 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 893 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 894 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 895 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 896 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 897 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 898 | UVD_CGC_CTRL__SYS_MODE_MASK 899 | UVD_CGC_CTRL__UDEC_MODE_MASK 900 | UVD_CGC_CTRL__MPEG2_MODE_MASK 901 | UVD_CGC_CTRL__REGS_MODE_MASK 902 | UVD_CGC_CTRL__RBC_MODE_MASK 903 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 904 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 905 | UVD_CGC_CTRL__IDCT_MODE_MASK 906 | UVD_CGC_CTRL__MPRD_MODE_MASK 907 | UVD_CGC_CTRL__MPC_MODE_MASK 908 | UVD_CGC_CTRL__LBSI_MODE_MASK 909 | UVD_CGC_CTRL__LRBBM_MODE_MASK 910 | UVD_CGC_CTRL__WCB_MODE_MASK 911 | UVD_CGC_CTRL__VCPU_MODE_MASK 912 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 913 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 914 915 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL); 916 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 917 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 918 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 919 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 920 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 921 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 922 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 923 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 924 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 925 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 926 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK 927 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK 928 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK 929 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK 930 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 931 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 932 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK 933 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK 934 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK); 935 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data); 936 } 937 938 static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 939 { 940 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr; 941 struct amdgpu_ring *ring; 942 uint32_t rb_bufsz, tmp; 943 944 /* disable register anti-hang mechanism */ 945 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1, 946 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 947 /* enable dynamic power gating mode */ 948 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS); 949 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 950 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 951 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp); 952 953 if (indirect) 954 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 955 956 /* enable clock gating */ 957 vcn_v3_0_clock_gating_dpg_mode(adev, 0, inst_idx, indirect); 958 959 /* enable VCPU clock */ 960 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 961 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 962 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK; 963 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 964 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 965 966 /* disable master interupt */ 967 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 968 VCN, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect); 969 970 /* setup mmUVD_LMI_CTRL */ 971 tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 972 UVD_LMI_CTRL__REQ_MODE_MASK | 973 UVD_LMI_CTRL__CRC_RESET_MASK | 974 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 975 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 976 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 977 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 978 0x00100000L); 979 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 980 VCN, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect); 981 982 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 983 VCN, inst_idx, mmUVD_MPC_CNTL), 984 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 985 986 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 987 VCN, inst_idx, mmUVD_MPC_SET_MUXA0), 988 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 989 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 990 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 991 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 992 993 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 994 VCN, inst_idx, mmUVD_MPC_SET_MUXB0), 995 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 996 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 997 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 998 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 999 1000 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1001 VCN, inst_idx, mmUVD_MPC_SET_MUX), 1002 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1003 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1004 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 1005 1006 vcn_v3_0_mc_resume_dpg_mode(adev, inst_idx, indirect); 1007 1008 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1009 VCN, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect); 1010 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1011 VCN, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect); 1012 1013 /* enable LMI MC and UMC channels */ 1014 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1015 VCN, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect); 1016 1017 /* unblock VCPU register access */ 1018 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1019 VCN, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect); 1020 1021 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 1022 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 1023 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1024 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 1025 1026 /* enable master interrupt */ 1027 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1028 VCN, inst_idx, mmUVD_MASTINT_EN), 1029 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 1030 1031 /* add nop to workaround PSP size check */ 1032 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1033 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 1034 1035 if (indirect) 1036 psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, 1037 (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr - 1038 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr)); 1039 1040 ring = &adev->vcn.inst[inst_idx].ring_dec; 1041 /* force RBC into idle state */ 1042 rb_bufsz = order_base_2(ring->ring_size); 1043 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1044 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1045 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1046 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1047 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1048 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp); 1049 1050 /* Stall DPG before WPTR/RPTR reset */ 1051 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1052 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1053 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1054 fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1055 1056 /* set the write pointer delay */ 1057 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0); 1058 1059 /* set the wb address */ 1060 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR, 1061 (upper_32_bits(ring->gpu_addr) >> 2)); 1062 1063 /* programm the RB_BASE for ring buffer */ 1064 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1065 lower_32_bits(ring->gpu_addr)); 1066 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1067 upper_32_bits(ring->gpu_addr)); 1068 1069 /* Initialize the ring buffer's read and write pointers */ 1070 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0); 1071 1072 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0); 1073 1074 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR); 1075 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, 1076 lower_32_bits(ring->wptr)); 1077 1078 /* Reset FW shared memory RBC WPTR/RPTR */ 1079 fw_shared->rb.rptr = 0; 1080 fw_shared->rb.wptr = lower_32_bits(ring->wptr); 1081 1082 /*resetting done, fw can check RB ring */ 1083 fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1084 1085 /* Unstall DPG */ 1086 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1087 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1088 1089 return 0; 1090 } 1091 1092 static int vcn_v3_0_start(struct amdgpu_device *adev) 1093 { 1094 volatile struct amdgpu_fw_shared *fw_shared; 1095 struct amdgpu_ring *ring; 1096 uint32_t rb_bufsz, tmp; 1097 int i, j, k, r; 1098 1099 if (adev->pm.dpm_enabled) 1100 amdgpu_dpm_enable_uvd(adev, true); 1101 1102 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1103 if (adev->vcn.harvest_config & (1 << i)) 1104 continue; 1105 1106 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG){ 1107 r = vcn_v3_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram); 1108 continue; 1109 } 1110 1111 /* disable VCN power gating */ 1112 vcn_v3_0_disable_static_power_gating(adev, i); 1113 1114 /* set VCN status busy */ 1115 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 1116 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp); 1117 1118 /*SW clock gating */ 1119 vcn_v3_0_disable_clock_gating(adev, i); 1120 1121 /* enable VCPU clock */ 1122 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1123 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 1124 1125 /* disable master interrupt */ 1126 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0, 1127 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1128 1129 /* enable LMI MC and UMC channels */ 1130 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0, 1131 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1132 1133 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1134 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1135 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1136 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1137 1138 /* setup mmUVD_LMI_CTRL */ 1139 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL); 1140 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | 1141 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1142 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1143 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1144 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1145 1146 /* setup mmUVD_MPC_CNTL */ 1147 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL); 1148 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1149 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1150 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp); 1151 1152 /* setup UVD_MPC_SET_MUXA0 */ 1153 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0, 1154 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1155 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1156 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1157 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1158 1159 /* setup UVD_MPC_SET_MUXB0 */ 1160 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0, 1161 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1162 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1163 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1164 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1165 1166 /* setup mmUVD_MPC_SET_MUX */ 1167 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX, 1168 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1169 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1170 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1171 1172 vcn_v3_0_mc_resume(adev, i); 1173 1174 /* VCN global tiling registers */ 1175 WREG32_SOC15(VCN, i, mmUVD_GFX10_ADDR_CONFIG, 1176 adev->gfx.config.gb_addr_config); 1177 1178 /* unblock VCPU register access */ 1179 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0, 1180 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1181 1182 /* release VCPU reset to boot */ 1183 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1184 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1185 1186 for (j = 0; j < 10; ++j) { 1187 uint32_t status; 1188 1189 for (k = 0; k < 100; ++k) { 1190 status = RREG32_SOC15(VCN, i, mmUVD_STATUS); 1191 if (status & 2) 1192 break; 1193 mdelay(10); 1194 } 1195 r = 0; 1196 if (status & 2) 1197 break; 1198 1199 DRM_ERROR("VCN[%d] decode not responding, trying to reset the VCPU!!!\n", i); 1200 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1201 UVD_VCPU_CNTL__BLK_RST_MASK, 1202 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1203 mdelay(10); 1204 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1205 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1206 1207 mdelay(10); 1208 r = -1; 1209 } 1210 1211 if (r) { 1212 DRM_ERROR("VCN[%d] decode not responding, giving up!!!\n", i); 1213 return r; 1214 } 1215 1216 /* enable master interrupt */ 1217 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 1218 UVD_MASTINT_EN__VCPU_EN_MASK, 1219 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1220 1221 /* clear the busy bit of VCN_STATUS */ 1222 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0, 1223 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1224 1225 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0); 1226 1227 ring = &adev->vcn.inst[i].ring_dec; 1228 /* force RBC into idle state */ 1229 rb_bufsz = order_base_2(ring->ring_size); 1230 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1231 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1232 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1233 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1234 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1235 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp); 1236 1237 fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr; 1238 fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1239 1240 /* programm the RB_BASE for ring buffer */ 1241 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1242 lower_32_bits(ring->gpu_addr)); 1243 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1244 upper_32_bits(ring->gpu_addr)); 1245 1246 /* Initialize the ring buffer's read and write pointers */ 1247 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0); 1248 1249 WREG32_SOC15(VCN, i, mmUVD_SCRATCH2, 0); 1250 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR); 1251 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR, 1252 lower_32_bits(ring->wptr)); 1253 fw_shared->rb.wptr = lower_32_bits(ring->wptr); 1254 fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1255 1256 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1257 ring = &adev->vcn.inst[i].ring_enc[0]; 1258 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1259 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1260 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr); 1261 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1262 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4); 1263 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1264 1265 fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1266 ring = &adev->vcn.inst[i].ring_enc[1]; 1267 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1268 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1269 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1270 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1271 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4); 1272 fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1273 } 1274 1275 return 0; 1276 } 1277 1278 static int vcn_v3_0_start_sriov(struct amdgpu_device *adev) 1279 { 1280 int i, j; 1281 struct amdgpu_ring *ring; 1282 uint64_t cache_addr; 1283 uint64_t rb_addr; 1284 uint64_t ctx_addr; 1285 uint32_t param, resp, expected; 1286 uint32_t offset, cache_size; 1287 uint32_t tmp, timeout; 1288 uint32_t id; 1289 1290 struct amdgpu_mm_table *table = &adev->virt.mm_table; 1291 uint32_t *table_loc; 1292 uint32_t table_size; 1293 uint32_t size, size_dw; 1294 1295 bool is_vcn_ready; 1296 1297 struct mmsch_v3_0_cmd_direct_write 1298 direct_wt = { {0} }; 1299 struct mmsch_v3_0_cmd_direct_read_modify_write 1300 direct_rd_mod_wt = { {0} }; 1301 struct mmsch_v3_0_cmd_end end = { {0} }; 1302 struct mmsch_v3_0_init_header header; 1303 1304 direct_wt.cmd_header.command_type = 1305 MMSCH_COMMAND__DIRECT_REG_WRITE; 1306 direct_rd_mod_wt.cmd_header.command_type = 1307 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1308 end.cmd_header.command_type = 1309 MMSCH_COMMAND__END; 1310 1311 header.version = MMSCH_VERSION; 1312 header.total_size = sizeof(struct mmsch_v3_0_init_header) >> 2; 1313 for (i = 0; i < AMDGPU_MAX_VCN_INSTANCES; i++) { 1314 header.inst[i].init_status = 0; 1315 header.inst[i].table_offset = 0; 1316 header.inst[i].table_size = 0; 1317 } 1318 1319 table_loc = (uint32_t *)table->cpu_addr; 1320 table_loc += header.total_size; 1321 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1322 if (adev->vcn.harvest_config & (1 << i)) 1323 continue; 1324 1325 table_size = 0; 1326 1327 MMSCH_V3_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i, 1328 mmUVD_STATUS), 1329 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 1330 1331 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 1332 1333 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1334 id = amdgpu_ucode_id_vcns[i]; 1335 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1336 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1337 adev->firmware.ucode[id].tmr_mc_addr_lo); 1338 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1339 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1340 adev->firmware.ucode[id].tmr_mc_addr_hi); 1341 offset = 0; 1342 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1343 mmUVD_VCPU_CACHE_OFFSET0), 1344 0); 1345 } else { 1346 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1347 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1348 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 1349 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1350 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1351 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 1352 offset = cache_size; 1353 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1354 mmUVD_VCPU_CACHE_OFFSET0), 1355 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 1356 } 1357 1358 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1359 mmUVD_VCPU_CACHE_SIZE0), 1360 cache_size); 1361 1362 cache_addr = adev->vcn.inst[i].gpu_addr + offset; 1363 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1364 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 1365 lower_32_bits(cache_addr)); 1366 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1367 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 1368 upper_32_bits(cache_addr)); 1369 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1370 mmUVD_VCPU_CACHE_OFFSET1), 1371 0); 1372 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1373 mmUVD_VCPU_CACHE_SIZE1), 1374 AMDGPU_VCN_STACK_SIZE); 1375 1376 cache_addr = adev->vcn.inst[i].gpu_addr + offset + 1377 AMDGPU_VCN_STACK_SIZE; 1378 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1379 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 1380 lower_32_bits(cache_addr)); 1381 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1382 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 1383 upper_32_bits(cache_addr)); 1384 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1385 mmUVD_VCPU_CACHE_OFFSET2), 1386 0); 1387 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1388 mmUVD_VCPU_CACHE_SIZE2), 1389 AMDGPU_VCN_CONTEXT_SIZE); 1390 1391 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 1392 ring = &adev->vcn.inst[i].ring_enc[j]; 1393 ring->wptr = 0; 1394 rb_addr = ring->gpu_addr; 1395 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1396 mmUVD_RB_BASE_LO), 1397 lower_32_bits(rb_addr)); 1398 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1399 mmUVD_RB_BASE_HI), 1400 upper_32_bits(rb_addr)); 1401 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1402 mmUVD_RB_SIZE), 1403 ring->ring_size / 4); 1404 } 1405 1406 ring = &adev->vcn.inst[i].ring_dec; 1407 ring->wptr = 0; 1408 rb_addr = ring->gpu_addr; 1409 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1410 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW), 1411 lower_32_bits(rb_addr)); 1412 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1413 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH), 1414 upper_32_bits(rb_addr)); 1415 /* force RBC into idle state */ 1416 tmp = order_base_2(ring->ring_size); 1417 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp); 1418 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1419 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1420 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1421 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1422 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1423 mmUVD_RBC_RB_CNTL), 1424 tmp); 1425 1426 /* add end packet */ 1427 MMSCH_V3_0_INSERT_END(); 1428 1429 /* refine header */ 1430 header.inst[i].init_status = 0; 1431 header.inst[i].table_offset = header.total_size; 1432 header.inst[i].table_size = table_size; 1433 header.total_size += table_size; 1434 } 1435 1436 /* Update init table header in memory */ 1437 size = sizeof(struct mmsch_v3_0_init_header); 1438 table_loc = (uint32_t *)table->cpu_addr; 1439 memcpy((void *)table_loc, &header, size); 1440 1441 /* message MMSCH (in VCN[0]) to initialize this client 1442 * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr 1443 * of memory descriptor location 1444 */ 1445 ctx_addr = table->gpu_addr; 1446 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 1447 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 1448 1449 /* 2, update vmid of descriptor */ 1450 tmp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID); 1451 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1452 /* use domain0 for MM scheduler */ 1453 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1454 WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, tmp); 1455 1456 /* 3, notify mmsch about the size of this descriptor */ 1457 size = header.total_size; 1458 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size); 1459 1460 /* 4, set resp to zero */ 1461 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0); 1462 1463 /* 5, kick off the initialization and wait until 1464 * MMSCH_VF_MAILBOX_RESP becomes non-zero 1465 */ 1466 param = 0x10000001; 1467 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, param); 1468 tmp = 0; 1469 timeout = 1000; 1470 resp = 0; 1471 expected = param + 1; 1472 while (resp != expected) { 1473 resp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); 1474 if (resp == expected) 1475 break; 1476 1477 udelay(10); 1478 tmp = tmp + 10; 1479 if (tmp >= timeout) { 1480 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 1481 " waiting for mmMMSCH_VF_MAILBOX_RESP "\ 1482 "(expected=0x%08x, readback=0x%08x)\n", 1483 tmp, expected, resp); 1484 return -EBUSY; 1485 } 1486 } 1487 1488 /* 6, check each VCN's init_status 1489 * if it remains as 0, then this VCN is not assigned to current VF 1490 * do not start ring for this VCN 1491 */ 1492 size = sizeof(struct mmsch_v3_0_init_header); 1493 table_loc = (uint32_t *)table->cpu_addr; 1494 memcpy(&header, (void *)table_loc, size); 1495 1496 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1497 if (adev->vcn.harvest_config & (1 << i)) 1498 continue; 1499 1500 is_vcn_ready = (header.inst[i].init_status == 1); 1501 if (!is_vcn_ready) 1502 DRM_INFO("VCN(%d) engine is disabled by hypervisor\n", i); 1503 1504 ring = &adev->vcn.inst[i].ring_dec; 1505 ring->sched.ready = is_vcn_ready; 1506 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 1507 ring = &adev->vcn.inst[i].ring_enc[j]; 1508 ring->sched.ready = is_vcn_ready; 1509 } 1510 } 1511 1512 return 0; 1513 } 1514 1515 static int vcn_v3_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) 1516 { 1517 uint32_t tmp; 1518 1519 /* Wait for power status to be 1 */ 1520 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1521 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1522 1523 /* wait for read ptr to be equal to write ptr */ 1524 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR); 1525 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1526 1527 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2); 1528 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); 1529 1530 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1531 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); 1532 1533 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1534 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1535 1536 /* disable dynamic power gating mode */ 1537 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0, 1538 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1539 1540 return 0; 1541 } 1542 1543 static int vcn_v3_0_stop(struct amdgpu_device *adev) 1544 { 1545 uint32_t tmp; 1546 int i, r = 0; 1547 1548 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1549 if (adev->vcn.harvest_config & (1 << i)) 1550 continue; 1551 1552 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1553 r = vcn_v3_0_stop_dpg_mode(adev, i); 1554 continue; 1555 } 1556 1557 /* wait for vcn idle */ 1558 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1559 if (r) 1560 return r; 1561 1562 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1563 UVD_LMI_STATUS__READ_CLEAN_MASK | 1564 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1565 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1566 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1567 if (r) 1568 return r; 1569 1570 /* disable LMI UMC channel */ 1571 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2); 1572 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1573 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp); 1574 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK| 1575 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1576 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1577 if (r) 1578 return r; 1579 1580 /* block VCPU register access */ 1581 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 1582 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1583 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1584 1585 /* reset VCPU */ 1586 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1587 UVD_VCPU_CNTL__BLK_RST_MASK, 1588 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1589 1590 /* disable VCPU clock */ 1591 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1592 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1593 1594 /* apply soft reset */ 1595 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1596 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1597 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1598 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1599 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1600 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1601 1602 /* clear status */ 1603 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0); 1604 1605 /* apply HW clock gating */ 1606 vcn_v3_0_enable_clock_gating(adev, i); 1607 1608 /* enable VCN power gating */ 1609 vcn_v3_0_enable_static_power_gating(adev, i); 1610 } 1611 1612 if (adev->pm.dpm_enabled) 1613 amdgpu_dpm_enable_uvd(adev, false); 1614 1615 return 0; 1616 } 1617 1618 static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev, 1619 int inst_idx, struct dpg_pause_state *new_state) 1620 { 1621 volatile struct amdgpu_fw_shared *fw_shared; 1622 struct amdgpu_ring *ring; 1623 uint32_t reg_data = 0; 1624 int ret_code; 1625 1626 /* pause/unpause if state is changed */ 1627 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1628 DRM_DEBUG("dpg pause state changed %d -> %d", 1629 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1630 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) & 1631 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1632 1633 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1634 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, 1635 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1636 1637 if (!ret_code) { 1638 /* pause DPG */ 1639 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1640 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1641 1642 /* wait for ACK */ 1643 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE, 1644 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1645 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1646 1647 /* Stall DPG before WPTR/RPTR reset */ 1648 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1649 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1650 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1651 1652 /* Restore */ 1653 fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr; 1654 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1655 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 1656 ring->wptr = 0; 1657 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr); 1658 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1659 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4); 1660 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1661 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1662 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1663 1664 fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1665 ring = &adev->vcn.inst[inst_idx].ring_enc[1]; 1666 ring->wptr = 0; 1667 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1668 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1669 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4); 1670 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1671 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1672 fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1673 1674 /* restore wptr/rptr with pointers saved in FW shared memory*/ 1675 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, fw_shared->rb.rptr); 1676 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, fw_shared->rb.wptr); 1677 1678 /* Unstall DPG */ 1679 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1680 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1681 1682 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1683 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1684 } 1685 } else { 1686 /* unpause dpg, no need to wait */ 1687 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1688 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1689 } 1690 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1691 } 1692 1693 return 0; 1694 } 1695 1696 /** 1697 * vcn_v3_0_dec_ring_get_rptr - get read pointer 1698 * 1699 * @ring: amdgpu_ring pointer 1700 * 1701 * Returns the current hardware read pointer 1702 */ 1703 static uint64_t vcn_v3_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 1704 { 1705 struct amdgpu_device *adev = ring->adev; 1706 1707 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR); 1708 } 1709 1710 /** 1711 * vcn_v3_0_dec_ring_get_wptr - get write pointer 1712 * 1713 * @ring: amdgpu_ring pointer 1714 * 1715 * Returns the current hardware write pointer 1716 */ 1717 static uint64_t vcn_v3_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 1718 { 1719 struct amdgpu_device *adev = ring->adev; 1720 1721 if (ring->use_doorbell) 1722 return adev->wb.wb[ring->wptr_offs]; 1723 else 1724 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR); 1725 } 1726 1727 /** 1728 * vcn_v3_0_dec_ring_set_wptr - set write pointer 1729 * 1730 * @ring: amdgpu_ring pointer 1731 * 1732 * Commits the write pointer to the hardware 1733 */ 1734 static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 1735 { 1736 struct amdgpu_device *adev = ring->adev; 1737 volatile struct amdgpu_fw_shared *fw_shared; 1738 1739 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1740 /*whenever update RBC_RB_WPTR, we save the wptr in shared rb.wptr and scratch2 */ 1741 fw_shared = adev->vcn.inst[ring->me].fw_shared_cpu_addr; 1742 fw_shared->rb.wptr = lower_32_bits(ring->wptr); 1743 WREG32_SOC15(VCN, ring->me, mmUVD_SCRATCH2, 1744 lower_32_bits(ring->wptr)); 1745 } 1746 1747 if (ring->use_doorbell) { 1748 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 1749 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1750 } else { 1751 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1752 } 1753 } 1754 1755 static void vcn_v3_0_dec_sw_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1756 u64 seq, uint32_t flags) 1757 { 1758 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1759 1760 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_FENCE); 1761 amdgpu_ring_write(ring, addr); 1762 amdgpu_ring_write(ring, upper_32_bits(addr)); 1763 amdgpu_ring_write(ring, seq); 1764 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_TRAP); 1765 } 1766 1767 static void vcn_v3_0_dec_sw_ring_insert_end(struct amdgpu_ring *ring) 1768 { 1769 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END); 1770 } 1771 1772 static void vcn_v3_0_dec_sw_ring_emit_ib(struct amdgpu_ring *ring, 1773 struct amdgpu_job *job, 1774 struct amdgpu_ib *ib, 1775 uint32_t flags) 1776 { 1777 uint32_t vmid = AMDGPU_JOB_GET_VMID(job); 1778 1779 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_IB); 1780 amdgpu_ring_write(ring, vmid); 1781 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1782 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1783 amdgpu_ring_write(ring, ib->length_dw); 1784 } 1785 1786 static void vcn_v3_0_dec_sw_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1787 uint32_t val, uint32_t mask) 1788 { 1789 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WAIT); 1790 amdgpu_ring_write(ring, reg << 2); 1791 amdgpu_ring_write(ring, mask); 1792 amdgpu_ring_write(ring, val); 1793 } 1794 1795 static void vcn_v3_0_dec_sw_ring_emit_vm_flush(struct amdgpu_ring *ring, 1796 uint32_t vmid, uint64_t pd_addr) 1797 { 1798 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1799 uint32_t data0, data1, mask; 1800 1801 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1802 1803 /* wait for register write */ 1804 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance; 1805 data1 = lower_32_bits(pd_addr); 1806 mask = 0xffffffff; 1807 vcn_v3_0_dec_sw_ring_emit_reg_wait(ring, data0, data1, mask); 1808 } 1809 1810 static void vcn_v3_0_dec_sw_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) 1811 { 1812 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WRITE); 1813 amdgpu_ring_write(ring, reg << 2); 1814 amdgpu_ring_write(ring, val); 1815 } 1816 1817 static const struct amdgpu_ring_funcs vcn_v3_0_dec_sw_ring_vm_funcs = { 1818 .type = AMDGPU_RING_TYPE_VCN_DEC, 1819 .align_mask = 0x3f, 1820 .nop = VCN_DEC_SW_CMD_NO_OP, 1821 .vmhub = AMDGPU_MMHUB_0, 1822 .get_rptr = vcn_v3_0_dec_ring_get_rptr, 1823 .get_wptr = vcn_v3_0_dec_ring_get_wptr, 1824 .set_wptr = vcn_v3_0_dec_ring_set_wptr, 1825 .emit_frame_size = 1826 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1827 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1828 4 + /* vcn_v3_0_dec_sw_ring_emit_vm_flush */ 1829 5 + 5 + /* vcn_v3_0_dec_sw_ring_emit_fdec_swe x2 vm fdec_swe */ 1830 1, /* vcn_v3_0_dec_sw_ring_insert_end */ 1831 .emit_ib_size = 5, /* vcn_v3_0_dec_sw_ring_emit_ib */ 1832 .emit_ib = vcn_v3_0_dec_sw_ring_emit_ib, 1833 .emit_fence = vcn_v3_0_dec_sw_ring_emit_fence, 1834 .emit_vm_flush = vcn_v3_0_dec_sw_ring_emit_vm_flush, 1835 .test_ring = amdgpu_vcn_dec_sw_ring_test_ring, 1836 .test_ib = NULL,//amdgpu_vcn_dec_sw_ring_test_ib, 1837 .insert_nop = amdgpu_ring_insert_nop, 1838 .insert_end = vcn_v3_0_dec_sw_ring_insert_end, 1839 .pad_ib = amdgpu_ring_generic_pad_ib, 1840 .begin_use = amdgpu_vcn_ring_begin_use, 1841 .end_use = amdgpu_vcn_ring_end_use, 1842 .emit_wreg = vcn_v3_0_dec_sw_ring_emit_wreg, 1843 .emit_reg_wait = vcn_v3_0_dec_sw_ring_emit_reg_wait, 1844 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1845 }; 1846 1847 static const struct amdgpu_ring_funcs vcn_v3_0_dec_ring_vm_funcs = { 1848 .type = AMDGPU_RING_TYPE_VCN_DEC, 1849 .align_mask = 0xf, 1850 .vmhub = AMDGPU_MMHUB_0, 1851 .get_rptr = vcn_v3_0_dec_ring_get_rptr, 1852 .get_wptr = vcn_v3_0_dec_ring_get_wptr, 1853 .set_wptr = vcn_v3_0_dec_ring_set_wptr, 1854 .emit_frame_size = 1855 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1856 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1857 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */ 1858 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */ 1859 6, 1860 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */ 1861 .emit_ib = vcn_v2_0_dec_ring_emit_ib, 1862 .emit_fence = vcn_v2_0_dec_ring_emit_fence, 1863 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush, 1864 .test_ring = vcn_v2_0_dec_ring_test_ring, 1865 .test_ib = amdgpu_vcn_dec_ring_test_ib, 1866 .insert_nop = vcn_v2_0_dec_ring_insert_nop, 1867 .insert_start = vcn_v2_0_dec_ring_insert_start, 1868 .insert_end = vcn_v2_0_dec_ring_insert_end, 1869 .pad_ib = amdgpu_ring_generic_pad_ib, 1870 .begin_use = amdgpu_vcn_ring_begin_use, 1871 .end_use = amdgpu_vcn_ring_end_use, 1872 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg, 1873 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait, 1874 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1875 }; 1876 1877 /** 1878 * vcn_v3_0_enc_ring_get_rptr - get enc read pointer 1879 * 1880 * @ring: amdgpu_ring pointer 1881 * 1882 * Returns the current hardware enc read pointer 1883 */ 1884 static uint64_t vcn_v3_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 1885 { 1886 struct amdgpu_device *adev = ring->adev; 1887 1888 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) 1889 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR); 1890 else 1891 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2); 1892 } 1893 1894 /** 1895 * vcn_v3_0_enc_ring_get_wptr - get enc write pointer 1896 * 1897 * @ring: amdgpu_ring pointer 1898 * 1899 * Returns the current hardware enc write pointer 1900 */ 1901 static uint64_t vcn_v3_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 1902 { 1903 struct amdgpu_device *adev = ring->adev; 1904 1905 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 1906 if (ring->use_doorbell) 1907 return adev->wb.wb[ring->wptr_offs]; 1908 else 1909 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR); 1910 } else { 1911 if (ring->use_doorbell) 1912 return adev->wb.wb[ring->wptr_offs]; 1913 else 1914 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2); 1915 } 1916 } 1917 1918 /** 1919 * vcn_v3_0_enc_ring_set_wptr - set enc write pointer 1920 * 1921 * @ring: amdgpu_ring pointer 1922 * 1923 * Commits the enc write pointer to the hardware 1924 */ 1925 static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 1926 { 1927 struct amdgpu_device *adev = ring->adev; 1928 1929 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 1930 if (ring->use_doorbell) { 1931 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 1932 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1933 } else { 1934 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1935 } 1936 } else { 1937 if (ring->use_doorbell) { 1938 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 1939 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1940 } else { 1941 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1942 } 1943 } 1944 } 1945 1946 static const struct amdgpu_ring_funcs vcn_v3_0_enc_ring_vm_funcs = { 1947 .type = AMDGPU_RING_TYPE_VCN_ENC, 1948 .align_mask = 0x3f, 1949 .nop = VCN_ENC_CMD_NO_OP, 1950 .vmhub = AMDGPU_MMHUB_0, 1951 .get_rptr = vcn_v3_0_enc_ring_get_rptr, 1952 .get_wptr = vcn_v3_0_enc_ring_get_wptr, 1953 .set_wptr = vcn_v3_0_enc_ring_set_wptr, 1954 .emit_frame_size = 1955 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1956 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1957 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1958 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1959 1, /* vcn_v2_0_enc_ring_insert_end */ 1960 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1961 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1962 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1963 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 1964 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1965 .test_ib = amdgpu_vcn_enc_ring_test_ib, 1966 .insert_nop = amdgpu_ring_insert_nop, 1967 .insert_end = vcn_v2_0_enc_ring_insert_end, 1968 .pad_ib = amdgpu_ring_generic_pad_ib, 1969 .begin_use = amdgpu_vcn_ring_begin_use, 1970 .end_use = amdgpu_vcn_ring_end_use, 1971 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 1972 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 1973 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1974 }; 1975 1976 static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev) 1977 { 1978 int i; 1979 1980 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1981 if (adev->vcn.harvest_config & (1 << i)) 1982 continue; 1983 1984 if (!DEC_SW_RING_ENABLED) 1985 adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_ring_vm_funcs; 1986 else 1987 adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_sw_ring_vm_funcs; 1988 adev->vcn.inst[i].ring_dec.me = i; 1989 DRM_INFO("VCN(%d) decode%s is enabled in VM mode\n", i, 1990 DEC_SW_RING_ENABLED?"(Software Ring)":""); 1991 } 1992 } 1993 1994 static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev) 1995 { 1996 int i, j; 1997 1998 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1999 if (adev->vcn.harvest_config & (1 << i)) 2000 continue; 2001 2002 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 2003 adev->vcn.inst[i].ring_enc[j].funcs = &vcn_v3_0_enc_ring_vm_funcs; 2004 adev->vcn.inst[i].ring_enc[j].me = i; 2005 } 2006 DRM_INFO("VCN(%d) encode is enabled in VM mode\n", i); 2007 } 2008 } 2009 2010 static bool vcn_v3_0_is_idle(void *handle) 2011 { 2012 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2013 int i, ret = 1; 2014 2015 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2016 if (adev->vcn.harvest_config & (1 << i)) 2017 continue; 2018 2019 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); 2020 } 2021 2022 return ret; 2023 } 2024 2025 static int vcn_v3_0_wait_for_idle(void *handle) 2026 { 2027 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2028 int i, ret = 0; 2029 2030 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2031 if (adev->vcn.harvest_config & (1 << i)) 2032 continue; 2033 2034 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 2035 UVD_STATUS__IDLE); 2036 if (ret) 2037 return ret; 2038 } 2039 2040 return ret; 2041 } 2042 2043 static int vcn_v3_0_set_clockgating_state(void *handle, 2044 enum amd_clockgating_state state) 2045 { 2046 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2047 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 2048 int i; 2049 2050 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2051 if (adev->vcn.harvest_config & (1 << i)) 2052 continue; 2053 2054 if (enable) { 2055 if (RREG32_SOC15(VCN, i, mmUVD_STATUS) != UVD_STATUS__IDLE) 2056 return -EBUSY; 2057 vcn_v3_0_enable_clock_gating(adev, i); 2058 } else { 2059 vcn_v3_0_disable_clock_gating(adev, i); 2060 } 2061 } 2062 2063 return 0; 2064 } 2065 2066 static int vcn_v3_0_set_powergating_state(void *handle, 2067 enum amd_powergating_state state) 2068 { 2069 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2070 int ret; 2071 2072 /* for SRIOV, guest should not control VCN Power-gating 2073 * MMSCH FW should control Power-gating and clock-gating 2074 * guest should avoid touching CGC and PG 2075 */ 2076 if (amdgpu_sriov_vf(adev)) { 2077 adev->vcn.cur_state = AMD_PG_STATE_UNGATE; 2078 return 0; 2079 } 2080 2081 if(state == adev->vcn.cur_state) 2082 return 0; 2083 2084 if (state == AMD_PG_STATE_GATE) 2085 ret = vcn_v3_0_stop(adev); 2086 else 2087 ret = vcn_v3_0_start(adev); 2088 2089 if(!ret) 2090 adev->vcn.cur_state = state; 2091 2092 return ret; 2093 } 2094 2095 static int vcn_v3_0_set_interrupt_state(struct amdgpu_device *adev, 2096 struct amdgpu_irq_src *source, 2097 unsigned type, 2098 enum amdgpu_interrupt_state state) 2099 { 2100 return 0; 2101 } 2102 2103 static int vcn_v3_0_process_interrupt(struct amdgpu_device *adev, 2104 struct amdgpu_irq_src *source, 2105 struct amdgpu_iv_entry *entry) 2106 { 2107 uint32_t ip_instance; 2108 2109 switch (entry->client_id) { 2110 case SOC15_IH_CLIENTID_VCN: 2111 ip_instance = 0; 2112 break; 2113 case SOC15_IH_CLIENTID_VCN1: 2114 ip_instance = 1; 2115 break; 2116 default: 2117 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 2118 return 0; 2119 } 2120 2121 DRM_DEBUG("IH: VCN TRAP\n"); 2122 2123 switch (entry->src_id) { 2124 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT: 2125 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec); 2126 break; 2127 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 2128 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 2129 break; 2130 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY: 2131 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]); 2132 break; 2133 default: 2134 DRM_ERROR("Unhandled interrupt: %d %d\n", 2135 entry->src_id, entry->src_data[0]); 2136 break; 2137 } 2138 2139 return 0; 2140 } 2141 2142 static const struct amdgpu_irq_src_funcs vcn_v3_0_irq_funcs = { 2143 .set = vcn_v3_0_set_interrupt_state, 2144 .process = vcn_v3_0_process_interrupt, 2145 }; 2146 2147 static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev) 2148 { 2149 int i; 2150 2151 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2152 if (adev->vcn.harvest_config & (1 << i)) 2153 continue; 2154 2155 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1; 2156 adev->vcn.inst[i].irq.funcs = &vcn_v3_0_irq_funcs; 2157 } 2158 } 2159 2160 static const struct amd_ip_funcs vcn_v3_0_ip_funcs = { 2161 .name = "vcn_v3_0", 2162 .early_init = vcn_v3_0_early_init, 2163 .late_init = NULL, 2164 .sw_init = vcn_v3_0_sw_init, 2165 .sw_fini = vcn_v3_0_sw_fini, 2166 .hw_init = vcn_v3_0_hw_init, 2167 .hw_fini = vcn_v3_0_hw_fini, 2168 .suspend = vcn_v3_0_suspend, 2169 .resume = vcn_v3_0_resume, 2170 .is_idle = vcn_v3_0_is_idle, 2171 .wait_for_idle = vcn_v3_0_wait_for_idle, 2172 .check_soft_reset = NULL, 2173 .pre_soft_reset = NULL, 2174 .soft_reset = NULL, 2175 .post_soft_reset = NULL, 2176 .set_clockgating_state = vcn_v3_0_set_clockgating_state, 2177 .set_powergating_state = vcn_v3_0_set_powergating_state, 2178 }; 2179 2180 const struct amdgpu_ip_block_version vcn_v3_0_ip_block = 2181 { 2182 .type = AMD_IP_BLOCK_TYPE_VCN, 2183 .major = 3, 2184 .minor = 0, 2185 .rev = 0, 2186 .funcs = &vcn_v3_0_ip_funcs, 2187 }; 2188