1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_vcn.h" 27 #include "amdgpu_pm.h" 28 #include "soc15.h" 29 #include "soc15d.h" 30 #include "vcn_v2_0.h" 31 #include "mmsch_v3_0.h" 32 33 #include "vcn/vcn_3_0_0_offset.h" 34 #include "vcn/vcn_3_0_0_sh_mask.h" 35 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 36 37 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x27 38 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x0f 39 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x10 40 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x11 41 #define mmUVD_NO_OP_INTERNAL_OFFSET 0x29 42 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x66 43 #define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d 44 45 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x431 46 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x3b4 47 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x3b5 48 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x25c 49 50 #define VCN_INSTANCES_SIENNA_CICHLID 2 51 #define DEC_SW_RING_ENABLED FALSE 52 53 static int amdgpu_ih_clientid_vcns[] = { 54 SOC15_IH_CLIENTID_VCN, 55 SOC15_IH_CLIENTID_VCN1 56 }; 57 58 static int amdgpu_ucode_id_vcns[] = { 59 AMDGPU_UCODE_ID_VCN, 60 AMDGPU_UCODE_ID_VCN1 61 }; 62 63 static int vcn_v3_0_start_sriov(struct amdgpu_device *adev); 64 static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev); 65 static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev); 66 static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev); 67 static int vcn_v3_0_set_powergating_state(void *handle, 68 enum amd_powergating_state state); 69 static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev, 70 int inst_idx, struct dpg_pause_state *new_state); 71 72 static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring); 73 static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring); 74 75 /** 76 * vcn_v3_0_early_init - set function pointers 77 * 78 * @handle: amdgpu_device pointer 79 * 80 * Set ring and irq function pointers 81 */ 82 static int vcn_v3_0_early_init(void *handle) 83 { 84 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 85 86 if (amdgpu_sriov_vf(adev)) { 87 adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID; 88 adev->vcn.harvest_config = 0; 89 adev->vcn.num_enc_rings = 1; 90 91 } else { 92 if (adev->asic_type == CHIP_SIENNA_CICHLID) { 93 u32 harvest; 94 int i; 95 96 adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID; 97 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 98 harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING); 99 if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK) 100 adev->vcn.harvest_config |= 1 << i; 101 } 102 103 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 | 104 AMDGPU_VCN_HARVEST_VCN1)) 105 /* both instances are harvested, disable the block */ 106 return -ENOENT; 107 } else 108 adev->vcn.num_vcn_inst = 1; 109 110 adev->vcn.num_enc_rings = 2; 111 } 112 113 vcn_v3_0_set_dec_ring_funcs(adev); 114 vcn_v3_0_set_enc_ring_funcs(adev); 115 vcn_v3_0_set_irq_funcs(adev); 116 117 return 0; 118 } 119 120 /** 121 * vcn_v3_0_sw_init - sw init for VCN block 122 * 123 * @handle: amdgpu_device pointer 124 * 125 * Load firmware and sw initialization 126 */ 127 static int vcn_v3_0_sw_init(void *handle) 128 { 129 struct amdgpu_ring *ring; 130 int i, j, r; 131 int vcn_doorbell_index = 0; 132 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 133 134 r = amdgpu_vcn_sw_init(adev); 135 if (r) 136 return r; 137 138 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 139 const struct common_firmware_header *hdr; 140 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 141 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN; 142 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw; 143 adev->firmware.fw_size += 144 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 145 146 if (adev->vcn.num_vcn_inst == VCN_INSTANCES_SIENNA_CICHLID) { 147 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].ucode_id = AMDGPU_UCODE_ID_VCN1; 148 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].fw = adev->vcn.fw; 149 adev->firmware.fw_size += 150 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 151 } 152 DRM_INFO("PSP loading VCN firmware\n"); 153 } 154 155 r = amdgpu_vcn_resume(adev); 156 if (r) 157 return r; 158 159 /* 160 * Note: doorbell assignment is fixed for SRIOV multiple VCN engines 161 * Formula: 162 * vcn_db_base = adev->doorbell_index.vcn.vcn_ring0_1 << 1; 163 * dec_ring_i = vcn_db_base + i * (adev->vcn.num_enc_rings + 1) 164 * enc_ring_i,j = vcn_db_base + i * (adev->vcn.num_enc_rings + 1) + 1 + j 165 */ 166 if (amdgpu_sriov_vf(adev)) { 167 vcn_doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1; 168 /* get DWORD offset */ 169 vcn_doorbell_index = vcn_doorbell_index << 1; 170 } 171 172 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 173 volatile struct amdgpu_fw_shared *fw_shared; 174 if (adev->vcn.harvest_config & (1 << i)) 175 continue; 176 177 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; 178 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; 179 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; 180 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; 181 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; 182 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; 183 184 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; 185 adev->vcn.inst[i].external.scratch9 = SOC15_REG_OFFSET(VCN, i, mmUVD_SCRATCH9); 186 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; 187 adev->vcn.inst[i].external.data0 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA0); 188 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; 189 adev->vcn.inst[i].external.data1 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA1); 190 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; 191 adev->vcn.inst[i].external.cmd = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_CMD); 192 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; 193 adev->vcn.inst[i].external.nop = SOC15_REG_OFFSET(VCN, i, mmUVD_NO_OP); 194 195 /* VCN DEC TRAP */ 196 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 197 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[i].irq); 198 if (r) 199 return r; 200 201 ring = &adev->vcn.inst[i].ring_dec; 202 ring->use_doorbell = true; 203 if (amdgpu_sriov_vf(adev)) { 204 ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1); 205 } else { 206 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i; 207 } 208 if (adev->asic_type == CHIP_SIENNA_CICHLID && i != 0) 209 ring->no_scheduler = true; 210 sprintf(ring->name, "vcn_dec_%d", i); 211 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 212 AMDGPU_RING_PRIO_DEFAULT); 213 if (r) 214 return r; 215 216 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 217 /* VCN ENC TRAP */ 218 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 219 j + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); 220 if (r) 221 return r; 222 223 ring = &adev->vcn.inst[i].ring_enc[j]; 224 ring->use_doorbell = true; 225 if (amdgpu_sriov_vf(adev)) { 226 ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1) + 1 + j; 227 } else { 228 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + j + 8 * i; 229 } 230 if (adev->asic_type == CHIP_SIENNA_CICHLID && i != 1) 231 ring->no_scheduler = true; 232 sprintf(ring->name, "vcn_enc_%d.%d", i, j); 233 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 234 AMDGPU_RING_PRIO_DEFAULT); 235 if (r) 236 return r; 237 } 238 239 fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr; 240 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SW_RING_FLAG); 241 fw_shared->sw_ring.is_enabled = cpu_to_le32(DEC_SW_RING_ENABLED); 242 } 243 244 if (amdgpu_sriov_vf(adev)) { 245 r = amdgpu_virt_alloc_mm_table(adev); 246 if (r) 247 return r; 248 } 249 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 250 adev->vcn.pause_dpg_mode = vcn_v3_0_pause_dpg_mode; 251 252 return 0; 253 } 254 255 /** 256 * vcn_v3_0_sw_fini - sw fini for VCN block 257 * 258 * @handle: amdgpu_device pointer 259 * 260 * VCN suspend and free up sw allocation 261 */ 262 static int vcn_v3_0_sw_fini(void *handle) 263 { 264 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 265 int i, r; 266 267 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 268 volatile struct amdgpu_fw_shared *fw_shared; 269 270 if (adev->vcn.harvest_config & (1 << i)) 271 continue; 272 fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr; 273 fw_shared->present_flag_0 = 0; 274 fw_shared->sw_ring.is_enabled = false; 275 } 276 277 if (amdgpu_sriov_vf(adev)) 278 amdgpu_virt_free_mm_table(adev); 279 280 r = amdgpu_vcn_suspend(adev); 281 if (r) 282 return r; 283 284 r = amdgpu_vcn_sw_fini(adev); 285 286 return r; 287 } 288 289 /** 290 * vcn_v3_0_hw_init - start and test VCN block 291 * 292 * @handle: amdgpu_device pointer 293 * 294 * Initialize the hardware, boot up the VCPU and do some testing 295 */ 296 static int vcn_v3_0_hw_init(void *handle) 297 { 298 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 299 struct amdgpu_ring *ring; 300 int i, j, r; 301 302 if (amdgpu_sriov_vf(adev)) { 303 r = vcn_v3_0_start_sriov(adev); 304 if (r) 305 goto done; 306 307 /* initialize VCN dec and enc ring buffers */ 308 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 309 if (adev->vcn.harvest_config & (1 << i)) 310 continue; 311 312 ring = &adev->vcn.inst[i].ring_dec; 313 if (ring->sched.ready) { 314 ring->wptr = 0; 315 ring->wptr_old = 0; 316 vcn_v3_0_dec_ring_set_wptr(ring); 317 } 318 319 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 320 ring = &adev->vcn.inst[i].ring_enc[j]; 321 if (ring->sched.ready) { 322 ring->wptr = 0; 323 ring->wptr_old = 0; 324 vcn_v3_0_enc_ring_set_wptr(ring); 325 } 326 } 327 } 328 } else { 329 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 330 if (adev->vcn.harvest_config & (1 << i)) 331 continue; 332 333 ring = &adev->vcn.inst[i].ring_dec; 334 335 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 336 ring->doorbell_index, i); 337 338 r = amdgpu_ring_test_helper(ring); 339 if (r) 340 goto done; 341 342 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 343 ring = &adev->vcn.inst[i].ring_enc[j]; 344 r = amdgpu_ring_test_helper(ring); 345 if (r) 346 goto done; 347 } 348 } 349 } 350 351 done: 352 if (!r) 353 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 354 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 355 356 return r; 357 } 358 359 /** 360 * vcn_v3_0_hw_fini - stop the hardware block 361 * 362 * @handle: amdgpu_device pointer 363 * 364 * Stop the VCN block, mark ring as not ready any more 365 */ 366 static int vcn_v3_0_hw_fini(void *handle) 367 { 368 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 369 struct amdgpu_ring *ring; 370 int i, j; 371 372 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 373 if (adev->vcn.harvest_config & (1 << i)) 374 continue; 375 376 ring = &adev->vcn.inst[i].ring_dec; 377 378 if (!amdgpu_sriov_vf(adev)) { 379 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 380 (adev->vcn.cur_state != AMD_PG_STATE_GATE && 381 RREG32_SOC15(VCN, i, mmUVD_STATUS))) { 382 vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 383 } 384 } 385 ring->sched.ready = false; 386 387 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 388 ring = &adev->vcn.inst[i].ring_enc[j]; 389 ring->sched.ready = false; 390 } 391 } 392 393 return 0; 394 } 395 396 /** 397 * vcn_v3_0_suspend - suspend VCN block 398 * 399 * @handle: amdgpu_device pointer 400 * 401 * HW fini and suspend VCN block 402 */ 403 static int vcn_v3_0_suspend(void *handle) 404 { 405 int r; 406 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 407 408 r = vcn_v3_0_hw_fini(adev); 409 if (r) 410 return r; 411 412 r = amdgpu_vcn_suspend(adev); 413 414 return r; 415 } 416 417 /** 418 * vcn_v3_0_resume - resume VCN block 419 * 420 * @handle: amdgpu_device pointer 421 * 422 * Resume firmware and hw init VCN block 423 */ 424 static int vcn_v3_0_resume(void *handle) 425 { 426 int r; 427 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 428 429 r = amdgpu_vcn_resume(adev); 430 if (r) 431 return r; 432 433 r = vcn_v3_0_hw_init(adev); 434 435 return r; 436 } 437 438 /** 439 * vcn_v3_0_mc_resume - memory controller programming 440 * 441 * @adev: amdgpu_device pointer 442 * @inst: instance number 443 * 444 * Let the VCN memory controller know it's offsets 445 */ 446 static void vcn_v3_0_mc_resume(struct amdgpu_device *adev, int inst) 447 { 448 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 449 uint32_t offset; 450 451 /* cache window 0: fw */ 452 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 453 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 454 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 455 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 456 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 457 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 0); 458 offset = 0; 459 } else { 460 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 461 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 462 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 463 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 464 offset = size; 465 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 466 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 467 } 468 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE0, size); 469 470 /* cache window 1: stack */ 471 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 472 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 473 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 474 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 475 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET1, 0); 476 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 477 478 /* cache window 2: context */ 479 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 480 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 481 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 482 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 483 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET2, 0); 484 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 485 486 /* non-cache window */ 487 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 488 lower_32_bits(adev->vcn.inst[inst].fw_shared_gpu_addr)); 489 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 490 upper_32_bits(adev->vcn.inst[inst].fw_shared_gpu_addr)); 491 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_OFFSET0, 0); 492 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_SIZE0, 493 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); 494 } 495 496 static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 497 { 498 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 499 uint32_t offset; 500 501 /* cache window 0: fw */ 502 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 503 if (!indirect) { 504 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 505 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 506 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); 507 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 508 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 509 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); 510 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 511 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 512 } else { 513 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 514 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 515 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 516 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 517 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 518 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 519 } 520 offset = 0; 521 } else { 522 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 523 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 524 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 525 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 526 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 527 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 528 offset = size; 529 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 530 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 531 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 532 } 533 534 if (!indirect) 535 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 536 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 537 else 538 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 539 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 540 541 /* cache window 1: stack */ 542 if (!indirect) { 543 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 544 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 545 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 546 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 547 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 548 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 549 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 550 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 551 } else { 552 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 553 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 554 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 555 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 556 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 557 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 558 } 559 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 560 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 561 562 /* cache window 2: context */ 563 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 564 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 565 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 566 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 567 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 568 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 569 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 570 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 571 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 572 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 573 574 /* non-cache window */ 575 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 576 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 577 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect); 578 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 579 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 580 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect); 581 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 582 VCN, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 583 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 584 VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), 585 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); 586 } 587 588 static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int inst) 589 { 590 uint32_t data = 0; 591 592 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 593 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 594 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 595 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 596 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 597 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 598 | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 599 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 600 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 601 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 602 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 603 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 604 | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 605 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 606 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 607 608 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 609 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 610 UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF); 611 } else { 612 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 613 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 614 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 615 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 616 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 617 | 1 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 618 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 619 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 620 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 621 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 622 | 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 623 | 1 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 624 | 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 625 | 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 626 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 627 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 0, 0x3F3FFFFF); 628 } 629 630 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); 631 data &= ~0x103; 632 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 633 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 634 UVD_POWER_STATUS__UVD_PG_EN_MASK; 635 636 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); 637 } 638 639 static void vcn_v3_0_enable_static_power_gating(struct amdgpu_device *adev, int inst) 640 { 641 uint32_t data; 642 643 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 644 /* Before power off, this indicator has to be turned on */ 645 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); 646 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 647 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 648 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); 649 650 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 651 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 652 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 653 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 654 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 655 | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 656 | 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 657 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 658 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 659 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 660 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 661 | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 662 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 663 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 664 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 665 666 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 667 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 668 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 669 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 670 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 671 | 2 << UVD_PGFSM_STATUS__UVDIRL_PWR_STATUS__SHIFT 672 | 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT 673 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 674 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 675 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 676 | 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT 677 | 2 << UVD_PGFSM_STATUS__UVDATD_PWR_STATUS__SHIFT 678 | 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT 679 | 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT); 680 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, data, 0x3F3FFFFF); 681 } 682 } 683 684 /** 685 * vcn_v3_0_disable_clock_gating - disable VCN clock gating 686 * 687 * @adev: amdgpu_device pointer 688 * @inst: instance number 689 * 690 * Disable clock gating for VCN block 691 */ 692 static void vcn_v3_0_disable_clock_gating(struct amdgpu_device *adev, int inst) 693 { 694 uint32_t data; 695 696 /* VCN disable CGC */ 697 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 698 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 699 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 700 else 701 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 702 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 703 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 704 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 705 706 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_GATE); 707 data &= ~(UVD_CGC_GATE__SYS_MASK 708 | UVD_CGC_GATE__UDEC_MASK 709 | UVD_CGC_GATE__MPEG2_MASK 710 | UVD_CGC_GATE__REGS_MASK 711 | UVD_CGC_GATE__RBC_MASK 712 | UVD_CGC_GATE__LMI_MC_MASK 713 | UVD_CGC_GATE__LMI_UMC_MASK 714 | UVD_CGC_GATE__IDCT_MASK 715 | UVD_CGC_GATE__MPRD_MASK 716 | UVD_CGC_GATE__MPC_MASK 717 | UVD_CGC_GATE__LBSI_MASK 718 | UVD_CGC_GATE__LRBBM_MASK 719 | UVD_CGC_GATE__UDEC_RE_MASK 720 | UVD_CGC_GATE__UDEC_CM_MASK 721 | UVD_CGC_GATE__UDEC_IT_MASK 722 | UVD_CGC_GATE__UDEC_DB_MASK 723 | UVD_CGC_GATE__UDEC_MP_MASK 724 | UVD_CGC_GATE__WCB_MASK 725 | UVD_CGC_GATE__VCPU_MASK 726 | UVD_CGC_GATE__MMSCH_MASK); 727 728 WREG32_SOC15(VCN, inst, mmUVD_CGC_GATE, data); 729 730 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); 731 732 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 733 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 734 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 735 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 736 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 737 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 738 | UVD_CGC_CTRL__SYS_MODE_MASK 739 | UVD_CGC_CTRL__UDEC_MODE_MASK 740 | UVD_CGC_CTRL__MPEG2_MODE_MASK 741 | UVD_CGC_CTRL__REGS_MODE_MASK 742 | UVD_CGC_CTRL__RBC_MODE_MASK 743 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 744 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 745 | UVD_CGC_CTRL__IDCT_MODE_MASK 746 | UVD_CGC_CTRL__MPRD_MODE_MASK 747 | UVD_CGC_CTRL__MPC_MODE_MASK 748 | UVD_CGC_CTRL__LBSI_MODE_MASK 749 | UVD_CGC_CTRL__LRBBM_MODE_MASK 750 | UVD_CGC_CTRL__WCB_MODE_MASK 751 | UVD_CGC_CTRL__VCPU_MODE_MASK 752 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 753 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 754 755 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE); 756 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 757 | UVD_SUVD_CGC_GATE__SIT_MASK 758 | UVD_SUVD_CGC_GATE__SMP_MASK 759 | UVD_SUVD_CGC_GATE__SCM_MASK 760 | UVD_SUVD_CGC_GATE__SDB_MASK 761 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 762 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 763 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 764 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 765 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 766 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 767 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 768 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 769 | UVD_SUVD_CGC_GATE__SCLR_MASK 770 | UVD_SUVD_CGC_GATE__ENT_MASK 771 | UVD_SUVD_CGC_GATE__IME_MASK 772 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 773 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 774 | UVD_SUVD_CGC_GATE__SITE_MASK 775 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 776 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 777 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 778 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 779 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK 780 | UVD_SUVD_CGC_GATE__EFC_MASK 781 | UVD_SUVD_CGC_GATE__SAOE_MASK 782 | UVD_SUVD_CGC_GATE__SRE_AV1_MASK 783 | UVD_SUVD_CGC_GATE__FBC_PCLK_MASK 784 | UVD_SUVD_CGC_GATE__FBC_CCLK_MASK 785 | UVD_SUVD_CGC_GATE__SCM_AV1_MASK 786 | UVD_SUVD_CGC_GATE__SMPA_MASK); 787 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE, data); 788 789 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2); 790 data |= (UVD_SUVD_CGC_GATE2__MPBE0_MASK 791 | UVD_SUVD_CGC_GATE2__MPBE1_MASK 792 | UVD_SUVD_CGC_GATE2__SIT_AV1_MASK 793 | UVD_SUVD_CGC_GATE2__SDB_AV1_MASK 794 | UVD_SUVD_CGC_GATE2__MPC1_MASK); 795 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2, data); 796 797 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL); 798 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 799 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 800 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 801 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 802 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 803 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 804 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 805 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 806 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 807 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 808 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK 809 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK 810 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK 811 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK 812 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 813 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 814 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK 815 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK 816 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK); 817 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data); 818 } 819 820 static void vcn_v3_0_clock_gating_dpg_mode(struct amdgpu_device *adev, 821 uint8_t sram_sel, int inst_idx, uint8_t indirect) 822 { 823 uint32_t reg_data = 0; 824 825 /* enable sw clock gating control */ 826 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 827 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 828 else 829 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 830 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 831 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 832 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 833 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 834 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 835 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 836 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 837 UVD_CGC_CTRL__SYS_MODE_MASK | 838 UVD_CGC_CTRL__UDEC_MODE_MASK | 839 UVD_CGC_CTRL__MPEG2_MODE_MASK | 840 UVD_CGC_CTRL__REGS_MODE_MASK | 841 UVD_CGC_CTRL__RBC_MODE_MASK | 842 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 843 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 844 UVD_CGC_CTRL__IDCT_MODE_MASK | 845 UVD_CGC_CTRL__MPRD_MODE_MASK | 846 UVD_CGC_CTRL__MPC_MODE_MASK | 847 UVD_CGC_CTRL__LBSI_MODE_MASK | 848 UVD_CGC_CTRL__LRBBM_MODE_MASK | 849 UVD_CGC_CTRL__WCB_MODE_MASK | 850 UVD_CGC_CTRL__VCPU_MODE_MASK | 851 UVD_CGC_CTRL__MMSCH_MODE_MASK); 852 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 853 VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); 854 855 /* turn off clock gating */ 856 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 857 VCN, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect); 858 859 /* turn on SUVD clock gating */ 860 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 861 VCN, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 862 863 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 864 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 865 VCN, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 866 } 867 868 /** 869 * vcn_v3_0_enable_clock_gating - enable VCN clock gating 870 * 871 * @adev: amdgpu_device pointer 872 * @inst: instance number 873 * 874 * Enable clock gating for VCN block 875 */ 876 static void vcn_v3_0_enable_clock_gating(struct amdgpu_device *adev, int inst) 877 { 878 uint32_t data; 879 880 /* enable VCN CGC */ 881 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 882 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 883 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 884 else 885 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 886 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 887 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 888 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 889 890 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 891 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 892 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 893 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 894 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 895 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 896 | UVD_CGC_CTRL__SYS_MODE_MASK 897 | UVD_CGC_CTRL__UDEC_MODE_MASK 898 | UVD_CGC_CTRL__MPEG2_MODE_MASK 899 | UVD_CGC_CTRL__REGS_MODE_MASK 900 | UVD_CGC_CTRL__RBC_MODE_MASK 901 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 902 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 903 | UVD_CGC_CTRL__IDCT_MODE_MASK 904 | UVD_CGC_CTRL__MPRD_MODE_MASK 905 | UVD_CGC_CTRL__MPC_MODE_MASK 906 | UVD_CGC_CTRL__LBSI_MODE_MASK 907 | UVD_CGC_CTRL__LRBBM_MODE_MASK 908 | UVD_CGC_CTRL__WCB_MODE_MASK 909 | UVD_CGC_CTRL__VCPU_MODE_MASK 910 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 911 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 912 913 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL); 914 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 915 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 916 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 917 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 918 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 919 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 920 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 921 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 922 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 923 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 924 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK 925 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK 926 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK 927 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK 928 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 929 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 930 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK 931 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK 932 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK); 933 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data); 934 } 935 936 static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 937 { 938 struct amdgpu_ring *ring; 939 uint32_t rb_bufsz, tmp; 940 941 /* disable register anti-hang mechanism */ 942 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1, 943 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 944 /* enable dynamic power gating mode */ 945 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS); 946 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 947 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 948 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp); 949 950 if (indirect) 951 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 952 953 /* enable clock gating */ 954 vcn_v3_0_clock_gating_dpg_mode(adev, 0, inst_idx, indirect); 955 956 /* enable VCPU clock */ 957 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 958 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 959 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK; 960 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 961 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 962 963 /* disable master interupt */ 964 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 965 VCN, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect); 966 967 /* setup mmUVD_LMI_CTRL */ 968 tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 969 UVD_LMI_CTRL__REQ_MODE_MASK | 970 UVD_LMI_CTRL__CRC_RESET_MASK | 971 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 972 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 973 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 974 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 975 0x00100000L); 976 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 977 VCN, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect); 978 979 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 980 VCN, inst_idx, mmUVD_MPC_CNTL), 981 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 982 983 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 984 VCN, inst_idx, mmUVD_MPC_SET_MUXA0), 985 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 986 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 987 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 988 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 989 990 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 991 VCN, inst_idx, mmUVD_MPC_SET_MUXB0), 992 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 993 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 994 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 995 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 996 997 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 998 VCN, inst_idx, mmUVD_MPC_SET_MUX), 999 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1000 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1001 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 1002 1003 vcn_v3_0_mc_resume_dpg_mode(adev, inst_idx, indirect); 1004 1005 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1006 VCN, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect); 1007 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1008 VCN, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect); 1009 1010 /* enable LMI MC and UMC channels */ 1011 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1012 VCN, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect); 1013 1014 /* unblock VCPU register access */ 1015 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1016 VCN, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect); 1017 1018 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 1019 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 1020 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1021 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 1022 1023 /* enable master interrupt */ 1024 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1025 VCN, inst_idx, mmUVD_MASTINT_EN), 1026 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 1027 1028 /* add nop to workaround PSP size check */ 1029 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1030 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 1031 1032 if (indirect) 1033 psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, 1034 (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr - 1035 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr)); 1036 1037 ring = &adev->vcn.inst[inst_idx].ring_dec; 1038 /* force RBC into idle state */ 1039 rb_bufsz = order_base_2(ring->ring_size); 1040 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1041 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1042 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1043 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1044 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1045 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp); 1046 1047 /* set the write pointer delay */ 1048 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0); 1049 1050 /* set the wb address */ 1051 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR, 1052 (upper_32_bits(ring->gpu_addr) >> 2)); 1053 1054 /* programm the RB_BASE for ring buffer */ 1055 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1056 lower_32_bits(ring->gpu_addr)); 1057 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1058 upper_32_bits(ring->gpu_addr)); 1059 1060 /* Initialize the ring buffer's read and write pointers */ 1061 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0); 1062 1063 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0); 1064 1065 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR); 1066 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, 1067 lower_32_bits(ring->wptr)); 1068 1069 return 0; 1070 } 1071 1072 static int vcn_v3_0_start(struct amdgpu_device *adev) 1073 { 1074 struct amdgpu_ring *ring; 1075 uint32_t rb_bufsz, tmp; 1076 int i, j, k, r; 1077 1078 if (adev->pm.dpm_enabled) 1079 amdgpu_dpm_enable_uvd(adev, true); 1080 1081 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1082 if (adev->vcn.harvest_config & (1 << i)) 1083 continue; 1084 1085 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG){ 1086 r = vcn_v3_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram); 1087 continue; 1088 } 1089 1090 /* disable VCN power gating */ 1091 vcn_v3_0_disable_static_power_gating(adev, i); 1092 1093 /* set VCN status busy */ 1094 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 1095 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp); 1096 1097 /*SW clock gating */ 1098 vcn_v3_0_disable_clock_gating(adev, i); 1099 1100 /* enable VCPU clock */ 1101 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1102 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 1103 1104 /* disable master interrupt */ 1105 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0, 1106 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1107 1108 /* enable LMI MC and UMC channels */ 1109 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0, 1110 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1111 1112 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1113 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1114 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1115 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1116 1117 /* setup mmUVD_LMI_CTRL */ 1118 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL); 1119 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | 1120 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1121 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1122 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1123 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1124 1125 /* setup mmUVD_MPC_CNTL */ 1126 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL); 1127 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1128 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1129 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp); 1130 1131 /* setup UVD_MPC_SET_MUXA0 */ 1132 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0, 1133 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1134 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1135 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1136 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1137 1138 /* setup UVD_MPC_SET_MUXB0 */ 1139 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0, 1140 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1141 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1142 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1143 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1144 1145 /* setup mmUVD_MPC_SET_MUX */ 1146 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX, 1147 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1148 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1149 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1150 1151 vcn_v3_0_mc_resume(adev, i); 1152 1153 /* VCN global tiling registers */ 1154 WREG32_SOC15(VCN, i, mmUVD_GFX10_ADDR_CONFIG, 1155 adev->gfx.config.gb_addr_config); 1156 1157 /* unblock VCPU register access */ 1158 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0, 1159 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1160 1161 /* release VCPU reset to boot */ 1162 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1163 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1164 1165 for (j = 0; j < 10; ++j) { 1166 uint32_t status; 1167 1168 for (k = 0; k < 100; ++k) { 1169 status = RREG32_SOC15(VCN, i, mmUVD_STATUS); 1170 if (status & 2) 1171 break; 1172 mdelay(10); 1173 } 1174 r = 0; 1175 if (status & 2) 1176 break; 1177 1178 DRM_ERROR("VCN[%d] decode not responding, trying to reset the VCPU!!!\n", i); 1179 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1180 UVD_VCPU_CNTL__BLK_RST_MASK, 1181 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1182 mdelay(10); 1183 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1184 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1185 1186 mdelay(10); 1187 r = -1; 1188 } 1189 1190 if (r) { 1191 DRM_ERROR("VCN[%d] decode not responding, giving up!!!\n", i); 1192 return r; 1193 } 1194 1195 /* enable master interrupt */ 1196 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 1197 UVD_MASTINT_EN__VCPU_EN_MASK, 1198 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1199 1200 /* clear the busy bit of VCN_STATUS */ 1201 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0, 1202 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1203 1204 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0); 1205 1206 ring = &adev->vcn.inst[i].ring_dec; 1207 /* force RBC into idle state */ 1208 rb_bufsz = order_base_2(ring->ring_size); 1209 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1210 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1211 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1212 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1213 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1214 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp); 1215 1216 /* programm the RB_BASE for ring buffer */ 1217 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1218 lower_32_bits(ring->gpu_addr)); 1219 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1220 upper_32_bits(ring->gpu_addr)); 1221 1222 /* Initialize the ring buffer's read and write pointers */ 1223 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0); 1224 1225 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR); 1226 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR, 1227 lower_32_bits(ring->wptr)); 1228 ring = &adev->vcn.inst[i].ring_enc[0]; 1229 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1230 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1231 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr); 1232 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1233 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4); 1234 1235 ring = &adev->vcn.inst[i].ring_enc[1]; 1236 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1237 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1238 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1239 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1240 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4); 1241 } 1242 1243 return 0; 1244 } 1245 1246 static int vcn_v3_0_start_sriov(struct amdgpu_device *adev) 1247 { 1248 int i, j; 1249 struct amdgpu_ring *ring; 1250 uint64_t cache_addr; 1251 uint64_t rb_addr; 1252 uint64_t ctx_addr; 1253 uint32_t param, resp, expected; 1254 uint32_t offset, cache_size; 1255 uint32_t tmp, timeout; 1256 uint32_t id; 1257 1258 struct amdgpu_mm_table *table = &adev->virt.mm_table; 1259 uint32_t *table_loc; 1260 uint32_t table_size; 1261 uint32_t size, size_dw; 1262 1263 bool is_vcn_ready; 1264 1265 struct mmsch_v3_0_cmd_direct_write 1266 direct_wt = { {0} }; 1267 struct mmsch_v3_0_cmd_direct_read_modify_write 1268 direct_rd_mod_wt = { {0} }; 1269 struct mmsch_v3_0_cmd_direct_polling 1270 direct_poll = { {0} }; 1271 struct mmsch_v3_0_cmd_end end = { {0} }; 1272 struct mmsch_v3_0_init_header header; 1273 1274 direct_wt.cmd_header.command_type = 1275 MMSCH_COMMAND__DIRECT_REG_WRITE; 1276 direct_rd_mod_wt.cmd_header.command_type = 1277 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1278 direct_poll.cmd_header.command_type = 1279 MMSCH_COMMAND__DIRECT_REG_POLLING; 1280 end.cmd_header.command_type = 1281 MMSCH_COMMAND__END; 1282 1283 header.version = MMSCH_VERSION; 1284 header.total_size = sizeof(struct mmsch_v3_0_init_header) >> 2; 1285 for (i = 0; i < AMDGPU_MAX_VCN_INSTANCES; i++) { 1286 header.inst[i].init_status = 0; 1287 header.inst[i].table_offset = 0; 1288 header.inst[i].table_size = 0; 1289 } 1290 1291 table_loc = (uint32_t *)table->cpu_addr; 1292 table_loc += header.total_size; 1293 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1294 if (adev->vcn.harvest_config & (1 << i)) 1295 continue; 1296 1297 table_size = 0; 1298 1299 MMSCH_V3_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i, 1300 mmUVD_STATUS), 1301 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 1302 1303 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 1304 1305 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1306 id = amdgpu_ucode_id_vcns[i]; 1307 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1308 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1309 adev->firmware.ucode[id].tmr_mc_addr_lo); 1310 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1311 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1312 adev->firmware.ucode[id].tmr_mc_addr_hi); 1313 offset = 0; 1314 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1315 mmUVD_VCPU_CACHE_OFFSET0), 1316 0); 1317 } else { 1318 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1319 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1320 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 1321 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1322 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1323 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 1324 offset = cache_size; 1325 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1326 mmUVD_VCPU_CACHE_OFFSET0), 1327 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 1328 } 1329 1330 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1331 mmUVD_VCPU_CACHE_SIZE0), 1332 cache_size); 1333 1334 cache_addr = adev->vcn.inst[i].gpu_addr + offset; 1335 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1336 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 1337 lower_32_bits(cache_addr)); 1338 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1339 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 1340 upper_32_bits(cache_addr)); 1341 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1342 mmUVD_VCPU_CACHE_OFFSET1), 1343 0); 1344 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1345 mmUVD_VCPU_CACHE_SIZE1), 1346 AMDGPU_VCN_STACK_SIZE); 1347 1348 cache_addr = adev->vcn.inst[i].gpu_addr + offset + 1349 AMDGPU_VCN_STACK_SIZE; 1350 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1351 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 1352 lower_32_bits(cache_addr)); 1353 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1354 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 1355 upper_32_bits(cache_addr)); 1356 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1357 mmUVD_VCPU_CACHE_OFFSET2), 1358 0); 1359 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1360 mmUVD_VCPU_CACHE_SIZE2), 1361 AMDGPU_VCN_CONTEXT_SIZE); 1362 1363 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 1364 ring = &adev->vcn.inst[i].ring_enc[j]; 1365 ring->wptr = 0; 1366 rb_addr = ring->gpu_addr; 1367 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1368 mmUVD_RB_BASE_LO), 1369 lower_32_bits(rb_addr)); 1370 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1371 mmUVD_RB_BASE_HI), 1372 upper_32_bits(rb_addr)); 1373 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1374 mmUVD_RB_SIZE), 1375 ring->ring_size / 4); 1376 } 1377 1378 ring = &adev->vcn.inst[i].ring_dec; 1379 ring->wptr = 0; 1380 rb_addr = ring->gpu_addr; 1381 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1382 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW), 1383 lower_32_bits(rb_addr)); 1384 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1385 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH), 1386 upper_32_bits(rb_addr)); 1387 /* force RBC into idle state */ 1388 tmp = order_base_2(ring->ring_size); 1389 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp); 1390 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1391 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1392 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1393 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1394 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1395 mmUVD_RBC_RB_CNTL), 1396 tmp); 1397 1398 /* add end packet */ 1399 MMSCH_V3_0_INSERT_END(); 1400 1401 /* refine header */ 1402 header.inst[i].init_status = 0; 1403 header.inst[i].table_offset = header.total_size; 1404 header.inst[i].table_size = table_size; 1405 header.total_size += table_size; 1406 } 1407 1408 /* Update init table header in memory */ 1409 size = sizeof(struct mmsch_v3_0_init_header); 1410 table_loc = (uint32_t *)table->cpu_addr; 1411 memcpy((void *)table_loc, &header, size); 1412 1413 /* message MMSCH (in VCN[0]) to initialize this client 1414 * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr 1415 * of memory descriptor location 1416 */ 1417 ctx_addr = table->gpu_addr; 1418 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 1419 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 1420 1421 /* 2, update vmid of descriptor */ 1422 tmp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID); 1423 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1424 /* use domain0 for MM scheduler */ 1425 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1426 WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, tmp); 1427 1428 /* 3, notify mmsch about the size of this descriptor */ 1429 size = header.total_size; 1430 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size); 1431 1432 /* 4, set resp to zero */ 1433 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0); 1434 1435 /* 5, kick off the initialization and wait until 1436 * MMSCH_VF_MAILBOX_RESP becomes non-zero 1437 */ 1438 param = 0x10000001; 1439 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, param); 1440 tmp = 0; 1441 timeout = 1000; 1442 resp = 0; 1443 expected = param + 1; 1444 while (resp != expected) { 1445 resp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); 1446 if (resp == expected) 1447 break; 1448 1449 udelay(10); 1450 tmp = tmp + 10; 1451 if (tmp >= timeout) { 1452 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 1453 " waiting for mmMMSCH_VF_MAILBOX_RESP "\ 1454 "(expected=0x%08x, readback=0x%08x)\n", 1455 tmp, expected, resp); 1456 return -EBUSY; 1457 } 1458 } 1459 1460 /* 6, check each VCN's init_status 1461 * if it remains as 0, then this VCN is not assigned to current VF 1462 * do not start ring for this VCN 1463 */ 1464 size = sizeof(struct mmsch_v3_0_init_header); 1465 table_loc = (uint32_t *)table->cpu_addr; 1466 memcpy(&header, (void *)table_loc, size); 1467 1468 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1469 if (adev->vcn.harvest_config & (1 << i)) 1470 continue; 1471 1472 is_vcn_ready = (header.inst[i].init_status == 1); 1473 if (!is_vcn_ready) 1474 DRM_INFO("VCN(%d) engine is disabled by hypervisor\n", i); 1475 1476 ring = &adev->vcn.inst[i].ring_dec; 1477 ring->sched.ready = is_vcn_ready; 1478 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 1479 ring = &adev->vcn.inst[i].ring_enc[j]; 1480 ring->sched.ready = is_vcn_ready; 1481 } 1482 } 1483 1484 return 0; 1485 } 1486 1487 static int vcn_v3_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) 1488 { 1489 uint32_t tmp; 1490 1491 /* Wait for power status to be 1 */ 1492 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1493 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1494 1495 /* wait for read ptr to be equal to write ptr */ 1496 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR); 1497 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1498 1499 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2); 1500 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); 1501 1502 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1503 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); 1504 1505 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1506 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1507 1508 /* disable dynamic power gating mode */ 1509 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0, 1510 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1511 1512 return 0; 1513 } 1514 1515 static int vcn_v3_0_stop(struct amdgpu_device *adev) 1516 { 1517 uint32_t tmp; 1518 int i, r = 0; 1519 1520 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1521 if (adev->vcn.harvest_config & (1 << i)) 1522 continue; 1523 1524 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1525 r = vcn_v3_0_stop_dpg_mode(adev, i); 1526 continue; 1527 } 1528 1529 /* wait for vcn idle */ 1530 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1531 if (r) 1532 return r; 1533 1534 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1535 UVD_LMI_STATUS__READ_CLEAN_MASK | 1536 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1537 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1538 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1539 if (r) 1540 return r; 1541 1542 /* disable LMI UMC channel */ 1543 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2); 1544 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1545 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp); 1546 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK| 1547 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1548 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1549 if (r) 1550 return r; 1551 1552 /* block VCPU register access */ 1553 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 1554 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1555 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1556 1557 /* reset VCPU */ 1558 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1559 UVD_VCPU_CNTL__BLK_RST_MASK, 1560 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1561 1562 /* disable VCPU clock */ 1563 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1564 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1565 1566 /* apply soft reset */ 1567 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1568 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1569 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1570 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1571 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1572 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1573 1574 /* clear status */ 1575 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0); 1576 1577 /* apply HW clock gating */ 1578 vcn_v3_0_enable_clock_gating(adev, i); 1579 1580 /* enable VCN power gating */ 1581 vcn_v3_0_enable_static_power_gating(adev, i); 1582 } 1583 1584 if (adev->pm.dpm_enabled) 1585 amdgpu_dpm_enable_uvd(adev, false); 1586 1587 return 0; 1588 } 1589 1590 static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev, 1591 int inst_idx, struct dpg_pause_state *new_state) 1592 { 1593 struct amdgpu_ring *ring; 1594 uint32_t reg_data = 0; 1595 int ret_code; 1596 1597 /* pause/unpause if state is changed */ 1598 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1599 DRM_DEBUG("dpg pause state changed %d -> %d", 1600 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1601 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) & 1602 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1603 1604 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1605 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, 1606 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1607 1608 if (!ret_code) { 1609 /* pause DPG */ 1610 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1611 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1612 1613 /* wait for ACK */ 1614 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE, 1615 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1616 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1617 1618 /* Restore */ 1619 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 1620 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr); 1621 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1622 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4); 1623 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1624 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1625 1626 ring = &adev->vcn.inst[inst_idx].ring_enc[1]; 1627 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1628 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1629 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4); 1630 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1631 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1632 1633 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, 1634 RREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2) & 0x7FFFFFFF); 1635 1636 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1637 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1638 } 1639 } else { 1640 /* unpause dpg, no need to wait */ 1641 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1642 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1643 } 1644 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1645 } 1646 1647 return 0; 1648 } 1649 1650 /** 1651 * vcn_v3_0_dec_ring_get_rptr - get read pointer 1652 * 1653 * @ring: amdgpu_ring pointer 1654 * 1655 * Returns the current hardware read pointer 1656 */ 1657 static uint64_t vcn_v3_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 1658 { 1659 struct amdgpu_device *adev = ring->adev; 1660 1661 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR); 1662 } 1663 1664 /** 1665 * vcn_v3_0_dec_ring_get_wptr - get write pointer 1666 * 1667 * @ring: amdgpu_ring pointer 1668 * 1669 * Returns the current hardware write pointer 1670 */ 1671 static uint64_t vcn_v3_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 1672 { 1673 struct amdgpu_device *adev = ring->adev; 1674 1675 if (ring->use_doorbell) 1676 return adev->wb.wb[ring->wptr_offs]; 1677 else 1678 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR); 1679 } 1680 1681 /** 1682 * vcn_v3_0_dec_ring_set_wptr - set write pointer 1683 * 1684 * @ring: amdgpu_ring pointer 1685 * 1686 * Commits the write pointer to the hardware 1687 */ 1688 static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 1689 { 1690 struct amdgpu_device *adev = ring->adev; 1691 1692 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1693 WREG32_SOC15(VCN, ring->me, mmUVD_SCRATCH2, 1694 lower_32_bits(ring->wptr) | 0x80000000); 1695 1696 if (ring->use_doorbell) { 1697 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 1698 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1699 } else { 1700 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1701 } 1702 } 1703 1704 void vcn_v3_0_dec_sw_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1705 u64 seq, uint32_t flags) 1706 { 1707 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1708 1709 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_FENCE); 1710 amdgpu_ring_write(ring, addr); 1711 amdgpu_ring_write(ring, upper_32_bits(addr)); 1712 amdgpu_ring_write(ring, seq); 1713 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_TRAP); 1714 } 1715 1716 void vcn_v3_0_dec_sw_ring_insert_end(struct amdgpu_ring *ring) 1717 { 1718 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END); 1719 } 1720 1721 void vcn_v3_0_dec_sw_ring_emit_ib(struct amdgpu_ring *ring, 1722 struct amdgpu_job *job, 1723 struct amdgpu_ib *ib, 1724 uint32_t flags) 1725 { 1726 uint32_t vmid = AMDGPU_JOB_GET_VMID(job); 1727 1728 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_IB); 1729 amdgpu_ring_write(ring, vmid); 1730 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1731 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1732 amdgpu_ring_write(ring, ib->length_dw); 1733 } 1734 1735 void vcn_v3_0_dec_sw_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1736 uint32_t val, uint32_t mask) 1737 { 1738 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WAIT); 1739 amdgpu_ring_write(ring, reg << 2); 1740 amdgpu_ring_write(ring, mask); 1741 amdgpu_ring_write(ring, val); 1742 } 1743 1744 void vcn_v3_0_dec_sw_ring_emit_vm_flush(struct amdgpu_ring *ring, 1745 uint32_t vmid, uint64_t pd_addr) 1746 { 1747 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1748 uint32_t data0, data1, mask; 1749 1750 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1751 1752 /* wait for register write */ 1753 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance; 1754 data1 = lower_32_bits(pd_addr); 1755 mask = 0xffffffff; 1756 vcn_v3_0_dec_sw_ring_emit_reg_wait(ring, data0, data1, mask); 1757 } 1758 1759 void vcn_v3_0_dec_sw_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) 1760 { 1761 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WRITE); 1762 amdgpu_ring_write(ring, reg << 2); 1763 amdgpu_ring_write(ring, val); 1764 } 1765 1766 static const struct amdgpu_ring_funcs vcn_v3_0_dec_sw_ring_vm_funcs = { 1767 .type = AMDGPU_RING_TYPE_VCN_DEC, 1768 .align_mask = 0x3f, 1769 .nop = VCN_DEC_SW_CMD_NO_OP, 1770 .vmhub = AMDGPU_MMHUB_0, 1771 .get_rptr = vcn_v3_0_dec_ring_get_rptr, 1772 .get_wptr = vcn_v3_0_dec_ring_get_wptr, 1773 .set_wptr = vcn_v3_0_dec_ring_set_wptr, 1774 .emit_frame_size = 1775 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1776 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1777 4 + /* vcn_v3_0_dec_sw_ring_emit_vm_flush */ 1778 5 + 5 + /* vcn_v3_0_dec_sw_ring_emit_fdec_swe x2 vm fdec_swe */ 1779 1, /* vcn_v3_0_dec_sw_ring_insert_end */ 1780 .emit_ib_size = 5, /* vcn_v3_0_dec_sw_ring_emit_ib */ 1781 .emit_ib = vcn_v3_0_dec_sw_ring_emit_ib, 1782 .emit_fence = vcn_v3_0_dec_sw_ring_emit_fence, 1783 .emit_vm_flush = vcn_v3_0_dec_sw_ring_emit_vm_flush, 1784 .test_ring = amdgpu_vcn_dec_sw_ring_test_ring, 1785 .test_ib = NULL,//amdgpu_vcn_dec_sw_ring_test_ib, 1786 .insert_nop = amdgpu_ring_insert_nop, 1787 .insert_end = vcn_v3_0_dec_sw_ring_insert_end, 1788 .pad_ib = amdgpu_ring_generic_pad_ib, 1789 .begin_use = amdgpu_vcn_ring_begin_use, 1790 .end_use = amdgpu_vcn_ring_end_use, 1791 .emit_wreg = vcn_v3_0_dec_sw_ring_emit_wreg, 1792 .emit_reg_wait = vcn_v3_0_dec_sw_ring_emit_reg_wait, 1793 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1794 }; 1795 1796 static const struct amdgpu_ring_funcs vcn_v3_0_dec_ring_vm_funcs = { 1797 .type = AMDGPU_RING_TYPE_VCN_DEC, 1798 .align_mask = 0xf, 1799 .vmhub = AMDGPU_MMHUB_0, 1800 .get_rptr = vcn_v3_0_dec_ring_get_rptr, 1801 .get_wptr = vcn_v3_0_dec_ring_get_wptr, 1802 .set_wptr = vcn_v3_0_dec_ring_set_wptr, 1803 .emit_frame_size = 1804 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1805 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1806 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */ 1807 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */ 1808 6, 1809 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */ 1810 .emit_ib = vcn_v2_0_dec_ring_emit_ib, 1811 .emit_fence = vcn_v2_0_dec_ring_emit_fence, 1812 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush, 1813 .test_ring = vcn_v2_0_dec_ring_test_ring, 1814 .test_ib = amdgpu_vcn_dec_ring_test_ib, 1815 .insert_nop = vcn_v2_0_dec_ring_insert_nop, 1816 .insert_start = vcn_v2_0_dec_ring_insert_start, 1817 .insert_end = vcn_v2_0_dec_ring_insert_end, 1818 .pad_ib = amdgpu_ring_generic_pad_ib, 1819 .begin_use = amdgpu_vcn_ring_begin_use, 1820 .end_use = amdgpu_vcn_ring_end_use, 1821 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg, 1822 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait, 1823 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1824 }; 1825 1826 /** 1827 * vcn_v3_0_enc_ring_get_rptr - get enc read pointer 1828 * 1829 * @ring: amdgpu_ring pointer 1830 * 1831 * Returns the current hardware enc read pointer 1832 */ 1833 static uint64_t vcn_v3_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 1834 { 1835 struct amdgpu_device *adev = ring->adev; 1836 1837 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) 1838 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR); 1839 else 1840 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2); 1841 } 1842 1843 /** 1844 * vcn_v3_0_enc_ring_get_wptr - get enc write pointer 1845 * 1846 * @ring: amdgpu_ring pointer 1847 * 1848 * Returns the current hardware enc write pointer 1849 */ 1850 static uint64_t vcn_v3_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 1851 { 1852 struct amdgpu_device *adev = ring->adev; 1853 1854 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 1855 if (ring->use_doorbell) 1856 return adev->wb.wb[ring->wptr_offs]; 1857 else 1858 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR); 1859 } else { 1860 if (ring->use_doorbell) 1861 return adev->wb.wb[ring->wptr_offs]; 1862 else 1863 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2); 1864 } 1865 } 1866 1867 /** 1868 * vcn_v3_0_enc_ring_set_wptr - set enc write pointer 1869 * 1870 * @ring: amdgpu_ring pointer 1871 * 1872 * Commits the enc write pointer to the hardware 1873 */ 1874 static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 1875 { 1876 struct amdgpu_device *adev = ring->adev; 1877 1878 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 1879 if (ring->use_doorbell) { 1880 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 1881 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1882 } else { 1883 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1884 } 1885 } else { 1886 if (ring->use_doorbell) { 1887 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 1888 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1889 } else { 1890 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1891 } 1892 } 1893 } 1894 1895 static const struct amdgpu_ring_funcs vcn_v3_0_enc_ring_vm_funcs = { 1896 .type = AMDGPU_RING_TYPE_VCN_ENC, 1897 .align_mask = 0x3f, 1898 .nop = VCN_ENC_CMD_NO_OP, 1899 .vmhub = AMDGPU_MMHUB_0, 1900 .get_rptr = vcn_v3_0_enc_ring_get_rptr, 1901 .get_wptr = vcn_v3_0_enc_ring_get_wptr, 1902 .set_wptr = vcn_v3_0_enc_ring_set_wptr, 1903 .emit_frame_size = 1904 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1905 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1906 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1907 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1908 1, /* vcn_v2_0_enc_ring_insert_end */ 1909 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1910 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1911 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1912 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 1913 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1914 .test_ib = amdgpu_vcn_enc_ring_test_ib, 1915 .insert_nop = amdgpu_ring_insert_nop, 1916 .insert_end = vcn_v2_0_enc_ring_insert_end, 1917 .pad_ib = amdgpu_ring_generic_pad_ib, 1918 .begin_use = amdgpu_vcn_ring_begin_use, 1919 .end_use = amdgpu_vcn_ring_end_use, 1920 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 1921 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 1922 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1923 }; 1924 1925 static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev) 1926 { 1927 int i; 1928 1929 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1930 if (adev->vcn.harvest_config & (1 << i)) 1931 continue; 1932 1933 if (!DEC_SW_RING_ENABLED) 1934 adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_ring_vm_funcs; 1935 else 1936 adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_sw_ring_vm_funcs; 1937 adev->vcn.inst[i].ring_dec.me = i; 1938 DRM_INFO("VCN(%d) decode%s is enabled in VM mode\n", i, 1939 DEC_SW_RING_ENABLED?"(Software Ring)":""); 1940 } 1941 } 1942 1943 static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev) 1944 { 1945 int i, j; 1946 1947 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1948 if (adev->vcn.harvest_config & (1 << i)) 1949 continue; 1950 1951 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 1952 adev->vcn.inst[i].ring_enc[j].funcs = &vcn_v3_0_enc_ring_vm_funcs; 1953 adev->vcn.inst[i].ring_enc[j].me = i; 1954 } 1955 DRM_INFO("VCN(%d) encode is enabled in VM mode\n", i); 1956 } 1957 } 1958 1959 static bool vcn_v3_0_is_idle(void *handle) 1960 { 1961 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1962 int i, ret = 1; 1963 1964 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1965 if (adev->vcn.harvest_config & (1 << i)) 1966 continue; 1967 1968 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); 1969 } 1970 1971 return ret; 1972 } 1973 1974 static int vcn_v3_0_wait_for_idle(void *handle) 1975 { 1976 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1977 int i, ret = 0; 1978 1979 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1980 if (adev->vcn.harvest_config & (1 << i)) 1981 continue; 1982 1983 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 1984 UVD_STATUS__IDLE); 1985 if (ret) 1986 return ret; 1987 } 1988 1989 return ret; 1990 } 1991 1992 static int vcn_v3_0_set_clockgating_state(void *handle, 1993 enum amd_clockgating_state state) 1994 { 1995 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1996 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 1997 int i; 1998 1999 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2000 if (adev->vcn.harvest_config & (1 << i)) 2001 continue; 2002 2003 if (enable) { 2004 if (RREG32_SOC15(VCN, i, mmUVD_STATUS) != UVD_STATUS__IDLE) 2005 return -EBUSY; 2006 vcn_v3_0_enable_clock_gating(adev, i); 2007 } else { 2008 vcn_v3_0_disable_clock_gating(adev, i); 2009 } 2010 } 2011 2012 return 0; 2013 } 2014 2015 static int vcn_v3_0_set_powergating_state(void *handle, 2016 enum amd_powergating_state state) 2017 { 2018 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2019 int ret; 2020 2021 /* for SRIOV, guest should not control VCN Power-gating 2022 * MMSCH FW should control Power-gating and clock-gating 2023 * guest should avoid touching CGC and PG 2024 */ 2025 if (amdgpu_sriov_vf(adev)) { 2026 adev->vcn.cur_state = AMD_PG_STATE_UNGATE; 2027 return 0; 2028 } 2029 2030 if(state == adev->vcn.cur_state) 2031 return 0; 2032 2033 if (state == AMD_PG_STATE_GATE) 2034 ret = vcn_v3_0_stop(adev); 2035 else 2036 ret = vcn_v3_0_start(adev); 2037 2038 if(!ret) 2039 adev->vcn.cur_state = state; 2040 2041 return ret; 2042 } 2043 2044 static int vcn_v3_0_set_interrupt_state(struct amdgpu_device *adev, 2045 struct amdgpu_irq_src *source, 2046 unsigned type, 2047 enum amdgpu_interrupt_state state) 2048 { 2049 return 0; 2050 } 2051 2052 static int vcn_v3_0_process_interrupt(struct amdgpu_device *adev, 2053 struct amdgpu_irq_src *source, 2054 struct amdgpu_iv_entry *entry) 2055 { 2056 uint32_t ip_instance; 2057 2058 switch (entry->client_id) { 2059 case SOC15_IH_CLIENTID_VCN: 2060 ip_instance = 0; 2061 break; 2062 case SOC15_IH_CLIENTID_VCN1: 2063 ip_instance = 1; 2064 break; 2065 default: 2066 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 2067 return 0; 2068 } 2069 2070 DRM_DEBUG("IH: VCN TRAP\n"); 2071 2072 switch (entry->src_id) { 2073 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT: 2074 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec); 2075 break; 2076 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 2077 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 2078 break; 2079 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY: 2080 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]); 2081 break; 2082 default: 2083 DRM_ERROR("Unhandled interrupt: %d %d\n", 2084 entry->src_id, entry->src_data[0]); 2085 break; 2086 } 2087 2088 return 0; 2089 } 2090 2091 static const struct amdgpu_irq_src_funcs vcn_v3_0_irq_funcs = { 2092 .set = vcn_v3_0_set_interrupt_state, 2093 .process = vcn_v3_0_process_interrupt, 2094 }; 2095 2096 static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev) 2097 { 2098 int i; 2099 2100 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2101 if (adev->vcn.harvest_config & (1 << i)) 2102 continue; 2103 2104 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1; 2105 adev->vcn.inst[i].irq.funcs = &vcn_v3_0_irq_funcs; 2106 } 2107 } 2108 2109 static const struct amd_ip_funcs vcn_v3_0_ip_funcs = { 2110 .name = "vcn_v3_0", 2111 .early_init = vcn_v3_0_early_init, 2112 .late_init = NULL, 2113 .sw_init = vcn_v3_0_sw_init, 2114 .sw_fini = vcn_v3_0_sw_fini, 2115 .hw_init = vcn_v3_0_hw_init, 2116 .hw_fini = vcn_v3_0_hw_fini, 2117 .suspend = vcn_v3_0_suspend, 2118 .resume = vcn_v3_0_resume, 2119 .is_idle = vcn_v3_0_is_idle, 2120 .wait_for_idle = vcn_v3_0_wait_for_idle, 2121 .check_soft_reset = NULL, 2122 .pre_soft_reset = NULL, 2123 .soft_reset = NULL, 2124 .post_soft_reset = NULL, 2125 .set_clockgating_state = vcn_v3_0_set_clockgating_state, 2126 .set_powergating_state = vcn_v3_0_set_powergating_state, 2127 }; 2128 2129 const struct amdgpu_ip_block_version vcn_v3_0_ip_block = 2130 { 2131 .type = AMD_IP_BLOCK_TYPE_VCN, 2132 .major = 3, 2133 .minor = 0, 2134 .rev = 0, 2135 .funcs = &vcn_v3_0_ip_funcs, 2136 }; 2137