1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drm_drv.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_vcn.h" 29 #include "amdgpu_pm.h" 30 #include "soc15.h" 31 #include "soc15d.h" 32 #include "vcn_v2_0.h" 33 #include "mmsch_v1_0.h" 34 #include "vcn_v2_5.h" 35 36 #include "vcn/vcn_2_5_offset.h" 37 #include "vcn/vcn_2_5_sh_mask.h" 38 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 39 40 #define VCN_VID_SOC_ADDRESS_2_0 0x1fa00 41 #define VCN1_VID_SOC_ADDRESS_3_0 0x48200 42 43 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x27 44 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x0f 45 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x10 46 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x11 47 #define mmUVD_NO_OP_INTERNAL_OFFSET 0x29 48 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x66 49 #define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d 50 51 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x431 52 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x3b4 53 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x3b5 54 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x25c 55 56 #define VCN25_MAX_HW_INSTANCES_ARCTURUS 2 57 58 static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev); 59 static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev); 60 static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev); 61 static int vcn_v2_5_set_powergating_state(void *handle, 62 enum amd_powergating_state state); 63 static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev, 64 int inst_idx, struct dpg_pause_state *new_state); 65 static int vcn_v2_5_sriov_start(struct amdgpu_device *adev); 66 static void vcn_v2_5_set_ras_funcs(struct amdgpu_device *adev); 67 68 static int amdgpu_ih_clientid_vcns[] = { 69 SOC15_IH_CLIENTID_VCN, 70 SOC15_IH_CLIENTID_VCN1 71 }; 72 73 /** 74 * vcn_v2_5_early_init - set function pointers 75 * 76 * @handle: amdgpu_device pointer 77 * 78 * Set ring and irq function pointers 79 */ 80 static int vcn_v2_5_early_init(void *handle) 81 { 82 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 83 84 if (amdgpu_sriov_vf(adev)) { 85 adev->vcn.num_vcn_inst = 2; 86 adev->vcn.harvest_config = 0; 87 adev->vcn.num_enc_rings = 1; 88 } else { 89 u32 harvest; 90 int i; 91 92 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 93 harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING); 94 if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK) 95 adev->vcn.harvest_config |= 1 << i; 96 } 97 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 | 98 AMDGPU_VCN_HARVEST_VCN1)) 99 /* both instances are harvested, disable the block */ 100 return -ENOENT; 101 102 adev->vcn.num_enc_rings = 2; 103 } 104 105 vcn_v2_5_set_dec_ring_funcs(adev); 106 vcn_v2_5_set_enc_ring_funcs(adev); 107 vcn_v2_5_set_irq_funcs(adev); 108 vcn_v2_5_set_ras_funcs(adev); 109 110 return 0; 111 } 112 113 /** 114 * vcn_v2_5_sw_init - sw init for VCN block 115 * 116 * @handle: amdgpu_device pointer 117 * 118 * Load firmware and sw initialization 119 */ 120 static int vcn_v2_5_sw_init(void *handle) 121 { 122 struct amdgpu_ring *ring; 123 int i, j, r; 124 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 125 126 for (j = 0; j < adev->vcn.num_vcn_inst; j++) { 127 if (adev->vcn.harvest_config & (1 << j)) 128 continue; 129 /* VCN DEC TRAP */ 130 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j], 131 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[j].irq); 132 if (r) 133 return r; 134 135 /* VCN ENC TRAP */ 136 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 137 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j], 138 i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[j].irq); 139 if (r) 140 return r; 141 } 142 143 /* VCN POISON TRAP */ 144 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j], 145 VCN_2_6__SRCID_UVD_POISON, &adev->vcn.inst[j].irq); 146 if (r) 147 return r; 148 } 149 150 r = amdgpu_vcn_sw_init(adev); 151 if (r) 152 return r; 153 154 amdgpu_vcn_setup_ucode(adev); 155 156 r = amdgpu_vcn_resume(adev); 157 if (r) 158 return r; 159 160 for (j = 0; j < adev->vcn.num_vcn_inst; j++) { 161 volatile struct amdgpu_fw_shared *fw_shared; 162 163 if (adev->vcn.harvest_config & (1 << j)) 164 continue; 165 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; 166 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; 167 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; 168 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; 169 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; 170 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; 171 172 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; 173 adev->vcn.inst[j].external.scratch9 = SOC15_REG_OFFSET(VCN, j, mmUVD_SCRATCH9); 174 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; 175 adev->vcn.inst[j].external.data0 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA0); 176 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; 177 adev->vcn.inst[j].external.data1 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA1); 178 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; 179 adev->vcn.inst[j].external.cmd = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_CMD); 180 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; 181 adev->vcn.inst[j].external.nop = SOC15_REG_OFFSET(VCN, j, mmUVD_NO_OP); 182 183 ring = &adev->vcn.inst[j].ring_dec; 184 ring->use_doorbell = true; 185 186 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 187 (amdgpu_sriov_vf(adev) ? 2*j : 8*j); 188 sprintf(ring->name, "vcn_dec_%d", j); 189 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq, 190 0, AMDGPU_RING_PRIO_DEFAULT, NULL); 191 if (r) 192 return r; 193 194 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 195 enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(i); 196 197 ring = &adev->vcn.inst[j].ring_enc[i]; 198 ring->use_doorbell = true; 199 200 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 201 (amdgpu_sriov_vf(adev) ? (1 + i + 2*j) : (2 + i + 8*j)); 202 203 sprintf(ring->name, "vcn_enc_%d.%d", j, i); 204 r = amdgpu_ring_init(adev, ring, 512, 205 &adev->vcn.inst[j].irq, 0, 206 hw_prio, NULL); 207 if (r) 208 return r; 209 } 210 211 fw_shared = adev->vcn.inst[j].fw_shared.cpu_addr; 212 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG); 213 214 if (amdgpu_vcnfw_log) 215 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]); 216 } 217 218 if (amdgpu_sriov_vf(adev)) { 219 r = amdgpu_virt_alloc_mm_table(adev); 220 if (r) 221 return r; 222 } 223 224 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 225 adev->vcn.pause_dpg_mode = vcn_v2_5_pause_dpg_mode; 226 227 return 0; 228 } 229 230 /** 231 * vcn_v2_5_sw_fini - sw fini for VCN block 232 * 233 * @handle: amdgpu_device pointer 234 * 235 * VCN suspend and free up sw allocation 236 */ 237 static int vcn_v2_5_sw_fini(void *handle) 238 { 239 int i, r, idx; 240 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 241 volatile struct amdgpu_fw_shared *fw_shared; 242 243 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 244 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 245 if (adev->vcn.harvest_config & (1 << i)) 246 continue; 247 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 248 fw_shared->present_flag_0 = 0; 249 } 250 drm_dev_exit(idx); 251 } 252 253 254 if (amdgpu_sriov_vf(adev)) 255 amdgpu_virt_free_mm_table(adev); 256 257 r = amdgpu_vcn_suspend(adev); 258 if (r) 259 return r; 260 261 r = amdgpu_vcn_sw_fini(adev); 262 263 return r; 264 } 265 266 /** 267 * vcn_v2_5_hw_init - start and test VCN block 268 * 269 * @handle: amdgpu_device pointer 270 * 271 * Initialize the hardware, boot up the VCPU and do some testing 272 */ 273 static int vcn_v2_5_hw_init(void *handle) 274 { 275 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 276 struct amdgpu_ring *ring; 277 int i, j, r = 0; 278 279 if (amdgpu_sriov_vf(adev)) 280 r = vcn_v2_5_sriov_start(adev); 281 282 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 283 if (adev->vcn.harvest_config & (1 << j)) 284 continue; 285 286 if (amdgpu_sriov_vf(adev)) { 287 adev->vcn.inst[j].ring_enc[0].sched.ready = true; 288 adev->vcn.inst[j].ring_enc[1].sched.ready = false; 289 adev->vcn.inst[j].ring_enc[2].sched.ready = false; 290 adev->vcn.inst[j].ring_dec.sched.ready = true; 291 } else { 292 293 ring = &adev->vcn.inst[j].ring_dec; 294 295 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 296 ring->doorbell_index, j); 297 298 r = amdgpu_ring_test_helper(ring); 299 if (r) 300 goto done; 301 302 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 303 ring = &adev->vcn.inst[j].ring_enc[i]; 304 r = amdgpu_ring_test_helper(ring); 305 if (r) 306 goto done; 307 } 308 } 309 } 310 311 done: 312 if (!r) 313 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 314 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 315 316 return r; 317 } 318 319 /** 320 * vcn_v2_5_hw_fini - stop the hardware block 321 * 322 * @handle: amdgpu_device pointer 323 * 324 * Stop the VCN block, mark ring as not ready any more 325 */ 326 static int vcn_v2_5_hw_fini(void *handle) 327 { 328 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 329 int i; 330 331 cancel_delayed_work_sync(&adev->vcn.idle_work); 332 333 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 334 if (adev->vcn.harvest_config & (1 << i)) 335 continue; 336 337 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 338 (adev->vcn.cur_state != AMD_PG_STATE_GATE && 339 RREG32_SOC15(VCN, i, mmUVD_STATUS))) 340 vcn_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE); 341 } 342 343 return 0; 344 } 345 346 /** 347 * vcn_v2_5_suspend - suspend VCN block 348 * 349 * @handle: amdgpu_device pointer 350 * 351 * HW fini and suspend VCN block 352 */ 353 static int vcn_v2_5_suspend(void *handle) 354 { 355 int r; 356 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 357 358 r = vcn_v2_5_hw_fini(adev); 359 if (r) 360 return r; 361 362 r = amdgpu_vcn_suspend(adev); 363 364 return r; 365 } 366 367 /** 368 * vcn_v2_5_resume - resume VCN block 369 * 370 * @handle: amdgpu_device pointer 371 * 372 * Resume firmware and hw init VCN block 373 */ 374 static int vcn_v2_5_resume(void *handle) 375 { 376 int r; 377 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 378 379 r = amdgpu_vcn_resume(adev); 380 if (r) 381 return r; 382 383 r = vcn_v2_5_hw_init(adev); 384 385 return r; 386 } 387 388 /** 389 * vcn_v2_5_mc_resume - memory controller programming 390 * 391 * @adev: amdgpu_device pointer 392 * 393 * Let the VCN memory controller know it's offsets 394 */ 395 static void vcn_v2_5_mc_resume(struct amdgpu_device *adev) 396 { 397 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 398 uint32_t offset; 399 int i; 400 401 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 402 if (adev->vcn.harvest_config & (1 << i)) 403 continue; 404 /* cache window 0: fw */ 405 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 406 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 407 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo)); 408 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 409 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi)); 410 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, 0); 411 offset = 0; 412 } else { 413 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 414 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 415 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 416 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 417 offset = size; 418 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, 419 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 420 } 421 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE0, size); 422 423 /* cache window 1: stack */ 424 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 425 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset)); 426 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 427 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset)); 428 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET1, 0); 429 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 430 431 /* cache window 2: context */ 432 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 433 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 434 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 435 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 436 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET2, 0); 437 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 438 439 /* non-cache window */ 440 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 441 lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); 442 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 443 upper_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); 444 WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_OFFSET0, 0); 445 WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_SIZE0, 446 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); 447 } 448 } 449 450 static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 451 { 452 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 453 uint32_t offset; 454 455 /* cache window 0: fw */ 456 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 457 if (!indirect) { 458 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 459 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 460 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); 461 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 462 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 463 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); 464 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 465 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 466 } else { 467 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 468 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 469 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 470 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 471 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 472 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 473 } 474 offset = 0; 475 } else { 476 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 477 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 478 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 479 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 480 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 481 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 482 offset = size; 483 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 484 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 485 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 486 } 487 488 if (!indirect) 489 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 490 VCN, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 491 else 492 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 493 VCN, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 494 495 /* cache window 1: stack */ 496 if (!indirect) { 497 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 498 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 499 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 500 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 501 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 502 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 503 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 504 VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 505 } else { 506 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 507 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 508 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 509 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 510 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 511 VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 512 } 513 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 514 VCN, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 515 516 /* cache window 2: context */ 517 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 518 VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 519 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 520 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 521 VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 522 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 523 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 524 VCN, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 525 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 526 VCN, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 527 528 /* non-cache window */ 529 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 530 VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 531 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 532 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 533 VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 534 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 535 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 536 VCN, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 537 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 538 VCN, 0, mmUVD_VCPU_NONCACHE_SIZE0), 539 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); 540 541 /* VCN global tiling registers */ 542 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 543 VCN, 0, mmUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 544 } 545 546 /** 547 * vcn_v2_5_disable_clock_gating - disable VCN clock gating 548 * 549 * @adev: amdgpu_device pointer 550 * 551 * Disable clock gating for VCN block 552 */ 553 static void vcn_v2_5_disable_clock_gating(struct amdgpu_device *adev) 554 { 555 uint32_t data; 556 int i; 557 558 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 559 if (adev->vcn.harvest_config & (1 << i)) 560 continue; 561 /* UVD disable CGC */ 562 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); 563 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 564 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 565 else 566 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 567 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 568 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 569 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); 570 571 data = RREG32_SOC15(VCN, i, mmUVD_CGC_GATE); 572 data &= ~(UVD_CGC_GATE__SYS_MASK 573 | UVD_CGC_GATE__UDEC_MASK 574 | UVD_CGC_GATE__MPEG2_MASK 575 | UVD_CGC_GATE__REGS_MASK 576 | UVD_CGC_GATE__RBC_MASK 577 | UVD_CGC_GATE__LMI_MC_MASK 578 | UVD_CGC_GATE__LMI_UMC_MASK 579 | UVD_CGC_GATE__IDCT_MASK 580 | UVD_CGC_GATE__MPRD_MASK 581 | UVD_CGC_GATE__MPC_MASK 582 | UVD_CGC_GATE__LBSI_MASK 583 | UVD_CGC_GATE__LRBBM_MASK 584 | UVD_CGC_GATE__UDEC_RE_MASK 585 | UVD_CGC_GATE__UDEC_CM_MASK 586 | UVD_CGC_GATE__UDEC_IT_MASK 587 | UVD_CGC_GATE__UDEC_DB_MASK 588 | UVD_CGC_GATE__UDEC_MP_MASK 589 | UVD_CGC_GATE__WCB_MASK 590 | UVD_CGC_GATE__VCPU_MASK 591 | UVD_CGC_GATE__MMSCH_MASK); 592 593 WREG32_SOC15(VCN, i, mmUVD_CGC_GATE, data); 594 595 SOC15_WAIT_ON_RREG(VCN, i, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); 596 597 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); 598 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 599 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 600 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 601 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 602 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 603 | UVD_CGC_CTRL__SYS_MODE_MASK 604 | UVD_CGC_CTRL__UDEC_MODE_MASK 605 | UVD_CGC_CTRL__MPEG2_MODE_MASK 606 | UVD_CGC_CTRL__REGS_MODE_MASK 607 | UVD_CGC_CTRL__RBC_MODE_MASK 608 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 609 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 610 | UVD_CGC_CTRL__IDCT_MODE_MASK 611 | UVD_CGC_CTRL__MPRD_MODE_MASK 612 | UVD_CGC_CTRL__MPC_MODE_MASK 613 | UVD_CGC_CTRL__LBSI_MODE_MASK 614 | UVD_CGC_CTRL__LRBBM_MODE_MASK 615 | UVD_CGC_CTRL__WCB_MODE_MASK 616 | UVD_CGC_CTRL__VCPU_MODE_MASK 617 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 618 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); 619 620 /* turn on */ 621 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE); 622 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 623 | UVD_SUVD_CGC_GATE__SIT_MASK 624 | UVD_SUVD_CGC_GATE__SMP_MASK 625 | UVD_SUVD_CGC_GATE__SCM_MASK 626 | UVD_SUVD_CGC_GATE__SDB_MASK 627 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 628 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 629 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 630 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 631 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 632 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 633 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 634 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 635 | UVD_SUVD_CGC_GATE__SCLR_MASK 636 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 637 | UVD_SUVD_CGC_GATE__ENT_MASK 638 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 639 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 640 | UVD_SUVD_CGC_GATE__SITE_MASK 641 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 642 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 643 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 644 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 645 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 646 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE, data); 647 648 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL); 649 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 650 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 651 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 652 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 653 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 654 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 655 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 656 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 657 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 658 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 659 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data); 660 } 661 } 662 663 static void vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_device *adev, 664 uint8_t sram_sel, int inst_idx, uint8_t indirect) 665 { 666 uint32_t reg_data = 0; 667 668 /* enable sw clock gating control */ 669 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 670 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 671 else 672 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 673 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 674 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 675 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 676 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 677 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 678 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 679 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 680 UVD_CGC_CTRL__SYS_MODE_MASK | 681 UVD_CGC_CTRL__UDEC_MODE_MASK | 682 UVD_CGC_CTRL__MPEG2_MODE_MASK | 683 UVD_CGC_CTRL__REGS_MODE_MASK | 684 UVD_CGC_CTRL__RBC_MODE_MASK | 685 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 686 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 687 UVD_CGC_CTRL__IDCT_MODE_MASK | 688 UVD_CGC_CTRL__MPRD_MODE_MASK | 689 UVD_CGC_CTRL__MPC_MODE_MASK | 690 UVD_CGC_CTRL__LBSI_MODE_MASK | 691 UVD_CGC_CTRL__LRBBM_MODE_MASK | 692 UVD_CGC_CTRL__WCB_MODE_MASK | 693 UVD_CGC_CTRL__VCPU_MODE_MASK | 694 UVD_CGC_CTRL__MMSCH_MODE_MASK); 695 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 696 VCN, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); 697 698 /* turn off clock gating */ 699 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 700 VCN, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect); 701 702 /* turn on SUVD clock gating */ 703 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 704 VCN, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 705 706 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 707 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 708 VCN, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 709 } 710 711 /** 712 * vcn_v2_5_enable_clock_gating - enable VCN clock gating 713 * 714 * @adev: amdgpu_device pointer 715 * 716 * Enable clock gating for VCN block 717 */ 718 static void vcn_v2_5_enable_clock_gating(struct amdgpu_device *adev) 719 { 720 uint32_t data = 0; 721 int i; 722 723 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 724 if (adev->vcn.harvest_config & (1 << i)) 725 continue; 726 /* enable UVD CGC */ 727 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); 728 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 729 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 730 else 731 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 732 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 733 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 734 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); 735 736 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); 737 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 738 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 739 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 740 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 741 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 742 | UVD_CGC_CTRL__SYS_MODE_MASK 743 | UVD_CGC_CTRL__UDEC_MODE_MASK 744 | UVD_CGC_CTRL__MPEG2_MODE_MASK 745 | UVD_CGC_CTRL__REGS_MODE_MASK 746 | UVD_CGC_CTRL__RBC_MODE_MASK 747 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 748 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 749 | UVD_CGC_CTRL__IDCT_MODE_MASK 750 | UVD_CGC_CTRL__MPRD_MODE_MASK 751 | UVD_CGC_CTRL__MPC_MODE_MASK 752 | UVD_CGC_CTRL__LBSI_MODE_MASK 753 | UVD_CGC_CTRL__LRBBM_MODE_MASK 754 | UVD_CGC_CTRL__WCB_MODE_MASK 755 | UVD_CGC_CTRL__VCPU_MODE_MASK); 756 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); 757 758 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL); 759 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 760 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 761 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 762 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 763 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 764 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 765 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 766 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 767 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 768 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 769 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data); 770 } 771 } 772 773 static void vcn_v2_6_enable_ras(struct amdgpu_device *adev, int inst_idx, 774 bool indirect) 775 { 776 uint32_t tmp; 777 778 if (adev->ip_versions[UVD_HWIP][0] != IP_VERSION(2, 6, 0)) 779 return; 780 781 tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK | 782 VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK | 783 VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK | 784 VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK; 785 WREG32_SOC15_DPG_MODE(inst_idx, 786 SOC15_DPG_MODE_OFFSET(VCN, 0, mmVCN_RAS_CNTL), 787 tmp, 0, indirect); 788 789 tmp = UVD_VCPU_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK; 790 WREG32_SOC15_DPG_MODE(inst_idx, 791 SOC15_DPG_MODE_OFFSET(VCN, 0, mmUVD_VCPU_INT_EN), 792 tmp, 0, indirect); 793 794 tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK; 795 WREG32_SOC15_DPG_MODE(inst_idx, 796 SOC15_DPG_MODE_OFFSET(VCN, 0, mmUVD_SYS_INT_EN), 797 tmp, 0, indirect); 798 } 799 800 static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 801 { 802 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 803 struct amdgpu_ring *ring; 804 uint32_t rb_bufsz, tmp; 805 806 /* disable register anti-hang mechanism */ 807 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1, 808 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 809 /* enable dynamic power gating mode */ 810 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS); 811 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 812 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 813 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp); 814 815 if (indirect) 816 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 817 818 /* enable clock gating */ 819 vcn_v2_5_clock_gating_dpg_mode(adev, 0, inst_idx, indirect); 820 821 /* enable VCPU clock */ 822 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 823 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 824 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK; 825 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 826 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); 827 828 /* disable master interupt */ 829 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 830 VCN, 0, mmUVD_MASTINT_EN), 0, 0, indirect); 831 832 /* setup mmUVD_LMI_CTRL */ 833 tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 834 UVD_LMI_CTRL__REQ_MODE_MASK | 835 UVD_LMI_CTRL__CRC_RESET_MASK | 836 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 837 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 838 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 839 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 840 0x00100000L); 841 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 842 VCN, 0, mmUVD_LMI_CTRL), tmp, 0, indirect); 843 844 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 845 VCN, 0, mmUVD_MPC_CNTL), 846 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 847 848 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 849 VCN, 0, mmUVD_MPC_SET_MUXA0), 850 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 851 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 852 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 853 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 854 855 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 856 VCN, 0, mmUVD_MPC_SET_MUXB0), 857 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 858 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 859 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 860 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 861 862 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 863 VCN, 0, mmUVD_MPC_SET_MUX), 864 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 865 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 866 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 867 868 vcn_v2_5_mc_resume_dpg_mode(adev, inst_idx, indirect); 869 870 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 871 VCN, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect); 872 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 873 VCN, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect); 874 875 /* enable LMI MC and UMC channels */ 876 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 877 VCN, 0, mmUVD_LMI_CTRL2), 0, 0, indirect); 878 879 vcn_v2_6_enable_ras(adev, inst_idx, indirect); 880 881 /* unblock VCPU register access */ 882 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 883 VCN, 0, mmUVD_RB_ARB_CTRL), 0, 0, indirect); 884 885 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 886 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 887 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 888 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); 889 890 /* enable master interrupt */ 891 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 892 VCN, 0, mmUVD_MASTINT_EN), 893 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 894 895 if (indirect) 896 psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, 897 (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr - 898 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr)); 899 900 ring = &adev->vcn.inst[inst_idx].ring_dec; 901 /* force RBC into idle state */ 902 rb_bufsz = order_base_2(ring->ring_size); 903 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 904 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 905 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 906 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 907 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 908 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp); 909 910 /* Stall DPG before WPTR/RPTR reset */ 911 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 912 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 913 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 914 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET; 915 916 /* set the write pointer delay */ 917 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0); 918 919 /* set the wb address */ 920 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR, 921 (upper_32_bits(ring->gpu_addr) >> 2)); 922 923 /* program the RB_BASE for ring buffer */ 924 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 925 lower_32_bits(ring->gpu_addr)); 926 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 927 upper_32_bits(ring->gpu_addr)); 928 929 /* Initialize the ring buffer's read and write pointers */ 930 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0); 931 932 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0); 933 934 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR); 935 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, 936 lower_32_bits(ring->wptr)); 937 938 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET; 939 /* Unstall DPG */ 940 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 941 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 942 943 return 0; 944 } 945 946 static int vcn_v2_5_start(struct amdgpu_device *adev) 947 { 948 struct amdgpu_ring *ring; 949 uint32_t rb_bufsz, tmp; 950 int i, j, k, r; 951 952 if (adev->pm.dpm_enabled) 953 amdgpu_dpm_enable_uvd(adev, true); 954 955 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 956 if (adev->vcn.harvest_config & (1 << i)) 957 continue; 958 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 959 r = vcn_v2_5_start_dpg_mode(adev, i, adev->vcn.indirect_sram); 960 continue; 961 } 962 963 /* disable register anti-hang mechanism */ 964 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), 0, 965 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 966 967 /* set uvd status busy */ 968 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 969 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp); 970 } 971 972 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 973 return 0; 974 975 /*SW clock gating */ 976 vcn_v2_5_disable_clock_gating(adev); 977 978 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 979 if (adev->vcn.harvest_config & (1 << i)) 980 continue; 981 /* enable VCPU clock */ 982 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 983 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 984 985 /* disable master interrupt */ 986 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0, 987 ~UVD_MASTINT_EN__VCPU_EN_MASK); 988 989 /* setup mmUVD_LMI_CTRL */ 990 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL); 991 tmp &= ~0xff; 992 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | 0x8| 993 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 994 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 995 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 996 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 997 998 /* setup mmUVD_MPC_CNTL */ 999 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL); 1000 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1001 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1002 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp); 1003 1004 /* setup UVD_MPC_SET_MUXA0 */ 1005 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0, 1006 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1007 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1008 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1009 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1010 1011 /* setup UVD_MPC_SET_MUXB0 */ 1012 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0, 1013 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1014 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1015 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1016 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1017 1018 /* setup mmUVD_MPC_SET_MUX */ 1019 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX, 1020 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1021 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1022 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1023 } 1024 1025 vcn_v2_5_mc_resume(adev); 1026 1027 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1028 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1029 if (adev->vcn.harvest_config & (1 << i)) 1030 continue; 1031 /* VCN global tiling registers */ 1032 WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG, 1033 adev->gfx.config.gb_addr_config); 1034 WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG, 1035 adev->gfx.config.gb_addr_config); 1036 1037 /* enable LMI MC and UMC channels */ 1038 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0, 1039 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1040 1041 /* unblock VCPU register access */ 1042 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0, 1043 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1044 1045 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1046 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1047 1048 for (k = 0; k < 10; ++k) { 1049 uint32_t status; 1050 1051 for (j = 0; j < 100; ++j) { 1052 status = RREG32_SOC15(VCN, i, mmUVD_STATUS); 1053 if (status & 2) 1054 break; 1055 if (amdgpu_emu_mode == 1) 1056 msleep(500); 1057 else 1058 mdelay(10); 1059 } 1060 r = 0; 1061 if (status & 2) 1062 break; 1063 1064 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n"); 1065 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1066 UVD_VCPU_CNTL__BLK_RST_MASK, 1067 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1068 mdelay(10); 1069 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1070 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1071 1072 mdelay(10); 1073 r = -1; 1074 } 1075 1076 if (r) { 1077 DRM_ERROR("VCN decode not responding, giving up!!!\n"); 1078 return r; 1079 } 1080 1081 /* enable master interrupt */ 1082 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 1083 UVD_MASTINT_EN__VCPU_EN_MASK, 1084 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1085 1086 /* clear the busy bit of VCN_STATUS */ 1087 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0, 1088 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1089 1090 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0); 1091 1092 ring = &adev->vcn.inst[i].ring_dec; 1093 /* force RBC into idle state */ 1094 rb_bufsz = order_base_2(ring->ring_size); 1095 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1096 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1097 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1098 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1099 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1100 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp); 1101 1102 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET; 1103 /* program the RB_BASE for ring buffer */ 1104 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1105 lower_32_bits(ring->gpu_addr)); 1106 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1107 upper_32_bits(ring->gpu_addr)); 1108 1109 /* Initialize the ring buffer's read and write pointers */ 1110 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0); 1111 1112 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR); 1113 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR, 1114 lower_32_bits(ring->wptr)); 1115 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET; 1116 1117 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET; 1118 ring = &adev->vcn.inst[i].ring_enc[0]; 1119 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1120 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1121 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr); 1122 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1123 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4); 1124 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET; 1125 1126 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET; 1127 ring = &adev->vcn.inst[i].ring_enc[1]; 1128 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1129 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1130 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1131 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1132 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4); 1133 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET; 1134 } 1135 1136 return 0; 1137 } 1138 1139 static int vcn_v2_5_mmsch_start(struct amdgpu_device *adev, 1140 struct amdgpu_mm_table *table) 1141 { 1142 uint32_t data = 0, loop = 0, size = 0; 1143 uint64_t addr = table->gpu_addr; 1144 struct mmsch_v1_1_init_header *header = NULL; 1145 1146 header = (struct mmsch_v1_1_init_header *)table->cpu_addr; 1147 size = header->total_size; 1148 1149 /* 1150 * 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr of 1151 * memory descriptor location 1152 */ 1153 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr)); 1154 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr)); 1155 1156 /* 2, update vmid of descriptor */ 1157 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID); 1158 data &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1159 /* use domain0 for MM scheduler */ 1160 data |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1161 WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, data); 1162 1163 /* 3, notify mmsch about the size of this descriptor */ 1164 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size); 1165 1166 /* 4, set resp to zero */ 1167 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0); 1168 1169 /* 1170 * 5, kick off the initialization and wait until 1171 * VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero 1172 */ 1173 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, 0x10000001); 1174 1175 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); 1176 loop = 10; 1177 while ((data & 0x10000002) != 0x10000002) { 1178 udelay(100); 1179 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); 1180 loop--; 1181 if (!loop) 1182 break; 1183 } 1184 1185 if (!loop) { 1186 dev_err(adev->dev, 1187 "failed to init MMSCH, mmMMSCH_VF_MAILBOX_RESP = %x\n", 1188 data); 1189 return -EBUSY; 1190 } 1191 1192 return 0; 1193 } 1194 1195 static int vcn_v2_5_sriov_start(struct amdgpu_device *adev) 1196 { 1197 struct amdgpu_ring *ring; 1198 uint32_t offset, size, tmp, i, rb_bufsz; 1199 uint32_t table_size = 0; 1200 struct mmsch_v1_0_cmd_direct_write direct_wt = { { 0 } }; 1201 struct mmsch_v1_0_cmd_direct_read_modify_write direct_rd_mod_wt = { { 0 } }; 1202 struct mmsch_v1_0_cmd_end end = { { 0 } }; 1203 uint32_t *init_table = adev->virt.mm_table.cpu_addr; 1204 struct mmsch_v1_1_init_header *header = (struct mmsch_v1_1_init_header *)init_table; 1205 1206 direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE; 1207 direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1208 end.cmd_header.command_type = MMSCH_COMMAND__END; 1209 1210 header->version = MMSCH_VERSION; 1211 header->total_size = sizeof(struct mmsch_v1_1_init_header) >> 2; 1212 init_table += header->total_size; 1213 1214 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1215 header->eng[i].table_offset = header->total_size; 1216 header->eng[i].init_status = 0; 1217 header->eng[i].table_size = 0; 1218 1219 table_size = 0; 1220 1221 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT( 1222 SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 1223 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 1224 1225 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 1226 /* mc resume*/ 1227 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1228 MMSCH_V1_0_INSERT_DIRECT_WT( 1229 SOC15_REG_OFFSET(VCN, i, 1230 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1231 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo); 1232 MMSCH_V1_0_INSERT_DIRECT_WT( 1233 SOC15_REG_OFFSET(VCN, i, 1234 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1235 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi); 1236 offset = 0; 1237 MMSCH_V1_0_INSERT_DIRECT_WT( 1238 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0), 0); 1239 } else { 1240 MMSCH_V1_0_INSERT_DIRECT_WT( 1241 SOC15_REG_OFFSET(VCN, i, 1242 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1243 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 1244 MMSCH_V1_0_INSERT_DIRECT_WT( 1245 SOC15_REG_OFFSET(VCN, i, 1246 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1247 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 1248 offset = size; 1249 MMSCH_V1_0_INSERT_DIRECT_WT( 1250 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0), 1251 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 1252 } 1253 1254 MMSCH_V1_0_INSERT_DIRECT_WT( 1255 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE0), 1256 size); 1257 MMSCH_V1_0_INSERT_DIRECT_WT( 1258 SOC15_REG_OFFSET(VCN, i, 1259 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 1260 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset)); 1261 MMSCH_V1_0_INSERT_DIRECT_WT( 1262 SOC15_REG_OFFSET(VCN, i, 1263 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 1264 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset)); 1265 MMSCH_V1_0_INSERT_DIRECT_WT( 1266 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET1), 1267 0); 1268 MMSCH_V1_0_INSERT_DIRECT_WT( 1269 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE1), 1270 AMDGPU_VCN_STACK_SIZE); 1271 MMSCH_V1_0_INSERT_DIRECT_WT( 1272 SOC15_REG_OFFSET(VCN, i, 1273 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 1274 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + 1275 AMDGPU_VCN_STACK_SIZE)); 1276 MMSCH_V1_0_INSERT_DIRECT_WT( 1277 SOC15_REG_OFFSET(VCN, i, 1278 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 1279 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + 1280 AMDGPU_VCN_STACK_SIZE)); 1281 MMSCH_V1_0_INSERT_DIRECT_WT( 1282 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET2), 1283 0); 1284 MMSCH_V1_0_INSERT_DIRECT_WT( 1285 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE2), 1286 AMDGPU_VCN_CONTEXT_SIZE); 1287 1288 ring = &adev->vcn.inst[i].ring_enc[0]; 1289 ring->wptr = 0; 1290 1291 MMSCH_V1_0_INSERT_DIRECT_WT( 1292 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_LO), 1293 lower_32_bits(ring->gpu_addr)); 1294 MMSCH_V1_0_INSERT_DIRECT_WT( 1295 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_HI), 1296 upper_32_bits(ring->gpu_addr)); 1297 MMSCH_V1_0_INSERT_DIRECT_WT( 1298 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_SIZE), 1299 ring->ring_size / 4); 1300 1301 ring = &adev->vcn.inst[i].ring_dec; 1302 ring->wptr = 0; 1303 MMSCH_V1_0_INSERT_DIRECT_WT( 1304 SOC15_REG_OFFSET(VCN, i, 1305 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW), 1306 lower_32_bits(ring->gpu_addr)); 1307 MMSCH_V1_0_INSERT_DIRECT_WT( 1308 SOC15_REG_OFFSET(VCN, i, 1309 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH), 1310 upper_32_bits(ring->gpu_addr)); 1311 1312 /* force RBC into idle state */ 1313 rb_bufsz = order_base_2(ring->ring_size); 1314 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1315 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1316 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1317 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1318 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1319 MMSCH_V1_0_INSERT_DIRECT_WT( 1320 SOC15_REG_OFFSET(VCN, i, mmUVD_RBC_RB_CNTL), tmp); 1321 1322 /* add end packet */ 1323 memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end)); 1324 table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4; 1325 init_table += sizeof(struct mmsch_v1_0_cmd_end) / 4; 1326 1327 /* refine header */ 1328 header->eng[i].table_size = table_size; 1329 header->total_size += table_size; 1330 } 1331 1332 return vcn_v2_5_mmsch_start(adev, &adev->virt.mm_table); 1333 } 1334 1335 static int vcn_v2_5_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) 1336 { 1337 uint32_t tmp; 1338 1339 /* Wait for power status to be 1 */ 1340 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1341 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1342 1343 /* wait for read ptr to be equal to write ptr */ 1344 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR); 1345 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1346 1347 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2); 1348 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); 1349 1350 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1351 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); 1352 1353 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1354 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1355 1356 /* disable dynamic power gating mode */ 1357 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0, 1358 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1359 1360 return 0; 1361 } 1362 1363 static int vcn_v2_5_stop(struct amdgpu_device *adev) 1364 { 1365 uint32_t tmp; 1366 int i, r = 0; 1367 1368 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1369 if (adev->vcn.harvest_config & (1 << i)) 1370 continue; 1371 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1372 r = vcn_v2_5_stop_dpg_mode(adev, i); 1373 continue; 1374 } 1375 1376 /* wait for vcn idle */ 1377 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1378 if (r) 1379 return r; 1380 1381 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1382 UVD_LMI_STATUS__READ_CLEAN_MASK | 1383 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1384 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1385 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1386 if (r) 1387 return r; 1388 1389 /* block LMI UMC channel */ 1390 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2); 1391 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1392 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp); 1393 1394 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK| 1395 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1396 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1397 if (r) 1398 return r; 1399 1400 /* block VCPU register access */ 1401 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 1402 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1403 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1404 1405 /* reset VCPU */ 1406 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1407 UVD_VCPU_CNTL__BLK_RST_MASK, 1408 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1409 1410 /* disable VCPU clock */ 1411 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1412 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1413 1414 /* clear status */ 1415 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0); 1416 1417 vcn_v2_5_enable_clock_gating(adev); 1418 1419 /* enable register anti-hang mechanism */ 1420 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), 1421 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, 1422 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1423 } 1424 1425 if (adev->pm.dpm_enabled) 1426 amdgpu_dpm_enable_uvd(adev, false); 1427 1428 return 0; 1429 } 1430 1431 static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev, 1432 int inst_idx, struct dpg_pause_state *new_state) 1433 { 1434 struct amdgpu_ring *ring; 1435 uint32_t reg_data = 0; 1436 int ret_code = 0; 1437 1438 /* pause/unpause if state is changed */ 1439 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1440 DRM_DEBUG("dpg pause state changed %d -> %d", 1441 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1442 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) & 1443 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1444 1445 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1446 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, 1447 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1448 1449 if (!ret_code) { 1450 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 1451 1452 /* pause DPG */ 1453 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1454 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1455 1456 /* wait for ACK */ 1457 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE, 1458 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1459 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1460 1461 /* Stall DPG before WPTR/RPTR reset */ 1462 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1463 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1464 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1465 1466 /* Restore */ 1467 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET; 1468 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 1469 ring->wptr = 0; 1470 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr); 1471 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1472 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4); 1473 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1474 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1475 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET; 1476 1477 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET; 1478 ring = &adev->vcn.inst[inst_idx].ring_enc[1]; 1479 ring->wptr = 0; 1480 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1481 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1482 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4); 1483 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1484 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1485 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET; 1486 1487 /* Unstall DPG */ 1488 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1489 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1490 1491 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1492 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1493 } 1494 } else { 1495 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1496 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1497 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, 1498 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1499 } 1500 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1501 } 1502 1503 return 0; 1504 } 1505 1506 /** 1507 * vcn_v2_5_dec_ring_get_rptr - get read pointer 1508 * 1509 * @ring: amdgpu_ring pointer 1510 * 1511 * Returns the current hardware read pointer 1512 */ 1513 static uint64_t vcn_v2_5_dec_ring_get_rptr(struct amdgpu_ring *ring) 1514 { 1515 struct amdgpu_device *adev = ring->adev; 1516 1517 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR); 1518 } 1519 1520 /** 1521 * vcn_v2_5_dec_ring_get_wptr - get write pointer 1522 * 1523 * @ring: amdgpu_ring pointer 1524 * 1525 * Returns the current hardware write pointer 1526 */ 1527 static uint64_t vcn_v2_5_dec_ring_get_wptr(struct amdgpu_ring *ring) 1528 { 1529 struct amdgpu_device *adev = ring->adev; 1530 1531 if (ring->use_doorbell) 1532 return *ring->wptr_cpu_addr; 1533 else 1534 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR); 1535 } 1536 1537 /** 1538 * vcn_v2_5_dec_ring_set_wptr - set write pointer 1539 * 1540 * @ring: amdgpu_ring pointer 1541 * 1542 * Commits the write pointer to the hardware 1543 */ 1544 static void vcn_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring) 1545 { 1546 struct amdgpu_device *adev = ring->adev; 1547 1548 if (ring->use_doorbell) { 1549 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1550 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1551 } else { 1552 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1553 } 1554 } 1555 1556 static const struct amdgpu_ring_funcs vcn_v2_5_dec_ring_vm_funcs = { 1557 .type = AMDGPU_RING_TYPE_VCN_DEC, 1558 .align_mask = 0xf, 1559 .secure_submission_supported = true, 1560 .vmhub = AMDGPU_MMHUB_1, 1561 .get_rptr = vcn_v2_5_dec_ring_get_rptr, 1562 .get_wptr = vcn_v2_5_dec_ring_get_wptr, 1563 .set_wptr = vcn_v2_5_dec_ring_set_wptr, 1564 .emit_frame_size = 1565 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1566 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1567 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */ 1568 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */ 1569 6, 1570 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */ 1571 .emit_ib = vcn_v2_0_dec_ring_emit_ib, 1572 .emit_fence = vcn_v2_0_dec_ring_emit_fence, 1573 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush, 1574 .test_ring = vcn_v2_0_dec_ring_test_ring, 1575 .test_ib = amdgpu_vcn_dec_ring_test_ib, 1576 .insert_nop = vcn_v2_0_dec_ring_insert_nop, 1577 .insert_start = vcn_v2_0_dec_ring_insert_start, 1578 .insert_end = vcn_v2_0_dec_ring_insert_end, 1579 .pad_ib = amdgpu_ring_generic_pad_ib, 1580 .begin_use = amdgpu_vcn_ring_begin_use, 1581 .end_use = amdgpu_vcn_ring_end_use, 1582 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg, 1583 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait, 1584 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1585 }; 1586 1587 static const struct amdgpu_ring_funcs vcn_v2_6_dec_ring_vm_funcs = { 1588 .type = AMDGPU_RING_TYPE_VCN_DEC, 1589 .align_mask = 0xf, 1590 .secure_submission_supported = true, 1591 .vmhub = AMDGPU_MMHUB_0, 1592 .get_rptr = vcn_v2_5_dec_ring_get_rptr, 1593 .get_wptr = vcn_v2_5_dec_ring_get_wptr, 1594 .set_wptr = vcn_v2_5_dec_ring_set_wptr, 1595 .emit_frame_size = 1596 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1597 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1598 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */ 1599 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */ 1600 6, 1601 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */ 1602 .emit_ib = vcn_v2_0_dec_ring_emit_ib, 1603 .emit_fence = vcn_v2_0_dec_ring_emit_fence, 1604 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush, 1605 .test_ring = vcn_v2_0_dec_ring_test_ring, 1606 .test_ib = amdgpu_vcn_dec_ring_test_ib, 1607 .insert_nop = vcn_v2_0_dec_ring_insert_nop, 1608 .insert_start = vcn_v2_0_dec_ring_insert_start, 1609 .insert_end = vcn_v2_0_dec_ring_insert_end, 1610 .pad_ib = amdgpu_ring_generic_pad_ib, 1611 .begin_use = amdgpu_vcn_ring_begin_use, 1612 .end_use = amdgpu_vcn_ring_end_use, 1613 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg, 1614 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait, 1615 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1616 }; 1617 1618 /** 1619 * vcn_v2_5_enc_ring_get_rptr - get enc read pointer 1620 * 1621 * @ring: amdgpu_ring pointer 1622 * 1623 * Returns the current hardware enc read pointer 1624 */ 1625 static uint64_t vcn_v2_5_enc_ring_get_rptr(struct amdgpu_ring *ring) 1626 { 1627 struct amdgpu_device *adev = ring->adev; 1628 1629 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) 1630 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR); 1631 else 1632 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2); 1633 } 1634 1635 /** 1636 * vcn_v2_5_enc_ring_get_wptr - get enc write pointer 1637 * 1638 * @ring: amdgpu_ring pointer 1639 * 1640 * Returns the current hardware enc write pointer 1641 */ 1642 static uint64_t vcn_v2_5_enc_ring_get_wptr(struct amdgpu_ring *ring) 1643 { 1644 struct amdgpu_device *adev = ring->adev; 1645 1646 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 1647 if (ring->use_doorbell) 1648 return *ring->wptr_cpu_addr; 1649 else 1650 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR); 1651 } else { 1652 if (ring->use_doorbell) 1653 return *ring->wptr_cpu_addr; 1654 else 1655 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2); 1656 } 1657 } 1658 1659 /** 1660 * vcn_v2_5_enc_ring_set_wptr - set enc write pointer 1661 * 1662 * @ring: amdgpu_ring pointer 1663 * 1664 * Commits the enc write pointer to the hardware 1665 */ 1666 static void vcn_v2_5_enc_ring_set_wptr(struct amdgpu_ring *ring) 1667 { 1668 struct amdgpu_device *adev = ring->adev; 1669 1670 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 1671 if (ring->use_doorbell) { 1672 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1673 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1674 } else { 1675 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1676 } 1677 } else { 1678 if (ring->use_doorbell) { 1679 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1680 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1681 } else { 1682 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1683 } 1684 } 1685 } 1686 1687 static const struct amdgpu_ring_funcs vcn_v2_5_enc_ring_vm_funcs = { 1688 .type = AMDGPU_RING_TYPE_VCN_ENC, 1689 .align_mask = 0x3f, 1690 .nop = VCN_ENC_CMD_NO_OP, 1691 .vmhub = AMDGPU_MMHUB_1, 1692 .get_rptr = vcn_v2_5_enc_ring_get_rptr, 1693 .get_wptr = vcn_v2_5_enc_ring_get_wptr, 1694 .set_wptr = vcn_v2_5_enc_ring_set_wptr, 1695 .emit_frame_size = 1696 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1697 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1698 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1699 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1700 1, /* vcn_v2_0_enc_ring_insert_end */ 1701 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1702 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1703 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1704 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 1705 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1706 .test_ib = amdgpu_vcn_enc_ring_test_ib, 1707 .insert_nop = amdgpu_ring_insert_nop, 1708 .insert_end = vcn_v2_0_enc_ring_insert_end, 1709 .pad_ib = amdgpu_ring_generic_pad_ib, 1710 .begin_use = amdgpu_vcn_ring_begin_use, 1711 .end_use = amdgpu_vcn_ring_end_use, 1712 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 1713 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 1714 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1715 }; 1716 1717 static const struct amdgpu_ring_funcs vcn_v2_6_enc_ring_vm_funcs = { 1718 .type = AMDGPU_RING_TYPE_VCN_ENC, 1719 .align_mask = 0x3f, 1720 .nop = VCN_ENC_CMD_NO_OP, 1721 .vmhub = AMDGPU_MMHUB_0, 1722 .get_rptr = vcn_v2_5_enc_ring_get_rptr, 1723 .get_wptr = vcn_v2_5_enc_ring_get_wptr, 1724 .set_wptr = vcn_v2_5_enc_ring_set_wptr, 1725 .emit_frame_size = 1726 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1727 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1728 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1729 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1730 1, /* vcn_v2_0_enc_ring_insert_end */ 1731 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1732 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1733 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1734 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 1735 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1736 .test_ib = amdgpu_vcn_enc_ring_test_ib, 1737 .insert_nop = amdgpu_ring_insert_nop, 1738 .insert_end = vcn_v2_0_enc_ring_insert_end, 1739 .pad_ib = amdgpu_ring_generic_pad_ib, 1740 .begin_use = amdgpu_vcn_ring_begin_use, 1741 .end_use = amdgpu_vcn_ring_end_use, 1742 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 1743 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 1744 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1745 }; 1746 1747 static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev) 1748 { 1749 int i; 1750 1751 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1752 if (adev->vcn.harvest_config & (1 << i)) 1753 continue; 1754 if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(2, 5, 0)) 1755 adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs; 1756 else /* CHIP_ALDEBARAN */ 1757 adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_6_dec_ring_vm_funcs; 1758 adev->vcn.inst[i].ring_dec.me = i; 1759 DRM_INFO("VCN(%d) decode is enabled in VM mode\n", i); 1760 } 1761 } 1762 1763 static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev) 1764 { 1765 int i, j; 1766 1767 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 1768 if (adev->vcn.harvest_config & (1 << j)) 1769 continue; 1770 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 1771 if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(2, 5, 0)) 1772 adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs; 1773 else /* CHIP_ALDEBARAN */ 1774 adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_6_enc_ring_vm_funcs; 1775 adev->vcn.inst[j].ring_enc[i].me = j; 1776 } 1777 DRM_INFO("VCN(%d) encode is enabled in VM mode\n", j); 1778 } 1779 } 1780 1781 static bool vcn_v2_5_is_idle(void *handle) 1782 { 1783 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1784 int i, ret = 1; 1785 1786 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1787 if (adev->vcn.harvest_config & (1 << i)) 1788 continue; 1789 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); 1790 } 1791 1792 return ret; 1793 } 1794 1795 static int vcn_v2_5_wait_for_idle(void *handle) 1796 { 1797 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1798 int i, ret = 0; 1799 1800 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1801 if (adev->vcn.harvest_config & (1 << i)) 1802 continue; 1803 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 1804 UVD_STATUS__IDLE); 1805 if (ret) 1806 return ret; 1807 } 1808 1809 return ret; 1810 } 1811 1812 static int vcn_v2_5_set_clockgating_state(void *handle, 1813 enum amd_clockgating_state state) 1814 { 1815 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1816 bool enable = (state == AMD_CG_STATE_GATE); 1817 1818 if (amdgpu_sriov_vf(adev)) 1819 return 0; 1820 1821 if (enable) { 1822 if (!vcn_v2_5_is_idle(handle)) 1823 return -EBUSY; 1824 vcn_v2_5_enable_clock_gating(adev); 1825 } else { 1826 vcn_v2_5_disable_clock_gating(adev); 1827 } 1828 1829 return 0; 1830 } 1831 1832 static int vcn_v2_5_set_powergating_state(void *handle, 1833 enum amd_powergating_state state) 1834 { 1835 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1836 int ret; 1837 1838 if (amdgpu_sriov_vf(adev)) 1839 return 0; 1840 1841 if(state == adev->vcn.cur_state) 1842 return 0; 1843 1844 if (state == AMD_PG_STATE_GATE) 1845 ret = vcn_v2_5_stop(adev); 1846 else 1847 ret = vcn_v2_5_start(adev); 1848 1849 if(!ret) 1850 adev->vcn.cur_state = state; 1851 1852 return ret; 1853 } 1854 1855 static int vcn_v2_5_set_interrupt_state(struct amdgpu_device *adev, 1856 struct amdgpu_irq_src *source, 1857 unsigned type, 1858 enum amdgpu_interrupt_state state) 1859 { 1860 return 0; 1861 } 1862 1863 static int vcn_v2_5_process_interrupt(struct amdgpu_device *adev, 1864 struct amdgpu_irq_src *source, 1865 struct amdgpu_iv_entry *entry) 1866 { 1867 uint32_t ip_instance; 1868 1869 switch (entry->client_id) { 1870 case SOC15_IH_CLIENTID_VCN: 1871 ip_instance = 0; 1872 break; 1873 case SOC15_IH_CLIENTID_VCN1: 1874 ip_instance = 1; 1875 break; 1876 default: 1877 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 1878 return 0; 1879 } 1880 1881 DRM_DEBUG("IH: VCN TRAP\n"); 1882 1883 switch (entry->src_id) { 1884 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT: 1885 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec); 1886 break; 1887 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1888 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 1889 break; 1890 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY: 1891 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]); 1892 break; 1893 case VCN_2_6__SRCID_UVD_POISON: 1894 amdgpu_vcn_process_poison_irq(adev, source, entry); 1895 break; 1896 default: 1897 DRM_ERROR("Unhandled interrupt: %d %d\n", 1898 entry->src_id, entry->src_data[0]); 1899 break; 1900 } 1901 1902 return 0; 1903 } 1904 1905 static const struct amdgpu_irq_src_funcs vcn_v2_5_irq_funcs = { 1906 .set = vcn_v2_5_set_interrupt_state, 1907 .process = vcn_v2_5_process_interrupt, 1908 }; 1909 1910 static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev) 1911 { 1912 int i; 1913 1914 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1915 if (adev->vcn.harvest_config & (1 << i)) 1916 continue; 1917 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1; 1918 adev->vcn.inst[i].irq.funcs = &vcn_v2_5_irq_funcs; 1919 } 1920 } 1921 1922 static const struct amd_ip_funcs vcn_v2_5_ip_funcs = { 1923 .name = "vcn_v2_5", 1924 .early_init = vcn_v2_5_early_init, 1925 .late_init = NULL, 1926 .sw_init = vcn_v2_5_sw_init, 1927 .sw_fini = vcn_v2_5_sw_fini, 1928 .hw_init = vcn_v2_5_hw_init, 1929 .hw_fini = vcn_v2_5_hw_fini, 1930 .suspend = vcn_v2_5_suspend, 1931 .resume = vcn_v2_5_resume, 1932 .is_idle = vcn_v2_5_is_idle, 1933 .wait_for_idle = vcn_v2_5_wait_for_idle, 1934 .check_soft_reset = NULL, 1935 .pre_soft_reset = NULL, 1936 .soft_reset = NULL, 1937 .post_soft_reset = NULL, 1938 .set_clockgating_state = vcn_v2_5_set_clockgating_state, 1939 .set_powergating_state = vcn_v2_5_set_powergating_state, 1940 }; 1941 1942 static const struct amd_ip_funcs vcn_v2_6_ip_funcs = { 1943 .name = "vcn_v2_6", 1944 .early_init = vcn_v2_5_early_init, 1945 .late_init = NULL, 1946 .sw_init = vcn_v2_5_sw_init, 1947 .sw_fini = vcn_v2_5_sw_fini, 1948 .hw_init = vcn_v2_5_hw_init, 1949 .hw_fini = vcn_v2_5_hw_fini, 1950 .suspend = vcn_v2_5_suspend, 1951 .resume = vcn_v2_5_resume, 1952 .is_idle = vcn_v2_5_is_idle, 1953 .wait_for_idle = vcn_v2_5_wait_for_idle, 1954 .check_soft_reset = NULL, 1955 .pre_soft_reset = NULL, 1956 .soft_reset = NULL, 1957 .post_soft_reset = NULL, 1958 .set_clockgating_state = vcn_v2_5_set_clockgating_state, 1959 .set_powergating_state = vcn_v2_5_set_powergating_state, 1960 }; 1961 1962 const struct amdgpu_ip_block_version vcn_v2_5_ip_block = 1963 { 1964 .type = AMD_IP_BLOCK_TYPE_VCN, 1965 .major = 2, 1966 .minor = 5, 1967 .rev = 0, 1968 .funcs = &vcn_v2_5_ip_funcs, 1969 }; 1970 1971 const struct amdgpu_ip_block_version vcn_v2_6_ip_block = 1972 { 1973 .type = AMD_IP_BLOCK_TYPE_VCN, 1974 .major = 2, 1975 .minor = 6, 1976 .rev = 0, 1977 .funcs = &vcn_v2_6_ip_funcs, 1978 }; 1979 1980 static uint32_t vcn_v2_6_query_poison_by_instance(struct amdgpu_device *adev, 1981 uint32_t instance, uint32_t sub_block) 1982 { 1983 uint32_t poison_stat = 0, reg_value = 0; 1984 1985 switch (sub_block) { 1986 case AMDGPU_VCN_V2_6_VCPU_VCODEC: 1987 reg_value = RREG32_SOC15(VCN, instance, mmUVD_RAS_VCPU_VCODEC_STATUS); 1988 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF); 1989 break; 1990 default: 1991 break; 1992 } 1993 1994 if (poison_stat) 1995 dev_info(adev->dev, "Poison detected in VCN%d, sub_block%d\n", 1996 instance, sub_block); 1997 1998 return poison_stat; 1999 } 2000 2001 static bool vcn_v2_6_query_poison_status(struct amdgpu_device *adev) 2002 { 2003 uint32_t inst, sub; 2004 uint32_t poison_stat = 0; 2005 2006 for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++) 2007 for (sub = 0; sub < AMDGPU_VCN_V2_6_MAX_SUB_BLOCK; sub++) 2008 poison_stat += 2009 vcn_v2_6_query_poison_by_instance(adev, inst, sub); 2010 2011 return !!poison_stat; 2012 } 2013 2014 const struct amdgpu_ras_block_hw_ops vcn_v2_6_ras_hw_ops = { 2015 .query_poison_status = vcn_v2_6_query_poison_status, 2016 }; 2017 2018 static struct amdgpu_vcn_ras vcn_v2_6_ras = { 2019 .ras_block = { 2020 .hw_ops = &vcn_v2_6_ras_hw_ops, 2021 }, 2022 }; 2023 2024 static void vcn_v2_5_set_ras_funcs(struct amdgpu_device *adev) 2025 { 2026 switch (adev->ip_versions[VCN_HWIP][0]) { 2027 case IP_VERSION(2, 6, 0): 2028 adev->vcn.ras = &vcn_v2_6_ras; 2029 break; 2030 default: 2031 break; 2032 } 2033 2034 amdgpu_vcn_set_ras_funcs(adev); 2035 } 2036