1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_vcn.h" 28 #include "amdgpu_pm.h" 29 #include "soc15.h" 30 #include "soc15d.h" 31 #include "vcn_v2_0.h" 32 #include "mmsch_v1_0.h" 33 34 #include "vcn/vcn_2_5_offset.h" 35 #include "vcn/vcn_2_5_sh_mask.h" 36 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 37 38 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x27 39 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x0f 40 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x10 41 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x11 42 #define mmUVD_NO_OP_INTERNAL_OFFSET 0x29 43 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x66 44 #define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d 45 46 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x431 47 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x3b4 48 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x3b5 49 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x25c 50 51 #define VCN25_MAX_HW_INSTANCES_ARCTURUS 2 52 53 static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev); 54 static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev); 55 static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev); 56 static int vcn_v2_5_set_powergating_state(void *handle, 57 enum amd_powergating_state state); 58 static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev, 59 int inst_idx, struct dpg_pause_state *new_state); 60 static int vcn_v2_5_sriov_start(struct amdgpu_device *adev); 61 62 static int amdgpu_ih_clientid_vcns[] = { 63 SOC15_IH_CLIENTID_VCN, 64 SOC15_IH_CLIENTID_VCN1 65 }; 66 67 /** 68 * vcn_v2_5_early_init - set function pointers 69 * 70 * @handle: amdgpu_device pointer 71 * 72 * Set ring and irq function pointers 73 */ 74 static int vcn_v2_5_early_init(void *handle) 75 { 76 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 77 78 if (amdgpu_sriov_vf(adev)) { 79 adev->vcn.num_vcn_inst = 2; 80 adev->vcn.harvest_config = 0; 81 adev->vcn.num_enc_rings = 1; 82 } else { 83 u32 harvest; 84 int i; 85 adev->vcn.num_vcn_inst = VCN25_MAX_HW_INSTANCES_ARCTURUS; 86 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 87 harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING); 88 if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK) 89 adev->vcn.harvest_config |= 1 << i; 90 } 91 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 | 92 AMDGPU_VCN_HARVEST_VCN1)) 93 /* both instances are harvested, disable the block */ 94 return -ENOENT; 95 96 adev->vcn.num_enc_rings = 2; 97 } 98 99 vcn_v2_5_set_dec_ring_funcs(adev); 100 vcn_v2_5_set_enc_ring_funcs(adev); 101 vcn_v2_5_set_irq_funcs(adev); 102 103 return 0; 104 } 105 106 /** 107 * vcn_v2_5_sw_init - sw init for VCN block 108 * 109 * @handle: amdgpu_device pointer 110 * 111 * Load firmware and sw initialization 112 */ 113 static int vcn_v2_5_sw_init(void *handle) 114 { 115 struct amdgpu_ring *ring; 116 int i, j, r; 117 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 118 119 for (j = 0; j < adev->vcn.num_vcn_inst; j++) { 120 if (adev->vcn.harvest_config & (1 << j)) 121 continue; 122 /* VCN DEC TRAP */ 123 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j], 124 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[j].irq); 125 if (r) 126 return r; 127 128 /* VCN ENC TRAP */ 129 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 130 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j], 131 i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[j].irq); 132 if (r) 133 return r; 134 } 135 } 136 137 r = amdgpu_vcn_sw_init(adev); 138 if (r) 139 return r; 140 141 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 142 const struct common_firmware_header *hdr; 143 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 144 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN; 145 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw; 146 adev->firmware.fw_size += 147 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 148 149 if (adev->vcn.num_vcn_inst == VCN25_MAX_HW_INSTANCES_ARCTURUS) { 150 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].ucode_id = AMDGPU_UCODE_ID_VCN1; 151 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].fw = adev->vcn.fw; 152 adev->firmware.fw_size += 153 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 154 } 155 dev_info(adev->dev, "Will use PSP to load VCN firmware\n"); 156 } 157 158 r = amdgpu_vcn_resume(adev); 159 if (r) 160 return r; 161 162 for (j = 0; j < adev->vcn.num_vcn_inst; j++) { 163 volatile struct amdgpu_fw_shared *fw_shared; 164 165 if (adev->vcn.harvest_config & (1 << j)) 166 continue; 167 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; 168 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; 169 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; 170 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; 171 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; 172 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; 173 174 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; 175 adev->vcn.inst[j].external.scratch9 = SOC15_REG_OFFSET(VCN, j, mmUVD_SCRATCH9); 176 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; 177 adev->vcn.inst[j].external.data0 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA0); 178 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; 179 adev->vcn.inst[j].external.data1 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA1); 180 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; 181 adev->vcn.inst[j].external.cmd = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_CMD); 182 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; 183 adev->vcn.inst[j].external.nop = SOC15_REG_OFFSET(VCN, j, mmUVD_NO_OP); 184 185 ring = &adev->vcn.inst[j].ring_dec; 186 ring->use_doorbell = true; 187 188 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 189 (amdgpu_sriov_vf(adev) ? 2*j : 8*j); 190 sprintf(ring->name, "vcn_dec_%d", j); 191 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq, 192 0, AMDGPU_RING_PRIO_DEFAULT, NULL); 193 if (r) 194 return r; 195 196 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 197 enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(i); 198 199 ring = &adev->vcn.inst[j].ring_enc[i]; 200 ring->use_doorbell = true; 201 202 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 203 (amdgpu_sriov_vf(adev) ? (1 + i + 2*j) : (2 + i + 8*j)); 204 205 sprintf(ring->name, "vcn_enc_%d.%d", j, i); 206 r = amdgpu_ring_init(adev, ring, 512, 207 &adev->vcn.inst[j].irq, 0, 208 hw_prio, NULL); 209 if (r) 210 return r; 211 } 212 213 fw_shared = adev->vcn.inst[j].fw_shared_cpu_addr; 214 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG); 215 } 216 217 if (amdgpu_sriov_vf(adev)) { 218 r = amdgpu_virt_alloc_mm_table(adev); 219 if (r) 220 return r; 221 } 222 223 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 224 adev->vcn.pause_dpg_mode = vcn_v2_5_pause_dpg_mode; 225 226 return 0; 227 } 228 229 /** 230 * vcn_v2_5_sw_fini - sw fini for VCN block 231 * 232 * @handle: amdgpu_device pointer 233 * 234 * VCN suspend and free up sw allocation 235 */ 236 static int vcn_v2_5_sw_fini(void *handle) 237 { 238 int i, r; 239 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 240 volatile struct amdgpu_fw_shared *fw_shared; 241 242 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 243 if (adev->vcn.harvest_config & (1 << i)) 244 continue; 245 fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr; 246 fw_shared->present_flag_0 = 0; 247 } 248 249 if (amdgpu_sriov_vf(adev)) 250 amdgpu_virt_free_mm_table(adev); 251 252 r = amdgpu_vcn_suspend(adev); 253 if (r) 254 return r; 255 256 r = amdgpu_vcn_sw_fini(adev); 257 258 return r; 259 } 260 261 /** 262 * vcn_v2_5_hw_init - start and test VCN block 263 * 264 * @handle: amdgpu_device pointer 265 * 266 * Initialize the hardware, boot up the VCPU and do some testing 267 */ 268 static int vcn_v2_5_hw_init(void *handle) 269 { 270 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 271 struct amdgpu_ring *ring; 272 int i, j, r = 0; 273 274 if (amdgpu_sriov_vf(adev)) 275 r = vcn_v2_5_sriov_start(adev); 276 277 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 278 if (adev->vcn.harvest_config & (1 << j)) 279 continue; 280 281 if (amdgpu_sriov_vf(adev)) { 282 adev->vcn.inst[j].ring_enc[0].sched.ready = true; 283 adev->vcn.inst[j].ring_enc[1].sched.ready = false; 284 adev->vcn.inst[j].ring_enc[2].sched.ready = false; 285 adev->vcn.inst[j].ring_dec.sched.ready = true; 286 } else { 287 288 ring = &adev->vcn.inst[j].ring_dec; 289 290 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 291 ring->doorbell_index, j); 292 293 r = amdgpu_ring_test_helper(ring); 294 if (r) 295 goto done; 296 297 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 298 ring = &adev->vcn.inst[j].ring_enc[i]; 299 r = amdgpu_ring_test_helper(ring); 300 if (r) 301 goto done; 302 } 303 } 304 } 305 306 done: 307 if (!r) 308 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 309 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 310 311 return r; 312 } 313 314 /** 315 * vcn_v2_5_hw_fini - stop the hardware block 316 * 317 * @handle: amdgpu_device pointer 318 * 319 * Stop the VCN block, mark ring as not ready any more 320 */ 321 static int vcn_v2_5_hw_fini(void *handle) 322 { 323 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 324 int i; 325 326 cancel_delayed_work_sync(&adev->vcn.idle_work); 327 328 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 329 if (adev->vcn.harvest_config & (1 << i)) 330 continue; 331 332 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 333 (adev->vcn.cur_state != AMD_PG_STATE_GATE && 334 RREG32_SOC15(VCN, i, mmUVD_STATUS))) 335 vcn_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE); 336 } 337 338 return 0; 339 } 340 341 /** 342 * vcn_v2_5_suspend - suspend VCN block 343 * 344 * @handle: amdgpu_device pointer 345 * 346 * HW fini and suspend VCN block 347 */ 348 static int vcn_v2_5_suspend(void *handle) 349 { 350 int r; 351 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 352 353 r = vcn_v2_5_hw_fini(adev); 354 if (r) 355 return r; 356 357 r = amdgpu_vcn_suspend(adev); 358 359 return r; 360 } 361 362 /** 363 * vcn_v2_5_resume - resume VCN block 364 * 365 * @handle: amdgpu_device pointer 366 * 367 * Resume firmware and hw init VCN block 368 */ 369 static int vcn_v2_5_resume(void *handle) 370 { 371 int r; 372 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 373 374 r = amdgpu_vcn_resume(adev); 375 if (r) 376 return r; 377 378 r = vcn_v2_5_hw_init(adev); 379 380 return r; 381 } 382 383 /** 384 * vcn_v2_5_mc_resume - memory controller programming 385 * 386 * @adev: amdgpu_device pointer 387 * 388 * Let the VCN memory controller know it's offsets 389 */ 390 static void vcn_v2_5_mc_resume(struct amdgpu_device *adev) 391 { 392 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 393 uint32_t offset; 394 int i; 395 396 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 397 if (adev->vcn.harvest_config & (1 << i)) 398 continue; 399 /* cache window 0: fw */ 400 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 401 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 402 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo)); 403 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 404 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi)); 405 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, 0); 406 offset = 0; 407 } else { 408 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 409 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 410 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 411 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 412 offset = size; 413 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, 414 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 415 } 416 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE0, size); 417 418 /* cache window 1: stack */ 419 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 420 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset)); 421 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 422 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset)); 423 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET1, 0); 424 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 425 426 /* cache window 2: context */ 427 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 428 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 429 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 430 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 431 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET2, 0); 432 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 433 434 /* non-cache window */ 435 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 436 lower_32_bits(adev->vcn.inst[i].fw_shared_gpu_addr)); 437 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 438 upper_32_bits(adev->vcn.inst[i].fw_shared_gpu_addr)); 439 WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_OFFSET0, 0); 440 WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_SIZE0, 441 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); 442 } 443 } 444 445 static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 446 { 447 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 448 uint32_t offset; 449 450 /* cache window 0: fw */ 451 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 452 if (!indirect) { 453 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 454 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 455 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); 456 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 457 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 458 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); 459 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 460 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 461 } else { 462 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 463 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 464 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 465 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 466 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 467 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 468 } 469 offset = 0; 470 } else { 471 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 472 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 473 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 474 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 475 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 476 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 477 offset = size; 478 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 479 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 480 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 481 } 482 483 if (!indirect) 484 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 485 VCN, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 486 else 487 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 488 VCN, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 489 490 /* cache window 1: stack */ 491 if (!indirect) { 492 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 493 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 494 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 495 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 496 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 497 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 498 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 499 VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 500 } else { 501 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 502 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 503 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 504 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 505 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 506 VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 507 } 508 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 509 VCN, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 510 511 /* cache window 2: context */ 512 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 513 VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 514 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 515 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 516 VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 517 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 518 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 519 VCN, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 520 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 521 VCN, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 522 523 /* non-cache window */ 524 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 525 VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 526 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect); 527 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 528 VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 529 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect); 530 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 531 VCN, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 532 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 533 VCN, 0, mmUVD_VCPU_NONCACHE_SIZE0), 534 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); 535 536 /* VCN global tiling registers */ 537 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 538 VCN, 0, mmUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 539 } 540 541 /** 542 * vcn_v2_5_disable_clock_gating - disable VCN clock gating 543 * 544 * @adev: amdgpu_device pointer 545 * 546 * Disable clock gating for VCN block 547 */ 548 static void vcn_v2_5_disable_clock_gating(struct amdgpu_device *adev) 549 { 550 uint32_t data; 551 int i; 552 553 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 554 if (adev->vcn.harvest_config & (1 << i)) 555 continue; 556 /* UVD disable CGC */ 557 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); 558 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 559 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 560 else 561 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 562 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 563 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 564 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); 565 566 data = RREG32_SOC15(VCN, i, mmUVD_CGC_GATE); 567 data &= ~(UVD_CGC_GATE__SYS_MASK 568 | UVD_CGC_GATE__UDEC_MASK 569 | UVD_CGC_GATE__MPEG2_MASK 570 | UVD_CGC_GATE__REGS_MASK 571 | UVD_CGC_GATE__RBC_MASK 572 | UVD_CGC_GATE__LMI_MC_MASK 573 | UVD_CGC_GATE__LMI_UMC_MASK 574 | UVD_CGC_GATE__IDCT_MASK 575 | UVD_CGC_GATE__MPRD_MASK 576 | UVD_CGC_GATE__MPC_MASK 577 | UVD_CGC_GATE__LBSI_MASK 578 | UVD_CGC_GATE__LRBBM_MASK 579 | UVD_CGC_GATE__UDEC_RE_MASK 580 | UVD_CGC_GATE__UDEC_CM_MASK 581 | UVD_CGC_GATE__UDEC_IT_MASK 582 | UVD_CGC_GATE__UDEC_DB_MASK 583 | UVD_CGC_GATE__UDEC_MP_MASK 584 | UVD_CGC_GATE__WCB_MASK 585 | UVD_CGC_GATE__VCPU_MASK 586 | UVD_CGC_GATE__MMSCH_MASK); 587 588 WREG32_SOC15(VCN, i, mmUVD_CGC_GATE, data); 589 590 SOC15_WAIT_ON_RREG(VCN, i, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); 591 592 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); 593 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 594 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 595 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 596 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 597 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 598 | UVD_CGC_CTRL__SYS_MODE_MASK 599 | UVD_CGC_CTRL__UDEC_MODE_MASK 600 | UVD_CGC_CTRL__MPEG2_MODE_MASK 601 | UVD_CGC_CTRL__REGS_MODE_MASK 602 | UVD_CGC_CTRL__RBC_MODE_MASK 603 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 604 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 605 | UVD_CGC_CTRL__IDCT_MODE_MASK 606 | UVD_CGC_CTRL__MPRD_MODE_MASK 607 | UVD_CGC_CTRL__MPC_MODE_MASK 608 | UVD_CGC_CTRL__LBSI_MODE_MASK 609 | UVD_CGC_CTRL__LRBBM_MODE_MASK 610 | UVD_CGC_CTRL__WCB_MODE_MASK 611 | UVD_CGC_CTRL__VCPU_MODE_MASK 612 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 613 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); 614 615 /* turn on */ 616 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE); 617 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 618 | UVD_SUVD_CGC_GATE__SIT_MASK 619 | UVD_SUVD_CGC_GATE__SMP_MASK 620 | UVD_SUVD_CGC_GATE__SCM_MASK 621 | UVD_SUVD_CGC_GATE__SDB_MASK 622 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 623 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 624 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 625 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 626 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 627 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 628 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 629 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 630 | UVD_SUVD_CGC_GATE__SCLR_MASK 631 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 632 | UVD_SUVD_CGC_GATE__ENT_MASK 633 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 634 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 635 | UVD_SUVD_CGC_GATE__SITE_MASK 636 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 637 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 638 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 639 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 640 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 641 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE, data); 642 643 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL); 644 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 645 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 646 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 647 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 648 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 649 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 650 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 651 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 652 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 653 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 654 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data); 655 } 656 } 657 658 static void vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_device *adev, 659 uint8_t sram_sel, int inst_idx, uint8_t indirect) 660 { 661 uint32_t reg_data = 0; 662 663 /* enable sw clock gating control */ 664 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 665 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 666 else 667 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 668 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 669 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 670 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 671 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 672 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 673 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 674 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 675 UVD_CGC_CTRL__SYS_MODE_MASK | 676 UVD_CGC_CTRL__UDEC_MODE_MASK | 677 UVD_CGC_CTRL__MPEG2_MODE_MASK | 678 UVD_CGC_CTRL__REGS_MODE_MASK | 679 UVD_CGC_CTRL__RBC_MODE_MASK | 680 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 681 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 682 UVD_CGC_CTRL__IDCT_MODE_MASK | 683 UVD_CGC_CTRL__MPRD_MODE_MASK | 684 UVD_CGC_CTRL__MPC_MODE_MASK | 685 UVD_CGC_CTRL__LBSI_MODE_MASK | 686 UVD_CGC_CTRL__LRBBM_MODE_MASK | 687 UVD_CGC_CTRL__WCB_MODE_MASK | 688 UVD_CGC_CTRL__VCPU_MODE_MASK | 689 UVD_CGC_CTRL__MMSCH_MODE_MASK); 690 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 691 VCN, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); 692 693 /* turn off clock gating */ 694 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 695 VCN, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect); 696 697 /* turn on SUVD clock gating */ 698 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 699 VCN, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 700 701 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 702 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 703 VCN, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 704 } 705 706 /** 707 * vcn_v2_5_enable_clock_gating - enable VCN clock gating 708 * 709 * @adev: amdgpu_device pointer 710 * 711 * Enable clock gating for VCN block 712 */ 713 static void vcn_v2_5_enable_clock_gating(struct amdgpu_device *adev) 714 { 715 uint32_t data = 0; 716 int i; 717 718 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 719 if (adev->vcn.harvest_config & (1 << i)) 720 continue; 721 /* enable UVD CGC */ 722 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); 723 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 724 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 725 else 726 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 727 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 728 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 729 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); 730 731 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); 732 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 733 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 734 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 735 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 736 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 737 | UVD_CGC_CTRL__SYS_MODE_MASK 738 | UVD_CGC_CTRL__UDEC_MODE_MASK 739 | UVD_CGC_CTRL__MPEG2_MODE_MASK 740 | UVD_CGC_CTRL__REGS_MODE_MASK 741 | UVD_CGC_CTRL__RBC_MODE_MASK 742 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 743 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 744 | UVD_CGC_CTRL__IDCT_MODE_MASK 745 | UVD_CGC_CTRL__MPRD_MODE_MASK 746 | UVD_CGC_CTRL__MPC_MODE_MASK 747 | UVD_CGC_CTRL__LBSI_MODE_MASK 748 | UVD_CGC_CTRL__LRBBM_MODE_MASK 749 | UVD_CGC_CTRL__WCB_MODE_MASK 750 | UVD_CGC_CTRL__VCPU_MODE_MASK); 751 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); 752 753 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL); 754 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 755 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 756 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 757 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 758 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 759 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 760 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 761 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 762 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 763 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 764 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data); 765 } 766 } 767 768 static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 769 { 770 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr; 771 struct amdgpu_ring *ring; 772 uint32_t rb_bufsz, tmp; 773 774 /* disable register anti-hang mechanism */ 775 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1, 776 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 777 /* enable dynamic power gating mode */ 778 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS); 779 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 780 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 781 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp); 782 783 if (indirect) 784 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 785 786 /* enable clock gating */ 787 vcn_v2_5_clock_gating_dpg_mode(adev, 0, inst_idx, indirect); 788 789 /* enable VCPU clock */ 790 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 791 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 792 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK; 793 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 794 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); 795 796 /* disable master interupt */ 797 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 798 VCN, 0, mmUVD_MASTINT_EN), 0, 0, indirect); 799 800 /* setup mmUVD_LMI_CTRL */ 801 tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 802 UVD_LMI_CTRL__REQ_MODE_MASK | 803 UVD_LMI_CTRL__CRC_RESET_MASK | 804 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 805 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 806 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 807 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 808 0x00100000L); 809 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 810 VCN, 0, mmUVD_LMI_CTRL), tmp, 0, indirect); 811 812 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 813 VCN, 0, mmUVD_MPC_CNTL), 814 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 815 816 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 817 VCN, 0, mmUVD_MPC_SET_MUXA0), 818 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 819 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 820 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 821 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 822 823 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 824 VCN, 0, mmUVD_MPC_SET_MUXB0), 825 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 826 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 827 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 828 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 829 830 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 831 VCN, 0, mmUVD_MPC_SET_MUX), 832 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 833 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 834 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 835 836 vcn_v2_5_mc_resume_dpg_mode(adev, inst_idx, indirect); 837 838 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 839 VCN, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect); 840 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 841 VCN, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect); 842 843 /* enable LMI MC and UMC channels */ 844 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 845 VCN, 0, mmUVD_LMI_CTRL2), 0, 0, indirect); 846 847 /* unblock VCPU register access */ 848 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 849 VCN, 0, mmUVD_RB_ARB_CTRL), 0, 0, indirect); 850 851 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 852 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 853 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 854 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); 855 856 /* enable master interrupt */ 857 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 858 VCN, 0, mmUVD_MASTINT_EN), 859 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 860 861 if (indirect) 862 psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, 863 (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr - 864 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr)); 865 866 ring = &adev->vcn.inst[inst_idx].ring_dec; 867 /* force RBC into idle state */ 868 rb_bufsz = order_base_2(ring->ring_size); 869 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 870 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 871 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 872 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 873 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 874 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp); 875 876 /* Stall DPG before WPTR/RPTR reset */ 877 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 878 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 879 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 880 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET; 881 882 /* set the write pointer delay */ 883 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0); 884 885 /* set the wb address */ 886 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR, 887 (upper_32_bits(ring->gpu_addr) >> 2)); 888 889 /* program the RB_BASE for ring buffer */ 890 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 891 lower_32_bits(ring->gpu_addr)); 892 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 893 upper_32_bits(ring->gpu_addr)); 894 895 /* Initialize the ring buffer's read and write pointers */ 896 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0); 897 898 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0); 899 900 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR); 901 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, 902 lower_32_bits(ring->wptr)); 903 904 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET; 905 /* Unstall DPG */ 906 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 907 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 908 909 return 0; 910 } 911 912 static int vcn_v2_5_start(struct amdgpu_device *adev) 913 { 914 struct amdgpu_ring *ring; 915 uint32_t rb_bufsz, tmp; 916 int i, j, k, r; 917 918 if (adev->pm.dpm_enabled) 919 amdgpu_dpm_enable_uvd(adev, true); 920 921 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 922 if (adev->vcn.harvest_config & (1 << i)) 923 continue; 924 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 925 r = vcn_v2_5_start_dpg_mode(adev, i, adev->vcn.indirect_sram); 926 continue; 927 } 928 929 /* disable register anti-hang mechanism */ 930 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), 0, 931 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 932 933 /* set uvd status busy */ 934 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 935 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp); 936 } 937 938 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 939 return 0; 940 941 /*SW clock gating */ 942 vcn_v2_5_disable_clock_gating(adev); 943 944 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 945 if (adev->vcn.harvest_config & (1 << i)) 946 continue; 947 /* enable VCPU clock */ 948 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 949 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 950 951 /* disable master interrupt */ 952 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0, 953 ~UVD_MASTINT_EN__VCPU_EN_MASK); 954 955 /* setup mmUVD_LMI_CTRL */ 956 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL); 957 tmp &= ~0xff; 958 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | 0x8| 959 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 960 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 961 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 962 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 963 964 /* setup mmUVD_MPC_CNTL */ 965 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL); 966 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 967 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 968 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp); 969 970 /* setup UVD_MPC_SET_MUXA0 */ 971 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0, 972 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 973 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 974 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 975 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 976 977 /* setup UVD_MPC_SET_MUXB0 */ 978 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0, 979 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 980 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 981 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 982 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 983 984 /* setup mmUVD_MPC_SET_MUX */ 985 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX, 986 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 987 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 988 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 989 } 990 991 vcn_v2_5_mc_resume(adev); 992 993 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 994 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr; 995 if (adev->vcn.harvest_config & (1 << i)) 996 continue; 997 /* VCN global tiling registers */ 998 WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG, 999 adev->gfx.config.gb_addr_config); 1000 WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG, 1001 adev->gfx.config.gb_addr_config); 1002 1003 /* enable LMI MC and UMC channels */ 1004 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0, 1005 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1006 1007 /* unblock VCPU register access */ 1008 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0, 1009 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1010 1011 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1012 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1013 1014 for (k = 0; k < 10; ++k) { 1015 uint32_t status; 1016 1017 for (j = 0; j < 100; ++j) { 1018 status = RREG32_SOC15(VCN, i, mmUVD_STATUS); 1019 if (status & 2) 1020 break; 1021 if (amdgpu_emu_mode == 1) 1022 msleep(500); 1023 else 1024 mdelay(10); 1025 } 1026 r = 0; 1027 if (status & 2) 1028 break; 1029 1030 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n"); 1031 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1032 UVD_VCPU_CNTL__BLK_RST_MASK, 1033 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1034 mdelay(10); 1035 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1036 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1037 1038 mdelay(10); 1039 r = -1; 1040 } 1041 1042 if (r) { 1043 DRM_ERROR("VCN decode not responding, giving up!!!\n"); 1044 return r; 1045 } 1046 1047 /* enable master interrupt */ 1048 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 1049 UVD_MASTINT_EN__VCPU_EN_MASK, 1050 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1051 1052 /* clear the busy bit of VCN_STATUS */ 1053 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0, 1054 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1055 1056 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0); 1057 1058 ring = &adev->vcn.inst[i].ring_dec; 1059 /* force RBC into idle state */ 1060 rb_bufsz = order_base_2(ring->ring_size); 1061 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1062 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1063 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1064 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1065 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1066 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp); 1067 1068 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET; 1069 /* program the RB_BASE for ring buffer */ 1070 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1071 lower_32_bits(ring->gpu_addr)); 1072 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1073 upper_32_bits(ring->gpu_addr)); 1074 1075 /* Initialize the ring buffer's read and write pointers */ 1076 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0); 1077 1078 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR); 1079 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR, 1080 lower_32_bits(ring->wptr)); 1081 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET; 1082 1083 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET; 1084 ring = &adev->vcn.inst[i].ring_enc[0]; 1085 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1086 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1087 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr); 1088 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1089 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4); 1090 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET; 1091 1092 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET; 1093 ring = &adev->vcn.inst[i].ring_enc[1]; 1094 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1095 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1096 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1097 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1098 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4); 1099 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET; 1100 } 1101 1102 return 0; 1103 } 1104 1105 static int vcn_v2_5_mmsch_start(struct amdgpu_device *adev, 1106 struct amdgpu_mm_table *table) 1107 { 1108 uint32_t data = 0, loop = 0, size = 0; 1109 uint64_t addr = table->gpu_addr; 1110 struct mmsch_v1_1_init_header *header = NULL; 1111 1112 header = (struct mmsch_v1_1_init_header *)table->cpu_addr; 1113 size = header->total_size; 1114 1115 /* 1116 * 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr of 1117 * memory descriptor location 1118 */ 1119 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr)); 1120 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr)); 1121 1122 /* 2, update vmid of descriptor */ 1123 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID); 1124 data &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1125 /* use domain0 for MM scheduler */ 1126 data |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1127 WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, data); 1128 1129 /* 3, notify mmsch about the size of this descriptor */ 1130 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size); 1131 1132 /* 4, set resp to zero */ 1133 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0); 1134 1135 /* 1136 * 5, kick off the initialization and wait until 1137 * VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero 1138 */ 1139 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, 0x10000001); 1140 1141 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); 1142 loop = 10; 1143 while ((data & 0x10000002) != 0x10000002) { 1144 udelay(100); 1145 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); 1146 loop--; 1147 if (!loop) 1148 break; 1149 } 1150 1151 if (!loop) { 1152 dev_err(adev->dev, 1153 "failed to init MMSCH, mmMMSCH_VF_MAILBOX_RESP = %x\n", 1154 data); 1155 return -EBUSY; 1156 } 1157 1158 return 0; 1159 } 1160 1161 static int vcn_v2_5_sriov_start(struct amdgpu_device *adev) 1162 { 1163 struct amdgpu_ring *ring; 1164 uint32_t offset, size, tmp, i, rb_bufsz; 1165 uint32_t table_size = 0; 1166 struct mmsch_v1_0_cmd_direct_write direct_wt = { { 0 } }; 1167 struct mmsch_v1_0_cmd_direct_read_modify_write direct_rd_mod_wt = { { 0 } }; 1168 struct mmsch_v1_0_cmd_end end = { { 0 } }; 1169 uint32_t *init_table = adev->virt.mm_table.cpu_addr; 1170 struct mmsch_v1_1_init_header *header = (struct mmsch_v1_1_init_header *)init_table; 1171 1172 direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE; 1173 direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1174 end.cmd_header.command_type = MMSCH_COMMAND__END; 1175 1176 header->version = MMSCH_VERSION; 1177 header->total_size = sizeof(struct mmsch_v1_1_init_header) >> 2; 1178 init_table += header->total_size; 1179 1180 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1181 header->eng[i].table_offset = header->total_size; 1182 header->eng[i].init_status = 0; 1183 header->eng[i].table_size = 0; 1184 1185 table_size = 0; 1186 1187 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT( 1188 SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 1189 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 1190 1191 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 1192 /* mc resume*/ 1193 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1194 MMSCH_V1_0_INSERT_DIRECT_WT( 1195 SOC15_REG_OFFSET(VCN, i, 1196 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1197 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo); 1198 MMSCH_V1_0_INSERT_DIRECT_WT( 1199 SOC15_REG_OFFSET(VCN, i, 1200 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1201 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi); 1202 offset = 0; 1203 MMSCH_V1_0_INSERT_DIRECT_WT( 1204 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0), 0); 1205 } else { 1206 MMSCH_V1_0_INSERT_DIRECT_WT( 1207 SOC15_REG_OFFSET(VCN, i, 1208 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1209 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 1210 MMSCH_V1_0_INSERT_DIRECT_WT( 1211 SOC15_REG_OFFSET(VCN, i, 1212 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1213 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 1214 offset = size; 1215 MMSCH_V1_0_INSERT_DIRECT_WT( 1216 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0), 1217 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 1218 } 1219 1220 MMSCH_V1_0_INSERT_DIRECT_WT( 1221 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE0), 1222 size); 1223 MMSCH_V1_0_INSERT_DIRECT_WT( 1224 SOC15_REG_OFFSET(VCN, i, 1225 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 1226 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset)); 1227 MMSCH_V1_0_INSERT_DIRECT_WT( 1228 SOC15_REG_OFFSET(VCN, i, 1229 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 1230 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset)); 1231 MMSCH_V1_0_INSERT_DIRECT_WT( 1232 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET1), 1233 0); 1234 MMSCH_V1_0_INSERT_DIRECT_WT( 1235 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE1), 1236 AMDGPU_VCN_STACK_SIZE); 1237 MMSCH_V1_0_INSERT_DIRECT_WT( 1238 SOC15_REG_OFFSET(VCN, i, 1239 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 1240 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + 1241 AMDGPU_VCN_STACK_SIZE)); 1242 MMSCH_V1_0_INSERT_DIRECT_WT( 1243 SOC15_REG_OFFSET(VCN, i, 1244 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 1245 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + 1246 AMDGPU_VCN_STACK_SIZE)); 1247 MMSCH_V1_0_INSERT_DIRECT_WT( 1248 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET2), 1249 0); 1250 MMSCH_V1_0_INSERT_DIRECT_WT( 1251 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE2), 1252 AMDGPU_VCN_CONTEXT_SIZE); 1253 1254 ring = &adev->vcn.inst[i].ring_enc[0]; 1255 ring->wptr = 0; 1256 1257 MMSCH_V1_0_INSERT_DIRECT_WT( 1258 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_LO), 1259 lower_32_bits(ring->gpu_addr)); 1260 MMSCH_V1_0_INSERT_DIRECT_WT( 1261 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_HI), 1262 upper_32_bits(ring->gpu_addr)); 1263 MMSCH_V1_0_INSERT_DIRECT_WT( 1264 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_SIZE), 1265 ring->ring_size / 4); 1266 1267 ring = &adev->vcn.inst[i].ring_dec; 1268 ring->wptr = 0; 1269 MMSCH_V1_0_INSERT_DIRECT_WT( 1270 SOC15_REG_OFFSET(VCN, i, 1271 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW), 1272 lower_32_bits(ring->gpu_addr)); 1273 MMSCH_V1_0_INSERT_DIRECT_WT( 1274 SOC15_REG_OFFSET(VCN, i, 1275 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH), 1276 upper_32_bits(ring->gpu_addr)); 1277 1278 /* force RBC into idle state */ 1279 rb_bufsz = order_base_2(ring->ring_size); 1280 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1281 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1282 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1283 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1284 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1285 MMSCH_V1_0_INSERT_DIRECT_WT( 1286 SOC15_REG_OFFSET(VCN, i, mmUVD_RBC_RB_CNTL), tmp); 1287 1288 /* add end packet */ 1289 memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end)); 1290 table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4; 1291 init_table += sizeof(struct mmsch_v1_0_cmd_end) / 4; 1292 1293 /* refine header */ 1294 header->eng[i].table_size = table_size; 1295 header->total_size += table_size; 1296 } 1297 1298 return vcn_v2_5_mmsch_start(adev, &adev->virt.mm_table); 1299 } 1300 1301 static int vcn_v2_5_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) 1302 { 1303 uint32_t tmp; 1304 1305 /* Wait for power status to be 1 */ 1306 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1307 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1308 1309 /* wait for read ptr to be equal to write ptr */ 1310 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR); 1311 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1312 1313 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2); 1314 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); 1315 1316 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1317 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); 1318 1319 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1320 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1321 1322 /* disable dynamic power gating mode */ 1323 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0, 1324 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1325 1326 return 0; 1327 } 1328 1329 static int vcn_v2_5_stop(struct amdgpu_device *adev) 1330 { 1331 uint32_t tmp; 1332 int i, r = 0; 1333 1334 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1335 if (adev->vcn.harvest_config & (1 << i)) 1336 continue; 1337 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1338 r = vcn_v2_5_stop_dpg_mode(adev, i); 1339 continue; 1340 } 1341 1342 /* wait for vcn idle */ 1343 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1344 if (r) 1345 return r; 1346 1347 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1348 UVD_LMI_STATUS__READ_CLEAN_MASK | 1349 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1350 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1351 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1352 if (r) 1353 return r; 1354 1355 /* block LMI UMC channel */ 1356 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2); 1357 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1358 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp); 1359 1360 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK| 1361 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1362 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1363 if (r) 1364 return r; 1365 1366 /* block VCPU register access */ 1367 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 1368 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1369 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1370 1371 /* reset VCPU */ 1372 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1373 UVD_VCPU_CNTL__BLK_RST_MASK, 1374 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1375 1376 /* disable VCPU clock */ 1377 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1378 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1379 1380 /* clear status */ 1381 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0); 1382 1383 vcn_v2_5_enable_clock_gating(adev); 1384 1385 /* enable register anti-hang mechanism */ 1386 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), 1387 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, 1388 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1389 } 1390 1391 if (adev->pm.dpm_enabled) 1392 amdgpu_dpm_enable_uvd(adev, false); 1393 1394 return 0; 1395 } 1396 1397 static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev, 1398 int inst_idx, struct dpg_pause_state *new_state) 1399 { 1400 struct amdgpu_ring *ring; 1401 uint32_t reg_data = 0; 1402 int ret_code = 0; 1403 1404 /* pause/unpause if state is changed */ 1405 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1406 DRM_DEBUG("dpg pause state changed %d -> %d", 1407 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1408 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) & 1409 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1410 1411 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1412 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, 1413 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1414 1415 if (!ret_code) { 1416 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr; 1417 1418 /* pause DPG */ 1419 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1420 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1421 1422 /* wait for ACK */ 1423 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE, 1424 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1425 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1426 1427 /* Stall DPG before WPTR/RPTR reset */ 1428 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1429 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1430 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1431 1432 /* Restore */ 1433 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET; 1434 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 1435 ring->wptr = 0; 1436 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr); 1437 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1438 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4); 1439 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1440 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1441 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET; 1442 1443 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET; 1444 ring = &adev->vcn.inst[inst_idx].ring_enc[1]; 1445 ring->wptr = 0; 1446 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1447 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1448 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4); 1449 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1450 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1451 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET; 1452 1453 /* Unstall DPG */ 1454 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1455 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1456 1457 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1458 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1459 } 1460 } else { 1461 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1462 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1463 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, 1464 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1465 } 1466 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1467 } 1468 1469 return 0; 1470 } 1471 1472 /** 1473 * vcn_v2_5_dec_ring_get_rptr - get read pointer 1474 * 1475 * @ring: amdgpu_ring pointer 1476 * 1477 * Returns the current hardware read pointer 1478 */ 1479 static uint64_t vcn_v2_5_dec_ring_get_rptr(struct amdgpu_ring *ring) 1480 { 1481 struct amdgpu_device *adev = ring->adev; 1482 1483 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR); 1484 } 1485 1486 /** 1487 * vcn_v2_5_dec_ring_get_wptr - get write pointer 1488 * 1489 * @ring: amdgpu_ring pointer 1490 * 1491 * Returns the current hardware write pointer 1492 */ 1493 static uint64_t vcn_v2_5_dec_ring_get_wptr(struct amdgpu_ring *ring) 1494 { 1495 struct amdgpu_device *adev = ring->adev; 1496 1497 if (ring->use_doorbell) 1498 return adev->wb.wb[ring->wptr_offs]; 1499 else 1500 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR); 1501 } 1502 1503 /** 1504 * vcn_v2_5_dec_ring_set_wptr - set write pointer 1505 * 1506 * @ring: amdgpu_ring pointer 1507 * 1508 * Commits the write pointer to the hardware 1509 */ 1510 static void vcn_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring) 1511 { 1512 struct amdgpu_device *adev = ring->adev; 1513 1514 if (ring->use_doorbell) { 1515 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 1516 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1517 } else { 1518 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1519 } 1520 } 1521 1522 static const struct amdgpu_ring_funcs vcn_v2_5_dec_ring_vm_funcs = { 1523 .type = AMDGPU_RING_TYPE_VCN_DEC, 1524 .align_mask = 0xf, 1525 .vmhub = AMDGPU_MMHUB_1, 1526 .get_rptr = vcn_v2_5_dec_ring_get_rptr, 1527 .get_wptr = vcn_v2_5_dec_ring_get_wptr, 1528 .set_wptr = vcn_v2_5_dec_ring_set_wptr, 1529 .emit_frame_size = 1530 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1531 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1532 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */ 1533 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */ 1534 6, 1535 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */ 1536 .emit_ib = vcn_v2_0_dec_ring_emit_ib, 1537 .emit_fence = vcn_v2_0_dec_ring_emit_fence, 1538 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush, 1539 .test_ring = vcn_v2_0_dec_ring_test_ring, 1540 .test_ib = amdgpu_vcn_dec_ring_test_ib, 1541 .insert_nop = vcn_v2_0_dec_ring_insert_nop, 1542 .insert_start = vcn_v2_0_dec_ring_insert_start, 1543 .insert_end = vcn_v2_0_dec_ring_insert_end, 1544 .pad_ib = amdgpu_ring_generic_pad_ib, 1545 .begin_use = amdgpu_vcn_ring_begin_use, 1546 .end_use = amdgpu_vcn_ring_end_use, 1547 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg, 1548 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait, 1549 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1550 }; 1551 1552 static const struct amdgpu_ring_funcs vcn_v2_6_dec_ring_vm_funcs = { 1553 .type = AMDGPU_RING_TYPE_VCN_DEC, 1554 .align_mask = 0xf, 1555 .vmhub = AMDGPU_MMHUB_0, 1556 .get_rptr = vcn_v2_5_dec_ring_get_rptr, 1557 .get_wptr = vcn_v2_5_dec_ring_get_wptr, 1558 .set_wptr = vcn_v2_5_dec_ring_set_wptr, 1559 .emit_frame_size = 1560 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1561 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1562 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */ 1563 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */ 1564 6, 1565 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */ 1566 .emit_ib = vcn_v2_0_dec_ring_emit_ib, 1567 .emit_fence = vcn_v2_0_dec_ring_emit_fence, 1568 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush, 1569 .test_ring = vcn_v2_0_dec_ring_test_ring, 1570 .test_ib = amdgpu_vcn_dec_ring_test_ib, 1571 .insert_nop = vcn_v2_0_dec_ring_insert_nop, 1572 .insert_start = vcn_v2_0_dec_ring_insert_start, 1573 .insert_end = vcn_v2_0_dec_ring_insert_end, 1574 .pad_ib = amdgpu_ring_generic_pad_ib, 1575 .begin_use = amdgpu_vcn_ring_begin_use, 1576 .end_use = amdgpu_vcn_ring_end_use, 1577 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg, 1578 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait, 1579 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1580 }; 1581 1582 /** 1583 * vcn_v2_5_enc_ring_get_rptr - get enc read pointer 1584 * 1585 * @ring: amdgpu_ring pointer 1586 * 1587 * Returns the current hardware enc read pointer 1588 */ 1589 static uint64_t vcn_v2_5_enc_ring_get_rptr(struct amdgpu_ring *ring) 1590 { 1591 struct amdgpu_device *adev = ring->adev; 1592 1593 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) 1594 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR); 1595 else 1596 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2); 1597 } 1598 1599 /** 1600 * vcn_v2_5_enc_ring_get_wptr - get enc write pointer 1601 * 1602 * @ring: amdgpu_ring pointer 1603 * 1604 * Returns the current hardware enc write pointer 1605 */ 1606 static uint64_t vcn_v2_5_enc_ring_get_wptr(struct amdgpu_ring *ring) 1607 { 1608 struct amdgpu_device *adev = ring->adev; 1609 1610 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 1611 if (ring->use_doorbell) 1612 return adev->wb.wb[ring->wptr_offs]; 1613 else 1614 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR); 1615 } else { 1616 if (ring->use_doorbell) 1617 return adev->wb.wb[ring->wptr_offs]; 1618 else 1619 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2); 1620 } 1621 } 1622 1623 /** 1624 * vcn_v2_5_enc_ring_set_wptr - set enc write pointer 1625 * 1626 * @ring: amdgpu_ring pointer 1627 * 1628 * Commits the enc write pointer to the hardware 1629 */ 1630 static void vcn_v2_5_enc_ring_set_wptr(struct amdgpu_ring *ring) 1631 { 1632 struct amdgpu_device *adev = ring->adev; 1633 1634 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 1635 if (ring->use_doorbell) { 1636 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 1637 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1638 } else { 1639 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1640 } 1641 } else { 1642 if (ring->use_doorbell) { 1643 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 1644 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1645 } else { 1646 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1647 } 1648 } 1649 } 1650 1651 static const struct amdgpu_ring_funcs vcn_v2_5_enc_ring_vm_funcs = { 1652 .type = AMDGPU_RING_TYPE_VCN_ENC, 1653 .align_mask = 0x3f, 1654 .nop = VCN_ENC_CMD_NO_OP, 1655 .vmhub = AMDGPU_MMHUB_1, 1656 .get_rptr = vcn_v2_5_enc_ring_get_rptr, 1657 .get_wptr = vcn_v2_5_enc_ring_get_wptr, 1658 .set_wptr = vcn_v2_5_enc_ring_set_wptr, 1659 .emit_frame_size = 1660 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1661 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1662 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1663 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1664 1, /* vcn_v2_0_enc_ring_insert_end */ 1665 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1666 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1667 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1668 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 1669 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1670 .test_ib = amdgpu_vcn_enc_ring_test_ib, 1671 .insert_nop = amdgpu_ring_insert_nop, 1672 .insert_end = vcn_v2_0_enc_ring_insert_end, 1673 .pad_ib = amdgpu_ring_generic_pad_ib, 1674 .begin_use = amdgpu_vcn_ring_begin_use, 1675 .end_use = amdgpu_vcn_ring_end_use, 1676 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 1677 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 1678 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1679 }; 1680 1681 static const struct amdgpu_ring_funcs vcn_v2_6_enc_ring_vm_funcs = { 1682 .type = AMDGPU_RING_TYPE_VCN_ENC, 1683 .align_mask = 0x3f, 1684 .nop = VCN_ENC_CMD_NO_OP, 1685 .vmhub = AMDGPU_MMHUB_0, 1686 .get_rptr = vcn_v2_5_enc_ring_get_rptr, 1687 .get_wptr = vcn_v2_5_enc_ring_get_wptr, 1688 .set_wptr = vcn_v2_5_enc_ring_set_wptr, 1689 .emit_frame_size = 1690 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1691 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1692 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1693 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1694 1, /* vcn_v2_0_enc_ring_insert_end */ 1695 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1696 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1697 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1698 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 1699 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1700 .test_ib = amdgpu_vcn_enc_ring_test_ib, 1701 .insert_nop = amdgpu_ring_insert_nop, 1702 .insert_end = vcn_v2_0_enc_ring_insert_end, 1703 .pad_ib = amdgpu_ring_generic_pad_ib, 1704 .begin_use = amdgpu_vcn_ring_begin_use, 1705 .end_use = amdgpu_vcn_ring_end_use, 1706 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 1707 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 1708 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1709 }; 1710 1711 static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev) 1712 { 1713 int i; 1714 1715 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1716 if (adev->vcn.harvest_config & (1 << i)) 1717 continue; 1718 if (adev->asic_type == CHIP_ARCTURUS) 1719 adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs; 1720 else /* CHIP_ALDEBARAN */ 1721 adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_6_dec_ring_vm_funcs; 1722 adev->vcn.inst[i].ring_dec.me = i; 1723 DRM_INFO("VCN(%d) decode is enabled in VM mode\n", i); 1724 } 1725 } 1726 1727 static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev) 1728 { 1729 int i, j; 1730 1731 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 1732 if (adev->vcn.harvest_config & (1 << j)) 1733 continue; 1734 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 1735 if (adev->asic_type == CHIP_ARCTURUS) 1736 adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs; 1737 else /* CHIP_ALDEBARAN */ 1738 adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_6_enc_ring_vm_funcs; 1739 adev->vcn.inst[j].ring_enc[i].me = j; 1740 } 1741 DRM_INFO("VCN(%d) encode is enabled in VM mode\n", j); 1742 } 1743 } 1744 1745 static bool vcn_v2_5_is_idle(void *handle) 1746 { 1747 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1748 int i, ret = 1; 1749 1750 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1751 if (adev->vcn.harvest_config & (1 << i)) 1752 continue; 1753 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); 1754 } 1755 1756 return ret; 1757 } 1758 1759 static int vcn_v2_5_wait_for_idle(void *handle) 1760 { 1761 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1762 int i, ret = 0; 1763 1764 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1765 if (adev->vcn.harvest_config & (1 << i)) 1766 continue; 1767 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 1768 UVD_STATUS__IDLE); 1769 if (ret) 1770 return ret; 1771 } 1772 1773 return ret; 1774 } 1775 1776 static int vcn_v2_5_set_clockgating_state(void *handle, 1777 enum amd_clockgating_state state) 1778 { 1779 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1780 bool enable = (state == AMD_CG_STATE_GATE); 1781 1782 if (amdgpu_sriov_vf(adev)) 1783 return 0; 1784 1785 if (enable) { 1786 if (!vcn_v2_5_is_idle(handle)) 1787 return -EBUSY; 1788 vcn_v2_5_enable_clock_gating(adev); 1789 } else { 1790 vcn_v2_5_disable_clock_gating(adev); 1791 } 1792 1793 return 0; 1794 } 1795 1796 static int vcn_v2_5_set_powergating_state(void *handle, 1797 enum amd_powergating_state state) 1798 { 1799 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1800 int ret; 1801 1802 if (amdgpu_sriov_vf(adev)) 1803 return 0; 1804 1805 if(state == adev->vcn.cur_state) 1806 return 0; 1807 1808 if (state == AMD_PG_STATE_GATE) 1809 ret = vcn_v2_5_stop(adev); 1810 else 1811 ret = vcn_v2_5_start(adev); 1812 1813 if(!ret) 1814 adev->vcn.cur_state = state; 1815 1816 return ret; 1817 } 1818 1819 static int vcn_v2_5_set_interrupt_state(struct amdgpu_device *adev, 1820 struct amdgpu_irq_src *source, 1821 unsigned type, 1822 enum amdgpu_interrupt_state state) 1823 { 1824 return 0; 1825 } 1826 1827 static int vcn_v2_5_process_interrupt(struct amdgpu_device *adev, 1828 struct amdgpu_irq_src *source, 1829 struct amdgpu_iv_entry *entry) 1830 { 1831 uint32_t ip_instance; 1832 1833 switch (entry->client_id) { 1834 case SOC15_IH_CLIENTID_VCN: 1835 ip_instance = 0; 1836 break; 1837 case SOC15_IH_CLIENTID_VCN1: 1838 ip_instance = 1; 1839 break; 1840 default: 1841 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 1842 return 0; 1843 } 1844 1845 DRM_DEBUG("IH: VCN TRAP\n"); 1846 1847 switch (entry->src_id) { 1848 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT: 1849 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec); 1850 break; 1851 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1852 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 1853 break; 1854 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY: 1855 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]); 1856 break; 1857 default: 1858 DRM_ERROR("Unhandled interrupt: %d %d\n", 1859 entry->src_id, entry->src_data[0]); 1860 break; 1861 } 1862 1863 return 0; 1864 } 1865 1866 static const struct amdgpu_irq_src_funcs vcn_v2_5_irq_funcs = { 1867 .set = vcn_v2_5_set_interrupt_state, 1868 .process = vcn_v2_5_process_interrupt, 1869 }; 1870 1871 static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev) 1872 { 1873 int i; 1874 1875 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1876 if (adev->vcn.harvest_config & (1 << i)) 1877 continue; 1878 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1; 1879 adev->vcn.inst[i].irq.funcs = &vcn_v2_5_irq_funcs; 1880 } 1881 } 1882 1883 static const struct amd_ip_funcs vcn_v2_5_ip_funcs = { 1884 .name = "vcn_v2_5", 1885 .early_init = vcn_v2_5_early_init, 1886 .late_init = NULL, 1887 .sw_init = vcn_v2_5_sw_init, 1888 .sw_fini = vcn_v2_5_sw_fini, 1889 .hw_init = vcn_v2_5_hw_init, 1890 .hw_fini = vcn_v2_5_hw_fini, 1891 .suspend = vcn_v2_5_suspend, 1892 .resume = vcn_v2_5_resume, 1893 .is_idle = vcn_v2_5_is_idle, 1894 .wait_for_idle = vcn_v2_5_wait_for_idle, 1895 .check_soft_reset = NULL, 1896 .pre_soft_reset = NULL, 1897 .soft_reset = NULL, 1898 .post_soft_reset = NULL, 1899 .set_clockgating_state = vcn_v2_5_set_clockgating_state, 1900 .set_powergating_state = vcn_v2_5_set_powergating_state, 1901 }; 1902 1903 static const struct amd_ip_funcs vcn_v2_6_ip_funcs = { 1904 .name = "vcn_v2_6", 1905 .early_init = vcn_v2_5_early_init, 1906 .late_init = NULL, 1907 .sw_init = vcn_v2_5_sw_init, 1908 .sw_fini = vcn_v2_5_sw_fini, 1909 .hw_init = vcn_v2_5_hw_init, 1910 .hw_fini = vcn_v2_5_hw_fini, 1911 .suspend = vcn_v2_5_suspend, 1912 .resume = vcn_v2_5_resume, 1913 .is_idle = vcn_v2_5_is_idle, 1914 .wait_for_idle = vcn_v2_5_wait_for_idle, 1915 .check_soft_reset = NULL, 1916 .pre_soft_reset = NULL, 1917 .soft_reset = NULL, 1918 .post_soft_reset = NULL, 1919 .set_clockgating_state = vcn_v2_5_set_clockgating_state, 1920 .set_powergating_state = vcn_v2_5_set_powergating_state, 1921 }; 1922 1923 const struct amdgpu_ip_block_version vcn_v2_5_ip_block = 1924 { 1925 .type = AMD_IP_BLOCK_TYPE_VCN, 1926 .major = 2, 1927 .minor = 5, 1928 .rev = 0, 1929 .funcs = &vcn_v2_5_ip_funcs, 1930 }; 1931 1932 const struct amdgpu_ip_block_version vcn_v2_6_ip_block = 1933 { 1934 .type = AMD_IP_BLOCK_TYPE_VCN, 1935 .major = 2, 1936 .minor = 6, 1937 .rev = 0, 1938 .funcs = &vcn_v2_6_ip_funcs, 1939 }; 1940