1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drm_drv.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_vcn.h" 29 #include "amdgpu_pm.h" 30 #include "soc15.h" 31 #include "soc15d.h" 32 #include "vcn_v2_0.h" 33 #include "mmsch_v1_0.h" 34 #include "vcn_v2_5.h" 35 36 #include "vcn/vcn_2_5_offset.h" 37 #include "vcn/vcn_2_5_sh_mask.h" 38 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 39 40 #define VCN_VID_SOC_ADDRESS_2_0 0x1fa00 41 #define VCN1_VID_SOC_ADDRESS_3_0 0x48200 42 43 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x27 44 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x0f 45 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x10 46 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x11 47 #define mmUVD_NO_OP_INTERNAL_OFFSET 0x29 48 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x66 49 #define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d 50 51 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x431 52 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x3b4 53 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x3b5 54 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x25c 55 56 #define VCN25_MAX_HW_INSTANCES_ARCTURUS 2 57 58 static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev); 59 static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev); 60 static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev); 61 static int vcn_v2_5_set_powergating_state(void *handle, 62 enum amd_powergating_state state); 63 static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev, 64 int inst_idx, struct dpg_pause_state *new_state); 65 static int vcn_v2_5_sriov_start(struct amdgpu_device *adev); 66 static void vcn_v2_5_set_ras_funcs(struct amdgpu_device *adev); 67 68 static int amdgpu_ih_clientid_vcns[] = { 69 SOC15_IH_CLIENTID_VCN, 70 SOC15_IH_CLIENTID_VCN1 71 }; 72 73 /** 74 * vcn_v2_5_early_init - set function pointers and load microcode 75 * 76 * @handle: amdgpu_device pointer 77 * 78 * Set ring and irq function pointers 79 * Load microcode from filesystem 80 */ 81 static int vcn_v2_5_early_init(void *handle) 82 { 83 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 84 85 if (amdgpu_sriov_vf(adev)) { 86 adev->vcn.num_vcn_inst = 2; 87 adev->vcn.harvest_config = 0; 88 adev->vcn.num_enc_rings = 1; 89 } else { 90 u32 harvest; 91 int i; 92 93 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 94 harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING); 95 if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK) 96 adev->vcn.harvest_config |= 1 << i; 97 } 98 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 | 99 AMDGPU_VCN_HARVEST_VCN1)) 100 /* both instances are harvested, disable the block */ 101 return -ENOENT; 102 103 adev->vcn.num_enc_rings = 2; 104 } 105 106 vcn_v2_5_set_dec_ring_funcs(adev); 107 vcn_v2_5_set_enc_ring_funcs(adev); 108 vcn_v2_5_set_irq_funcs(adev); 109 vcn_v2_5_set_ras_funcs(adev); 110 111 return amdgpu_vcn_early_init(adev); 112 } 113 114 /** 115 * vcn_v2_5_sw_init - sw init for VCN block 116 * 117 * @handle: amdgpu_device pointer 118 * 119 * Load firmware and sw initialization 120 */ 121 static int vcn_v2_5_sw_init(void *handle) 122 { 123 struct amdgpu_ring *ring; 124 int i, j, r; 125 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 126 127 for (j = 0; j < adev->vcn.num_vcn_inst; j++) { 128 if (adev->vcn.harvest_config & (1 << j)) 129 continue; 130 /* VCN DEC TRAP */ 131 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j], 132 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[j].irq); 133 if (r) 134 return r; 135 136 /* VCN ENC TRAP */ 137 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 138 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j], 139 i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[j].irq); 140 if (r) 141 return r; 142 } 143 144 /* VCN POISON TRAP */ 145 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j], 146 VCN_2_6__SRCID_UVD_POISON, &adev->vcn.inst[j].irq); 147 if (r) 148 return r; 149 } 150 151 r = amdgpu_vcn_sw_init(adev); 152 if (r) 153 return r; 154 155 amdgpu_vcn_setup_ucode(adev); 156 157 r = amdgpu_vcn_resume(adev); 158 if (r) 159 return r; 160 161 for (j = 0; j < adev->vcn.num_vcn_inst; j++) { 162 volatile struct amdgpu_fw_shared *fw_shared; 163 164 if (adev->vcn.harvest_config & (1 << j)) 165 continue; 166 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; 167 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; 168 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; 169 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; 170 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; 171 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; 172 173 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; 174 adev->vcn.inst[j].external.scratch9 = SOC15_REG_OFFSET(VCN, j, mmUVD_SCRATCH9); 175 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; 176 adev->vcn.inst[j].external.data0 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA0); 177 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; 178 adev->vcn.inst[j].external.data1 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA1); 179 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; 180 adev->vcn.inst[j].external.cmd = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_CMD); 181 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; 182 adev->vcn.inst[j].external.nop = SOC15_REG_OFFSET(VCN, j, mmUVD_NO_OP); 183 184 ring = &adev->vcn.inst[j].ring_dec; 185 ring->use_doorbell = true; 186 187 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 188 (amdgpu_sriov_vf(adev) ? 2*j : 8*j); 189 sprintf(ring->name, "vcn_dec_%d", j); 190 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq, 191 0, AMDGPU_RING_PRIO_DEFAULT, NULL); 192 if (r) 193 return r; 194 195 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 196 enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(i); 197 198 ring = &adev->vcn.inst[j].ring_enc[i]; 199 ring->use_doorbell = true; 200 201 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 202 (amdgpu_sriov_vf(adev) ? (1 + i + 2*j) : (2 + i + 8*j)); 203 204 sprintf(ring->name, "vcn_enc_%d.%d", j, i); 205 r = amdgpu_ring_init(adev, ring, 512, 206 &adev->vcn.inst[j].irq, 0, 207 hw_prio, NULL); 208 if (r) 209 return r; 210 } 211 212 fw_shared = adev->vcn.inst[j].fw_shared.cpu_addr; 213 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG); 214 215 if (amdgpu_vcnfw_log) 216 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]); 217 } 218 219 if (amdgpu_sriov_vf(adev)) { 220 r = amdgpu_virt_alloc_mm_table(adev); 221 if (r) 222 return r; 223 } 224 225 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 226 adev->vcn.pause_dpg_mode = vcn_v2_5_pause_dpg_mode; 227 228 r = amdgpu_vcn_ras_sw_init(adev); 229 if (r) 230 return r; 231 232 return 0; 233 } 234 235 /** 236 * vcn_v2_5_sw_fini - sw fini for VCN block 237 * 238 * @handle: amdgpu_device pointer 239 * 240 * VCN suspend and free up sw allocation 241 */ 242 static int vcn_v2_5_sw_fini(void *handle) 243 { 244 int i, r, idx; 245 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 246 volatile struct amdgpu_fw_shared *fw_shared; 247 248 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 249 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 250 if (adev->vcn.harvest_config & (1 << i)) 251 continue; 252 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 253 fw_shared->present_flag_0 = 0; 254 } 255 drm_dev_exit(idx); 256 } 257 258 259 if (amdgpu_sriov_vf(adev)) 260 amdgpu_virt_free_mm_table(adev); 261 262 r = amdgpu_vcn_suspend(adev); 263 if (r) 264 return r; 265 266 r = amdgpu_vcn_sw_fini(adev); 267 268 return r; 269 } 270 271 /** 272 * vcn_v2_5_hw_init - start and test VCN block 273 * 274 * @handle: amdgpu_device pointer 275 * 276 * Initialize the hardware, boot up the VCPU and do some testing 277 */ 278 static int vcn_v2_5_hw_init(void *handle) 279 { 280 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 281 struct amdgpu_ring *ring; 282 int i, j, r = 0; 283 284 if (amdgpu_sriov_vf(adev)) 285 r = vcn_v2_5_sriov_start(adev); 286 287 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 288 if (adev->vcn.harvest_config & (1 << j)) 289 continue; 290 291 if (amdgpu_sriov_vf(adev)) { 292 adev->vcn.inst[j].ring_enc[0].sched.ready = true; 293 adev->vcn.inst[j].ring_enc[1].sched.ready = false; 294 adev->vcn.inst[j].ring_enc[2].sched.ready = false; 295 adev->vcn.inst[j].ring_dec.sched.ready = true; 296 } else { 297 298 ring = &adev->vcn.inst[j].ring_dec; 299 300 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 301 ring->doorbell_index, j); 302 303 r = amdgpu_ring_test_helper(ring); 304 if (r) 305 goto done; 306 307 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 308 ring = &adev->vcn.inst[j].ring_enc[i]; 309 r = amdgpu_ring_test_helper(ring); 310 if (r) 311 goto done; 312 } 313 } 314 } 315 316 done: 317 if (!r) 318 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 319 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 320 321 return r; 322 } 323 324 /** 325 * vcn_v2_5_hw_fini - stop the hardware block 326 * 327 * @handle: amdgpu_device pointer 328 * 329 * Stop the VCN block, mark ring as not ready any more 330 */ 331 static int vcn_v2_5_hw_fini(void *handle) 332 { 333 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 334 int i; 335 336 cancel_delayed_work_sync(&adev->vcn.idle_work); 337 338 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 339 if (adev->vcn.harvest_config & (1 << i)) 340 continue; 341 342 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 343 (adev->vcn.cur_state != AMD_PG_STATE_GATE && 344 RREG32_SOC15(VCN, i, mmUVD_STATUS))) 345 vcn_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE); 346 } 347 348 return 0; 349 } 350 351 /** 352 * vcn_v2_5_suspend - suspend VCN block 353 * 354 * @handle: amdgpu_device pointer 355 * 356 * HW fini and suspend VCN block 357 */ 358 static int vcn_v2_5_suspend(void *handle) 359 { 360 int r; 361 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 362 363 r = vcn_v2_5_hw_fini(adev); 364 if (r) 365 return r; 366 367 r = amdgpu_vcn_suspend(adev); 368 369 return r; 370 } 371 372 /** 373 * vcn_v2_5_resume - resume VCN block 374 * 375 * @handle: amdgpu_device pointer 376 * 377 * Resume firmware and hw init VCN block 378 */ 379 static int vcn_v2_5_resume(void *handle) 380 { 381 int r; 382 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 383 384 r = amdgpu_vcn_resume(adev); 385 if (r) 386 return r; 387 388 r = vcn_v2_5_hw_init(adev); 389 390 return r; 391 } 392 393 /** 394 * vcn_v2_5_mc_resume - memory controller programming 395 * 396 * @adev: amdgpu_device pointer 397 * 398 * Let the VCN memory controller know it's offsets 399 */ 400 static void vcn_v2_5_mc_resume(struct amdgpu_device *adev) 401 { 402 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 403 uint32_t offset; 404 int i; 405 406 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 407 if (adev->vcn.harvest_config & (1 << i)) 408 continue; 409 /* cache window 0: fw */ 410 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 411 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 412 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo)); 413 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 414 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi)); 415 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, 0); 416 offset = 0; 417 } else { 418 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 419 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 420 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 421 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 422 offset = size; 423 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, 424 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 425 } 426 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE0, size); 427 428 /* cache window 1: stack */ 429 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 430 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset)); 431 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 432 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset)); 433 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET1, 0); 434 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 435 436 /* cache window 2: context */ 437 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 438 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 439 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 440 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 441 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET2, 0); 442 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 443 444 /* non-cache window */ 445 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 446 lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); 447 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 448 upper_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); 449 WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_OFFSET0, 0); 450 WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_SIZE0, 451 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); 452 } 453 } 454 455 static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 456 { 457 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 458 uint32_t offset; 459 460 /* cache window 0: fw */ 461 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 462 if (!indirect) { 463 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 464 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 465 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); 466 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 467 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 468 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); 469 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 470 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 471 } else { 472 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 473 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 474 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 475 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 476 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 477 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 478 } 479 offset = 0; 480 } else { 481 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 482 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 483 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 484 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 485 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 486 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 487 offset = size; 488 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 489 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 490 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 491 } 492 493 if (!indirect) 494 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 495 VCN, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 496 else 497 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 498 VCN, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 499 500 /* cache window 1: stack */ 501 if (!indirect) { 502 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 503 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 504 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 505 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 506 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 507 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 508 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 509 VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 510 } else { 511 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 512 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 513 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 514 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 515 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 516 VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 517 } 518 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 519 VCN, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 520 521 /* cache window 2: context */ 522 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 523 VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 524 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 525 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 526 VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 527 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 528 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 529 VCN, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 530 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 531 VCN, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 532 533 /* non-cache window */ 534 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 535 VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 536 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 537 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 538 VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 539 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 540 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 541 VCN, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 542 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 543 VCN, 0, mmUVD_VCPU_NONCACHE_SIZE0), 544 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); 545 546 /* VCN global tiling registers */ 547 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 548 VCN, 0, mmUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 549 } 550 551 /** 552 * vcn_v2_5_disable_clock_gating - disable VCN clock gating 553 * 554 * @adev: amdgpu_device pointer 555 * 556 * Disable clock gating for VCN block 557 */ 558 static void vcn_v2_5_disable_clock_gating(struct amdgpu_device *adev) 559 { 560 uint32_t data; 561 int i; 562 563 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 564 if (adev->vcn.harvest_config & (1 << i)) 565 continue; 566 /* UVD disable CGC */ 567 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); 568 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 569 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 570 else 571 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 572 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 573 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 574 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); 575 576 data = RREG32_SOC15(VCN, i, mmUVD_CGC_GATE); 577 data &= ~(UVD_CGC_GATE__SYS_MASK 578 | UVD_CGC_GATE__UDEC_MASK 579 | UVD_CGC_GATE__MPEG2_MASK 580 | UVD_CGC_GATE__REGS_MASK 581 | UVD_CGC_GATE__RBC_MASK 582 | UVD_CGC_GATE__LMI_MC_MASK 583 | UVD_CGC_GATE__LMI_UMC_MASK 584 | UVD_CGC_GATE__IDCT_MASK 585 | UVD_CGC_GATE__MPRD_MASK 586 | UVD_CGC_GATE__MPC_MASK 587 | UVD_CGC_GATE__LBSI_MASK 588 | UVD_CGC_GATE__LRBBM_MASK 589 | UVD_CGC_GATE__UDEC_RE_MASK 590 | UVD_CGC_GATE__UDEC_CM_MASK 591 | UVD_CGC_GATE__UDEC_IT_MASK 592 | UVD_CGC_GATE__UDEC_DB_MASK 593 | UVD_CGC_GATE__UDEC_MP_MASK 594 | UVD_CGC_GATE__WCB_MASK 595 | UVD_CGC_GATE__VCPU_MASK 596 | UVD_CGC_GATE__MMSCH_MASK); 597 598 WREG32_SOC15(VCN, i, mmUVD_CGC_GATE, data); 599 600 SOC15_WAIT_ON_RREG(VCN, i, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); 601 602 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); 603 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 604 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 605 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 606 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 607 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 608 | UVD_CGC_CTRL__SYS_MODE_MASK 609 | UVD_CGC_CTRL__UDEC_MODE_MASK 610 | UVD_CGC_CTRL__MPEG2_MODE_MASK 611 | UVD_CGC_CTRL__REGS_MODE_MASK 612 | UVD_CGC_CTRL__RBC_MODE_MASK 613 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 614 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 615 | UVD_CGC_CTRL__IDCT_MODE_MASK 616 | UVD_CGC_CTRL__MPRD_MODE_MASK 617 | UVD_CGC_CTRL__MPC_MODE_MASK 618 | UVD_CGC_CTRL__LBSI_MODE_MASK 619 | UVD_CGC_CTRL__LRBBM_MODE_MASK 620 | UVD_CGC_CTRL__WCB_MODE_MASK 621 | UVD_CGC_CTRL__VCPU_MODE_MASK 622 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 623 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); 624 625 /* turn on */ 626 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE); 627 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 628 | UVD_SUVD_CGC_GATE__SIT_MASK 629 | UVD_SUVD_CGC_GATE__SMP_MASK 630 | UVD_SUVD_CGC_GATE__SCM_MASK 631 | UVD_SUVD_CGC_GATE__SDB_MASK 632 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 633 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 634 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 635 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 636 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 637 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 638 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 639 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 640 | UVD_SUVD_CGC_GATE__SCLR_MASK 641 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 642 | UVD_SUVD_CGC_GATE__ENT_MASK 643 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 644 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 645 | UVD_SUVD_CGC_GATE__SITE_MASK 646 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 647 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 648 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 649 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 650 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 651 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE, data); 652 653 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL); 654 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 655 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 656 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 657 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 658 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 659 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 660 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 661 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 662 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 663 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 664 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data); 665 } 666 } 667 668 static void vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_device *adev, 669 uint8_t sram_sel, int inst_idx, uint8_t indirect) 670 { 671 uint32_t reg_data = 0; 672 673 /* enable sw clock gating control */ 674 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 675 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 676 else 677 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 678 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 679 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 680 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 681 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 682 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 683 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 684 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 685 UVD_CGC_CTRL__SYS_MODE_MASK | 686 UVD_CGC_CTRL__UDEC_MODE_MASK | 687 UVD_CGC_CTRL__MPEG2_MODE_MASK | 688 UVD_CGC_CTRL__REGS_MODE_MASK | 689 UVD_CGC_CTRL__RBC_MODE_MASK | 690 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 691 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 692 UVD_CGC_CTRL__IDCT_MODE_MASK | 693 UVD_CGC_CTRL__MPRD_MODE_MASK | 694 UVD_CGC_CTRL__MPC_MODE_MASK | 695 UVD_CGC_CTRL__LBSI_MODE_MASK | 696 UVD_CGC_CTRL__LRBBM_MODE_MASK | 697 UVD_CGC_CTRL__WCB_MODE_MASK | 698 UVD_CGC_CTRL__VCPU_MODE_MASK | 699 UVD_CGC_CTRL__MMSCH_MODE_MASK); 700 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 701 VCN, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); 702 703 /* turn off clock gating */ 704 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 705 VCN, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect); 706 707 /* turn on SUVD clock gating */ 708 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 709 VCN, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 710 711 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 712 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 713 VCN, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 714 } 715 716 /** 717 * vcn_v2_5_enable_clock_gating - enable VCN clock gating 718 * 719 * @adev: amdgpu_device pointer 720 * 721 * Enable clock gating for VCN block 722 */ 723 static void vcn_v2_5_enable_clock_gating(struct amdgpu_device *adev) 724 { 725 uint32_t data = 0; 726 int i; 727 728 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 729 if (adev->vcn.harvest_config & (1 << i)) 730 continue; 731 /* enable UVD CGC */ 732 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); 733 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 734 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 735 else 736 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 737 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 738 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 739 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); 740 741 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); 742 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 743 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 744 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 745 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 746 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 747 | UVD_CGC_CTRL__SYS_MODE_MASK 748 | UVD_CGC_CTRL__UDEC_MODE_MASK 749 | UVD_CGC_CTRL__MPEG2_MODE_MASK 750 | UVD_CGC_CTRL__REGS_MODE_MASK 751 | UVD_CGC_CTRL__RBC_MODE_MASK 752 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 753 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 754 | UVD_CGC_CTRL__IDCT_MODE_MASK 755 | UVD_CGC_CTRL__MPRD_MODE_MASK 756 | UVD_CGC_CTRL__MPC_MODE_MASK 757 | UVD_CGC_CTRL__LBSI_MODE_MASK 758 | UVD_CGC_CTRL__LRBBM_MODE_MASK 759 | UVD_CGC_CTRL__WCB_MODE_MASK 760 | UVD_CGC_CTRL__VCPU_MODE_MASK); 761 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); 762 763 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL); 764 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 765 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 766 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 767 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 768 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 769 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 770 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 771 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 772 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 773 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 774 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data); 775 } 776 } 777 778 static void vcn_v2_6_enable_ras(struct amdgpu_device *adev, int inst_idx, 779 bool indirect) 780 { 781 uint32_t tmp; 782 783 if (adev->ip_versions[UVD_HWIP][0] != IP_VERSION(2, 6, 0)) 784 return; 785 786 tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK | 787 VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK | 788 VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK | 789 VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK; 790 WREG32_SOC15_DPG_MODE(inst_idx, 791 SOC15_DPG_MODE_OFFSET(VCN, 0, mmVCN_RAS_CNTL), 792 tmp, 0, indirect); 793 794 tmp = UVD_VCPU_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK; 795 WREG32_SOC15_DPG_MODE(inst_idx, 796 SOC15_DPG_MODE_OFFSET(VCN, 0, mmUVD_VCPU_INT_EN), 797 tmp, 0, indirect); 798 799 tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK; 800 WREG32_SOC15_DPG_MODE(inst_idx, 801 SOC15_DPG_MODE_OFFSET(VCN, 0, mmUVD_SYS_INT_EN), 802 tmp, 0, indirect); 803 } 804 805 static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 806 { 807 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 808 struct amdgpu_ring *ring; 809 uint32_t rb_bufsz, tmp; 810 811 /* disable register anti-hang mechanism */ 812 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1, 813 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 814 /* enable dynamic power gating mode */ 815 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS); 816 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 817 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 818 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp); 819 820 if (indirect) 821 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 822 823 /* enable clock gating */ 824 vcn_v2_5_clock_gating_dpg_mode(adev, 0, inst_idx, indirect); 825 826 /* enable VCPU clock */ 827 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 828 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 829 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK; 830 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 831 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); 832 833 /* disable master interupt */ 834 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 835 VCN, 0, mmUVD_MASTINT_EN), 0, 0, indirect); 836 837 /* setup mmUVD_LMI_CTRL */ 838 tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 839 UVD_LMI_CTRL__REQ_MODE_MASK | 840 UVD_LMI_CTRL__CRC_RESET_MASK | 841 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 842 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 843 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 844 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 845 0x00100000L); 846 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 847 VCN, 0, mmUVD_LMI_CTRL), tmp, 0, indirect); 848 849 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 850 VCN, 0, mmUVD_MPC_CNTL), 851 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 852 853 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 854 VCN, 0, mmUVD_MPC_SET_MUXA0), 855 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 856 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 857 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 858 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 859 860 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 861 VCN, 0, mmUVD_MPC_SET_MUXB0), 862 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 863 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 864 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 865 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 866 867 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 868 VCN, 0, mmUVD_MPC_SET_MUX), 869 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 870 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 871 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 872 873 vcn_v2_5_mc_resume_dpg_mode(adev, inst_idx, indirect); 874 875 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 876 VCN, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect); 877 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 878 VCN, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect); 879 880 /* enable LMI MC and UMC channels */ 881 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 882 VCN, 0, mmUVD_LMI_CTRL2), 0, 0, indirect); 883 884 vcn_v2_6_enable_ras(adev, inst_idx, indirect); 885 886 /* unblock VCPU register access */ 887 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 888 VCN, 0, mmUVD_RB_ARB_CTRL), 0, 0, indirect); 889 890 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 891 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 892 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 893 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); 894 895 /* enable master interrupt */ 896 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 897 VCN, 0, mmUVD_MASTINT_EN), 898 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 899 900 if (indirect) 901 psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, 902 (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr - 903 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr)); 904 905 ring = &adev->vcn.inst[inst_idx].ring_dec; 906 /* force RBC into idle state */ 907 rb_bufsz = order_base_2(ring->ring_size); 908 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 909 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 910 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 911 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 912 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 913 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp); 914 915 /* Stall DPG before WPTR/RPTR reset */ 916 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 917 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 918 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 919 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET; 920 921 /* set the write pointer delay */ 922 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0); 923 924 /* set the wb address */ 925 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR, 926 (upper_32_bits(ring->gpu_addr) >> 2)); 927 928 /* program the RB_BASE for ring buffer */ 929 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 930 lower_32_bits(ring->gpu_addr)); 931 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 932 upper_32_bits(ring->gpu_addr)); 933 934 /* Initialize the ring buffer's read and write pointers */ 935 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0); 936 937 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0); 938 939 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR); 940 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, 941 lower_32_bits(ring->wptr)); 942 943 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET; 944 /* Unstall DPG */ 945 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 946 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 947 948 return 0; 949 } 950 951 static int vcn_v2_5_start(struct amdgpu_device *adev) 952 { 953 struct amdgpu_ring *ring; 954 uint32_t rb_bufsz, tmp; 955 int i, j, k, r; 956 957 if (adev->pm.dpm_enabled) 958 amdgpu_dpm_enable_uvd(adev, true); 959 960 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 961 if (adev->vcn.harvest_config & (1 << i)) 962 continue; 963 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 964 r = vcn_v2_5_start_dpg_mode(adev, i, adev->vcn.indirect_sram); 965 continue; 966 } 967 968 /* disable register anti-hang mechanism */ 969 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), 0, 970 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 971 972 /* set uvd status busy */ 973 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 974 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp); 975 } 976 977 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 978 return 0; 979 980 /*SW clock gating */ 981 vcn_v2_5_disable_clock_gating(adev); 982 983 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 984 if (adev->vcn.harvest_config & (1 << i)) 985 continue; 986 /* enable VCPU clock */ 987 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 988 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 989 990 /* disable master interrupt */ 991 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0, 992 ~UVD_MASTINT_EN__VCPU_EN_MASK); 993 994 /* setup mmUVD_LMI_CTRL */ 995 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL); 996 tmp &= ~0xff; 997 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | 0x8| 998 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 999 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1000 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1001 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1002 1003 /* setup mmUVD_MPC_CNTL */ 1004 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL); 1005 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1006 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1007 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp); 1008 1009 /* setup UVD_MPC_SET_MUXA0 */ 1010 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0, 1011 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1012 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1013 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1014 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1015 1016 /* setup UVD_MPC_SET_MUXB0 */ 1017 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0, 1018 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1019 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1020 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1021 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1022 1023 /* setup mmUVD_MPC_SET_MUX */ 1024 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX, 1025 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1026 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1027 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1028 } 1029 1030 vcn_v2_5_mc_resume(adev); 1031 1032 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1033 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1034 if (adev->vcn.harvest_config & (1 << i)) 1035 continue; 1036 /* VCN global tiling registers */ 1037 WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG, 1038 adev->gfx.config.gb_addr_config); 1039 WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG, 1040 adev->gfx.config.gb_addr_config); 1041 1042 /* enable LMI MC and UMC channels */ 1043 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0, 1044 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1045 1046 /* unblock VCPU register access */ 1047 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0, 1048 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1049 1050 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1051 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1052 1053 for (k = 0; k < 10; ++k) { 1054 uint32_t status; 1055 1056 for (j = 0; j < 100; ++j) { 1057 status = RREG32_SOC15(VCN, i, mmUVD_STATUS); 1058 if (status & 2) 1059 break; 1060 if (amdgpu_emu_mode == 1) 1061 msleep(500); 1062 else 1063 mdelay(10); 1064 } 1065 r = 0; 1066 if (status & 2) 1067 break; 1068 1069 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n"); 1070 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1071 UVD_VCPU_CNTL__BLK_RST_MASK, 1072 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1073 mdelay(10); 1074 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1075 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1076 1077 mdelay(10); 1078 r = -1; 1079 } 1080 1081 if (r) { 1082 DRM_ERROR("VCN decode not responding, giving up!!!\n"); 1083 return r; 1084 } 1085 1086 /* enable master interrupt */ 1087 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 1088 UVD_MASTINT_EN__VCPU_EN_MASK, 1089 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1090 1091 /* clear the busy bit of VCN_STATUS */ 1092 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0, 1093 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1094 1095 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0); 1096 1097 ring = &adev->vcn.inst[i].ring_dec; 1098 /* force RBC into idle state */ 1099 rb_bufsz = order_base_2(ring->ring_size); 1100 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1101 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1102 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1103 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1104 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1105 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp); 1106 1107 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET; 1108 /* program the RB_BASE for ring buffer */ 1109 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1110 lower_32_bits(ring->gpu_addr)); 1111 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1112 upper_32_bits(ring->gpu_addr)); 1113 1114 /* Initialize the ring buffer's read and write pointers */ 1115 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0); 1116 1117 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR); 1118 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR, 1119 lower_32_bits(ring->wptr)); 1120 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET; 1121 1122 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET; 1123 ring = &adev->vcn.inst[i].ring_enc[0]; 1124 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1125 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1126 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr); 1127 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1128 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4); 1129 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET; 1130 1131 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET; 1132 ring = &adev->vcn.inst[i].ring_enc[1]; 1133 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1134 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1135 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1136 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1137 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4); 1138 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET; 1139 } 1140 1141 return 0; 1142 } 1143 1144 static int vcn_v2_5_mmsch_start(struct amdgpu_device *adev, 1145 struct amdgpu_mm_table *table) 1146 { 1147 uint32_t data = 0, loop = 0, size = 0; 1148 uint64_t addr = table->gpu_addr; 1149 struct mmsch_v1_1_init_header *header = NULL; 1150 1151 header = (struct mmsch_v1_1_init_header *)table->cpu_addr; 1152 size = header->total_size; 1153 1154 /* 1155 * 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr of 1156 * memory descriptor location 1157 */ 1158 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr)); 1159 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr)); 1160 1161 /* 2, update vmid of descriptor */ 1162 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID); 1163 data &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1164 /* use domain0 for MM scheduler */ 1165 data |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1166 WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, data); 1167 1168 /* 3, notify mmsch about the size of this descriptor */ 1169 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size); 1170 1171 /* 4, set resp to zero */ 1172 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0); 1173 1174 /* 1175 * 5, kick off the initialization and wait until 1176 * VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero 1177 */ 1178 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, 0x10000001); 1179 1180 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); 1181 loop = 10; 1182 while ((data & 0x10000002) != 0x10000002) { 1183 udelay(100); 1184 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); 1185 loop--; 1186 if (!loop) 1187 break; 1188 } 1189 1190 if (!loop) { 1191 dev_err(adev->dev, 1192 "failed to init MMSCH, mmMMSCH_VF_MAILBOX_RESP = %x\n", 1193 data); 1194 return -EBUSY; 1195 } 1196 1197 return 0; 1198 } 1199 1200 static int vcn_v2_5_sriov_start(struct amdgpu_device *adev) 1201 { 1202 struct amdgpu_ring *ring; 1203 uint32_t offset, size, tmp, i, rb_bufsz; 1204 uint32_t table_size = 0; 1205 struct mmsch_v1_0_cmd_direct_write direct_wt = { { 0 } }; 1206 struct mmsch_v1_0_cmd_direct_read_modify_write direct_rd_mod_wt = { { 0 } }; 1207 struct mmsch_v1_0_cmd_end end = { { 0 } }; 1208 uint32_t *init_table = adev->virt.mm_table.cpu_addr; 1209 struct mmsch_v1_1_init_header *header = (struct mmsch_v1_1_init_header *)init_table; 1210 1211 direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE; 1212 direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1213 end.cmd_header.command_type = MMSCH_COMMAND__END; 1214 1215 header->version = MMSCH_VERSION; 1216 header->total_size = sizeof(struct mmsch_v1_1_init_header) >> 2; 1217 init_table += header->total_size; 1218 1219 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1220 header->eng[i].table_offset = header->total_size; 1221 header->eng[i].init_status = 0; 1222 header->eng[i].table_size = 0; 1223 1224 table_size = 0; 1225 1226 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT( 1227 SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 1228 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 1229 1230 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 1231 /* mc resume*/ 1232 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1233 MMSCH_V1_0_INSERT_DIRECT_WT( 1234 SOC15_REG_OFFSET(VCN, i, 1235 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1236 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo); 1237 MMSCH_V1_0_INSERT_DIRECT_WT( 1238 SOC15_REG_OFFSET(VCN, i, 1239 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1240 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi); 1241 offset = 0; 1242 MMSCH_V1_0_INSERT_DIRECT_WT( 1243 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0), 0); 1244 } else { 1245 MMSCH_V1_0_INSERT_DIRECT_WT( 1246 SOC15_REG_OFFSET(VCN, i, 1247 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1248 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 1249 MMSCH_V1_0_INSERT_DIRECT_WT( 1250 SOC15_REG_OFFSET(VCN, i, 1251 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1252 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 1253 offset = size; 1254 MMSCH_V1_0_INSERT_DIRECT_WT( 1255 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0), 1256 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 1257 } 1258 1259 MMSCH_V1_0_INSERT_DIRECT_WT( 1260 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE0), 1261 size); 1262 MMSCH_V1_0_INSERT_DIRECT_WT( 1263 SOC15_REG_OFFSET(VCN, i, 1264 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 1265 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset)); 1266 MMSCH_V1_0_INSERT_DIRECT_WT( 1267 SOC15_REG_OFFSET(VCN, i, 1268 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 1269 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset)); 1270 MMSCH_V1_0_INSERT_DIRECT_WT( 1271 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET1), 1272 0); 1273 MMSCH_V1_0_INSERT_DIRECT_WT( 1274 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE1), 1275 AMDGPU_VCN_STACK_SIZE); 1276 MMSCH_V1_0_INSERT_DIRECT_WT( 1277 SOC15_REG_OFFSET(VCN, i, 1278 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 1279 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + 1280 AMDGPU_VCN_STACK_SIZE)); 1281 MMSCH_V1_0_INSERT_DIRECT_WT( 1282 SOC15_REG_OFFSET(VCN, i, 1283 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 1284 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + 1285 AMDGPU_VCN_STACK_SIZE)); 1286 MMSCH_V1_0_INSERT_DIRECT_WT( 1287 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET2), 1288 0); 1289 MMSCH_V1_0_INSERT_DIRECT_WT( 1290 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE2), 1291 AMDGPU_VCN_CONTEXT_SIZE); 1292 1293 ring = &adev->vcn.inst[i].ring_enc[0]; 1294 ring->wptr = 0; 1295 1296 MMSCH_V1_0_INSERT_DIRECT_WT( 1297 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_LO), 1298 lower_32_bits(ring->gpu_addr)); 1299 MMSCH_V1_0_INSERT_DIRECT_WT( 1300 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_HI), 1301 upper_32_bits(ring->gpu_addr)); 1302 MMSCH_V1_0_INSERT_DIRECT_WT( 1303 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_SIZE), 1304 ring->ring_size / 4); 1305 1306 ring = &adev->vcn.inst[i].ring_dec; 1307 ring->wptr = 0; 1308 MMSCH_V1_0_INSERT_DIRECT_WT( 1309 SOC15_REG_OFFSET(VCN, i, 1310 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW), 1311 lower_32_bits(ring->gpu_addr)); 1312 MMSCH_V1_0_INSERT_DIRECT_WT( 1313 SOC15_REG_OFFSET(VCN, i, 1314 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH), 1315 upper_32_bits(ring->gpu_addr)); 1316 1317 /* force RBC into idle state */ 1318 rb_bufsz = order_base_2(ring->ring_size); 1319 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1320 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1321 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1322 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1323 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1324 MMSCH_V1_0_INSERT_DIRECT_WT( 1325 SOC15_REG_OFFSET(VCN, i, mmUVD_RBC_RB_CNTL), tmp); 1326 1327 /* add end packet */ 1328 memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end)); 1329 table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4; 1330 init_table += sizeof(struct mmsch_v1_0_cmd_end) / 4; 1331 1332 /* refine header */ 1333 header->eng[i].table_size = table_size; 1334 header->total_size += table_size; 1335 } 1336 1337 return vcn_v2_5_mmsch_start(adev, &adev->virt.mm_table); 1338 } 1339 1340 static int vcn_v2_5_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) 1341 { 1342 uint32_t tmp; 1343 1344 /* Wait for power status to be 1 */ 1345 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1346 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1347 1348 /* wait for read ptr to be equal to write ptr */ 1349 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR); 1350 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1351 1352 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2); 1353 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); 1354 1355 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1356 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); 1357 1358 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1359 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1360 1361 /* disable dynamic power gating mode */ 1362 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0, 1363 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1364 1365 return 0; 1366 } 1367 1368 static int vcn_v2_5_stop(struct amdgpu_device *adev) 1369 { 1370 uint32_t tmp; 1371 int i, r = 0; 1372 1373 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1374 if (adev->vcn.harvest_config & (1 << i)) 1375 continue; 1376 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1377 r = vcn_v2_5_stop_dpg_mode(adev, i); 1378 continue; 1379 } 1380 1381 /* wait for vcn idle */ 1382 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1383 if (r) 1384 return r; 1385 1386 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1387 UVD_LMI_STATUS__READ_CLEAN_MASK | 1388 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1389 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1390 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1391 if (r) 1392 return r; 1393 1394 /* block LMI UMC channel */ 1395 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2); 1396 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1397 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp); 1398 1399 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK| 1400 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1401 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1402 if (r) 1403 return r; 1404 1405 /* block VCPU register access */ 1406 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 1407 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1408 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1409 1410 /* reset VCPU */ 1411 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1412 UVD_VCPU_CNTL__BLK_RST_MASK, 1413 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1414 1415 /* disable VCPU clock */ 1416 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1417 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1418 1419 /* clear status */ 1420 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0); 1421 1422 vcn_v2_5_enable_clock_gating(adev); 1423 1424 /* enable register anti-hang mechanism */ 1425 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), 1426 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, 1427 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1428 } 1429 1430 if (adev->pm.dpm_enabled) 1431 amdgpu_dpm_enable_uvd(adev, false); 1432 1433 return 0; 1434 } 1435 1436 static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev, 1437 int inst_idx, struct dpg_pause_state *new_state) 1438 { 1439 struct amdgpu_ring *ring; 1440 uint32_t reg_data = 0; 1441 int ret_code = 0; 1442 1443 /* pause/unpause if state is changed */ 1444 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1445 DRM_DEBUG("dpg pause state changed %d -> %d", 1446 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1447 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) & 1448 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1449 1450 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1451 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, 1452 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1453 1454 if (!ret_code) { 1455 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 1456 1457 /* pause DPG */ 1458 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1459 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1460 1461 /* wait for ACK */ 1462 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE, 1463 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1464 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1465 1466 /* Stall DPG before WPTR/RPTR reset */ 1467 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1468 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1469 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1470 1471 /* Restore */ 1472 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET; 1473 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 1474 ring->wptr = 0; 1475 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr); 1476 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1477 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4); 1478 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1479 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1480 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET; 1481 1482 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET; 1483 ring = &adev->vcn.inst[inst_idx].ring_enc[1]; 1484 ring->wptr = 0; 1485 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1486 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1487 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4); 1488 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1489 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1490 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET; 1491 1492 /* Unstall DPG */ 1493 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1494 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1495 1496 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1497 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1498 } 1499 } else { 1500 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1501 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1502 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, 1503 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1504 } 1505 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1506 } 1507 1508 return 0; 1509 } 1510 1511 /** 1512 * vcn_v2_5_dec_ring_get_rptr - get read pointer 1513 * 1514 * @ring: amdgpu_ring pointer 1515 * 1516 * Returns the current hardware read pointer 1517 */ 1518 static uint64_t vcn_v2_5_dec_ring_get_rptr(struct amdgpu_ring *ring) 1519 { 1520 struct amdgpu_device *adev = ring->adev; 1521 1522 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR); 1523 } 1524 1525 /** 1526 * vcn_v2_5_dec_ring_get_wptr - get write pointer 1527 * 1528 * @ring: amdgpu_ring pointer 1529 * 1530 * Returns the current hardware write pointer 1531 */ 1532 static uint64_t vcn_v2_5_dec_ring_get_wptr(struct amdgpu_ring *ring) 1533 { 1534 struct amdgpu_device *adev = ring->adev; 1535 1536 if (ring->use_doorbell) 1537 return *ring->wptr_cpu_addr; 1538 else 1539 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR); 1540 } 1541 1542 /** 1543 * vcn_v2_5_dec_ring_set_wptr - set write pointer 1544 * 1545 * @ring: amdgpu_ring pointer 1546 * 1547 * Commits the write pointer to the hardware 1548 */ 1549 static void vcn_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring) 1550 { 1551 struct amdgpu_device *adev = ring->adev; 1552 1553 if (ring->use_doorbell) { 1554 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1555 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1556 } else { 1557 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1558 } 1559 } 1560 1561 static const struct amdgpu_ring_funcs vcn_v2_5_dec_ring_vm_funcs = { 1562 .type = AMDGPU_RING_TYPE_VCN_DEC, 1563 .align_mask = 0xf, 1564 .secure_submission_supported = true, 1565 .vmhub = AMDGPU_MMHUB_1, 1566 .get_rptr = vcn_v2_5_dec_ring_get_rptr, 1567 .get_wptr = vcn_v2_5_dec_ring_get_wptr, 1568 .set_wptr = vcn_v2_5_dec_ring_set_wptr, 1569 .emit_frame_size = 1570 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1571 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1572 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */ 1573 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */ 1574 6, 1575 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */ 1576 .emit_ib = vcn_v2_0_dec_ring_emit_ib, 1577 .emit_fence = vcn_v2_0_dec_ring_emit_fence, 1578 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush, 1579 .test_ring = vcn_v2_0_dec_ring_test_ring, 1580 .test_ib = amdgpu_vcn_dec_ring_test_ib, 1581 .insert_nop = vcn_v2_0_dec_ring_insert_nop, 1582 .insert_start = vcn_v2_0_dec_ring_insert_start, 1583 .insert_end = vcn_v2_0_dec_ring_insert_end, 1584 .pad_ib = amdgpu_ring_generic_pad_ib, 1585 .begin_use = amdgpu_vcn_ring_begin_use, 1586 .end_use = amdgpu_vcn_ring_end_use, 1587 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg, 1588 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait, 1589 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1590 }; 1591 1592 static const struct amdgpu_ring_funcs vcn_v2_6_dec_ring_vm_funcs = { 1593 .type = AMDGPU_RING_TYPE_VCN_DEC, 1594 .align_mask = 0xf, 1595 .secure_submission_supported = true, 1596 .vmhub = AMDGPU_MMHUB_0, 1597 .get_rptr = vcn_v2_5_dec_ring_get_rptr, 1598 .get_wptr = vcn_v2_5_dec_ring_get_wptr, 1599 .set_wptr = vcn_v2_5_dec_ring_set_wptr, 1600 .emit_frame_size = 1601 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1602 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1603 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */ 1604 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */ 1605 6, 1606 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */ 1607 .emit_ib = vcn_v2_0_dec_ring_emit_ib, 1608 .emit_fence = vcn_v2_0_dec_ring_emit_fence, 1609 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush, 1610 .test_ring = vcn_v2_0_dec_ring_test_ring, 1611 .test_ib = amdgpu_vcn_dec_ring_test_ib, 1612 .insert_nop = vcn_v2_0_dec_ring_insert_nop, 1613 .insert_start = vcn_v2_0_dec_ring_insert_start, 1614 .insert_end = vcn_v2_0_dec_ring_insert_end, 1615 .pad_ib = amdgpu_ring_generic_pad_ib, 1616 .begin_use = amdgpu_vcn_ring_begin_use, 1617 .end_use = amdgpu_vcn_ring_end_use, 1618 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg, 1619 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait, 1620 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1621 }; 1622 1623 /** 1624 * vcn_v2_5_enc_ring_get_rptr - get enc read pointer 1625 * 1626 * @ring: amdgpu_ring pointer 1627 * 1628 * Returns the current hardware enc read pointer 1629 */ 1630 static uint64_t vcn_v2_5_enc_ring_get_rptr(struct amdgpu_ring *ring) 1631 { 1632 struct amdgpu_device *adev = ring->adev; 1633 1634 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) 1635 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR); 1636 else 1637 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2); 1638 } 1639 1640 /** 1641 * vcn_v2_5_enc_ring_get_wptr - get enc write pointer 1642 * 1643 * @ring: amdgpu_ring pointer 1644 * 1645 * Returns the current hardware enc write pointer 1646 */ 1647 static uint64_t vcn_v2_5_enc_ring_get_wptr(struct amdgpu_ring *ring) 1648 { 1649 struct amdgpu_device *adev = ring->adev; 1650 1651 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 1652 if (ring->use_doorbell) 1653 return *ring->wptr_cpu_addr; 1654 else 1655 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR); 1656 } else { 1657 if (ring->use_doorbell) 1658 return *ring->wptr_cpu_addr; 1659 else 1660 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2); 1661 } 1662 } 1663 1664 /** 1665 * vcn_v2_5_enc_ring_set_wptr - set enc write pointer 1666 * 1667 * @ring: amdgpu_ring pointer 1668 * 1669 * Commits the enc write pointer to the hardware 1670 */ 1671 static void vcn_v2_5_enc_ring_set_wptr(struct amdgpu_ring *ring) 1672 { 1673 struct amdgpu_device *adev = ring->adev; 1674 1675 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 1676 if (ring->use_doorbell) { 1677 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1678 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1679 } else { 1680 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1681 } 1682 } else { 1683 if (ring->use_doorbell) { 1684 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1685 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1686 } else { 1687 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1688 } 1689 } 1690 } 1691 1692 static const struct amdgpu_ring_funcs vcn_v2_5_enc_ring_vm_funcs = { 1693 .type = AMDGPU_RING_TYPE_VCN_ENC, 1694 .align_mask = 0x3f, 1695 .nop = VCN_ENC_CMD_NO_OP, 1696 .vmhub = AMDGPU_MMHUB_1, 1697 .get_rptr = vcn_v2_5_enc_ring_get_rptr, 1698 .get_wptr = vcn_v2_5_enc_ring_get_wptr, 1699 .set_wptr = vcn_v2_5_enc_ring_set_wptr, 1700 .emit_frame_size = 1701 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1702 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1703 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1704 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1705 1, /* vcn_v2_0_enc_ring_insert_end */ 1706 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1707 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1708 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1709 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 1710 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1711 .test_ib = amdgpu_vcn_enc_ring_test_ib, 1712 .insert_nop = amdgpu_ring_insert_nop, 1713 .insert_end = vcn_v2_0_enc_ring_insert_end, 1714 .pad_ib = amdgpu_ring_generic_pad_ib, 1715 .begin_use = amdgpu_vcn_ring_begin_use, 1716 .end_use = amdgpu_vcn_ring_end_use, 1717 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 1718 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 1719 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1720 }; 1721 1722 static const struct amdgpu_ring_funcs vcn_v2_6_enc_ring_vm_funcs = { 1723 .type = AMDGPU_RING_TYPE_VCN_ENC, 1724 .align_mask = 0x3f, 1725 .nop = VCN_ENC_CMD_NO_OP, 1726 .vmhub = AMDGPU_MMHUB_0, 1727 .get_rptr = vcn_v2_5_enc_ring_get_rptr, 1728 .get_wptr = vcn_v2_5_enc_ring_get_wptr, 1729 .set_wptr = vcn_v2_5_enc_ring_set_wptr, 1730 .emit_frame_size = 1731 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1732 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1733 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1734 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1735 1, /* vcn_v2_0_enc_ring_insert_end */ 1736 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1737 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1738 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1739 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 1740 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1741 .test_ib = amdgpu_vcn_enc_ring_test_ib, 1742 .insert_nop = amdgpu_ring_insert_nop, 1743 .insert_end = vcn_v2_0_enc_ring_insert_end, 1744 .pad_ib = amdgpu_ring_generic_pad_ib, 1745 .begin_use = amdgpu_vcn_ring_begin_use, 1746 .end_use = amdgpu_vcn_ring_end_use, 1747 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 1748 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 1749 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1750 }; 1751 1752 static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev) 1753 { 1754 int i; 1755 1756 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1757 if (adev->vcn.harvest_config & (1 << i)) 1758 continue; 1759 if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(2, 5, 0)) 1760 adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs; 1761 else /* CHIP_ALDEBARAN */ 1762 adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_6_dec_ring_vm_funcs; 1763 adev->vcn.inst[i].ring_dec.me = i; 1764 DRM_INFO("VCN(%d) decode is enabled in VM mode\n", i); 1765 } 1766 } 1767 1768 static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev) 1769 { 1770 int i, j; 1771 1772 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 1773 if (adev->vcn.harvest_config & (1 << j)) 1774 continue; 1775 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 1776 if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(2, 5, 0)) 1777 adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs; 1778 else /* CHIP_ALDEBARAN */ 1779 adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_6_enc_ring_vm_funcs; 1780 adev->vcn.inst[j].ring_enc[i].me = j; 1781 } 1782 DRM_INFO("VCN(%d) encode is enabled in VM mode\n", j); 1783 } 1784 } 1785 1786 static bool vcn_v2_5_is_idle(void *handle) 1787 { 1788 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1789 int i, ret = 1; 1790 1791 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1792 if (adev->vcn.harvest_config & (1 << i)) 1793 continue; 1794 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); 1795 } 1796 1797 return ret; 1798 } 1799 1800 static int vcn_v2_5_wait_for_idle(void *handle) 1801 { 1802 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1803 int i, ret = 0; 1804 1805 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1806 if (adev->vcn.harvest_config & (1 << i)) 1807 continue; 1808 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 1809 UVD_STATUS__IDLE); 1810 if (ret) 1811 return ret; 1812 } 1813 1814 return ret; 1815 } 1816 1817 static int vcn_v2_5_set_clockgating_state(void *handle, 1818 enum amd_clockgating_state state) 1819 { 1820 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1821 bool enable = (state == AMD_CG_STATE_GATE); 1822 1823 if (amdgpu_sriov_vf(adev)) 1824 return 0; 1825 1826 if (enable) { 1827 if (!vcn_v2_5_is_idle(handle)) 1828 return -EBUSY; 1829 vcn_v2_5_enable_clock_gating(adev); 1830 } else { 1831 vcn_v2_5_disable_clock_gating(adev); 1832 } 1833 1834 return 0; 1835 } 1836 1837 static int vcn_v2_5_set_powergating_state(void *handle, 1838 enum amd_powergating_state state) 1839 { 1840 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1841 int ret; 1842 1843 if (amdgpu_sriov_vf(adev)) 1844 return 0; 1845 1846 if(state == adev->vcn.cur_state) 1847 return 0; 1848 1849 if (state == AMD_PG_STATE_GATE) 1850 ret = vcn_v2_5_stop(adev); 1851 else 1852 ret = vcn_v2_5_start(adev); 1853 1854 if(!ret) 1855 adev->vcn.cur_state = state; 1856 1857 return ret; 1858 } 1859 1860 static int vcn_v2_5_set_interrupt_state(struct amdgpu_device *adev, 1861 struct amdgpu_irq_src *source, 1862 unsigned type, 1863 enum amdgpu_interrupt_state state) 1864 { 1865 return 0; 1866 } 1867 1868 static int vcn_v2_5_process_interrupt(struct amdgpu_device *adev, 1869 struct amdgpu_irq_src *source, 1870 struct amdgpu_iv_entry *entry) 1871 { 1872 uint32_t ip_instance; 1873 1874 switch (entry->client_id) { 1875 case SOC15_IH_CLIENTID_VCN: 1876 ip_instance = 0; 1877 break; 1878 case SOC15_IH_CLIENTID_VCN1: 1879 ip_instance = 1; 1880 break; 1881 default: 1882 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 1883 return 0; 1884 } 1885 1886 DRM_DEBUG("IH: VCN TRAP\n"); 1887 1888 switch (entry->src_id) { 1889 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT: 1890 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec); 1891 break; 1892 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1893 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 1894 break; 1895 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY: 1896 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]); 1897 break; 1898 case VCN_2_6__SRCID_UVD_POISON: 1899 amdgpu_vcn_process_poison_irq(adev, source, entry); 1900 break; 1901 default: 1902 DRM_ERROR("Unhandled interrupt: %d %d\n", 1903 entry->src_id, entry->src_data[0]); 1904 break; 1905 } 1906 1907 return 0; 1908 } 1909 1910 static const struct amdgpu_irq_src_funcs vcn_v2_5_irq_funcs = { 1911 .set = vcn_v2_5_set_interrupt_state, 1912 .process = vcn_v2_5_process_interrupt, 1913 }; 1914 1915 static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev) 1916 { 1917 int i; 1918 1919 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1920 if (adev->vcn.harvest_config & (1 << i)) 1921 continue; 1922 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1; 1923 adev->vcn.inst[i].irq.funcs = &vcn_v2_5_irq_funcs; 1924 } 1925 } 1926 1927 static const struct amd_ip_funcs vcn_v2_5_ip_funcs = { 1928 .name = "vcn_v2_5", 1929 .early_init = vcn_v2_5_early_init, 1930 .late_init = NULL, 1931 .sw_init = vcn_v2_5_sw_init, 1932 .sw_fini = vcn_v2_5_sw_fini, 1933 .hw_init = vcn_v2_5_hw_init, 1934 .hw_fini = vcn_v2_5_hw_fini, 1935 .suspend = vcn_v2_5_suspend, 1936 .resume = vcn_v2_5_resume, 1937 .is_idle = vcn_v2_5_is_idle, 1938 .wait_for_idle = vcn_v2_5_wait_for_idle, 1939 .check_soft_reset = NULL, 1940 .pre_soft_reset = NULL, 1941 .soft_reset = NULL, 1942 .post_soft_reset = NULL, 1943 .set_clockgating_state = vcn_v2_5_set_clockgating_state, 1944 .set_powergating_state = vcn_v2_5_set_powergating_state, 1945 }; 1946 1947 static const struct amd_ip_funcs vcn_v2_6_ip_funcs = { 1948 .name = "vcn_v2_6", 1949 .early_init = vcn_v2_5_early_init, 1950 .late_init = NULL, 1951 .sw_init = vcn_v2_5_sw_init, 1952 .sw_fini = vcn_v2_5_sw_fini, 1953 .hw_init = vcn_v2_5_hw_init, 1954 .hw_fini = vcn_v2_5_hw_fini, 1955 .suspend = vcn_v2_5_suspend, 1956 .resume = vcn_v2_5_resume, 1957 .is_idle = vcn_v2_5_is_idle, 1958 .wait_for_idle = vcn_v2_5_wait_for_idle, 1959 .check_soft_reset = NULL, 1960 .pre_soft_reset = NULL, 1961 .soft_reset = NULL, 1962 .post_soft_reset = NULL, 1963 .set_clockgating_state = vcn_v2_5_set_clockgating_state, 1964 .set_powergating_state = vcn_v2_5_set_powergating_state, 1965 }; 1966 1967 const struct amdgpu_ip_block_version vcn_v2_5_ip_block = 1968 { 1969 .type = AMD_IP_BLOCK_TYPE_VCN, 1970 .major = 2, 1971 .minor = 5, 1972 .rev = 0, 1973 .funcs = &vcn_v2_5_ip_funcs, 1974 }; 1975 1976 const struct amdgpu_ip_block_version vcn_v2_6_ip_block = 1977 { 1978 .type = AMD_IP_BLOCK_TYPE_VCN, 1979 .major = 2, 1980 .minor = 6, 1981 .rev = 0, 1982 .funcs = &vcn_v2_6_ip_funcs, 1983 }; 1984 1985 static uint32_t vcn_v2_6_query_poison_by_instance(struct amdgpu_device *adev, 1986 uint32_t instance, uint32_t sub_block) 1987 { 1988 uint32_t poison_stat = 0, reg_value = 0; 1989 1990 switch (sub_block) { 1991 case AMDGPU_VCN_V2_6_VCPU_VCODEC: 1992 reg_value = RREG32_SOC15(VCN, instance, mmUVD_RAS_VCPU_VCODEC_STATUS); 1993 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF); 1994 break; 1995 default: 1996 break; 1997 } 1998 1999 if (poison_stat) 2000 dev_info(adev->dev, "Poison detected in VCN%d, sub_block%d\n", 2001 instance, sub_block); 2002 2003 return poison_stat; 2004 } 2005 2006 static bool vcn_v2_6_query_poison_status(struct amdgpu_device *adev) 2007 { 2008 uint32_t inst, sub; 2009 uint32_t poison_stat = 0; 2010 2011 for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++) 2012 for (sub = 0; sub < AMDGPU_VCN_V2_6_MAX_SUB_BLOCK; sub++) 2013 poison_stat += 2014 vcn_v2_6_query_poison_by_instance(adev, inst, sub); 2015 2016 return !!poison_stat; 2017 } 2018 2019 const struct amdgpu_ras_block_hw_ops vcn_v2_6_ras_hw_ops = { 2020 .query_poison_status = vcn_v2_6_query_poison_status, 2021 }; 2022 2023 static struct amdgpu_vcn_ras vcn_v2_6_ras = { 2024 .ras_block = { 2025 .hw_ops = &vcn_v2_6_ras_hw_ops, 2026 }, 2027 }; 2028 2029 static void vcn_v2_5_set_ras_funcs(struct amdgpu_device *adev) 2030 { 2031 switch (adev->ip_versions[VCN_HWIP][0]) { 2032 case IP_VERSION(2, 6, 0): 2033 adev->vcn.ras = &vcn_v2_6_ras; 2034 break; 2035 default: 2036 break; 2037 } 2038 } 2039