1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drm_drv.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_vcn.h" 29 #include "amdgpu_pm.h" 30 #include "soc15.h" 31 #include "soc15d.h" 32 #include "vcn_v2_0.h" 33 #include "mmsch_v1_0.h" 34 #include "vcn_v2_5.h" 35 36 #include "vcn/vcn_2_5_offset.h" 37 #include "vcn/vcn_2_5_sh_mask.h" 38 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 39 40 #define VCN_VID_SOC_ADDRESS_2_0 0x1fa00 41 #define VCN1_VID_SOC_ADDRESS_3_0 0x48200 42 43 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x27 44 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x0f 45 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x10 46 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x11 47 #define mmUVD_NO_OP_INTERNAL_OFFSET 0x29 48 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x66 49 #define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d 50 51 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x431 52 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x3b4 53 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x3b5 54 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x25c 55 56 #define VCN25_MAX_HW_INSTANCES_ARCTURUS 2 57 58 static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev); 59 static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev); 60 static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev); 61 static int vcn_v2_5_set_powergating_state(void *handle, 62 enum amd_powergating_state state); 63 static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev, 64 int inst_idx, struct dpg_pause_state *new_state); 65 static int vcn_v2_5_sriov_start(struct amdgpu_device *adev); 66 static void vcn_v2_5_set_ras_funcs(struct amdgpu_device *adev); 67 68 static int amdgpu_ih_clientid_vcns[] = { 69 SOC15_IH_CLIENTID_VCN, 70 SOC15_IH_CLIENTID_VCN1 71 }; 72 73 /** 74 * vcn_v2_5_early_init - set function pointers 75 * 76 * @handle: amdgpu_device pointer 77 * 78 * Set ring and irq function pointers 79 */ 80 static int vcn_v2_5_early_init(void *handle) 81 { 82 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 83 84 if (amdgpu_sriov_vf(adev)) { 85 adev->vcn.num_vcn_inst = 2; 86 adev->vcn.harvest_config = 0; 87 adev->vcn.num_enc_rings = 1; 88 } else { 89 u32 harvest; 90 int i; 91 92 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 93 harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING); 94 if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK) 95 adev->vcn.harvest_config |= 1 << i; 96 } 97 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 | 98 AMDGPU_VCN_HARVEST_VCN1)) 99 /* both instances are harvested, disable the block */ 100 return -ENOENT; 101 102 adev->vcn.num_enc_rings = 2; 103 } 104 105 vcn_v2_5_set_dec_ring_funcs(adev); 106 vcn_v2_5_set_enc_ring_funcs(adev); 107 vcn_v2_5_set_irq_funcs(adev); 108 vcn_v2_5_set_ras_funcs(adev); 109 110 return 0; 111 } 112 113 /** 114 * vcn_v2_5_sw_init - sw init for VCN block 115 * 116 * @handle: amdgpu_device pointer 117 * 118 * Load firmware and sw initialization 119 */ 120 static int vcn_v2_5_sw_init(void *handle) 121 { 122 struct amdgpu_ring *ring; 123 int i, j, r; 124 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 125 126 for (j = 0; j < adev->vcn.num_vcn_inst; j++) { 127 if (adev->vcn.harvest_config & (1 << j)) 128 continue; 129 /* VCN DEC TRAP */ 130 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j], 131 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[j].irq); 132 if (r) 133 return r; 134 135 /* VCN ENC TRAP */ 136 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 137 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j], 138 i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[j].irq); 139 if (r) 140 return r; 141 } 142 } 143 144 r = amdgpu_vcn_sw_init(adev); 145 if (r) 146 return r; 147 148 amdgpu_vcn_setup_ucode(adev); 149 150 r = amdgpu_vcn_resume(adev); 151 if (r) 152 return r; 153 154 for (j = 0; j < adev->vcn.num_vcn_inst; j++) { 155 volatile struct amdgpu_fw_shared *fw_shared; 156 157 if (adev->vcn.harvest_config & (1 << j)) 158 continue; 159 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; 160 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; 161 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; 162 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; 163 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; 164 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; 165 166 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; 167 adev->vcn.inst[j].external.scratch9 = SOC15_REG_OFFSET(VCN, j, mmUVD_SCRATCH9); 168 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; 169 adev->vcn.inst[j].external.data0 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA0); 170 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; 171 adev->vcn.inst[j].external.data1 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA1); 172 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; 173 adev->vcn.inst[j].external.cmd = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_CMD); 174 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; 175 adev->vcn.inst[j].external.nop = SOC15_REG_OFFSET(VCN, j, mmUVD_NO_OP); 176 177 ring = &adev->vcn.inst[j].ring_dec; 178 ring->use_doorbell = true; 179 180 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 181 (amdgpu_sriov_vf(adev) ? 2*j : 8*j); 182 sprintf(ring->name, "vcn_dec_%d", j); 183 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq, 184 0, AMDGPU_RING_PRIO_DEFAULT, NULL); 185 if (r) 186 return r; 187 188 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 189 enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(i); 190 191 ring = &adev->vcn.inst[j].ring_enc[i]; 192 ring->use_doorbell = true; 193 194 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 195 (amdgpu_sriov_vf(adev) ? (1 + i + 2*j) : (2 + i + 8*j)); 196 197 sprintf(ring->name, "vcn_enc_%d.%d", j, i); 198 r = amdgpu_ring_init(adev, ring, 512, 199 &adev->vcn.inst[j].irq, 0, 200 hw_prio, NULL); 201 if (r) 202 return r; 203 } 204 205 fw_shared = adev->vcn.inst[j].fw_shared.cpu_addr; 206 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG); 207 208 if (amdgpu_vcnfw_log) 209 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]); 210 } 211 212 if (amdgpu_sriov_vf(adev)) { 213 r = amdgpu_virt_alloc_mm_table(adev); 214 if (r) 215 return r; 216 } 217 218 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 219 adev->vcn.pause_dpg_mode = vcn_v2_5_pause_dpg_mode; 220 221 return 0; 222 } 223 224 /** 225 * vcn_v2_5_sw_fini - sw fini for VCN block 226 * 227 * @handle: amdgpu_device pointer 228 * 229 * VCN suspend and free up sw allocation 230 */ 231 static int vcn_v2_5_sw_fini(void *handle) 232 { 233 int i, r, idx; 234 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 235 volatile struct amdgpu_fw_shared *fw_shared; 236 237 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 238 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 239 if (adev->vcn.harvest_config & (1 << i)) 240 continue; 241 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 242 fw_shared->present_flag_0 = 0; 243 } 244 drm_dev_exit(idx); 245 } 246 247 248 if (amdgpu_sriov_vf(adev)) 249 amdgpu_virt_free_mm_table(adev); 250 251 r = amdgpu_vcn_suspend(adev); 252 if (r) 253 return r; 254 255 r = amdgpu_vcn_sw_fini(adev); 256 257 return r; 258 } 259 260 /** 261 * vcn_v2_5_hw_init - start and test VCN block 262 * 263 * @handle: amdgpu_device pointer 264 * 265 * Initialize the hardware, boot up the VCPU and do some testing 266 */ 267 static int vcn_v2_5_hw_init(void *handle) 268 { 269 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 270 struct amdgpu_ring *ring; 271 int i, j, r = 0; 272 273 if (amdgpu_sriov_vf(adev)) 274 r = vcn_v2_5_sriov_start(adev); 275 276 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 277 if (adev->vcn.harvest_config & (1 << j)) 278 continue; 279 280 if (amdgpu_sriov_vf(adev)) { 281 adev->vcn.inst[j].ring_enc[0].sched.ready = true; 282 adev->vcn.inst[j].ring_enc[1].sched.ready = false; 283 adev->vcn.inst[j].ring_enc[2].sched.ready = false; 284 adev->vcn.inst[j].ring_dec.sched.ready = true; 285 } else { 286 287 ring = &adev->vcn.inst[j].ring_dec; 288 289 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 290 ring->doorbell_index, j); 291 292 r = amdgpu_ring_test_helper(ring); 293 if (r) 294 goto done; 295 296 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 297 ring = &adev->vcn.inst[j].ring_enc[i]; 298 r = amdgpu_ring_test_helper(ring); 299 if (r) 300 goto done; 301 } 302 } 303 } 304 305 done: 306 if (!r) 307 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 308 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 309 310 return r; 311 } 312 313 /** 314 * vcn_v2_5_hw_fini - stop the hardware block 315 * 316 * @handle: amdgpu_device pointer 317 * 318 * Stop the VCN block, mark ring as not ready any more 319 */ 320 static int vcn_v2_5_hw_fini(void *handle) 321 { 322 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 323 int i; 324 325 cancel_delayed_work_sync(&adev->vcn.idle_work); 326 327 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 328 if (adev->vcn.harvest_config & (1 << i)) 329 continue; 330 331 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 332 (adev->vcn.cur_state != AMD_PG_STATE_GATE && 333 RREG32_SOC15(VCN, i, mmUVD_STATUS))) 334 vcn_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE); 335 } 336 337 return 0; 338 } 339 340 /** 341 * vcn_v2_5_suspend - suspend VCN block 342 * 343 * @handle: amdgpu_device pointer 344 * 345 * HW fini and suspend VCN block 346 */ 347 static int vcn_v2_5_suspend(void *handle) 348 { 349 int r; 350 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 351 352 r = vcn_v2_5_hw_fini(adev); 353 if (r) 354 return r; 355 356 r = amdgpu_vcn_suspend(adev); 357 358 return r; 359 } 360 361 /** 362 * vcn_v2_5_resume - resume VCN block 363 * 364 * @handle: amdgpu_device pointer 365 * 366 * Resume firmware and hw init VCN block 367 */ 368 static int vcn_v2_5_resume(void *handle) 369 { 370 int r; 371 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 372 373 r = amdgpu_vcn_resume(adev); 374 if (r) 375 return r; 376 377 r = vcn_v2_5_hw_init(adev); 378 379 return r; 380 } 381 382 /** 383 * vcn_v2_5_mc_resume - memory controller programming 384 * 385 * @adev: amdgpu_device pointer 386 * 387 * Let the VCN memory controller know it's offsets 388 */ 389 static void vcn_v2_5_mc_resume(struct amdgpu_device *adev) 390 { 391 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 392 uint32_t offset; 393 int i; 394 395 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 396 if (adev->vcn.harvest_config & (1 << i)) 397 continue; 398 /* cache window 0: fw */ 399 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 400 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 401 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo)); 402 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 403 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi)); 404 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, 0); 405 offset = 0; 406 } else { 407 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 408 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 409 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 410 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 411 offset = size; 412 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, 413 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 414 } 415 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE0, size); 416 417 /* cache window 1: stack */ 418 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 419 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset)); 420 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 421 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset)); 422 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET1, 0); 423 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 424 425 /* cache window 2: context */ 426 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 427 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 428 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 429 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 430 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET2, 0); 431 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 432 433 /* non-cache window */ 434 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 435 lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); 436 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 437 upper_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); 438 WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_OFFSET0, 0); 439 WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_SIZE0, 440 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); 441 } 442 } 443 444 static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 445 { 446 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 447 uint32_t offset; 448 449 /* cache window 0: fw */ 450 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 451 if (!indirect) { 452 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 453 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 454 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); 455 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 456 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 457 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); 458 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 459 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 460 } else { 461 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 462 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 463 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 464 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 465 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 466 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 467 } 468 offset = 0; 469 } else { 470 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 471 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 472 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 473 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 474 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 475 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 476 offset = size; 477 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 478 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 479 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 480 } 481 482 if (!indirect) 483 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 484 VCN, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 485 else 486 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 487 VCN, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 488 489 /* cache window 1: stack */ 490 if (!indirect) { 491 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 492 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 493 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 494 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 495 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 496 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 497 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 498 VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 499 } else { 500 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 501 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 502 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 503 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 504 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 505 VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 506 } 507 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 508 VCN, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 509 510 /* cache window 2: context */ 511 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 512 VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 513 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 514 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 515 VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 516 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 517 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 518 VCN, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 519 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 520 VCN, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 521 522 /* non-cache window */ 523 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 524 VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 525 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 526 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 527 VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 528 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 529 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 530 VCN, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 531 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 532 VCN, 0, mmUVD_VCPU_NONCACHE_SIZE0), 533 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); 534 535 /* VCN global tiling registers */ 536 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 537 VCN, 0, mmUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 538 } 539 540 /** 541 * vcn_v2_5_disable_clock_gating - disable VCN clock gating 542 * 543 * @adev: amdgpu_device pointer 544 * 545 * Disable clock gating for VCN block 546 */ 547 static void vcn_v2_5_disable_clock_gating(struct amdgpu_device *adev) 548 { 549 uint32_t data; 550 int i; 551 552 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 553 if (adev->vcn.harvest_config & (1 << i)) 554 continue; 555 /* UVD disable CGC */ 556 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); 557 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 558 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 559 else 560 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 561 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 562 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 563 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); 564 565 data = RREG32_SOC15(VCN, i, mmUVD_CGC_GATE); 566 data &= ~(UVD_CGC_GATE__SYS_MASK 567 | UVD_CGC_GATE__UDEC_MASK 568 | UVD_CGC_GATE__MPEG2_MASK 569 | UVD_CGC_GATE__REGS_MASK 570 | UVD_CGC_GATE__RBC_MASK 571 | UVD_CGC_GATE__LMI_MC_MASK 572 | UVD_CGC_GATE__LMI_UMC_MASK 573 | UVD_CGC_GATE__IDCT_MASK 574 | UVD_CGC_GATE__MPRD_MASK 575 | UVD_CGC_GATE__MPC_MASK 576 | UVD_CGC_GATE__LBSI_MASK 577 | UVD_CGC_GATE__LRBBM_MASK 578 | UVD_CGC_GATE__UDEC_RE_MASK 579 | UVD_CGC_GATE__UDEC_CM_MASK 580 | UVD_CGC_GATE__UDEC_IT_MASK 581 | UVD_CGC_GATE__UDEC_DB_MASK 582 | UVD_CGC_GATE__UDEC_MP_MASK 583 | UVD_CGC_GATE__WCB_MASK 584 | UVD_CGC_GATE__VCPU_MASK 585 | UVD_CGC_GATE__MMSCH_MASK); 586 587 WREG32_SOC15(VCN, i, mmUVD_CGC_GATE, data); 588 589 SOC15_WAIT_ON_RREG(VCN, i, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); 590 591 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); 592 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 593 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 594 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 595 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 596 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 597 | UVD_CGC_CTRL__SYS_MODE_MASK 598 | UVD_CGC_CTRL__UDEC_MODE_MASK 599 | UVD_CGC_CTRL__MPEG2_MODE_MASK 600 | UVD_CGC_CTRL__REGS_MODE_MASK 601 | UVD_CGC_CTRL__RBC_MODE_MASK 602 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 603 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 604 | UVD_CGC_CTRL__IDCT_MODE_MASK 605 | UVD_CGC_CTRL__MPRD_MODE_MASK 606 | UVD_CGC_CTRL__MPC_MODE_MASK 607 | UVD_CGC_CTRL__LBSI_MODE_MASK 608 | UVD_CGC_CTRL__LRBBM_MODE_MASK 609 | UVD_CGC_CTRL__WCB_MODE_MASK 610 | UVD_CGC_CTRL__VCPU_MODE_MASK 611 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 612 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); 613 614 /* turn on */ 615 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE); 616 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 617 | UVD_SUVD_CGC_GATE__SIT_MASK 618 | UVD_SUVD_CGC_GATE__SMP_MASK 619 | UVD_SUVD_CGC_GATE__SCM_MASK 620 | UVD_SUVD_CGC_GATE__SDB_MASK 621 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 622 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 623 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 624 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 625 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 626 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 627 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 628 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 629 | UVD_SUVD_CGC_GATE__SCLR_MASK 630 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 631 | UVD_SUVD_CGC_GATE__ENT_MASK 632 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 633 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 634 | UVD_SUVD_CGC_GATE__SITE_MASK 635 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 636 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 637 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 638 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 639 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 640 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE, data); 641 642 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL); 643 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 644 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 645 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 646 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 647 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 648 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 649 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 650 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 651 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 652 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 653 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data); 654 } 655 } 656 657 static void vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_device *adev, 658 uint8_t sram_sel, int inst_idx, uint8_t indirect) 659 { 660 uint32_t reg_data = 0; 661 662 /* enable sw clock gating control */ 663 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 664 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 665 else 666 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 667 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 668 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 669 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 670 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 671 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 672 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 673 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 674 UVD_CGC_CTRL__SYS_MODE_MASK | 675 UVD_CGC_CTRL__UDEC_MODE_MASK | 676 UVD_CGC_CTRL__MPEG2_MODE_MASK | 677 UVD_CGC_CTRL__REGS_MODE_MASK | 678 UVD_CGC_CTRL__RBC_MODE_MASK | 679 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 680 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 681 UVD_CGC_CTRL__IDCT_MODE_MASK | 682 UVD_CGC_CTRL__MPRD_MODE_MASK | 683 UVD_CGC_CTRL__MPC_MODE_MASK | 684 UVD_CGC_CTRL__LBSI_MODE_MASK | 685 UVD_CGC_CTRL__LRBBM_MODE_MASK | 686 UVD_CGC_CTRL__WCB_MODE_MASK | 687 UVD_CGC_CTRL__VCPU_MODE_MASK | 688 UVD_CGC_CTRL__MMSCH_MODE_MASK); 689 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 690 VCN, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); 691 692 /* turn off clock gating */ 693 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 694 VCN, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect); 695 696 /* turn on SUVD clock gating */ 697 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 698 VCN, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 699 700 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 701 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 702 VCN, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 703 } 704 705 /** 706 * vcn_v2_5_enable_clock_gating - enable VCN clock gating 707 * 708 * @adev: amdgpu_device pointer 709 * 710 * Enable clock gating for VCN block 711 */ 712 static void vcn_v2_5_enable_clock_gating(struct amdgpu_device *adev) 713 { 714 uint32_t data = 0; 715 int i; 716 717 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 718 if (adev->vcn.harvest_config & (1 << i)) 719 continue; 720 /* enable UVD CGC */ 721 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); 722 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 723 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 724 else 725 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 726 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 727 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 728 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); 729 730 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); 731 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 732 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 733 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 734 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 735 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 736 | UVD_CGC_CTRL__SYS_MODE_MASK 737 | UVD_CGC_CTRL__UDEC_MODE_MASK 738 | UVD_CGC_CTRL__MPEG2_MODE_MASK 739 | UVD_CGC_CTRL__REGS_MODE_MASK 740 | UVD_CGC_CTRL__RBC_MODE_MASK 741 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 742 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 743 | UVD_CGC_CTRL__IDCT_MODE_MASK 744 | UVD_CGC_CTRL__MPRD_MODE_MASK 745 | UVD_CGC_CTRL__MPC_MODE_MASK 746 | UVD_CGC_CTRL__LBSI_MODE_MASK 747 | UVD_CGC_CTRL__LRBBM_MODE_MASK 748 | UVD_CGC_CTRL__WCB_MODE_MASK 749 | UVD_CGC_CTRL__VCPU_MODE_MASK); 750 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); 751 752 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL); 753 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 754 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 755 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 756 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 757 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 758 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 759 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 760 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 761 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 762 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 763 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data); 764 } 765 } 766 767 static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 768 { 769 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 770 struct amdgpu_ring *ring; 771 uint32_t rb_bufsz, tmp; 772 773 /* disable register anti-hang mechanism */ 774 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1, 775 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 776 /* enable dynamic power gating mode */ 777 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS); 778 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 779 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 780 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp); 781 782 if (indirect) 783 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 784 785 /* enable clock gating */ 786 vcn_v2_5_clock_gating_dpg_mode(adev, 0, inst_idx, indirect); 787 788 /* enable VCPU clock */ 789 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 790 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 791 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK; 792 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 793 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); 794 795 /* disable master interupt */ 796 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 797 VCN, 0, mmUVD_MASTINT_EN), 0, 0, indirect); 798 799 /* setup mmUVD_LMI_CTRL */ 800 tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 801 UVD_LMI_CTRL__REQ_MODE_MASK | 802 UVD_LMI_CTRL__CRC_RESET_MASK | 803 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 804 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 805 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 806 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 807 0x00100000L); 808 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 809 VCN, 0, mmUVD_LMI_CTRL), tmp, 0, indirect); 810 811 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 812 VCN, 0, mmUVD_MPC_CNTL), 813 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 814 815 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 816 VCN, 0, mmUVD_MPC_SET_MUXA0), 817 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 818 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 819 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 820 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 821 822 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 823 VCN, 0, mmUVD_MPC_SET_MUXB0), 824 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 825 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 826 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 827 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 828 829 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 830 VCN, 0, mmUVD_MPC_SET_MUX), 831 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 832 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 833 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 834 835 vcn_v2_5_mc_resume_dpg_mode(adev, inst_idx, indirect); 836 837 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 838 VCN, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect); 839 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 840 VCN, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect); 841 842 /* enable LMI MC and UMC channels */ 843 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 844 VCN, 0, mmUVD_LMI_CTRL2), 0, 0, indirect); 845 846 /* unblock VCPU register access */ 847 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 848 VCN, 0, mmUVD_RB_ARB_CTRL), 0, 0, indirect); 849 850 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 851 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 852 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 853 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); 854 855 /* enable master interrupt */ 856 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 857 VCN, 0, mmUVD_MASTINT_EN), 858 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 859 860 if (indirect) 861 psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, 862 (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr - 863 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr)); 864 865 ring = &adev->vcn.inst[inst_idx].ring_dec; 866 /* force RBC into idle state */ 867 rb_bufsz = order_base_2(ring->ring_size); 868 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 869 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 870 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 871 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 872 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 873 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp); 874 875 /* Stall DPG before WPTR/RPTR reset */ 876 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 877 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 878 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 879 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET; 880 881 /* set the write pointer delay */ 882 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0); 883 884 /* set the wb address */ 885 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR, 886 (upper_32_bits(ring->gpu_addr) >> 2)); 887 888 /* program the RB_BASE for ring buffer */ 889 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 890 lower_32_bits(ring->gpu_addr)); 891 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 892 upper_32_bits(ring->gpu_addr)); 893 894 /* Initialize the ring buffer's read and write pointers */ 895 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0); 896 897 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0); 898 899 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR); 900 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, 901 lower_32_bits(ring->wptr)); 902 903 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET; 904 /* Unstall DPG */ 905 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 906 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 907 908 return 0; 909 } 910 911 static int vcn_v2_5_start(struct amdgpu_device *adev) 912 { 913 struct amdgpu_ring *ring; 914 uint32_t rb_bufsz, tmp; 915 int i, j, k, r; 916 917 if (adev->pm.dpm_enabled) 918 amdgpu_dpm_enable_uvd(adev, true); 919 920 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 921 if (adev->vcn.harvest_config & (1 << i)) 922 continue; 923 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 924 r = vcn_v2_5_start_dpg_mode(adev, i, adev->vcn.indirect_sram); 925 continue; 926 } 927 928 /* disable register anti-hang mechanism */ 929 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), 0, 930 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 931 932 /* set uvd status busy */ 933 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 934 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp); 935 } 936 937 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 938 return 0; 939 940 /*SW clock gating */ 941 vcn_v2_5_disable_clock_gating(adev); 942 943 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 944 if (adev->vcn.harvest_config & (1 << i)) 945 continue; 946 /* enable VCPU clock */ 947 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 948 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 949 950 /* disable master interrupt */ 951 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0, 952 ~UVD_MASTINT_EN__VCPU_EN_MASK); 953 954 /* setup mmUVD_LMI_CTRL */ 955 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL); 956 tmp &= ~0xff; 957 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | 0x8| 958 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 959 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 960 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 961 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 962 963 /* setup mmUVD_MPC_CNTL */ 964 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL); 965 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 966 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 967 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp); 968 969 /* setup UVD_MPC_SET_MUXA0 */ 970 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0, 971 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 972 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 973 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 974 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 975 976 /* setup UVD_MPC_SET_MUXB0 */ 977 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0, 978 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 979 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 980 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 981 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 982 983 /* setup mmUVD_MPC_SET_MUX */ 984 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX, 985 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 986 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 987 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 988 } 989 990 vcn_v2_5_mc_resume(adev); 991 992 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 993 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 994 if (adev->vcn.harvest_config & (1 << i)) 995 continue; 996 /* VCN global tiling registers */ 997 WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG, 998 adev->gfx.config.gb_addr_config); 999 WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG, 1000 adev->gfx.config.gb_addr_config); 1001 1002 /* enable LMI MC and UMC channels */ 1003 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0, 1004 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1005 1006 /* unblock VCPU register access */ 1007 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0, 1008 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1009 1010 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1011 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1012 1013 for (k = 0; k < 10; ++k) { 1014 uint32_t status; 1015 1016 for (j = 0; j < 100; ++j) { 1017 status = RREG32_SOC15(VCN, i, mmUVD_STATUS); 1018 if (status & 2) 1019 break; 1020 if (amdgpu_emu_mode == 1) 1021 msleep(500); 1022 else 1023 mdelay(10); 1024 } 1025 r = 0; 1026 if (status & 2) 1027 break; 1028 1029 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n"); 1030 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1031 UVD_VCPU_CNTL__BLK_RST_MASK, 1032 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1033 mdelay(10); 1034 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1035 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1036 1037 mdelay(10); 1038 r = -1; 1039 } 1040 1041 if (r) { 1042 DRM_ERROR("VCN decode not responding, giving up!!!\n"); 1043 return r; 1044 } 1045 1046 /* enable master interrupt */ 1047 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 1048 UVD_MASTINT_EN__VCPU_EN_MASK, 1049 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1050 1051 /* clear the busy bit of VCN_STATUS */ 1052 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0, 1053 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1054 1055 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0); 1056 1057 ring = &adev->vcn.inst[i].ring_dec; 1058 /* force RBC into idle state */ 1059 rb_bufsz = order_base_2(ring->ring_size); 1060 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1061 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1062 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1063 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1064 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1065 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp); 1066 1067 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET; 1068 /* program the RB_BASE for ring buffer */ 1069 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1070 lower_32_bits(ring->gpu_addr)); 1071 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1072 upper_32_bits(ring->gpu_addr)); 1073 1074 /* Initialize the ring buffer's read and write pointers */ 1075 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0); 1076 1077 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR); 1078 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR, 1079 lower_32_bits(ring->wptr)); 1080 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET; 1081 1082 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET; 1083 ring = &adev->vcn.inst[i].ring_enc[0]; 1084 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1085 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1086 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr); 1087 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1088 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4); 1089 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET; 1090 1091 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET; 1092 ring = &adev->vcn.inst[i].ring_enc[1]; 1093 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1094 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1095 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1096 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1097 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4); 1098 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET; 1099 } 1100 1101 return 0; 1102 } 1103 1104 static int vcn_v2_5_mmsch_start(struct amdgpu_device *adev, 1105 struct amdgpu_mm_table *table) 1106 { 1107 uint32_t data = 0, loop = 0, size = 0; 1108 uint64_t addr = table->gpu_addr; 1109 struct mmsch_v1_1_init_header *header = NULL; 1110 1111 header = (struct mmsch_v1_1_init_header *)table->cpu_addr; 1112 size = header->total_size; 1113 1114 /* 1115 * 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr of 1116 * memory descriptor location 1117 */ 1118 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr)); 1119 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr)); 1120 1121 /* 2, update vmid of descriptor */ 1122 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID); 1123 data &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1124 /* use domain0 for MM scheduler */ 1125 data |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1126 WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, data); 1127 1128 /* 3, notify mmsch about the size of this descriptor */ 1129 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size); 1130 1131 /* 4, set resp to zero */ 1132 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0); 1133 1134 /* 1135 * 5, kick off the initialization and wait until 1136 * VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero 1137 */ 1138 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, 0x10000001); 1139 1140 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); 1141 loop = 10; 1142 while ((data & 0x10000002) != 0x10000002) { 1143 udelay(100); 1144 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); 1145 loop--; 1146 if (!loop) 1147 break; 1148 } 1149 1150 if (!loop) { 1151 dev_err(adev->dev, 1152 "failed to init MMSCH, mmMMSCH_VF_MAILBOX_RESP = %x\n", 1153 data); 1154 return -EBUSY; 1155 } 1156 1157 return 0; 1158 } 1159 1160 static int vcn_v2_5_sriov_start(struct amdgpu_device *adev) 1161 { 1162 struct amdgpu_ring *ring; 1163 uint32_t offset, size, tmp, i, rb_bufsz; 1164 uint32_t table_size = 0; 1165 struct mmsch_v1_0_cmd_direct_write direct_wt = { { 0 } }; 1166 struct mmsch_v1_0_cmd_direct_read_modify_write direct_rd_mod_wt = { { 0 } }; 1167 struct mmsch_v1_0_cmd_end end = { { 0 } }; 1168 uint32_t *init_table = adev->virt.mm_table.cpu_addr; 1169 struct mmsch_v1_1_init_header *header = (struct mmsch_v1_1_init_header *)init_table; 1170 1171 direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE; 1172 direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1173 end.cmd_header.command_type = MMSCH_COMMAND__END; 1174 1175 header->version = MMSCH_VERSION; 1176 header->total_size = sizeof(struct mmsch_v1_1_init_header) >> 2; 1177 init_table += header->total_size; 1178 1179 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1180 header->eng[i].table_offset = header->total_size; 1181 header->eng[i].init_status = 0; 1182 header->eng[i].table_size = 0; 1183 1184 table_size = 0; 1185 1186 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT( 1187 SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 1188 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 1189 1190 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 1191 /* mc resume*/ 1192 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1193 MMSCH_V1_0_INSERT_DIRECT_WT( 1194 SOC15_REG_OFFSET(VCN, i, 1195 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1196 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo); 1197 MMSCH_V1_0_INSERT_DIRECT_WT( 1198 SOC15_REG_OFFSET(VCN, i, 1199 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1200 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi); 1201 offset = 0; 1202 MMSCH_V1_0_INSERT_DIRECT_WT( 1203 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0), 0); 1204 } else { 1205 MMSCH_V1_0_INSERT_DIRECT_WT( 1206 SOC15_REG_OFFSET(VCN, i, 1207 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1208 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 1209 MMSCH_V1_0_INSERT_DIRECT_WT( 1210 SOC15_REG_OFFSET(VCN, i, 1211 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1212 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 1213 offset = size; 1214 MMSCH_V1_0_INSERT_DIRECT_WT( 1215 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0), 1216 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 1217 } 1218 1219 MMSCH_V1_0_INSERT_DIRECT_WT( 1220 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE0), 1221 size); 1222 MMSCH_V1_0_INSERT_DIRECT_WT( 1223 SOC15_REG_OFFSET(VCN, i, 1224 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 1225 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset)); 1226 MMSCH_V1_0_INSERT_DIRECT_WT( 1227 SOC15_REG_OFFSET(VCN, i, 1228 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 1229 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset)); 1230 MMSCH_V1_0_INSERT_DIRECT_WT( 1231 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET1), 1232 0); 1233 MMSCH_V1_0_INSERT_DIRECT_WT( 1234 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE1), 1235 AMDGPU_VCN_STACK_SIZE); 1236 MMSCH_V1_0_INSERT_DIRECT_WT( 1237 SOC15_REG_OFFSET(VCN, i, 1238 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 1239 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + 1240 AMDGPU_VCN_STACK_SIZE)); 1241 MMSCH_V1_0_INSERT_DIRECT_WT( 1242 SOC15_REG_OFFSET(VCN, i, 1243 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 1244 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + 1245 AMDGPU_VCN_STACK_SIZE)); 1246 MMSCH_V1_0_INSERT_DIRECT_WT( 1247 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET2), 1248 0); 1249 MMSCH_V1_0_INSERT_DIRECT_WT( 1250 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE2), 1251 AMDGPU_VCN_CONTEXT_SIZE); 1252 1253 ring = &adev->vcn.inst[i].ring_enc[0]; 1254 ring->wptr = 0; 1255 1256 MMSCH_V1_0_INSERT_DIRECT_WT( 1257 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_LO), 1258 lower_32_bits(ring->gpu_addr)); 1259 MMSCH_V1_0_INSERT_DIRECT_WT( 1260 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_HI), 1261 upper_32_bits(ring->gpu_addr)); 1262 MMSCH_V1_0_INSERT_DIRECT_WT( 1263 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_SIZE), 1264 ring->ring_size / 4); 1265 1266 ring = &adev->vcn.inst[i].ring_dec; 1267 ring->wptr = 0; 1268 MMSCH_V1_0_INSERT_DIRECT_WT( 1269 SOC15_REG_OFFSET(VCN, i, 1270 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW), 1271 lower_32_bits(ring->gpu_addr)); 1272 MMSCH_V1_0_INSERT_DIRECT_WT( 1273 SOC15_REG_OFFSET(VCN, i, 1274 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH), 1275 upper_32_bits(ring->gpu_addr)); 1276 1277 /* force RBC into idle state */ 1278 rb_bufsz = order_base_2(ring->ring_size); 1279 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1280 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1281 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1282 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1283 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1284 MMSCH_V1_0_INSERT_DIRECT_WT( 1285 SOC15_REG_OFFSET(VCN, i, mmUVD_RBC_RB_CNTL), tmp); 1286 1287 /* add end packet */ 1288 memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end)); 1289 table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4; 1290 init_table += sizeof(struct mmsch_v1_0_cmd_end) / 4; 1291 1292 /* refine header */ 1293 header->eng[i].table_size = table_size; 1294 header->total_size += table_size; 1295 } 1296 1297 return vcn_v2_5_mmsch_start(adev, &adev->virt.mm_table); 1298 } 1299 1300 static int vcn_v2_5_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) 1301 { 1302 uint32_t tmp; 1303 1304 /* Wait for power status to be 1 */ 1305 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1306 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1307 1308 /* wait for read ptr to be equal to write ptr */ 1309 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR); 1310 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1311 1312 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2); 1313 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); 1314 1315 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1316 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); 1317 1318 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1319 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1320 1321 /* disable dynamic power gating mode */ 1322 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0, 1323 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1324 1325 return 0; 1326 } 1327 1328 static int vcn_v2_5_stop(struct amdgpu_device *adev) 1329 { 1330 uint32_t tmp; 1331 int i, r = 0; 1332 1333 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1334 if (adev->vcn.harvest_config & (1 << i)) 1335 continue; 1336 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1337 r = vcn_v2_5_stop_dpg_mode(adev, i); 1338 continue; 1339 } 1340 1341 /* wait for vcn idle */ 1342 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1343 if (r) 1344 return r; 1345 1346 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1347 UVD_LMI_STATUS__READ_CLEAN_MASK | 1348 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1349 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1350 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1351 if (r) 1352 return r; 1353 1354 /* block LMI UMC channel */ 1355 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2); 1356 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1357 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp); 1358 1359 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK| 1360 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1361 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1362 if (r) 1363 return r; 1364 1365 /* block VCPU register access */ 1366 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 1367 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1368 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1369 1370 /* reset VCPU */ 1371 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1372 UVD_VCPU_CNTL__BLK_RST_MASK, 1373 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1374 1375 /* disable VCPU clock */ 1376 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1377 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1378 1379 /* clear status */ 1380 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0); 1381 1382 vcn_v2_5_enable_clock_gating(adev); 1383 1384 /* enable register anti-hang mechanism */ 1385 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), 1386 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, 1387 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1388 } 1389 1390 if (adev->pm.dpm_enabled) 1391 amdgpu_dpm_enable_uvd(adev, false); 1392 1393 return 0; 1394 } 1395 1396 static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev, 1397 int inst_idx, struct dpg_pause_state *new_state) 1398 { 1399 struct amdgpu_ring *ring; 1400 uint32_t reg_data = 0; 1401 int ret_code = 0; 1402 1403 /* pause/unpause if state is changed */ 1404 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1405 DRM_DEBUG("dpg pause state changed %d -> %d", 1406 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1407 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) & 1408 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1409 1410 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1411 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, 1412 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1413 1414 if (!ret_code) { 1415 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 1416 1417 /* pause DPG */ 1418 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1419 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1420 1421 /* wait for ACK */ 1422 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE, 1423 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1424 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1425 1426 /* Stall DPG before WPTR/RPTR reset */ 1427 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1428 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1429 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1430 1431 /* Restore */ 1432 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET; 1433 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 1434 ring->wptr = 0; 1435 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr); 1436 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1437 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4); 1438 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1439 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1440 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET; 1441 1442 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET; 1443 ring = &adev->vcn.inst[inst_idx].ring_enc[1]; 1444 ring->wptr = 0; 1445 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1446 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1447 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4); 1448 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1449 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1450 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET; 1451 1452 /* Unstall DPG */ 1453 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1454 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1455 1456 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1457 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1458 } 1459 } else { 1460 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1461 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1462 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, 1463 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1464 } 1465 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1466 } 1467 1468 return 0; 1469 } 1470 1471 /** 1472 * vcn_v2_5_dec_ring_get_rptr - get read pointer 1473 * 1474 * @ring: amdgpu_ring pointer 1475 * 1476 * Returns the current hardware read pointer 1477 */ 1478 static uint64_t vcn_v2_5_dec_ring_get_rptr(struct amdgpu_ring *ring) 1479 { 1480 struct amdgpu_device *adev = ring->adev; 1481 1482 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR); 1483 } 1484 1485 /** 1486 * vcn_v2_5_dec_ring_get_wptr - get write pointer 1487 * 1488 * @ring: amdgpu_ring pointer 1489 * 1490 * Returns the current hardware write pointer 1491 */ 1492 static uint64_t vcn_v2_5_dec_ring_get_wptr(struct amdgpu_ring *ring) 1493 { 1494 struct amdgpu_device *adev = ring->adev; 1495 1496 if (ring->use_doorbell) 1497 return *ring->wptr_cpu_addr; 1498 else 1499 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR); 1500 } 1501 1502 /** 1503 * vcn_v2_5_dec_ring_set_wptr - set write pointer 1504 * 1505 * @ring: amdgpu_ring pointer 1506 * 1507 * Commits the write pointer to the hardware 1508 */ 1509 static void vcn_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring) 1510 { 1511 struct amdgpu_device *adev = ring->adev; 1512 1513 if (ring->use_doorbell) { 1514 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1515 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1516 } else { 1517 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1518 } 1519 } 1520 1521 static const struct amdgpu_ring_funcs vcn_v2_5_dec_ring_vm_funcs = { 1522 .type = AMDGPU_RING_TYPE_VCN_DEC, 1523 .align_mask = 0xf, 1524 .secure_submission_supported = true, 1525 .vmhub = AMDGPU_MMHUB_1, 1526 .get_rptr = vcn_v2_5_dec_ring_get_rptr, 1527 .get_wptr = vcn_v2_5_dec_ring_get_wptr, 1528 .set_wptr = vcn_v2_5_dec_ring_set_wptr, 1529 .emit_frame_size = 1530 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1531 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1532 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */ 1533 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */ 1534 6, 1535 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */ 1536 .emit_ib = vcn_v2_0_dec_ring_emit_ib, 1537 .emit_fence = vcn_v2_0_dec_ring_emit_fence, 1538 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush, 1539 .test_ring = vcn_v2_0_dec_ring_test_ring, 1540 .test_ib = amdgpu_vcn_dec_ring_test_ib, 1541 .insert_nop = vcn_v2_0_dec_ring_insert_nop, 1542 .insert_start = vcn_v2_0_dec_ring_insert_start, 1543 .insert_end = vcn_v2_0_dec_ring_insert_end, 1544 .pad_ib = amdgpu_ring_generic_pad_ib, 1545 .begin_use = amdgpu_vcn_ring_begin_use, 1546 .end_use = amdgpu_vcn_ring_end_use, 1547 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg, 1548 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait, 1549 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1550 }; 1551 1552 static const struct amdgpu_ring_funcs vcn_v2_6_dec_ring_vm_funcs = { 1553 .type = AMDGPU_RING_TYPE_VCN_DEC, 1554 .align_mask = 0xf, 1555 .secure_submission_supported = true, 1556 .vmhub = AMDGPU_MMHUB_0, 1557 .get_rptr = vcn_v2_5_dec_ring_get_rptr, 1558 .get_wptr = vcn_v2_5_dec_ring_get_wptr, 1559 .set_wptr = vcn_v2_5_dec_ring_set_wptr, 1560 .emit_frame_size = 1561 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1562 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1563 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */ 1564 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */ 1565 6, 1566 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */ 1567 .emit_ib = vcn_v2_0_dec_ring_emit_ib, 1568 .emit_fence = vcn_v2_0_dec_ring_emit_fence, 1569 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush, 1570 .test_ring = vcn_v2_0_dec_ring_test_ring, 1571 .test_ib = amdgpu_vcn_dec_ring_test_ib, 1572 .insert_nop = vcn_v2_0_dec_ring_insert_nop, 1573 .insert_start = vcn_v2_0_dec_ring_insert_start, 1574 .insert_end = vcn_v2_0_dec_ring_insert_end, 1575 .pad_ib = amdgpu_ring_generic_pad_ib, 1576 .begin_use = amdgpu_vcn_ring_begin_use, 1577 .end_use = amdgpu_vcn_ring_end_use, 1578 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg, 1579 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait, 1580 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1581 }; 1582 1583 /** 1584 * vcn_v2_5_enc_ring_get_rptr - get enc read pointer 1585 * 1586 * @ring: amdgpu_ring pointer 1587 * 1588 * Returns the current hardware enc read pointer 1589 */ 1590 static uint64_t vcn_v2_5_enc_ring_get_rptr(struct amdgpu_ring *ring) 1591 { 1592 struct amdgpu_device *adev = ring->adev; 1593 1594 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) 1595 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR); 1596 else 1597 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2); 1598 } 1599 1600 /** 1601 * vcn_v2_5_enc_ring_get_wptr - get enc write pointer 1602 * 1603 * @ring: amdgpu_ring pointer 1604 * 1605 * Returns the current hardware enc write pointer 1606 */ 1607 static uint64_t vcn_v2_5_enc_ring_get_wptr(struct amdgpu_ring *ring) 1608 { 1609 struct amdgpu_device *adev = ring->adev; 1610 1611 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 1612 if (ring->use_doorbell) 1613 return *ring->wptr_cpu_addr; 1614 else 1615 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR); 1616 } else { 1617 if (ring->use_doorbell) 1618 return *ring->wptr_cpu_addr; 1619 else 1620 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2); 1621 } 1622 } 1623 1624 /** 1625 * vcn_v2_5_enc_ring_set_wptr - set enc write pointer 1626 * 1627 * @ring: amdgpu_ring pointer 1628 * 1629 * Commits the enc write pointer to the hardware 1630 */ 1631 static void vcn_v2_5_enc_ring_set_wptr(struct amdgpu_ring *ring) 1632 { 1633 struct amdgpu_device *adev = ring->adev; 1634 1635 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 1636 if (ring->use_doorbell) { 1637 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1638 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1639 } else { 1640 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1641 } 1642 } else { 1643 if (ring->use_doorbell) { 1644 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1645 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1646 } else { 1647 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1648 } 1649 } 1650 } 1651 1652 static const struct amdgpu_ring_funcs vcn_v2_5_enc_ring_vm_funcs = { 1653 .type = AMDGPU_RING_TYPE_VCN_ENC, 1654 .align_mask = 0x3f, 1655 .nop = VCN_ENC_CMD_NO_OP, 1656 .vmhub = AMDGPU_MMHUB_1, 1657 .get_rptr = vcn_v2_5_enc_ring_get_rptr, 1658 .get_wptr = vcn_v2_5_enc_ring_get_wptr, 1659 .set_wptr = vcn_v2_5_enc_ring_set_wptr, 1660 .emit_frame_size = 1661 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1662 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1663 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1664 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1665 1, /* vcn_v2_0_enc_ring_insert_end */ 1666 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1667 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1668 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1669 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 1670 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1671 .test_ib = amdgpu_vcn_enc_ring_test_ib, 1672 .insert_nop = amdgpu_ring_insert_nop, 1673 .insert_end = vcn_v2_0_enc_ring_insert_end, 1674 .pad_ib = amdgpu_ring_generic_pad_ib, 1675 .begin_use = amdgpu_vcn_ring_begin_use, 1676 .end_use = amdgpu_vcn_ring_end_use, 1677 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 1678 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 1679 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1680 }; 1681 1682 static const struct amdgpu_ring_funcs vcn_v2_6_enc_ring_vm_funcs = { 1683 .type = AMDGPU_RING_TYPE_VCN_ENC, 1684 .align_mask = 0x3f, 1685 .nop = VCN_ENC_CMD_NO_OP, 1686 .vmhub = AMDGPU_MMHUB_0, 1687 .get_rptr = vcn_v2_5_enc_ring_get_rptr, 1688 .get_wptr = vcn_v2_5_enc_ring_get_wptr, 1689 .set_wptr = vcn_v2_5_enc_ring_set_wptr, 1690 .emit_frame_size = 1691 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1692 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1693 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1694 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1695 1, /* vcn_v2_0_enc_ring_insert_end */ 1696 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1697 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1698 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1699 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 1700 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1701 .test_ib = amdgpu_vcn_enc_ring_test_ib, 1702 .insert_nop = amdgpu_ring_insert_nop, 1703 .insert_end = vcn_v2_0_enc_ring_insert_end, 1704 .pad_ib = amdgpu_ring_generic_pad_ib, 1705 .begin_use = amdgpu_vcn_ring_begin_use, 1706 .end_use = amdgpu_vcn_ring_end_use, 1707 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 1708 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 1709 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1710 }; 1711 1712 static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev) 1713 { 1714 int i; 1715 1716 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1717 if (adev->vcn.harvest_config & (1 << i)) 1718 continue; 1719 if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(2, 5, 0)) 1720 adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs; 1721 else /* CHIP_ALDEBARAN */ 1722 adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_6_dec_ring_vm_funcs; 1723 adev->vcn.inst[i].ring_dec.me = i; 1724 DRM_INFO("VCN(%d) decode is enabled in VM mode\n", i); 1725 } 1726 } 1727 1728 static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev) 1729 { 1730 int i, j; 1731 1732 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 1733 if (adev->vcn.harvest_config & (1 << j)) 1734 continue; 1735 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 1736 if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(2, 5, 0)) 1737 adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs; 1738 else /* CHIP_ALDEBARAN */ 1739 adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_6_enc_ring_vm_funcs; 1740 adev->vcn.inst[j].ring_enc[i].me = j; 1741 } 1742 DRM_INFO("VCN(%d) encode is enabled in VM mode\n", j); 1743 } 1744 } 1745 1746 static bool vcn_v2_5_is_idle(void *handle) 1747 { 1748 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1749 int i, ret = 1; 1750 1751 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1752 if (adev->vcn.harvest_config & (1 << i)) 1753 continue; 1754 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); 1755 } 1756 1757 return ret; 1758 } 1759 1760 static int vcn_v2_5_wait_for_idle(void *handle) 1761 { 1762 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1763 int i, ret = 0; 1764 1765 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1766 if (adev->vcn.harvest_config & (1 << i)) 1767 continue; 1768 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 1769 UVD_STATUS__IDLE); 1770 if (ret) 1771 return ret; 1772 } 1773 1774 return ret; 1775 } 1776 1777 static int vcn_v2_5_set_clockgating_state(void *handle, 1778 enum amd_clockgating_state state) 1779 { 1780 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1781 bool enable = (state == AMD_CG_STATE_GATE); 1782 1783 if (amdgpu_sriov_vf(adev)) 1784 return 0; 1785 1786 if (enable) { 1787 if (!vcn_v2_5_is_idle(handle)) 1788 return -EBUSY; 1789 vcn_v2_5_enable_clock_gating(adev); 1790 } else { 1791 vcn_v2_5_disable_clock_gating(adev); 1792 } 1793 1794 return 0; 1795 } 1796 1797 static int vcn_v2_5_set_powergating_state(void *handle, 1798 enum amd_powergating_state state) 1799 { 1800 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1801 int ret; 1802 1803 if (amdgpu_sriov_vf(adev)) 1804 return 0; 1805 1806 if(state == adev->vcn.cur_state) 1807 return 0; 1808 1809 if (state == AMD_PG_STATE_GATE) 1810 ret = vcn_v2_5_stop(adev); 1811 else 1812 ret = vcn_v2_5_start(adev); 1813 1814 if(!ret) 1815 adev->vcn.cur_state = state; 1816 1817 return ret; 1818 } 1819 1820 static int vcn_v2_5_set_interrupt_state(struct amdgpu_device *adev, 1821 struct amdgpu_irq_src *source, 1822 unsigned type, 1823 enum amdgpu_interrupt_state state) 1824 { 1825 return 0; 1826 } 1827 1828 static int vcn_v2_5_process_interrupt(struct amdgpu_device *adev, 1829 struct amdgpu_irq_src *source, 1830 struct amdgpu_iv_entry *entry) 1831 { 1832 uint32_t ip_instance; 1833 1834 switch (entry->client_id) { 1835 case SOC15_IH_CLIENTID_VCN: 1836 ip_instance = 0; 1837 break; 1838 case SOC15_IH_CLIENTID_VCN1: 1839 ip_instance = 1; 1840 break; 1841 default: 1842 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 1843 return 0; 1844 } 1845 1846 DRM_DEBUG("IH: VCN TRAP\n"); 1847 1848 switch (entry->src_id) { 1849 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT: 1850 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec); 1851 break; 1852 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1853 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 1854 break; 1855 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY: 1856 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]); 1857 break; 1858 default: 1859 DRM_ERROR("Unhandled interrupt: %d %d\n", 1860 entry->src_id, entry->src_data[0]); 1861 break; 1862 } 1863 1864 return 0; 1865 } 1866 1867 static const struct amdgpu_irq_src_funcs vcn_v2_5_irq_funcs = { 1868 .set = vcn_v2_5_set_interrupt_state, 1869 .process = vcn_v2_5_process_interrupt, 1870 }; 1871 1872 static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev) 1873 { 1874 int i; 1875 1876 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1877 if (adev->vcn.harvest_config & (1 << i)) 1878 continue; 1879 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1; 1880 adev->vcn.inst[i].irq.funcs = &vcn_v2_5_irq_funcs; 1881 } 1882 } 1883 1884 static const struct amd_ip_funcs vcn_v2_5_ip_funcs = { 1885 .name = "vcn_v2_5", 1886 .early_init = vcn_v2_5_early_init, 1887 .late_init = NULL, 1888 .sw_init = vcn_v2_5_sw_init, 1889 .sw_fini = vcn_v2_5_sw_fini, 1890 .hw_init = vcn_v2_5_hw_init, 1891 .hw_fini = vcn_v2_5_hw_fini, 1892 .suspend = vcn_v2_5_suspend, 1893 .resume = vcn_v2_5_resume, 1894 .is_idle = vcn_v2_5_is_idle, 1895 .wait_for_idle = vcn_v2_5_wait_for_idle, 1896 .check_soft_reset = NULL, 1897 .pre_soft_reset = NULL, 1898 .soft_reset = NULL, 1899 .post_soft_reset = NULL, 1900 .set_clockgating_state = vcn_v2_5_set_clockgating_state, 1901 .set_powergating_state = vcn_v2_5_set_powergating_state, 1902 }; 1903 1904 static const struct amd_ip_funcs vcn_v2_6_ip_funcs = { 1905 .name = "vcn_v2_6", 1906 .early_init = vcn_v2_5_early_init, 1907 .late_init = NULL, 1908 .sw_init = vcn_v2_5_sw_init, 1909 .sw_fini = vcn_v2_5_sw_fini, 1910 .hw_init = vcn_v2_5_hw_init, 1911 .hw_fini = vcn_v2_5_hw_fini, 1912 .suspend = vcn_v2_5_suspend, 1913 .resume = vcn_v2_5_resume, 1914 .is_idle = vcn_v2_5_is_idle, 1915 .wait_for_idle = vcn_v2_5_wait_for_idle, 1916 .check_soft_reset = NULL, 1917 .pre_soft_reset = NULL, 1918 .soft_reset = NULL, 1919 .post_soft_reset = NULL, 1920 .set_clockgating_state = vcn_v2_5_set_clockgating_state, 1921 .set_powergating_state = vcn_v2_5_set_powergating_state, 1922 }; 1923 1924 const struct amdgpu_ip_block_version vcn_v2_5_ip_block = 1925 { 1926 .type = AMD_IP_BLOCK_TYPE_VCN, 1927 .major = 2, 1928 .minor = 5, 1929 .rev = 0, 1930 .funcs = &vcn_v2_5_ip_funcs, 1931 }; 1932 1933 const struct amdgpu_ip_block_version vcn_v2_6_ip_block = 1934 { 1935 .type = AMD_IP_BLOCK_TYPE_VCN, 1936 .major = 2, 1937 .minor = 6, 1938 .rev = 0, 1939 .funcs = &vcn_v2_6_ip_funcs, 1940 }; 1941 1942 static uint32_t vcn_v2_6_query_poison_by_instance(struct amdgpu_device *adev, 1943 uint32_t instance, uint32_t sub_block) 1944 { 1945 uint32_t poison_stat = 0, reg_value = 0; 1946 1947 switch (sub_block) { 1948 case AMDGPU_VCN_V2_6_VCPU_VCODEC: 1949 reg_value = RREG32_SOC15(VCN, instance, mmUVD_RAS_VCPU_VCODEC_STATUS); 1950 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF); 1951 break; 1952 default: 1953 break; 1954 } 1955 1956 if (poison_stat) 1957 dev_info(adev->dev, "Poison detected in VCN%d, sub_block%d\n", 1958 instance, sub_block); 1959 1960 return poison_stat; 1961 } 1962 1963 static bool vcn_v2_6_query_poison_status(struct amdgpu_device *adev) 1964 { 1965 uint32_t inst, sub; 1966 uint32_t poison_stat = 0; 1967 1968 for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++) 1969 for (sub = 0; sub < AMDGPU_VCN_V2_6_MAX_SUB_BLOCK; sub++) 1970 poison_stat += 1971 vcn_v2_6_query_poison_by_instance(adev, inst, sub); 1972 1973 return !!poison_stat; 1974 } 1975 1976 const struct amdgpu_ras_block_hw_ops vcn_v2_6_ras_hw_ops = { 1977 .query_poison_status = vcn_v2_6_query_poison_status, 1978 }; 1979 1980 static struct amdgpu_vcn_ras vcn_v2_6_ras = { 1981 .ras_block = { 1982 .hw_ops = &vcn_v2_6_ras_hw_ops, 1983 }, 1984 }; 1985 1986 static void vcn_v2_5_set_ras_funcs(struct amdgpu_device *adev) 1987 { 1988 switch (adev->ip_versions[VCN_HWIP][0]) { 1989 case IP_VERSION(2, 6, 0): 1990 adev->vcn.ras = &vcn_v2_6_ras; 1991 break; 1992 default: 1993 break; 1994 } 1995 1996 if (adev->vcn.ras) { 1997 amdgpu_ras_register_ras_block(adev, &adev->vcn.ras->ras_block); 1998 1999 strcpy(adev->vcn.ras->ras_block.ras_comm.name, "vcn"); 2000 adev->vcn.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__VCN; 2001 adev->vcn.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON; 2002 adev->vcn.ras_if = &adev->vcn.ras->ras_block.ras_comm; 2003 2004 /* If don't define special ras_late_init function, use default ras_late_init */ 2005 if (!adev->vcn.ras->ras_block.ras_late_init) 2006 adev->vcn.ras->ras_block.ras_late_init = amdgpu_ras_block_late_init; 2007 } 2008 } 2009