1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drm_drv.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_vcn.h" 29 #include "soc15.h" 30 #include "soc15d.h" 31 #include "amdgpu_pm.h" 32 #include "amdgpu_psp.h" 33 #include "mmsch_v2_0.h" 34 #include "vcn_v2_0.h" 35 36 #include "vcn/vcn_2_0_0_offset.h" 37 #include "vcn/vcn_2_0_0_sh_mask.h" 38 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 39 40 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x1fd 41 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x503 42 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x504 43 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x505 44 #define mmUVD_NO_OP_INTERNAL_OFFSET 0x53f 45 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x54a 46 #define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d 47 48 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x1e1 49 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x5a6 50 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x5a7 51 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x1e2 52 53 static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev); 54 static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev); 55 static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev); 56 static int vcn_v2_0_set_powergating_state(void *handle, 57 enum amd_powergating_state state); 58 static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev, 59 int inst_idx, struct dpg_pause_state *new_state); 60 static int vcn_v2_0_start_sriov(struct amdgpu_device *adev); 61 /** 62 * vcn_v2_0_early_init - set function pointers 63 * 64 * @handle: amdgpu_device pointer 65 * 66 * Set ring and irq function pointers 67 */ 68 static int vcn_v2_0_early_init(void *handle) 69 { 70 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 71 72 if (amdgpu_sriov_vf(adev)) 73 adev->vcn.num_enc_rings = 1; 74 else 75 adev->vcn.num_enc_rings = 2; 76 77 vcn_v2_0_set_dec_ring_funcs(adev); 78 vcn_v2_0_set_enc_ring_funcs(adev); 79 vcn_v2_0_set_irq_funcs(adev); 80 81 return 0; 82 } 83 84 /** 85 * vcn_v2_0_sw_init - sw init for VCN block 86 * 87 * @handle: amdgpu_device pointer 88 * 89 * Load firmware and sw initialization 90 */ 91 static int vcn_v2_0_sw_init(void *handle) 92 { 93 struct amdgpu_ring *ring; 94 int i, r; 95 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 96 volatile struct amdgpu_fw_shared *fw_shared; 97 98 /* VCN DEC TRAP */ 99 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 100 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, 101 &adev->vcn.inst->irq); 102 if (r) 103 return r; 104 105 /* VCN ENC TRAP */ 106 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 107 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 108 i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, 109 &adev->vcn.inst->irq); 110 if (r) 111 return r; 112 } 113 114 r = amdgpu_vcn_sw_init(adev); 115 if (r) 116 return r; 117 118 amdgpu_vcn_setup_ucode(adev); 119 120 r = amdgpu_vcn_resume(adev); 121 if (r) 122 return r; 123 124 ring = &adev->vcn.inst->ring_dec; 125 126 ring->use_doorbell = true; 127 ring->doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1 << 1; 128 129 sprintf(ring->name, "vcn_dec"); 130 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, 131 AMDGPU_RING_PRIO_DEFAULT, NULL); 132 if (r) 133 return r; 134 135 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; 136 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; 137 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; 138 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; 139 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; 140 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; 141 142 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; 143 adev->vcn.inst->external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9); 144 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; 145 adev->vcn.inst->external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0); 146 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; 147 adev->vcn.inst->external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1); 148 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; 149 adev->vcn.inst->external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD); 150 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; 151 adev->vcn.inst->external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP); 152 153 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 154 enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(i); 155 156 ring = &adev->vcn.inst->ring_enc[i]; 157 ring->use_doorbell = true; 158 if (!amdgpu_sriov_vf(adev)) 159 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i; 160 else 161 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + i; 162 sprintf(ring->name, "vcn_enc%d", i); 163 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, 164 hw_prio, NULL); 165 if (r) 166 return r; 167 } 168 169 adev->vcn.pause_dpg_mode = vcn_v2_0_pause_dpg_mode; 170 171 r = amdgpu_virt_alloc_mm_table(adev); 172 if (r) 173 return r; 174 175 fw_shared = adev->vcn.inst->fw_shared.cpu_addr; 176 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG); 177 178 if (amdgpu_vcnfw_log) 179 amdgpu_vcn_fwlog_init(adev->vcn.inst); 180 181 return 0; 182 } 183 184 /** 185 * vcn_v2_0_sw_fini - sw fini for VCN block 186 * 187 * @handle: amdgpu_device pointer 188 * 189 * VCN suspend and free up sw allocation 190 */ 191 static int vcn_v2_0_sw_fini(void *handle) 192 { 193 int r, idx; 194 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 195 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr; 196 197 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 198 fw_shared->present_flag_0 = 0; 199 drm_dev_exit(idx); 200 } 201 202 amdgpu_virt_free_mm_table(adev); 203 204 r = amdgpu_vcn_suspend(adev); 205 if (r) 206 return r; 207 208 r = amdgpu_vcn_sw_fini(adev); 209 210 return r; 211 } 212 213 /** 214 * vcn_v2_0_hw_init - start and test VCN block 215 * 216 * @handle: amdgpu_device pointer 217 * 218 * Initialize the hardware, boot up the VCPU and do some testing 219 */ 220 static int vcn_v2_0_hw_init(void *handle) 221 { 222 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 223 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 224 int i, r; 225 226 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 227 ring->doorbell_index, 0); 228 229 if (amdgpu_sriov_vf(adev)) 230 vcn_v2_0_start_sriov(adev); 231 232 r = amdgpu_ring_test_helper(ring); 233 if (r) 234 goto done; 235 236 //Disable vcn decode for sriov 237 if (amdgpu_sriov_vf(adev)) 238 ring->sched.ready = false; 239 240 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 241 ring = &adev->vcn.inst->ring_enc[i]; 242 r = amdgpu_ring_test_helper(ring); 243 if (r) 244 goto done; 245 } 246 247 done: 248 if (!r) 249 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 250 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 251 252 return r; 253 } 254 255 /** 256 * vcn_v2_0_hw_fini - stop the hardware block 257 * 258 * @handle: amdgpu_device pointer 259 * 260 * Stop the VCN block, mark ring as not ready any more 261 */ 262 static int vcn_v2_0_hw_fini(void *handle) 263 { 264 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 265 266 cancel_delayed_work_sync(&adev->vcn.idle_work); 267 268 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 269 (adev->vcn.cur_state != AMD_PG_STATE_GATE && 270 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) 271 vcn_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 272 273 return 0; 274 } 275 276 /** 277 * vcn_v2_0_suspend - suspend VCN block 278 * 279 * @handle: amdgpu_device pointer 280 * 281 * HW fini and suspend VCN block 282 */ 283 static int vcn_v2_0_suspend(void *handle) 284 { 285 int r; 286 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 287 288 r = vcn_v2_0_hw_fini(adev); 289 if (r) 290 return r; 291 292 r = amdgpu_vcn_suspend(adev); 293 294 return r; 295 } 296 297 /** 298 * vcn_v2_0_resume - resume VCN block 299 * 300 * @handle: amdgpu_device pointer 301 * 302 * Resume firmware and hw init VCN block 303 */ 304 static int vcn_v2_0_resume(void *handle) 305 { 306 int r; 307 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 308 309 r = amdgpu_vcn_resume(adev); 310 if (r) 311 return r; 312 313 r = vcn_v2_0_hw_init(adev); 314 315 return r; 316 } 317 318 /** 319 * vcn_v2_0_mc_resume - memory controller programming 320 * 321 * @adev: amdgpu_device pointer 322 * 323 * Let the VCN memory controller know it's offsets 324 */ 325 static void vcn_v2_0_mc_resume(struct amdgpu_device *adev) 326 { 327 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 328 uint32_t offset; 329 330 if (amdgpu_sriov_vf(adev)) 331 return; 332 333 /* cache window 0: fw */ 334 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 335 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 336 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo)); 337 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 338 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi)); 339 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); 340 offset = 0; 341 } else { 342 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 343 lower_32_bits(adev->vcn.inst->gpu_addr)); 344 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 345 upper_32_bits(adev->vcn.inst->gpu_addr)); 346 offset = size; 347 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 348 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 349 } 350 351 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); 352 353 /* cache window 1: stack */ 354 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 355 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); 356 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 357 upper_32_bits(adev->vcn.inst->gpu_addr + offset)); 358 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0); 359 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 360 361 /* cache window 2: context */ 362 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 363 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 364 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 365 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 366 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0); 367 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 368 369 /* non-cache window */ 370 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 371 lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr)); 372 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 373 upper_32_bits(adev->vcn.inst->fw_shared.gpu_addr)); 374 WREG32_SOC15(UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0, 0); 375 WREG32_SOC15(UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0, 376 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); 377 378 WREG32_SOC15(UVD, 0, mmUVD_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 379 } 380 381 static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirect) 382 { 383 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 384 uint32_t offset; 385 386 /* cache window 0: fw */ 387 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 388 if (!indirect) { 389 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 390 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 391 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0, indirect); 392 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 393 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 394 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0, indirect); 395 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 396 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 397 } else { 398 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 399 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 400 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 401 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 402 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 403 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 404 } 405 offset = 0; 406 } else { 407 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 408 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 409 lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); 410 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 411 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 412 upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); 413 offset = size; 414 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 415 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 416 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 417 } 418 419 if (!indirect) 420 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 421 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 422 else 423 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 424 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 425 426 /* cache window 1: stack */ 427 if (!indirect) { 428 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 429 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 430 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect); 431 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 432 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 433 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect); 434 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 435 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 436 } else { 437 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 438 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 439 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 440 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 441 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 442 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 443 } 444 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 445 UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 446 447 /* cache window 2: context */ 448 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 449 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 450 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 451 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 452 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 453 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 454 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 455 UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 456 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 457 UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 458 459 /* non-cache window */ 460 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 461 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 462 lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr), 0, indirect); 463 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 464 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 465 upper_32_bits(adev->vcn.inst->fw_shared.gpu_addr), 0, indirect); 466 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 467 UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 468 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 469 UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0), 470 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); 471 472 /* VCN global tiling registers */ 473 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 474 UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 475 } 476 477 /** 478 * vcn_v2_0_disable_clock_gating - disable VCN clock gating 479 * 480 * @adev: amdgpu_device pointer 481 * 482 * Disable clock gating for VCN block 483 */ 484 static void vcn_v2_0_disable_clock_gating(struct amdgpu_device *adev) 485 { 486 uint32_t data; 487 488 if (amdgpu_sriov_vf(adev)) 489 return; 490 491 /* UVD disable CGC */ 492 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 493 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 494 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 495 else 496 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 497 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 498 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 499 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 500 501 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); 502 data &= ~(UVD_CGC_GATE__SYS_MASK 503 | UVD_CGC_GATE__UDEC_MASK 504 | UVD_CGC_GATE__MPEG2_MASK 505 | UVD_CGC_GATE__REGS_MASK 506 | UVD_CGC_GATE__RBC_MASK 507 | UVD_CGC_GATE__LMI_MC_MASK 508 | UVD_CGC_GATE__LMI_UMC_MASK 509 | UVD_CGC_GATE__IDCT_MASK 510 | UVD_CGC_GATE__MPRD_MASK 511 | UVD_CGC_GATE__MPC_MASK 512 | UVD_CGC_GATE__LBSI_MASK 513 | UVD_CGC_GATE__LRBBM_MASK 514 | UVD_CGC_GATE__UDEC_RE_MASK 515 | UVD_CGC_GATE__UDEC_CM_MASK 516 | UVD_CGC_GATE__UDEC_IT_MASK 517 | UVD_CGC_GATE__UDEC_DB_MASK 518 | UVD_CGC_GATE__UDEC_MP_MASK 519 | UVD_CGC_GATE__WCB_MASK 520 | UVD_CGC_GATE__VCPU_MASK 521 | UVD_CGC_GATE__SCPU_MASK); 522 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data); 523 524 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 525 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 526 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 527 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 528 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 529 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 530 | UVD_CGC_CTRL__SYS_MODE_MASK 531 | UVD_CGC_CTRL__UDEC_MODE_MASK 532 | UVD_CGC_CTRL__MPEG2_MODE_MASK 533 | UVD_CGC_CTRL__REGS_MODE_MASK 534 | UVD_CGC_CTRL__RBC_MODE_MASK 535 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 536 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 537 | UVD_CGC_CTRL__IDCT_MODE_MASK 538 | UVD_CGC_CTRL__MPRD_MODE_MASK 539 | UVD_CGC_CTRL__MPC_MODE_MASK 540 | UVD_CGC_CTRL__LBSI_MODE_MASK 541 | UVD_CGC_CTRL__LRBBM_MODE_MASK 542 | UVD_CGC_CTRL__WCB_MODE_MASK 543 | UVD_CGC_CTRL__VCPU_MODE_MASK 544 | UVD_CGC_CTRL__SCPU_MODE_MASK); 545 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 546 547 /* turn on */ 548 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); 549 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 550 | UVD_SUVD_CGC_GATE__SIT_MASK 551 | UVD_SUVD_CGC_GATE__SMP_MASK 552 | UVD_SUVD_CGC_GATE__SCM_MASK 553 | UVD_SUVD_CGC_GATE__SDB_MASK 554 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 555 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 556 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 557 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 558 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 559 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 560 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 561 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 562 | UVD_SUVD_CGC_GATE__SCLR_MASK 563 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 564 | UVD_SUVD_CGC_GATE__ENT_MASK 565 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 566 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 567 | UVD_SUVD_CGC_GATE__SITE_MASK 568 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 569 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 570 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 571 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 572 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 573 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data); 574 575 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); 576 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 577 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 578 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 579 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 580 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 581 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 582 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 583 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 584 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 585 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 586 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); 587 } 588 589 static void vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_device *adev, 590 uint8_t sram_sel, uint8_t indirect) 591 { 592 uint32_t reg_data = 0; 593 594 /* enable sw clock gating control */ 595 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 596 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 597 else 598 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 599 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 600 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 601 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 602 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 603 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 604 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 605 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 606 UVD_CGC_CTRL__SYS_MODE_MASK | 607 UVD_CGC_CTRL__UDEC_MODE_MASK | 608 UVD_CGC_CTRL__MPEG2_MODE_MASK | 609 UVD_CGC_CTRL__REGS_MODE_MASK | 610 UVD_CGC_CTRL__RBC_MODE_MASK | 611 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 612 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 613 UVD_CGC_CTRL__IDCT_MODE_MASK | 614 UVD_CGC_CTRL__MPRD_MODE_MASK | 615 UVD_CGC_CTRL__MPC_MODE_MASK | 616 UVD_CGC_CTRL__LBSI_MODE_MASK | 617 UVD_CGC_CTRL__LRBBM_MODE_MASK | 618 UVD_CGC_CTRL__WCB_MODE_MASK | 619 UVD_CGC_CTRL__VCPU_MODE_MASK | 620 UVD_CGC_CTRL__SCPU_MODE_MASK); 621 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 622 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); 623 624 /* turn off clock gating */ 625 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 626 UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect); 627 628 /* turn on SUVD clock gating */ 629 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 630 UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 631 632 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 633 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 634 UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 635 } 636 637 /** 638 * vcn_v2_0_enable_clock_gating - enable VCN clock gating 639 * 640 * @adev: amdgpu_device pointer 641 * 642 * Enable clock gating for VCN block 643 */ 644 static void vcn_v2_0_enable_clock_gating(struct amdgpu_device *adev) 645 { 646 uint32_t data = 0; 647 648 if (amdgpu_sriov_vf(adev)) 649 return; 650 651 /* enable UVD CGC */ 652 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 653 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 654 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 655 else 656 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 657 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 658 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 659 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 660 661 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 662 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 663 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 664 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 665 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 666 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 667 | UVD_CGC_CTRL__SYS_MODE_MASK 668 | UVD_CGC_CTRL__UDEC_MODE_MASK 669 | UVD_CGC_CTRL__MPEG2_MODE_MASK 670 | UVD_CGC_CTRL__REGS_MODE_MASK 671 | UVD_CGC_CTRL__RBC_MODE_MASK 672 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 673 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 674 | UVD_CGC_CTRL__IDCT_MODE_MASK 675 | UVD_CGC_CTRL__MPRD_MODE_MASK 676 | UVD_CGC_CTRL__MPC_MODE_MASK 677 | UVD_CGC_CTRL__LBSI_MODE_MASK 678 | UVD_CGC_CTRL__LRBBM_MODE_MASK 679 | UVD_CGC_CTRL__WCB_MODE_MASK 680 | UVD_CGC_CTRL__VCPU_MODE_MASK 681 | UVD_CGC_CTRL__SCPU_MODE_MASK); 682 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 683 684 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); 685 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 686 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 687 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 688 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 689 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 690 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 691 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 692 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 693 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 694 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 695 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); 696 } 697 698 static void vcn_v2_0_disable_static_power_gating(struct amdgpu_device *adev) 699 { 700 uint32_t data = 0; 701 702 if (amdgpu_sriov_vf(adev)) 703 return; 704 705 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 706 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 707 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 708 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 709 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 710 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 711 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 712 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 713 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 714 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 715 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT); 716 717 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 718 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 719 UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0, 0xFFFFF); 720 } else { 721 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 722 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 723 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 724 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 725 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 726 | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 727 | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 728 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 729 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 730 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT); 731 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 732 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFF); 733 } 734 735 /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS, 736 * UVDU_PWR_STATUS are 0 (power on) */ 737 738 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); 739 data &= ~0x103; 740 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 741 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 742 UVD_POWER_STATUS__UVD_PG_EN_MASK; 743 744 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); 745 } 746 747 static void vcn_v2_0_enable_static_power_gating(struct amdgpu_device *adev) 748 { 749 uint32_t data = 0; 750 751 if (amdgpu_sriov_vf(adev)) 752 return; 753 754 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 755 /* Before power off, this indicator has to be turned on */ 756 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); 757 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 758 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 759 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); 760 761 762 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 763 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 764 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 765 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 766 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 767 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 768 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 769 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 770 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 771 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT); 772 773 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 774 775 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 776 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 777 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 778 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 779 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 780 | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT 781 | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT 782 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 783 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 784 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT); 785 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFF); 786 } 787 } 788 789 static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect) 790 { 791 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr; 792 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 793 uint32_t rb_bufsz, tmp; 794 795 vcn_v2_0_enable_static_power_gating(adev); 796 797 /* enable dynamic power gating mode */ 798 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); 799 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 800 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 801 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp); 802 803 if (indirect) 804 adev->vcn.inst->dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst->dpg_sram_cpu_addr; 805 806 /* enable clock gating */ 807 vcn_v2_0_clock_gating_dpg_mode(adev, 0, indirect); 808 809 /* enable VCPU clock */ 810 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 811 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 812 tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK; 813 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 814 UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); 815 816 /* disable master interupt */ 817 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 818 UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect); 819 820 /* setup mmUVD_LMI_CTRL */ 821 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 822 UVD_LMI_CTRL__REQ_MODE_MASK | 823 UVD_LMI_CTRL__CRC_RESET_MASK | 824 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 825 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 826 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 827 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 828 0x00100000L); 829 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 830 UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect); 831 832 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 833 UVD, 0, mmUVD_MPC_CNTL), 834 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 835 836 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 837 UVD, 0, mmUVD_MPC_SET_MUXA0), 838 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 839 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 840 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 841 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 842 843 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 844 UVD, 0, mmUVD_MPC_SET_MUXB0), 845 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 846 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 847 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 848 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 849 850 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 851 UVD, 0, mmUVD_MPC_SET_MUX), 852 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 853 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 854 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 855 856 vcn_v2_0_mc_resume_dpg_mode(adev, indirect); 857 858 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 859 UVD, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect); 860 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 861 UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect); 862 863 /* release VCPU reset to boot */ 864 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 865 UVD, 0, mmUVD_SOFT_RESET), 0, 0, indirect); 866 867 /* enable LMI MC and UMC channels */ 868 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 869 UVD, 0, mmUVD_LMI_CTRL2), 870 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 0, indirect); 871 872 /* enable master interrupt */ 873 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 874 UVD, 0, mmUVD_MASTINT_EN), 875 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 876 877 if (indirect) 878 psp_update_vcn_sram(adev, 0, adev->vcn.inst->dpg_sram_gpu_addr, 879 (uint32_t)((uintptr_t)adev->vcn.inst->dpg_sram_curr_addr - 880 (uintptr_t)adev->vcn.inst->dpg_sram_cpu_addr)); 881 882 /* force RBC into idle state */ 883 rb_bufsz = order_base_2(ring->ring_size); 884 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 885 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 886 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 887 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 888 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 889 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 890 891 /* Stall DPG before WPTR/RPTR reset */ 892 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 893 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 894 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 895 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET; 896 897 /* set the write pointer delay */ 898 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); 899 900 /* set the wb address */ 901 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, 902 (upper_32_bits(ring->gpu_addr) >> 2)); 903 904 /* program the RB_BASE for ring buffer */ 905 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 906 lower_32_bits(ring->gpu_addr)); 907 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 908 upper_32_bits(ring->gpu_addr)); 909 910 /* Initialize the ring buffer's read and write pointers */ 911 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); 912 913 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); 914 915 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 916 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 917 lower_32_bits(ring->wptr)); 918 919 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET; 920 /* Unstall DPG */ 921 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 922 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 923 return 0; 924 } 925 926 static int vcn_v2_0_start(struct amdgpu_device *adev) 927 { 928 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr; 929 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 930 uint32_t rb_bufsz, tmp; 931 uint32_t lmi_swap_cntl; 932 int i, j, r; 933 934 if (adev->pm.dpm_enabled) 935 amdgpu_dpm_enable_uvd(adev, true); 936 937 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 938 return vcn_v2_0_start_dpg_mode(adev, adev->vcn.indirect_sram); 939 940 vcn_v2_0_disable_static_power_gating(adev); 941 942 /* set uvd status busy */ 943 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 944 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); 945 946 /*SW clock gating */ 947 vcn_v2_0_disable_clock_gating(adev); 948 949 /* enable VCPU clock */ 950 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 951 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 952 953 /* disable master interrupt */ 954 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, 955 ~UVD_MASTINT_EN__VCPU_EN_MASK); 956 957 /* setup mmUVD_LMI_CTRL */ 958 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL); 959 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp | 960 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 961 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 962 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 963 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 964 965 /* setup mmUVD_MPC_CNTL */ 966 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL); 967 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 968 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 969 WREG32_SOC15(VCN, 0, mmUVD_MPC_CNTL, tmp); 970 971 /* setup UVD_MPC_SET_MUXA0 */ 972 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, 973 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 974 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 975 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 976 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 977 978 /* setup UVD_MPC_SET_MUXB0 */ 979 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, 980 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 981 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 982 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 983 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 984 985 /* setup mmUVD_MPC_SET_MUX */ 986 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, 987 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 988 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 989 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 990 991 vcn_v2_0_mc_resume(adev); 992 993 /* release VCPU reset to boot */ 994 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 995 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 996 997 /* enable LMI MC and UMC channels */ 998 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, 999 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1000 1001 tmp = RREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET); 1002 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1003 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1004 WREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET, tmp); 1005 1006 /* disable byte swapping */ 1007 lmi_swap_cntl = 0; 1008 #ifdef __BIG_ENDIAN 1009 /* swap (8 in 32) RB and IB */ 1010 lmi_swap_cntl = 0xa; 1011 #endif 1012 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 1013 1014 for (i = 0; i < 10; ++i) { 1015 uint32_t status; 1016 1017 for (j = 0; j < 100; ++j) { 1018 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); 1019 if (status & 2) 1020 break; 1021 mdelay(10); 1022 } 1023 r = 0; 1024 if (status & 2) 1025 break; 1026 1027 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n"); 1028 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1029 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 1030 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1031 mdelay(10); 1032 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 1033 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1034 mdelay(10); 1035 r = -1; 1036 } 1037 1038 if (r) { 1039 DRM_ERROR("VCN decode not responding, giving up!!!\n"); 1040 return r; 1041 } 1042 1043 /* enable master interrupt */ 1044 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 1045 UVD_MASTINT_EN__VCPU_EN_MASK, 1046 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1047 1048 /* clear the busy bit of VCN_STATUS */ 1049 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0, 1050 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1051 1052 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_VMID, 0); 1053 1054 /* force RBC into idle state */ 1055 rb_bufsz = order_base_2(ring->ring_size); 1056 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1057 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1058 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1059 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1060 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1061 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 1062 1063 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET; 1064 /* program the RB_BASE for ring buffer */ 1065 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1066 lower_32_bits(ring->gpu_addr)); 1067 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1068 upper_32_bits(ring->gpu_addr)); 1069 1070 /* Initialize the ring buffer's read and write pointers */ 1071 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); 1072 1073 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 1074 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1075 lower_32_bits(ring->wptr)); 1076 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET; 1077 1078 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET; 1079 ring = &adev->vcn.inst->ring_enc[0]; 1080 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1081 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1082 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); 1083 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1084 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 1085 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET; 1086 1087 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET; 1088 ring = &adev->vcn.inst->ring_enc[1]; 1089 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1090 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1091 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1092 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1093 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); 1094 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET; 1095 1096 return 0; 1097 } 1098 1099 static int vcn_v2_0_stop_dpg_mode(struct amdgpu_device *adev) 1100 { 1101 struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE}; 1102 uint32_t tmp; 1103 1104 vcn_v2_0_pause_dpg_mode(adev, 0, &state); 1105 /* Wait for power status to be 1 */ 1106 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1, 1107 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1108 1109 /* wait for read ptr to be equal to write ptr */ 1110 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); 1111 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1112 1113 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); 1114 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); 1115 1116 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1117 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); 1118 1119 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1, 1120 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1121 1122 /* disable dynamic power gating mode */ 1123 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0, 1124 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1125 1126 return 0; 1127 } 1128 1129 static int vcn_v2_0_stop(struct amdgpu_device *adev) 1130 { 1131 uint32_t tmp; 1132 int r; 1133 1134 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1135 r = vcn_v2_0_stop_dpg_mode(adev); 1136 if (r) 1137 return r; 1138 goto power_off; 1139 } 1140 1141 /* wait for uvd idle */ 1142 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1143 if (r) 1144 return r; 1145 1146 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1147 UVD_LMI_STATUS__READ_CLEAN_MASK | 1148 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1149 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1150 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp); 1151 if (r) 1152 return r; 1153 1154 /* stall UMC channel */ 1155 tmp = RREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2); 1156 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1157 WREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2, tmp); 1158 1159 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK| 1160 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1161 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp); 1162 if (r) 1163 return r; 1164 1165 /* disable VCPU clock */ 1166 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0, 1167 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1168 1169 /* reset LMI UMC */ 1170 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1171 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK, 1172 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 1173 1174 /* reset LMI */ 1175 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1176 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK, 1177 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); 1178 1179 /* reset VCPU */ 1180 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1181 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 1182 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1183 1184 /* clear status */ 1185 WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0); 1186 1187 vcn_v2_0_enable_clock_gating(adev); 1188 vcn_v2_0_enable_static_power_gating(adev); 1189 1190 power_off: 1191 if (adev->pm.dpm_enabled) 1192 amdgpu_dpm_enable_uvd(adev, false); 1193 1194 return 0; 1195 } 1196 1197 static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev, 1198 int inst_idx, struct dpg_pause_state *new_state) 1199 { 1200 struct amdgpu_ring *ring; 1201 uint32_t reg_data = 0; 1202 int ret_code; 1203 1204 /* pause/unpause if state is changed */ 1205 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1206 DRM_DEBUG("dpg pause state changed %d -> %d", 1207 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1208 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & 1209 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1210 1211 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1212 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 0x1, 1213 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1214 1215 if (!ret_code) { 1216 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr; 1217 /* pause DPG */ 1218 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1219 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1220 1221 /* wait for ACK */ 1222 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, 1223 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1224 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1225 1226 /* Stall DPG before WPTR/RPTR reset */ 1227 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 1228 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1229 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1230 /* Restore */ 1231 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET; 1232 ring = &adev->vcn.inst->ring_enc[0]; 1233 ring->wptr = 0; 1234 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); 1235 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1236 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 1237 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1238 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1239 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET; 1240 1241 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET; 1242 ring = &adev->vcn.inst->ring_enc[1]; 1243 ring->wptr = 0; 1244 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1245 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1246 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); 1247 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1248 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1249 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET; 1250 1251 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET; 1252 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1253 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); 1254 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET; 1255 /* Unstall DPG */ 1256 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 1257 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1258 1259 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1260 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, 1261 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1262 } 1263 } else { 1264 /* unpause dpg, no need to wait */ 1265 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1266 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1267 } 1268 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1269 } 1270 1271 return 0; 1272 } 1273 1274 static bool vcn_v2_0_is_idle(void *handle) 1275 { 1276 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1277 1278 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); 1279 } 1280 1281 static int vcn_v2_0_wait_for_idle(void *handle) 1282 { 1283 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1284 int ret; 1285 1286 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 1287 UVD_STATUS__IDLE); 1288 1289 return ret; 1290 } 1291 1292 static int vcn_v2_0_set_clockgating_state(void *handle, 1293 enum amd_clockgating_state state) 1294 { 1295 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1296 bool enable = (state == AMD_CG_STATE_GATE); 1297 1298 if (amdgpu_sriov_vf(adev)) 1299 return 0; 1300 1301 if (enable) { 1302 /* wait for STATUS to clear */ 1303 if (!vcn_v2_0_is_idle(handle)) 1304 return -EBUSY; 1305 vcn_v2_0_enable_clock_gating(adev); 1306 } else { 1307 /* disable HW gating and enable Sw gating */ 1308 vcn_v2_0_disable_clock_gating(adev); 1309 } 1310 return 0; 1311 } 1312 1313 /** 1314 * vcn_v2_0_dec_ring_get_rptr - get read pointer 1315 * 1316 * @ring: amdgpu_ring pointer 1317 * 1318 * Returns the current hardware read pointer 1319 */ 1320 static uint64_t vcn_v2_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 1321 { 1322 struct amdgpu_device *adev = ring->adev; 1323 1324 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 1325 } 1326 1327 /** 1328 * vcn_v2_0_dec_ring_get_wptr - get write pointer 1329 * 1330 * @ring: amdgpu_ring pointer 1331 * 1332 * Returns the current hardware write pointer 1333 */ 1334 static uint64_t vcn_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 1335 { 1336 struct amdgpu_device *adev = ring->adev; 1337 1338 if (ring->use_doorbell) 1339 return adev->wb.wb[ring->wptr_offs]; 1340 else 1341 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR); 1342 } 1343 1344 /** 1345 * vcn_v2_0_dec_ring_set_wptr - set write pointer 1346 * 1347 * @ring: amdgpu_ring pointer 1348 * 1349 * Commits the write pointer to the hardware 1350 */ 1351 static void vcn_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 1352 { 1353 struct amdgpu_device *adev = ring->adev; 1354 1355 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1356 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 1357 lower_32_bits(ring->wptr) | 0x80000000); 1358 1359 if (ring->use_doorbell) { 1360 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 1361 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1362 } else { 1363 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1364 } 1365 } 1366 1367 /** 1368 * vcn_v2_0_dec_ring_insert_start - insert a start command 1369 * 1370 * @ring: amdgpu_ring pointer 1371 * 1372 * Write a start command to the ring. 1373 */ 1374 void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring) 1375 { 1376 struct amdgpu_device *adev = ring->adev; 1377 1378 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); 1379 amdgpu_ring_write(ring, 0); 1380 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); 1381 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1)); 1382 } 1383 1384 /** 1385 * vcn_v2_0_dec_ring_insert_end - insert a end command 1386 * 1387 * @ring: amdgpu_ring pointer 1388 * 1389 * Write a end command to the ring. 1390 */ 1391 void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring) 1392 { 1393 struct amdgpu_device *adev = ring->adev; 1394 1395 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); 1396 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END << 1)); 1397 } 1398 1399 /** 1400 * vcn_v2_0_dec_ring_insert_nop - insert a nop command 1401 * 1402 * @ring: amdgpu_ring pointer 1403 * @count: the number of NOP packets to insert 1404 * 1405 * Write a nop command to the ring. 1406 */ 1407 void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 1408 { 1409 struct amdgpu_device *adev = ring->adev; 1410 int i; 1411 1412 WARN_ON(ring->wptr % 2 || count % 2); 1413 1414 for (i = 0; i < count / 2; i++) { 1415 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.nop, 0)); 1416 amdgpu_ring_write(ring, 0); 1417 } 1418 } 1419 1420 /** 1421 * vcn_v2_0_dec_ring_emit_fence - emit an fence & trap command 1422 * 1423 * @ring: amdgpu_ring pointer 1424 * @addr: address 1425 * @seq: sequence number 1426 * @flags: fence related flags 1427 * 1428 * Write a fence and a trap command to the ring. 1429 */ 1430 void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 1431 unsigned flags) 1432 { 1433 struct amdgpu_device *adev = ring->adev; 1434 1435 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1436 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.context_id, 0)); 1437 amdgpu_ring_write(ring, seq); 1438 1439 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); 1440 amdgpu_ring_write(ring, addr & 0xffffffff); 1441 1442 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); 1443 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 1444 1445 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); 1446 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_FENCE << 1)); 1447 1448 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); 1449 amdgpu_ring_write(ring, 0); 1450 1451 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); 1452 amdgpu_ring_write(ring, 0); 1453 1454 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); 1455 1456 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_TRAP << 1)); 1457 } 1458 1459 /** 1460 * vcn_v2_0_dec_ring_emit_ib - execute indirect buffer 1461 * 1462 * @ring: amdgpu_ring pointer 1463 * @job: job to retrieve vmid from 1464 * @ib: indirect buffer to execute 1465 * @flags: unused 1466 * 1467 * Write ring commands to execute the indirect buffer 1468 */ 1469 void vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring, 1470 struct amdgpu_job *job, 1471 struct amdgpu_ib *ib, 1472 uint32_t flags) 1473 { 1474 struct amdgpu_device *adev = ring->adev; 1475 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1476 1477 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_vmid, 0)); 1478 amdgpu_ring_write(ring, vmid); 1479 1480 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_low, 0)); 1481 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1482 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_high, 0)); 1483 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1484 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_size, 0)); 1485 amdgpu_ring_write(ring, ib->length_dw); 1486 } 1487 1488 void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1489 uint32_t val, uint32_t mask) 1490 { 1491 struct amdgpu_device *adev = ring->adev; 1492 1493 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); 1494 amdgpu_ring_write(ring, reg << 2); 1495 1496 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); 1497 amdgpu_ring_write(ring, val); 1498 1499 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.gp_scratch8, 0)); 1500 amdgpu_ring_write(ring, mask); 1501 1502 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); 1503 1504 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_REG_READ_COND_WAIT << 1)); 1505 } 1506 1507 void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, 1508 unsigned vmid, uint64_t pd_addr) 1509 { 1510 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1511 uint32_t data0, data1, mask; 1512 1513 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1514 1515 /* wait for register write */ 1516 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance; 1517 data1 = lower_32_bits(pd_addr); 1518 mask = 0xffffffff; 1519 vcn_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask); 1520 } 1521 1522 void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, 1523 uint32_t reg, uint32_t val) 1524 { 1525 struct amdgpu_device *adev = ring->adev; 1526 1527 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); 1528 amdgpu_ring_write(ring, reg << 2); 1529 1530 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); 1531 amdgpu_ring_write(ring, val); 1532 1533 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); 1534 1535 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_WRITE_REG << 1)); 1536 } 1537 1538 /** 1539 * vcn_v2_0_enc_ring_get_rptr - get enc read pointer 1540 * 1541 * @ring: amdgpu_ring pointer 1542 * 1543 * Returns the current hardware enc read pointer 1544 */ 1545 static uint64_t vcn_v2_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 1546 { 1547 struct amdgpu_device *adev = ring->adev; 1548 1549 if (ring == &adev->vcn.inst->ring_enc[0]) 1550 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR); 1551 else 1552 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2); 1553 } 1554 1555 /** 1556 * vcn_v2_0_enc_ring_get_wptr - get enc write pointer 1557 * 1558 * @ring: amdgpu_ring pointer 1559 * 1560 * Returns the current hardware enc write pointer 1561 */ 1562 static uint64_t vcn_v2_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 1563 { 1564 struct amdgpu_device *adev = ring->adev; 1565 1566 if (ring == &adev->vcn.inst->ring_enc[0]) { 1567 if (ring->use_doorbell) 1568 return adev->wb.wb[ring->wptr_offs]; 1569 else 1570 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); 1571 } else { 1572 if (ring->use_doorbell) 1573 return adev->wb.wb[ring->wptr_offs]; 1574 else 1575 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); 1576 } 1577 } 1578 1579 /** 1580 * vcn_v2_0_enc_ring_set_wptr - set enc write pointer 1581 * 1582 * @ring: amdgpu_ring pointer 1583 * 1584 * Commits the enc write pointer to the hardware 1585 */ 1586 static void vcn_v2_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 1587 { 1588 struct amdgpu_device *adev = ring->adev; 1589 1590 if (ring == &adev->vcn.inst->ring_enc[0]) { 1591 if (ring->use_doorbell) { 1592 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 1593 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1594 } else { 1595 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1596 } 1597 } else { 1598 if (ring->use_doorbell) { 1599 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 1600 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1601 } else { 1602 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1603 } 1604 } 1605 } 1606 1607 /** 1608 * vcn_v2_0_enc_ring_emit_fence - emit an enc fence & trap command 1609 * 1610 * @ring: amdgpu_ring pointer 1611 * @addr: address 1612 * @seq: sequence number 1613 * @flags: fence related flags 1614 * 1615 * Write enc a fence and a trap command to the ring. 1616 */ 1617 void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1618 u64 seq, unsigned flags) 1619 { 1620 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1621 1622 amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE); 1623 amdgpu_ring_write(ring, addr); 1624 amdgpu_ring_write(ring, upper_32_bits(addr)); 1625 amdgpu_ring_write(ring, seq); 1626 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP); 1627 } 1628 1629 void vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring *ring) 1630 { 1631 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 1632 } 1633 1634 /** 1635 * vcn_v2_0_enc_ring_emit_ib - enc execute indirect buffer 1636 * 1637 * @ring: amdgpu_ring pointer 1638 * @job: job to retrive vmid from 1639 * @ib: indirect buffer to execute 1640 * @flags: unused 1641 * 1642 * Write enc ring commands to execute the indirect buffer 1643 */ 1644 void vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring *ring, 1645 struct amdgpu_job *job, 1646 struct amdgpu_ib *ib, 1647 uint32_t flags) 1648 { 1649 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1650 1651 amdgpu_ring_write(ring, VCN_ENC_CMD_IB); 1652 amdgpu_ring_write(ring, vmid); 1653 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1654 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1655 amdgpu_ring_write(ring, ib->length_dw); 1656 } 1657 1658 void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1659 uint32_t val, uint32_t mask) 1660 { 1661 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); 1662 amdgpu_ring_write(ring, reg << 2); 1663 amdgpu_ring_write(ring, mask); 1664 amdgpu_ring_write(ring, val); 1665 } 1666 1667 void vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1668 unsigned int vmid, uint64_t pd_addr) 1669 { 1670 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1671 1672 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1673 1674 /* wait for reg writes */ 1675 vcn_v2_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + 1676 vmid * hub->ctx_addr_distance, 1677 lower_32_bits(pd_addr), 0xffffffff); 1678 } 1679 1680 void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) 1681 { 1682 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); 1683 amdgpu_ring_write(ring, reg << 2); 1684 amdgpu_ring_write(ring, val); 1685 } 1686 1687 static int vcn_v2_0_set_interrupt_state(struct amdgpu_device *adev, 1688 struct amdgpu_irq_src *source, 1689 unsigned type, 1690 enum amdgpu_interrupt_state state) 1691 { 1692 return 0; 1693 } 1694 1695 static int vcn_v2_0_process_interrupt(struct amdgpu_device *adev, 1696 struct amdgpu_irq_src *source, 1697 struct amdgpu_iv_entry *entry) 1698 { 1699 DRM_DEBUG("IH: VCN TRAP\n"); 1700 1701 switch (entry->src_id) { 1702 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT: 1703 amdgpu_fence_process(&adev->vcn.inst->ring_dec); 1704 break; 1705 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1706 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]); 1707 break; 1708 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY: 1709 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]); 1710 break; 1711 default: 1712 DRM_ERROR("Unhandled interrupt: %d %d\n", 1713 entry->src_id, entry->src_data[0]); 1714 break; 1715 } 1716 1717 return 0; 1718 } 1719 1720 int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring) 1721 { 1722 struct amdgpu_device *adev = ring->adev; 1723 uint32_t tmp = 0; 1724 unsigned i; 1725 int r; 1726 1727 if (amdgpu_sriov_vf(adev)) 1728 return 0; 1729 1730 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); 1731 r = amdgpu_ring_alloc(ring, 4); 1732 if (r) 1733 return r; 1734 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); 1735 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1)); 1736 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0)); 1737 amdgpu_ring_write(ring, 0xDEADBEEF); 1738 amdgpu_ring_commit(ring); 1739 for (i = 0; i < adev->usec_timeout; i++) { 1740 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); 1741 if (tmp == 0xDEADBEEF) 1742 break; 1743 udelay(1); 1744 } 1745 1746 if (i >= adev->usec_timeout) 1747 r = -ETIMEDOUT; 1748 1749 return r; 1750 } 1751 1752 1753 static int vcn_v2_0_set_powergating_state(void *handle, 1754 enum amd_powergating_state state) 1755 { 1756 /* This doesn't actually powergate the VCN block. 1757 * That's done in the dpm code via the SMC. This 1758 * just re-inits the block as necessary. The actual 1759 * gating still happens in the dpm code. We should 1760 * revisit this when there is a cleaner line between 1761 * the smc and the hw blocks 1762 */ 1763 int ret; 1764 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1765 1766 if (amdgpu_sriov_vf(adev)) { 1767 adev->vcn.cur_state = AMD_PG_STATE_UNGATE; 1768 return 0; 1769 } 1770 1771 if (state == adev->vcn.cur_state) 1772 return 0; 1773 1774 if (state == AMD_PG_STATE_GATE) 1775 ret = vcn_v2_0_stop(adev); 1776 else 1777 ret = vcn_v2_0_start(adev); 1778 1779 if (!ret) 1780 adev->vcn.cur_state = state; 1781 return ret; 1782 } 1783 1784 static int vcn_v2_0_start_mmsch(struct amdgpu_device *adev, 1785 struct amdgpu_mm_table *table) 1786 { 1787 uint32_t data = 0, loop; 1788 uint64_t addr = table->gpu_addr; 1789 struct mmsch_v2_0_init_header *header; 1790 uint32_t size; 1791 int i; 1792 1793 header = (struct mmsch_v2_0_init_header *)table->cpu_addr; 1794 size = header->header_size + header->vcn_table_size; 1795 1796 /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr 1797 * of memory descriptor location 1798 */ 1799 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr)); 1800 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr)); 1801 1802 /* 2, update vmid of descriptor */ 1803 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID); 1804 data &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1805 /* use domain0 for MM scheduler */ 1806 data |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1807 WREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID, data); 1808 1809 /* 3, notify mmsch about the size of this descriptor */ 1810 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_SIZE, size); 1811 1812 /* 4, set resp to zero */ 1813 WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP, 0); 1814 1815 adev->vcn.inst->ring_dec.wptr = 0; 1816 adev->vcn.inst->ring_dec.wptr_old = 0; 1817 vcn_v2_0_dec_ring_set_wptr(&adev->vcn.inst->ring_dec); 1818 1819 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 1820 adev->vcn.inst->ring_enc[i].wptr = 0; 1821 adev->vcn.inst->ring_enc[i].wptr_old = 0; 1822 vcn_v2_0_enc_ring_set_wptr(&adev->vcn.inst->ring_enc[i]); 1823 } 1824 1825 /* 5, kick off the initialization and wait until 1826 * VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero 1827 */ 1828 WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_HOST, 0x10000001); 1829 1830 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP); 1831 loop = 1000; 1832 while ((data & 0x10000002) != 0x10000002) { 1833 udelay(10); 1834 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP); 1835 loop--; 1836 if (!loop) 1837 break; 1838 } 1839 1840 if (!loop) { 1841 DRM_ERROR("failed to init MMSCH, " \ 1842 "mmMMSCH_VF_MAILBOX_RESP = 0x%08x\n", data); 1843 return -EBUSY; 1844 } 1845 1846 return 0; 1847 } 1848 1849 static int vcn_v2_0_start_sriov(struct amdgpu_device *adev) 1850 { 1851 int r; 1852 uint32_t tmp; 1853 struct amdgpu_ring *ring; 1854 uint32_t offset, size; 1855 uint32_t table_size = 0; 1856 struct mmsch_v2_0_cmd_direct_write direct_wt = { {0} }; 1857 struct mmsch_v2_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} }; 1858 struct mmsch_v2_0_cmd_end end = { {0} }; 1859 struct mmsch_v2_0_init_header *header; 1860 uint32_t *init_table = adev->virt.mm_table.cpu_addr; 1861 uint8_t i = 0; 1862 1863 header = (struct mmsch_v2_0_init_header *)init_table; 1864 direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE; 1865 direct_rd_mod_wt.cmd_header.command_type = 1866 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1867 end.cmd_header.command_type = MMSCH_COMMAND__END; 1868 1869 if (header->vcn_table_offset == 0 && header->vcn_table_size == 0) { 1870 header->version = MMSCH_VERSION; 1871 header->header_size = sizeof(struct mmsch_v2_0_init_header) >> 2; 1872 1873 header->vcn_table_offset = header->header_size; 1874 1875 init_table += header->vcn_table_offset; 1876 1877 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 1878 1879 MMSCH_V2_0_INSERT_DIRECT_RD_MOD_WT( 1880 SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 1881 0xFFFFFFFF, 0x00000004); 1882 1883 /* mc resume*/ 1884 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1885 MMSCH_V2_0_INSERT_DIRECT_WT( 1886 SOC15_REG_OFFSET(UVD, i, 1887 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1888 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo); 1889 MMSCH_V2_0_INSERT_DIRECT_WT( 1890 SOC15_REG_OFFSET(UVD, i, 1891 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1892 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi); 1893 offset = 0; 1894 } else { 1895 MMSCH_V2_0_INSERT_DIRECT_WT( 1896 SOC15_REG_OFFSET(UVD, i, 1897 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1898 lower_32_bits(adev->vcn.inst->gpu_addr)); 1899 MMSCH_V2_0_INSERT_DIRECT_WT( 1900 SOC15_REG_OFFSET(UVD, i, 1901 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1902 upper_32_bits(adev->vcn.inst->gpu_addr)); 1903 offset = size; 1904 } 1905 1906 MMSCH_V2_0_INSERT_DIRECT_WT( 1907 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0), 1908 0); 1909 MMSCH_V2_0_INSERT_DIRECT_WT( 1910 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), 1911 size); 1912 1913 MMSCH_V2_0_INSERT_DIRECT_WT( 1914 SOC15_REG_OFFSET(UVD, i, 1915 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 1916 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); 1917 MMSCH_V2_0_INSERT_DIRECT_WT( 1918 SOC15_REG_OFFSET(UVD, i, 1919 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 1920 upper_32_bits(adev->vcn.inst->gpu_addr + offset)); 1921 MMSCH_V2_0_INSERT_DIRECT_WT( 1922 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1), 1923 0); 1924 MMSCH_V2_0_INSERT_DIRECT_WT( 1925 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1), 1926 AMDGPU_VCN_STACK_SIZE); 1927 1928 MMSCH_V2_0_INSERT_DIRECT_WT( 1929 SOC15_REG_OFFSET(UVD, i, 1930 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 1931 lower_32_bits(adev->vcn.inst->gpu_addr + offset + 1932 AMDGPU_VCN_STACK_SIZE)); 1933 MMSCH_V2_0_INSERT_DIRECT_WT( 1934 SOC15_REG_OFFSET(UVD, i, 1935 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 1936 upper_32_bits(adev->vcn.inst->gpu_addr + offset + 1937 AMDGPU_VCN_STACK_SIZE)); 1938 MMSCH_V2_0_INSERT_DIRECT_WT( 1939 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2), 1940 0); 1941 MMSCH_V2_0_INSERT_DIRECT_WT( 1942 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2), 1943 AMDGPU_VCN_CONTEXT_SIZE); 1944 1945 for (r = 0; r < adev->vcn.num_enc_rings; ++r) { 1946 ring = &adev->vcn.inst->ring_enc[r]; 1947 ring->wptr = 0; 1948 MMSCH_V2_0_INSERT_DIRECT_WT( 1949 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO), 1950 lower_32_bits(ring->gpu_addr)); 1951 MMSCH_V2_0_INSERT_DIRECT_WT( 1952 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), 1953 upper_32_bits(ring->gpu_addr)); 1954 MMSCH_V2_0_INSERT_DIRECT_WT( 1955 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE), 1956 ring->ring_size / 4); 1957 } 1958 1959 ring = &adev->vcn.inst->ring_dec; 1960 ring->wptr = 0; 1961 MMSCH_V2_0_INSERT_DIRECT_WT( 1962 SOC15_REG_OFFSET(UVD, i, 1963 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW), 1964 lower_32_bits(ring->gpu_addr)); 1965 MMSCH_V2_0_INSERT_DIRECT_WT( 1966 SOC15_REG_OFFSET(UVD, i, 1967 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH), 1968 upper_32_bits(ring->gpu_addr)); 1969 /* force RBC into idle state */ 1970 tmp = order_base_2(ring->ring_size); 1971 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp); 1972 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1973 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1974 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1975 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1976 MMSCH_V2_0_INSERT_DIRECT_WT( 1977 SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp); 1978 1979 /* add end packet */ 1980 tmp = sizeof(struct mmsch_v2_0_cmd_end); 1981 memcpy((void *)init_table, &end, tmp); 1982 table_size += (tmp / 4); 1983 header->vcn_table_size = table_size; 1984 1985 } 1986 return vcn_v2_0_start_mmsch(adev, &adev->virt.mm_table); 1987 } 1988 1989 static const struct amd_ip_funcs vcn_v2_0_ip_funcs = { 1990 .name = "vcn_v2_0", 1991 .early_init = vcn_v2_0_early_init, 1992 .late_init = NULL, 1993 .sw_init = vcn_v2_0_sw_init, 1994 .sw_fini = vcn_v2_0_sw_fini, 1995 .hw_init = vcn_v2_0_hw_init, 1996 .hw_fini = vcn_v2_0_hw_fini, 1997 .suspend = vcn_v2_0_suspend, 1998 .resume = vcn_v2_0_resume, 1999 .is_idle = vcn_v2_0_is_idle, 2000 .wait_for_idle = vcn_v2_0_wait_for_idle, 2001 .check_soft_reset = NULL, 2002 .pre_soft_reset = NULL, 2003 .soft_reset = NULL, 2004 .post_soft_reset = NULL, 2005 .set_clockgating_state = vcn_v2_0_set_clockgating_state, 2006 .set_powergating_state = vcn_v2_0_set_powergating_state, 2007 }; 2008 2009 static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = { 2010 .type = AMDGPU_RING_TYPE_VCN_DEC, 2011 .align_mask = 0xf, 2012 .secure_submission_supported = true, 2013 .vmhub = AMDGPU_MMHUB_0, 2014 .get_rptr = vcn_v2_0_dec_ring_get_rptr, 2015 .get_wptr = vcn_v2_0_dec_ring_get_wptr, 2016 .set_wptr = vcn_v2_0_dec_ring_set_wptr, 2017 .emit_frame_size = 2018 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 2019 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 2020 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */ 2021 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */ 2022 6, 2023 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */ 2024 .emit_ib = vcn_v2_0_dec_ring_emit_ib, 2025 .emit_fence = vcn_v2_0_dec_ring_emit_fence, 2026 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush, 2027 .test_ring = vcn_v2_0_dec_ring_test_ring, 2028 .test_ib = amdgpu_vcn_dec_ring_test_ib, 2029 .insert_nop = vcn_v2_0_dec_ring_insert_nop, 2030 .insert_start = vcn_v2_0_dec_ring_insert_start, 2031 .insert_end = vcn_v2_0_dec_ring_insert_end, 2032 .pad_ib = amdgpu_ring_generic_pad_ib, 2033 .begin_use = amdgpu_vcn_ring_begin_use, 2034 .end_use = amdgpu_vcn_ring_end_use, 2035 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg, 2036 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait, 2037 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2038 }; 2039 2040 static const struct amdgpu_ring_funcs vcn_v2_0_enc_ring_vm_funcs = { 2041 .type = AMDGPU_RING_TYPE_VCN_ENC, 2042 .align_mask = 0x3f, 2043 .nop = VCN_ENC_CMD_NO_OP, 2044 .vmhub = AMDGPU_MMHUB_0, 2045 .get_rptr = vcn_v2_0_enc_ring_get_rptr, 2046 .get_wptr = vcn_v2_0_enc_ring_get_wptr, 2047 .set_wptr = vcn_v2_0_enc_ring_set_wptr, 2048 .emit_frame_size = 2049 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2050 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 2051 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 2052 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 2053 1, /* vcn_v2_0_enc_ring_insert_end */ 2054 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 2055 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 2056 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 2057 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 2058 .test_ring = amdgpu_vcn_enc_ring_test_ring, 2059 .test_ib = amdgpu_vcn_enc_ring_test_ib, 2060 .insert_nop = amdgpu_ring_insert_nop, 2061 .insert_end = vcn_v2_0_enc_ring_insert_end, 2062 .pad_ib = amdgpu_ring_generic_pad_ib, 2063 .begin_use = amdgpu_vcn_ring_begin_use, 2064 .end_use = amdgpu_vcn_ring_end_use, 2065 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 2066 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 2067 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2068 }; 2069 2070 static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev) 2071 { 2072 adev->vcn.inst->ring_dec.funcs = &vcn_v2_0_dec_ring_vm_funcs; 2073 DRM_INFO("VCN decode is enabled in VM mode\n"); 2074 } 2075 2076 static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev) 2077 { 2078 int i; 2079 2080 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 2081 adev->vcn.inst->ring_enc[i].funcs = &vcn_v2_0_enc_ring_vm_funcs; 2082 2083 DRM_INFO("VCN encode is enabled in VM mode\n"); 2084 } 2085 2086 static const struct amdgpu_irq_src_funcs vcn_v2_0_irq_funcs = { 2087 .set = vcn_v2_0_set_interrupt_state, 2088 .process = vcn_v2_0_process_interrupt, 2089 }; 2090 2091 static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev) 2092 { 2093 adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 1; 2094 adev->vcn.inst->irq.funcs = &vcn_v2_0_irq_funcs; 2095 } 2096 2097 const struct amdgpu_ip_block_version vcn_v2_0_ip_block = 2098 { 2099 .type = AMD_IP_BLOCK_TYPE_VCN, 2100 .major = 2, 2101 .minor = 0, 2102 .rev = 0, 2103 .funcs = &vcn_v2_0_ip_funcs, 2104 }; 2105