1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_vcn.h" 28 #include "soc15.h" 29 #include "soc15d.h" 30 #include "amdgpu_pm.h" 31 #include "amdgpu_psp.h" 32 33 #include "vcn/vcn_2_0_0_offset.h" 34 #include "vcn/vcn_2_0_0_sh_mask.h" 35 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 36 37 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x1fd 38 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x503 39 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x504 40 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x505 41 #define mmUVD_NO_OP_INTERNAL_OFFSET 0x53f 42 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x54a 43 #define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d 44 45 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x1e1 46 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x5a6 47 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x5a7 48 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x1e2 49 50 #define mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET 0x1bfff 51 #define mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET 0x4029 52 #define mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET 0x402a 53 #define mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET 0x402b 54 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40ea 55 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40eb 56 #define mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET 0x40cf 57 #define mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET 0x40d1 58 #define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40e8 59 #define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40e9 60 #define mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET 0x4082 61 #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40ec 62 #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40ed 63 #define mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET 0x4085 64 #define mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET 0x4084 65 #define mmUVD_JRBC_STATUS_INTERNAL_OFFSET 0x4089 66 #define mmUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f 67 68 #define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR 0x18000 69 70 #define mmUVD_RBC_XX_IB_REG_CHECK 0x026b 71 #define mmUVD_RBC_XX_IB_REG_CHECK_BASE_IDX 1 72 #define mmUVD_REG_XX_MASK 0x026c 73 #define mmUVD_REG_XX_MASK_BASE_IDX 1 74 75 static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev); 76 static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev); 77 static void vcn_v2_0_set_jpeg_ring_funcs(struct amdgpu_device *adev); 78 static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev); 79 static int vcn_v2_0_set_powergating_state(void *handle, 80 enum amd_powergating_state state); 81 static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev, 82 struct dpg_pause_state *new_state); 83 84 /** 85 * vcn_v2_0_early_init - set function pointers 86 * 87 * @handle: amdgpu_device pointer 88 * 89 * Set ring and irq function pointers 90 */ 91 static int vcn_v2_0_early_init(void *handle) 92 { 93 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 94 95 adev->vcn.num_enc_rings = 2; 96 97 vcn_v2_0_set_dec_ring_funcs(adev); 98 vcn_v2_0_set_enc_ring_funcs(adev); 99 vcn_v2_0_set_jpeg_ring_funcs(adev); 100 vcn_v2_0_set_irq_funcs(adev); 101 102 return 0; 103 } 104 105 /** 106 * vcn_v2_0_sw_init - sw init for VCN block 107 * 108 * @handle: amdgpu_device pointer 109 * 110 * Load firmware and sw initialization 111 */ 112 static int vcn_v2_0_sw_init(void *handle) 113 { 114 struct amdgpu_ring *ring; 115 int i, r; 116 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 117 118 /* VCN DEC TRAP */ 119 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 120 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, 121 &adev->vcn.irq); 122 if (r) 123 return r; 124 125 /* VCN ENC TRAP */ 126 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 127 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 128 i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, 129 &adev->vcn.irq); 130 if (r) 131 return r; 132 } 133 134 /* VCN JPEG TRAP */ 135 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 136 VCN_2_0__SRCID__JPEG_DECODE, 137 &adev->vcn.irq); 138 if (r) 139 return r; 140 141 r = amdgpu_vcn_sw_init(adev); 142 if (r) 143 return r; 144 145 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 146 const struct common_firmware_header *hdr; 147 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 148 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN; 149 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw; 150 adev->firmware.fw_size += 151 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 152 DRM_INFO("PSP loading VCN firmware\n"); 153 } 154 155 r = amdgpu_vcn_resume(adev); 156 if (r) 157 return r; 158 159 ring = &adev->vcn.ring_dec; 160 161 ring->use_doorbell = true; 162 ring->doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1 << 1; 163 164 sprintf(ring->name, "vcn_dec"); 165 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0); 166 if (r) 167 return r; 168 169 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; 170 adev->vcn.external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9); 171 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; 172 adev->vcn.external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0); 173 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; 174 adev->vcn.external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1); 175 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; 176 adev->vcn.external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD); 177 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; 178 adev->vcn.external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP); 179 180 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 181 ring = &adev->vcn.ring_enc[i]; 182 ring->use_doorbell = true; 183 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i; 184 sprintf(ring->name, "vcn_enc%d", i); 185 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0); 186 if (r) 187 return r; 188 } 189 190 ring = &adev->vcn.ring_jpeg; 191 ring->use_doorbell = true; 192 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1; 193 sprintf(ring->name, "vcn_jpeg"); 194 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0); 195 if (r) 196 return r; 197 198 adev->vcn.pause_dpg_mode = vcn_v2_0_pause_dpg_mode; 199 200 adev->vcn.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET; 201 adev->vcn.external.jpeg_pitch = SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH); 202 203 return 0; 204 } 205 206 /** 207 * vcn_v2_0_sw_fini - sw fini for VCN block 208 * 209 * @handle: amdgpu_device pointer 210 * 211 * VCN suspend and free up sw allocation 212 */ 213 static int vcn_v2_0_sw_fini(void *handle) 214 { 215 int r; 216 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 217 218 r = amdgpu_vcn_suspend(adev); 219 if (r) 220 return r; 221 222 r = amdgpu_vcn_sw_fini(adev); 223 224 return r; 225 } 226 227 /** 228 * vcn_v2_0_hw_init - start and test VCN block 229 * 230 * @handle: amdgpu_device pointer 231 * 232 * Initialize the hardware, boot up the VCPU and do some testing 233 */ 234 static int vcn_v2_0_hw_init(void *handle) 235 { 236 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 237 struct amdgpu_ring *ring = &adev->vcn.ring_dec; 238 int i, r; 239 240 adev->nbio_funcs->vcn_doorbell_range(adev, ring->use_doorbell, 241 ring->doorbell_index); 242 243 ring->sched.ready = true; 244 r = amdgpu_ring_test_ring(ring); 245 if (r) { 246 ring->sched.ready = false; 247 goto done; 248 } 249 250 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 251 ring = &adev->vcn.ring_enc[i]; 252 ring->sched.ready = true; 253 r = amdgpu_ring_test_ring(ring); 254 if (r) { 255 ring->sched.ready = false; 256 goto done; 257 } 258 } 259 260 ring = &adev->vcn.ring_jpeg; 261 ring->sched.ready = true; 262 r = amdgpu_ring_test_ring(ring); 263 if (r) { 264 ring->sched.ready = false; 265 goto done; 266 } 267 268 done: 269 if (!r) 270 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 271 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 272 273 return r; 274 } 275 276 /** 277 * vcn_v2_0_hw_fini - stop the hardware block 278 * 279 * @handle: amdgpu_device pointer 280 * 281 * Stop the VCN block, mark ring as not ready any more 282 */ 283 static int vcn_v2_0_hw_fini(void *handle) 284 { 285 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 286 struct amdgpu_ring *ring = &adev->vcn.ring_dec; 287 int i; 288 289 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 290 (adev->vcn.cur_state != AMD_PG_STATE_GATE && 291 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) 292 vcn_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 293 294 ring->sched.ready = false; 295 296 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 297 ring = &adev->vcn.ring_enc[i]; 298 ring->sched.ready = false; 299 } 300 301 ring = &adev->vcn.ring_jpeg; 302 ring->sched.ready = false; 303 304 return 0; 305 } 306 307 /** 308 * vcn_v2_0_suspend - suspend VCN block 309 * 310 * @handle: amdgpu_device pointer 311 * 312 * HW fini and suspend VCN block 313 */ 314 static int vcn_v2_0_suspend(void *handle) 315 { 316 int r; 317 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 318 319 r = vcn_v2_0_hw_fini(adev); 320 if (r) 321 return r; 322 323 r = amdgpu_vcn_suspend(adev); 324 325 return r; 326 } 327 328 /** 329 * vcn_v2_0_resume - resume VCN block 330 * 331 * @handle: amdgpu_device pointer 332 * 333 * Resume firmware and hw init VCN block 334 */ 335 static int vcn_v2_0_resume(void *handle) 336 { 337 int r; 338 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 339 340 r = amdgpu_vcn_resume(adev); 341 if (r) 342 return r; 343 344 r = vcn_v2_0_hw_init(adev); 345 346 return r; 347 } 348 349 /** 350 * vcn_v2_0_mc_resume - memory controller programming 351 * 352 * @adev: amdgpu_device pointer 353 * 354 * Let the VCN memory controller know it's offsets 355 */ 356 static void vcn_v2_0_mc_resume(struct amdgpu_device *adev) 357 { 358 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 359 uint32_t offset; 360 361 /* cache window 0: fw */ 362 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 363 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 364 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo)); 365 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 366 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi)); 367 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); 368 offset = 0; 369 } else { 370 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 371 lower_32_bits(adev->vcn.gpu_addr)); 372 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 373 upper_32_bits(adev->vcn.gpu_addr)); 374 offset = size; 375 /* No signed header for now from firmware 376 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 377 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 378 */ 379 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); 380 } 381 382 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); 383 384 /* cache window 1: stack */ 385 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 386 lower_32_bits(adev->vcn.gpu_addr + offset)); 387 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 388 upper_32_bits(adev->vcn.gpu_addr + offset)); 389 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0); 390 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 391 392 /* cache window 2: context */ 393 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 394 lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 395 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 396 upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 397 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0); 398 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 399 400 WREG32_SOC15(UVD, 0, mmUVD_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 401 WREG32_SOC15(UVD, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 402 } 403 404 static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirect) 405 { 406 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 407 uint32_t offset; 408 409 /* cache window 0: fw */ 410 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 411 if (!indirect) { 412 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 413 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 414 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0, indirect); 415 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 416 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 417 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0, indirect); 418 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 419 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 420 } else { 421 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 422 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 423 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 424 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 425 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 426 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 427 } 428 offset = 0; 429 } else { 430 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 431 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 432 lower_32_bits(adev->vcn.gpu_addr), 0, indirect); 433 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 434 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 435 upper_32_bits(adev->vcn.gpu_addr), 0, indirect); 436 offset = size; 437 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 438 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 439 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 440 } 441 442 if (!indirect) 443 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 444 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 445 else 446 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 447 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 448 449 /* cache window 1: stack */ 450 if (!indirect) { 451 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 452 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 453 lower_32_bits(adev->vcn.gpu_addr + offset), 0, indirect); 454 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 455 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 456 upper_32_bits(adev->vcn.gpu_addr + offset), 0, indirect); 457 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 458 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 459 } else { 460 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 461 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 462 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 463 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 464 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 465 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 466 } 467 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 468 UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 469 470 /* cache window 2: context */ 471 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 472 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 473 lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 474 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 475 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 476 upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 477 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 478 UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 479 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 480 UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 481 482 /* non-cache window */ 483 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 484 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect); 485 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 486 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect); 487 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 488 UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 489 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 490 UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect); 491 492 /* VCN global tiling registers */ 493 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 494 UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 495 } 496 497 /** 498 * vcn_v2_0_disable_clock_gating - disable VCN clock gating 499 * 500 * @adev: amdgpu_device pointer 501 * @sw: enable SW clock gating 502 * 503 * Disable clock gating for VCN block 504 */ 505 static void vcn_v2_0_disable_clock_gating(struct amdgpu_device *adev) 506 { 507 uint32_t data; 508 509 /* UVD disable CGC */ 510 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 511 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 512 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 513 else 514 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 515 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 516 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 517 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 518 519 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); 520 data &= ~(UVD_CGC_GATE__SYS_MASK 521 | UVD_CGC_GATE__UDEC_MASK 522 | UVD_CGC_GATE__MPEG2_MASK 523 | UVD_CGC_GATE__REGS_MASK 524 | UVD_CGC_GATE__RBC_MASK 525 | UVD_CGC_GATE__LMI_MC_MASK 526 | UVD_CGC_GATE__LMI_UMC_MASK 527 | UVD_CGC_GATE__IDCT_MASK 528 | UVD_CGC_GATE__MPRD_MASK 529 | UVD_CGC_GATE__MPC_MASK 530 | UVD_CGC_GATE__LBSI_MASK 531 | UVD_CGC_GATE__LRBBM_MASK 532 | UVD_CGC_GATE__UDEC_RE_MASK 533 | UVD_CGC_GATE__UDEC_CM_MASK 534 | UVD_CGC_GATE__UDEC_IT_MASK 535 | UVD_CGC_GATE__UDEC_DB_MASK 536 | UVD_CGC_GATE__UDEC_MP_MASK 537 | UVD_CGC_GATE__WCB_MASK 538 | UVD_CGC_GATE__VCPU_MASK 539 | UVD_CGC_GATE__SCPU_MASK); 540 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data); 541 542 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 543 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 544 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 545 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 546 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 547 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 548 | UVD_CGC_CTRL__SYS_MODE_MASK 549 | UVD_CGC_CTRL__UDEC_MODE_MASK 550 | UVD_CGC_CTRL__MPEG2_MODE_MASK 551 | UVD_CGC_CTRL__REGS_MODE_MASK 552 | UVD_CGC_CTRL__RBC_MODE_MASK 553 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 554 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 555 | UVD_CGC_CTRL__IDCT_MODE_MASK 556 | UVD_CGC_CTRL__MPRD_MODE_MASK 557 | UVD_CGC_CTRL__MPC_MODE_MASK 558 | UVD_CGC_CTRL__LBSI_MODE_MASK 559 | UVD_CGC_CTRL__LRBBM_MODE_MASK 560 | UVD_CGC_CTRL__WCB_MODE_MASK 561 | UVD_CGC_CTRL__VCPU_MODE_MASK 562 | UVD_CGC_CTRL__SCPU_MODE_MASK); 563 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 564 565 /* turn on */ 566 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); 567 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 568 | UVD_SUVD_CGC_GATE__SIT_MASK 569 | UVD_SUVD_CGC_GATE__SMP_MASK 570 | UVD_SUVD_CGC_GATE__SCM_MASK 571 | UVD_SUVD_CGC_GATE__SDB_MASK 572 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 573 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 574 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 575 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 576 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 577 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 578 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 579 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 580 | UVD_SUVD_CGC_GATE__SCLR_MASK 581 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 582 | UVD_SUVD_CGC_GATE__ENT_MASK 583 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 584 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 585 | UVD_SUVD_CGC_GATE__SITE_MASK 586 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 587 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 588 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 589 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 590 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 591 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data); 592 593 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); 594 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 595 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 596 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 597 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 598 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 599 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 600 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 601 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 602 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 603 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 604 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); 605 } 606 607 static void vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_device *adev, 608 uint8_t sram_sel, uint8_t indirect) 609 { 610 uint32_t reg_data = 0; 611 612 /* enable sw clock gating control */ 613 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 614 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 615 else 616 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 617 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 618 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 619 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 620 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 621 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 622 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 623 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 624 UVD_CGC_CTRL__SYS_MODE_MASK | 625 UVD_CGC_CTRL__UDEC_MODE_MASK | 626 UVD_CGC_CTRL__MPEG2_MODE_MASK | 627 UVD_CGC_CTRL__REGS_MODE_MASK | 628 UVD_CGC_CTRL__RBC_MODE_MASK | 629 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 630 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 631 UVD_CGC_CTRL__IDCT_MODE_MASK | 632 UVD_CGC_CTRL__MPRD_MODE_MASK | 633 UVD_CGC_CTRL__MPC_MODE_MASK | 634 UVD_CGC_CTRL__LBSI_MODE_MASK | 635 UVD_CGC_CTRL__LRBBM_MODE_MASK | 636 UVD_CGC_CTRL__WCB_MODE_MASK | 637 UVD_CGC_CTRL__VCPU_MODE_MASK | 638 UVD_CGC_CTRL__SCPU_MODE_MASK); 639 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 640 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); 641 642 /* turn off clock gating */ 643 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 644 UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect); 645 646 /* turn on SUVD clock gating */ 647 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 648 UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 649 650 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 651 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 652 UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 653 } 654 655 /** 656 * jpeg_v2_0_start - start JPEG block 657 * 658 * @adev: amdgpu_device pointer 659 * 660 * Setup and start the JPEG block 661 */ 662 static int jpeg_v2_0_start(struct amdgpu_device *adev) 663 { 664 struct amdgpu_ring *ring = &adev->vcn.ring_jpeg; 665 uint32_t tmp; 666 int r = 0; 667 668 /* disable power gating */ 669 tmp = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT; 670 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_PGFSM_CONFIG), tmp); 671 672 SOC15_WAIT_ON_RREG(VCN, 0, 673 mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON, 674 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r); 675 676 if (r) { 677 DRM_ERROR("amdgpu: JPEG disable power gating failed\n"); 678 return r; 679 } 680 681 /* Removing the anti hang mechanism to indicate the UVDJ tile is ON */ 682 tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS)) & ~0x1; 683 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS), tmp); 684 685 /* JPEG disable CGC */ 686 tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); 687 tmp |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 688 tmp |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 689 tmp |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 690 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, tmp); 691 692 tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); 693 tmp &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK 694 | JPEG_CGC_GATE__JPEG2_DEC_MASK 695 | JPEG_CGC_GATE__JPEG_ENC_MASK 696 | JPEG_CGC_GATE__JMCIF_MASK 697 | JPEG_CGC_GATE__JRBBM_MASK); 698 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, tmp); 699 700 /* enable JMI channel */ 701 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_JMI_CNTL), 0, 702 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 703 704 /* enable System Interrupt for JRBC */ 705 WREG32_P(SOC15_REG_OFFSET(VCN, 0, mmJPEG_SYS_INT_EN), 706 JPEG_SYS_INT_EN__DJRBC_MASK, 707 ~JPEG_SYS_INT_EN__DJRBC_MASK); 708 709 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0); 710 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); 711 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 712 lower_32_bits(ring->gpu_addr)); 713 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 714 upper_32_bits(ring->gpu_addr)); 715 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, 0); 716 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, 0); 717 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L); 718 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4); 719 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); 720 721 return 0; 722 } 723 724 /** 725 * jpeg_v2_0_stop - stop JPEG block 726 * 727 * @adev: amdgpu_device pointer 728 * 729 * stop the JPEG block 730 */ 731 static int jpeg_v2_0_stop(struct amdgpu_device *adev) 732 { 733 uint32_t tmp; 734 int r = 0; 735 736 /* reset JMI */ 737 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_JMI_CNTL), 738 UVD_JMI_CNTL__SOFT_RESET_MASK, 739 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 740 741 /* enable JPEG CGC */ 742 tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); 743 tmp |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 744 tmp |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 745 tmp |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 746 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, tmp); 747 748 749 tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); 750 tmp |= (JPEG_CGC_GATE__JPEG_DEC_MASK 751 |JPEG_CGC_GATE__JPEG2_DEC_MASK 752 |JPEG_CGC_GATE__JPEG_ENC_MASK 753 |JPEG_CGC_GATE__JMCIF_MASK 754 |JPEG_CGC_GATE__JRBBM_MASK); 755 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, tmp); 756 757 /* enable power gating */ 758 tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS)); 759 tmp &= ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK; 760 tmp |= 0x1; //UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_TILES_OFF; 761 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS), tmp); 762 763 tmp = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT; 764 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_PGFSM_CONFIG), tmp); 765 766 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 767 (2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT), 768 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r); 769 770 if (r) { 771 DRM_ERROR("amdgpu: JPEG enable power gating failed\n"); 772 return r; 773 } 774 775 return r; 776 } 777 778 /** 779 * vcn_v2_0_enable_clock_gating - enable VCN clock gating 780 * 781 * @adev: amdgpu_device pointer 782 * @sw: enable SW clock gating 783 * 784 * Enable clock gating for VCN block 785 */ 786 static void vcn_v2_0_enable_clock_gating(struct amdgpu_device *adev) 787 { 788 uint32_t data = 0; 789 790 /* enable UVD CGC */ 791 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 792 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 793 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 794 else 795 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 796 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 797 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 798 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 799 800 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 801 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 802 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 803 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 804 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 805 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 806 | UVD_CGC_CTRL__SYS_MODE_MASK 807 | UVD_CGC_CTRL__UDEC_MODE_MASK 808 | UVD_CGC_CTRL__MPEG2_MODE_MASK 809 | UVD_CGC_CTRL__REGS_MODE_MASK 810 | UVD_CGC_CTRL__RBC_MODE_MASK 811 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 812 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 813 | UVD_CGC_CTRL__IDCT_MODE_MASK 814 | UVD_CGC_CTRL__MPRD_MODE_MASK 815 | UVD_CGC_CTRL__MPC_MODE_MASK 816 | UVD_CGC_CTRL__LBSI_MODE_MASK 817 | UVD_CGC_CTRL__LRBBM_MODE_MASK 818 | UVD_CGC_CTRL__WCB_MODE_MASK 819 | UVD_CGC_CTRL__VCPU_MODE_MASK 820 | UVD_CGC_CTRL__SCPU_MODE_MASK); 821 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 822 823 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); 824 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 825 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 826 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 827 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 828 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 829 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 830 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 831 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 832 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 833 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 834 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); 835 } 836 837 static void vcn_v2_0_disable_static_power_gating(struct amdgpu_device *adev) 838 { 839 uint32_t data = 0; 840 int ret; 841 842 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 843 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 844 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 845 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 846 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 847 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 848 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 849 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 850 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 851 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 852 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT); 853 854 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 855 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 856 UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0, 0xFFFFF, ret); 857 } else { 858 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 859 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 860 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 861 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 862 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 863 | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 864 | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 865 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 866 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 867 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT); 868 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 869 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFF, ret); 870 } 871 872 /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS, 873 * UVDU_PWR_STATUS are 0 (power on) */ 874 875 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); 876 data &= ~0x103; 877 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 878 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 879 UVD_POWER_STATUS__UVD_PG_EN_MASK; 880 881 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); 882 } 883 884 static void vcn_v2_0_enable_static_power_gating(struct amdgpu_device *adev) 885 { 886 uint32_t data = 0; 887 int ret; 888 889 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 890 /* Before power off, this indicator has to be turned on */ 891 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); 892 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 893 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 894 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); 895 896 897 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 898 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 899 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 900 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 901 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 902 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 903 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 904 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 905 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 906 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT); 907 908 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 909 910 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 911 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 912 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 913 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 914 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 915 | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT 916 | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT 917 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 918 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 919 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT); 920 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFF, ret); 921 } 922 } 923 924 static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect) 925 { 926 struct amdgpu_ring *ring = &adev->vcn.ring_dec; 927 uint32_t rb_bufsz, tmp; 928 929 vcn_v2_0_enable_static_power_gating(adev); 930 931 /* enable dynamic power gating mode */ 932 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); 933 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 934 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 935 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp); 936 937 if (indirect) 938 adev->vcn.dpg_sram_curr_addr = (uint32_t*)adev->vcn.dpg_sram_cpu_addr; 939 940 /* enable clock gating */ 941 vcn_v2_0_clock_gating_dpg_mode(adev, 0, indirect); 942 943 /* enable VCPU clock */ 944 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 945 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 946 tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK; 947 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 948 UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); 949 950 /* disable master interupt */ 951 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 952 UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect); 953 954 /* setup mmUVD_LMI_CTRL */ 955 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 956 UVD_LMI_CTRL__REQ_MODE_MASK | 957 UVD_LMI_CTRL__CRC_RESET_MASK | 958 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 959 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 960 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 961 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 962 0x00100000L); 963 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 964 UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect); 965 966 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 967 UVD, 0, mmUVD_MPC_CNTL), 968 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 969 970 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 971 UVD, 0, mmUVD_MPC_SET_MUXA0), 972 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 973 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 974 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 975 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 976 977 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 978 UVD, 0, mmUVD_MPC_SET_MUXB0), 979 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 980 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 981 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 982 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 983 984 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 985 UVD, 0, mmUVD_MPC_SET_MUX), 986 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 987 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 988 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 989 990 vcn_v2_0_mc_resume_dpg_mode(adev, indirect); 991 992 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 993 UVD, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect); 994 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 995 UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect); 996 997 /* release VCPU reset to boot */ 998 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 999 UVD, 0, mmUVD_SOFT_RESET), 0, 0, indirect); 1000 1001 /* enable LMI MC and UMC channels */ 1002 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 1003 UVD, 0, mmUVD_LMI_CTRL2), 1004 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 0, indirect); 1005 1006 /* enable master interrupt */ 1007 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 1008 UVD, 0, mmUVD_MASTINT_EN), 1009 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 1010 1011 if (indirect) 1012 psp_update_vcn_sram(adev, 0, adev->vcn.dpg_sram_gpu_addr, 1013 (uint32_t)((uintptr_t)adev->vcn.dpg_sram_curr_addr - 1014 (uintptr_t)adev->vcn.dpg_sram_cpu_addr)); 1015 1016 /* force RBC into idle state */ 1017 rb_bufsz = order_base_2(ring->ring_size); 1018 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1019 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1020 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1021 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1022 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1023 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 1024 1025 /* set the write pointer delay */ 1026 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); 1027 1028 /* set the wb address */ 1029 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, 1030 (upper_32_bits(ring->gpu_addr) >> 2)); 1031 1032 /* programm the RB_BASE for ring buffer */ 1033 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1034 lower_32_bits(ring->gpu_addr)); 1035 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1036 upper_32_bits(ring->gpu_addr)); 1037 1038 /* Initialize the ring buffer's read and write pointers */ 1039 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); 1040 1041 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); 1042 1043 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 1044 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1045 lower_32_bits(ring->wptr)); 1046 1047 return 0; 1048 } 1049 1050 static int vcn_v2_0_start(struct amdgpu_device *adev) 1051 { 1052 struct amdgpu_ring *ring = &adev->vcn.ring_dec; 1053 uint32_t rb_bufsz, tmp; 1054 uint32_t lmi_swap_cntl; 1055 int i, j, r; 1056 1057 if (adev->pm.dpm_enabled) 1058 amdgpu_dpm_enable_uvd(adev, true); 1059 1060 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1061 r = vcn_v2_0_start_dpg_mode(adev, adev->vcn.indirect_sram); 1062 if (r) 1063 return r; 1064 goto jpeg; 1065 } 1066 1067 vcn_v2_0_disable_static_power_gating(adev); 1068 1069 /* set uvd status busy */ 1070 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 1071 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); 1072 1073 /*SW clock gating */ 1074 vcn_v2_0_disable_clock_gating(adev); 1075 1076 /* enable VCPU clock */ 1077 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 1078 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 1079 1080 /* disable master interrupt */ 1081 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, 1082 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1083 1084 /* setup mmUVD_LMI_CTRL */ 1085 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL); 1086 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp | 1087 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1088 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1089 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1090 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1091 1092 /* setup mmUVD_MPC_CNTL */ 1093 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL); 1094 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1095 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1096 WREG32_SOC15(VCN, 0, mmUVD_MPC_CNTL, tmp); 1097 1098 /* setup UVD_MPC_SET_MUXA0 */ 1099 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, 1100 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1101 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1102 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1103 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1104 1105 /* setup UVD_MPC_SET_MUXB0 */ 1106 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, 1107 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1108 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1109 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1110 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1111 1112 /* setup mmUVD_MPC_SET_MUX */ 1113 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, 1114 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1115 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1116 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1117 1118 vcn_v2_0_mc_resume(adev); 1119 1120 /* release VCPU reset to boot */ 1121 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 1122 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1123 1124 /* enable LMI MC and UMC channels */ 1125 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, 1126 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1127 1128 tmp = RREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET); 1129 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1130 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1131 WREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET, tmp); 1132 1133 /* disable byte swapping */ 1134 lmi_swap_cntl = 0; 1135 #ifdef __BIG_ENDIAN 1136 /* swap (8 in 32) RB and IB */ 1137 lmi_swap_cntl = 0xa; 1138 #endif 1139 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 1140 1141 for (i = 0; i < 10; ++i) { 1142 uint32_t status; 1143 1144 for (j = 0; j < 100; ++j) { 1145 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); 1146 if (status & 2) 1147 break; 1148 mdelay(10); 1149 } 1150 r = 0; 1151 if (status & 2) 1152 break; 1153 1154 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n"); 1155 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1156 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 1157 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1158 mdelay(10); 1159 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 1160 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1161 mdelay(10); 1162 r = -1; 1163 } 1164 1165 if (r) { 1166 DRM_ERROR("VCN decode not responding, giving up!!!\n"); 1167 return r; 1168 } 1169 1170 /* enable master interrupt */ 1171 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 1172 UVD_MASTINT_EN__VCPU_EN_MASK, 1173 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1174 1175 /* clear the busy bit of VCN_STATUS */ 1176 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0, 1177 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1178 1179 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_VMID, 0); 1180 1181 /* force RBC into idle state */ 1182 rb_bufsz = order_base_2(ring->ring_size); 1183 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1184 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1185 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1186 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1187 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1188 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 1189 1190 /* programm the RB_BASE for ring buffer */ 1191 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1192 lower_32_bits(ring->gpu_addr)); 1193 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1194 upper_32_bits(ring->gpu_addr)); 1195 1196 /* Initialize the ring buffer's read and write pointers */ 1197 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); 1198 1199 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 1200 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1201 lower_32_bits(ring->wptr)); 1202 1203 ring = &adev->vcn.ring_enc[0]; 1204 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1205 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1206 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); 1207 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1208 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 1209 1210 ring = &adev->vcn.ring_enc[1]; 1211 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1212 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1213 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1214 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1215 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); 1216 1217 jpeg: 1218 r = jpeg_v2_0_start(adev); 1219 1220 return r; 1221 } 1222 1223 static int vcn_v2_0_stop_dpg_mode(struct amdgpu_device *adev) 1224 { 1225 int ret_code = 0; 1226 uint32_t tmp; 1227 1228 /* Wait for power status to be 1 */ 1229 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1, 1230 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1231 1232 /* wait for read ptr to be equal to write ptr */ 1233 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); 1234 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF, ret_code); 1235 1236 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); 1237 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF, ret_code); 1238 1239 tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); 1240 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code); 1241 1242 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1243 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code); 1244 1245 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1, 1246 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1247 1248 /* disable dynamic power gating mode */ 1249 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0, 1250 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1251 1252 return 0; 1253 } 1254 1255 static int vcn_v2_0_stop(struct amdgpu_device *adev) 1256 { 1257 uint32_t tmp; 1258 int r; 1259 1260 r = jpeg_v2_0_stop(adev); 1261 if (r) 1262 return r; 1263 1264 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1265 r = vcn_v2_0_stop_dpg_mode(adev); 1266 if (r) 1267 return r; 1268 goto power_off; 1269 } 1270 1271 /* wait for uvd idle */ 1272 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r); 1273 if (r) 1274 return r; 1275 1276 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1277 UVD_LMI_STATUS__READ_CLEAN_MASK | 1278 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1279 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1280 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp, r); 1281 if (r) 1282 return r; 1283 1284 /* stall UMC channel */ 1285 tmp = RREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2); 1286 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1287 WREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2, tmp); 1288 1289 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK| 1290 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1291 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp, r); 1292 if (r) 1293 return r; 1294 1295 /* disable VCPU clock */ 1296 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0, 1297 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1298 1299 /* reset LMI UMC */ 1300 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1301 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK, 1302 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 1303 1304 /* reset LMI */ 1305 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1306 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK, 1307 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); 1308 1309 /* reset VCPU */ 1310 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1311 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 1312 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1313 1314 /* clear status */ 1315 WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0); 1316 1317 vcn_v2_0_enable_clock_gating(adev); 1318 vcn_v2_0_enable_static_power_gating(adev); 1319 1320 power_off: 1321 if (adev->pm.dpm_enabled) 1322 amdgpu_dpm_enable_uvd(adev, false); 1323 1324 return 0; 1325 } 1326 1327 static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev, 1328 struct dpg_pause_state *new_state) 1329 { 1330 struct amdgpu_ring *ring; 1331 uint32_t reg_data = 0; 1332 int ret_code; 1333 1334 /* pause/unpause if state is changed */ 1335 if (adev->vcn.pause_state.fw_based != new_state->fw_based) { 1336 DRM_DEBUG("dpg pause state changed %d -> %d", 1337 adev->vcn.pause_state.fw_based, new_state->fw_based); 1338 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & 1339 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1340 1341 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1342 ret_code = 0; 1343 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 0x1, 1344 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1345 1346 if (!ret_code) { 1347 /* pause DPG */ 1348 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1349 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1350 1351 /* wait for ACK */ 1352 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, 1353 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1354 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code); 1355 1356 /* Restore */ 1357 ring = &adev->vcn.ring_enc[0]; 1358 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); 1359 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1360 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 1361 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1362 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1363 1364 ring = &adev->vcn.ring_enc[1]; 1365 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1366 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1367 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); 1368 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1369 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1370 1371 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1372 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); 1373 1374 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1375 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, 1376 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1377 } 1378 } else { 1379 /* unpause dpg, no need to wait */ 1380 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1381 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1382 } 1383 adev->vcn.pause_state.fw_based = new_state->fw_based; 1384 } 1385 1386 return 0; 1387 } 1388 1389 static bool vcn_v2_0_is_idle(void *handle) 1390 { 1391 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1392 1393 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); 1394 } 1395 1396 static int vcn_v2_0_wait_for_idle(void *handle) 1397 { 1398 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1399 int ret = 0; 1400 1401 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 1402 UVD_STATUS__IDLE, ret); 1403 1404 return ret; 1405 } 1406 1407 static int vcn_v2_0_set_clockgating_state(void *handle, 1408 enum amd_clockgating_state state) 1409 { 1410 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1411 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 1412 1413 if (enable) { 1414 /* wait for STATUS to clear */ 1415 if (vcn_v2_0_is_idle(handle)) 1416 return -EBUSY; 1417 vcn_v2_0_enable_clock_gating(adev); 1418 } else { 1419 /* disable HW gating and enable Sw gating */ 1420 vcn_v2_0_disable_clock_gating(adev); 1421 } 1422 return 0; 1423 } 1424 1425 /** 1426 * vcn_v2_0_dec_ring_get_rptr - get read pointer 1427 * 1428 * @ring: amdgpu_ring pointer 1429 * 1430 * Returns the current hardware read pointer 1431 */ 1432 static uint64_t vcn_v2_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 1433 { 1434 struct amdgpu_device *adev = ring->adev; 1435 1436 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 1437 } 1438 1439 /** 1440 * vcn_v2_0_dec_ring_get_wptr - get write pointer 1441 * 1442 * @ring: amdgpu_ring pointer 1443 * 1444 * Returns the current hardware write pointer 1445 */ 1446 static uint64_t vcn_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 1447 { 1448 struct amdgpu_device *adev = ring->adev; 1449 1450 if (ring->use_doorbell) 1451 return adev->wb.wb[ring->wptr_offs]; 1452 else 1453 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR); 1454 } 1455 1456 /** 1457 * vcn_v2_0_dec_ring_set_wptr - set write pointer 1458 * 1459 * @ring: amdgpu_ring pointer 1460 * 1461 * Commits the write pointer to the hardware 1462 */ 1463 static void vcn_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 1464 { 1465 struct amdgpu_device *adev = ring->adev; 1466 1467 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1468 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 1469 lower_32_bits(ring->wptr) | 0x80000000); 1470 1471 if (ring->use_doorbell) { 1472 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 1473 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1474 } else { 1475 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1476 } 1477 } 1478 1479 /** 1480 * vcn_v2_0_dec_ring_insert_start - insert a start command 1481 * 1482 * @ring: amdgpu_ring pointer 1483 * 1484 * Write a start command to the ring. 1485 */ 1486 static void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring) 1487 { 1488 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET, 0)); 1489 amdgpu_ring_write(ring, 0); 1490 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0)); 1491 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1); 1492 } 1493 1494 /** 1495 * vcn_v2_0_dec_ring_insert_end - insert a end command 1496 * 1497 * @ring: amdgpu_ring pointer 1498 * 1499 * Write a end command to the ring. 1500 */ 1501 static void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring) 1502 { 1503 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0)); 1504 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1); 1505 } 1506 1507 /** 1508 * vcn_v2_0_dec_ring_insert_nop - insert a nop command 1509 * 1510 * @ring: amdgpu_ring pointer 1511 * 1512 * Write a nop command to the ring. 1513 */ 1514 static void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 1515 { 1516 int i; 1517 1518 WARN_ON(ring->wptr % 2 || count % 2); 1519 1520 for (i = 0; i < count / 2; i++) { 1521 amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP_INTERNAL_OFFSET, 0)); 1522 amdgpu_ring_write(ring, 0); 1523 } 1524 } 1525 1526 /** 1527 * vcn_v2_0_dec_ring_emit_fence - emit an fence & trap command 1528 * 1529 * @ring: amdgpu_ring pointer 1530 * @fence: fence to emit 1531 * 1532 * Write a fence and a trap command to the ring. 1533 */ 1534 static void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 1535 unsigned flags) 1536 { 1537 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1538 1539 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID_INTERNAL_OFFSET, 0)); 1540 amdgpu_ring_write(ring, seq); 1541 1542 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET, 0)); 1543 amdgpu_ring_write(ring, addr & 0xffffffff); 1544 1545 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET, 0)); 1546 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 1547 1548 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0)); 1549 amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1); 1550 1551 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET, 0)); 1552 amdgpu_ring_write(ring, 0); 1553 1554 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET, 0)); 1555 amdgpu_ring_write(ring, 0); 1556 1557 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0)); 1558 1559 amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1); 1560 } 1561 1562 /** 1563 * vcn_v2_0_dec_ring_emit_ib - execute indirect buffer 1564 * 1565 * @ring: amdgpu_ring pointer 1566 * @ib: indirect buffer to execute 1567 * 1568 * Write ring commands to execute the indirect buffer 1569 */ 1570 static void vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring, 1571 struct amdgpu_job *job, 1572 struct amdgpu_ib *ib, 1573 uint32_t flags) 1574 { 1575 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1576 1577 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET, 0)); 1578 amdgpu_ring_write(ring, vmid); 1579 1580 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET, 0)); 1581 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1582 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET, 0)); 1583 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1584 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET, 0)); 1585 amdgpu_ring_write(ring, ib->length_dw); 1586 } 1587 1588 static void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, 1589 uint32_t reg, uint32_t val, 1590 uint32_t mask) 1591 { 1592 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET, 0)); 1593 amdgpu_ring_write(ring, reg << 2); 1594 1595 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET, 0)); 1596 amdgpu_ring_write(ring, val); 1597 1598 amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8_INTERNAL_OFFSET, 0)); 1599 amdgpu_ring_write(ring, mask); 1600 1601 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0)); 1602 1603 amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1); 1604 } 1605 1606 static void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, 1607 unsigned vmid, uint64_t pd_addr) 1608 { 1609 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1610 uint32_t data0, data1, mask; 1611 1612 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1613 1614 /* wait for register write */ 1615 data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2; 1616 data1 = lower_32_bits(pd_addr); 1617 mask = 0xffffffff; 1618 vcn_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask); 1619 } 1620 1621 static void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, 1622 uint32_t reg, uint32_t val) 1623 { 1624 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET, 0)); 1625 amdgpu_ring_write(ring, reg << 2); 1626 1627 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET, 0)); 1628 amdgpu_ring_write(ring, val); 1629 1630 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0)); 1631 1632 amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1); 1633 } 1634 1635 /** 1636 * vcn_v2_0_enc_ring_get_rptr - get enc read pointer 1637 * 1638 * @ring: amdgpu_ring pointer 1639 * 1640 * Returns the current hardware enc read pointer 1641 */ 1642 static uint64_t vcn_v2_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 1643 { 1644 struct amdgpu_device *adev = ring->adev; 1645 1646 if (ring == &adev->vcn.ring_enc[0]) 1647 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR); 1648 else 1649 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2); 1650 } 1651 1652 /** 1653 * vcn_v2_0_enc_ring_get_wptr - get enc write pointer 1654 * 1655 * @ring: amdgpu_ring pointer 1656 * 1657 * Returns the current hardware enc write pointer 1658 */ 1659 static uint64_t vcn_v2_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 1660 { 1661 struct amdgpu_device *adev = ring->adev; 1662 1663 if (ring == &adev->vcn.ring_enc[0]) { 1664 if (ring->use_doorbell) 1665 return adev->wb.wb[ring->wptr_offs]; 1666 else 1667 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); 1668 } else { 1669 if (ring->use_doorbell) 1670 return adev->wb.wb[ring->wptr_offs]; 1671 else 1672 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); 1673 } 1674 } 1675 1676 /** 1677 * vcn_v2_0_enc_ring_set_wptr - set enc write pointer 1678 * 1679 * @ring: amdgpu_ring pointer 1680 * 1681 * Commits the enc write pointer to the hardware 1682 */ 1683 static void vcn_v2_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 1684 { 1685 struct amdgpu_device *adev = ring->adev; 1686 1687 if (ring == &adev->vcn.ring_enc[0]) { 1688 if (ring->use_doorbell) { 1689 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 1690 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1691 } else { 1692 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1693 } 1694 } else { 1695 if (ring->use_doorbell) { 1696 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 1697 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1698 } else { 1699 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1700 } 1701 } 1702 } 1703 1704 /** 1705 * vcn_v2_0_enc_ring_emit_fence - emit an enc fence & trap command 1706 * 1707 * @ring: amdgpu_ring pointer 1708 * @fence: fence to emit 1709 * 1710 * Write enc a fence and a trap command to the ring. 1711 */ 1712 static void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1713 u64 seq, unsigned flags) 1714 { 1715 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1716 1717 amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE); 1718 amdgpu_ring_write(ring, addr); 1719 amdgpu_ring_write(ring, upper_32_bits(addr)); 1720 amdgpu_ring_write(ring, seq); 1721 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP); 1722 } 1723 1724 static void vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring *ring) 1725 { 1726 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 1727 } 1728 1729 /** 1730 * vcn_v2_0_enc_ring_emit_ib - enc execute indirect buffer 1731 * 1732 * @ring: amdgpu_ring pointer 1733 * @ib: indirect buffer to execute 1734 * 1735 * Write enc ring commands to execute the indirect buffer 1736 */ 1737 static void vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring *ring, 1738 struct amdgpu_job *job, 1739 struct amdgpu_ib *ib, 1740 uint32_t flags) 1741 { 1742 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1743 1744 amdgpu_ring_write(ring, VCN_ENC_CMD_IB); 1745 amdgpu_ring_write(ring, vmid); 1746 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1747 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1748 amdgpu_ring_write(ring, ib->length_dw); 1749 } 1750 1751 static void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, 1752 uint32_t reg, uint32_t val, 1753 uint32_t mask) 1754 { 1755 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); 1756 amdgpu_ring_write(ring, reg << 2); 1757 amdgpu_ring_write(ring, mask); 1758 amdgpu_ring_write(ring, val); 1759 } 1760 1761 static void vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1762 unsigned int vmid, uint64_t pd_addr) 1763 { 1764 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1765 1766 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1767 1768 /* wait for reg writes */ 1769 vcn_v2_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2, 1770 lower_32_bits(pd_addr), 0xffffffff); 1771 } 1772 1773 static void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, 1774 uint32_t reg, uint32_t val) 1775 { 1776 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); 1777 amdgpu_ring_write(ring, reg << 2); 1778 amdgpu_ring_write(ring, val); 1779 } 1780 1781 /** 1782 * vcn_v2_0_jpeg_ring_get_rptr - get read pointer 1783 * 1784 * @ring: amdgpu_ring pointer 1785 * 1786 * Returns the current hardware read pointer 1787 */ 1788 static uint64_t vcn_v2_0_jpeg_ring_get_rptr(struct amdgpu_ring *ring) 1789 { 1790 struct amdgpu_device *adev = ring->adev; 1791 1792 return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR); 1793 } 1794 1795 /** 1796 * vcn_v2_0_jpeg_ring_get_wptr - get write pointer 1797 * 1798 * @ring: amdgpu_ring pointer 1799 * 1800 * Returns the current hardware write pointer 1801 */ 1802 static uint64_t vcn_v2_0_jpeg_ring_get_wptr(struct amdgpu_ring *ring) 1803 { 1804 struct amdgpu_device *adev = ring->adev; 1805 1806 if (ring->use_doorbell) 1807 return adev->wb.wb[ring->wptr_offs]; 1808 else 1809 return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); 1810 } 1811 1812 /** 1813 * vcn_v2_0_jpeg_ring_set_wptr - set write pointer 1814 * 1815 * @ring: amdgpu_ring pointer 1816 * 1817 * Commits the write pointer to the hardware 1818 */ 1819 static void vcn_v2_0_jpeg_ring_set_wptr(struct amdgpu_ring *ring) 1820 { 1821 struct amdgpu_device *adev = ring->adev; 1822 1823 if (ring->use_doorbell) { 1824 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 1825 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1826 } else { 1827 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); 1828 } 1829 } 1830 1831 /** 1832 * vcn_v2_0_jpeg_ring_insert_start - insert a start command 1833 * 1834 * @ring: amdgpu_ring pointer 1835 * 1836 * Write a start command to the ring. 1837 */ 1838 static void vcn_v2_0_jpeg_ring_insert_start(struct amdgpu_ring *ring) 1839 { 1840 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 1841 0, 0, PACKETJ_TYPE0)); 1842 amdgpu_ring_write(ring, 0x68e04); 1843 1844 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 1845 0, 0, PACKETJ_TYPE0)); 1846 amdgpu_ring_write(ring, 0x80010000); 1847 } 1848 1849 /** 1850 * vcn_v2_0_jpeg_ring_insert_end - insert a end command 1851 * 1852 * @ring: amdgpu_ring pointer 1853 * 1854 * Write a end command to the ring. 1855 */ 1856 static void vcn_v2_0_jpeg_ring_insert_end(struct amdgpu_ring *ring) 1857 { 1858 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 1859 0, 0, PACKETJ_TYPE0)); 1860 amdgpu_ring_write(ring, 0x68e04); 1861 1862 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 1863 0, 0, PACKETJ_TYPE0)); 1864 amdgpu_ring_write(ring, 0x00010000); 1865 } 1866 1867 /** 1868 * vcn_v2_0_jpeg_ring_emit_fence - emit an fence & trap command 1869 * 1870 * @ring: amdgpu_ring pointer 1871 * @fence: fence to emit 1872 * 1873 * Write a fence and a trap command to the ring. 1874 */ 1875 static void vcn_v2_0_jpeg_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 1876 unsigned flags) 1877 { 1878 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1879 1880 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET, 1881 0, 0, PACKETJ_TYPE0)); 1882 amdgpu_ring_write(ring, seq); 1883 1884 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET, 1885 0, 0, PACKETJ_TYPE0)); 1886 amdgpu_ring_write(ring, seq); 1887 1888 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET, 1889 0, 0, PACKETJ_TYPE0)); 1890 amdgpu_ring_write(ring, lower_32_bits(addr)); 1891 1892 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET, 1893 0, 0, PACKETJ_TYPE0)); 1894 amdgpu_ring_write(ring, upper_32_bits(addr)); 1895 1896 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET, 1897 0, 0, PACKETJ_TYPE0)); 1898 amdgpu_ring_write(ring, 0x8); 1899 1900 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET, 1901 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4)); 1902 amdgpu_ring_write(ring, 0); 1903 1904 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 1905 0, 0, PACKETJ_TYPE0)); 1906 amdgpu_ring_write(ring, 0x3fbc); 1907 1908 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 1909 0, 0, PACKETJ_TYPE0)); 1910 amdgpu_ring_write(ring, 0x1); 1911 1912 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7)); 1913 amdgpu_ring_write(ring, 0); 1914 } 1915 1916 /** 1917 * vcn_v2_0_jpeg_ring_emit_ib - execute indirect buffer 1918 * 1919 * @ring: amdgpu_ring pointer 1920 * @ib: indirect buffer to execute 1921 * 1922 * Write ring commands to execute the indirect buffer. 1923 */ 1924 static void vcn_v2_0_jpeg_ring_emit_ib(struct amdgpu_ring *ring, 1925 struct amdgpu_job *job, 1926 struct amdgpu_ib *ib, 1927 uint32_t flags) 1928 { 1929 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1930 1931 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET, 1932 0, 0, PACKETJ_TYPE0)); 1933 amdgpu_ring_write(ring, (vmid | (vmid << 4))); 1934 1935 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET, 1936 0, 0, PACKETJ_TYPE0)); 1937 amdgpu_ring_write(ring, (vmid | (vmid << 4))); 1938 1939 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET, 1940 0, 0, PACKETJ_TYPE0)); 1941 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1942 1943 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET, 1944 0, 0, PACKETJ_TYPE0)); 1945 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1946 1947 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET, 1948 0, 0, PACKETJ_TYPE0)); 1949 amdgpu_ring_write(ring, ib->length_dw); 1950 1951 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET, 1952 0, 0, PACKETJ_TYPE0)); 1953 amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr)); 1954 1955 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET, 1956 0, 0, PACKETJ_TYPE0)); 1957 amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr)); 1958 1959 amdgpu_ring_write(ring, PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2)); 1960 amdgpu_ring_write(ring, 0); 1961 1962 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET, 1963 0, 0, PACKETJ_TYPE0)); 1964 amdgpu_ring_write(ring, 0x01400200); 1965 1966 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET, 1967 0, 0, PACKETJ_TYPE0)); 1968 amdgpu_ring_write(ring, 0x2); 1969 1970 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_STATUS_INTERNAL_OFFSET, 1971 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3)); 1972 amdgpu_ring_write(ring, 0x2); 1973 } 1974 1975 static void vcn_v2_0_jpeg_ring_emit_reg_wait(struct amdgpu_ring *ring, 1976 uint32_t reg, uint32_t val, 1977 uint32_t mask) 1978 { 1979 uint32_t reg_offset = (reg << 2); 1980 1981 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET, 1982 0, 0, PACKETJ_TYPE0)); 1983 amdgpu_ring_write(ring, 0x01400200); 1984 1985 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET, 1986 0, 0, PACKETJ_TYPE0)); 1987 amdgpu_ring_write(ring, val); 1988 1989 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 1990 0, 0, PACKETJ_TYPE0)); 1991 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { 1992 amdgpu_ring_write(ring, 0); 1993 amdgpu_ring_write(ring, 1994 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3)); 1995 } else { 1996 amdgpu_ring_write(ring, reg_offset); 1997 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 1998 0, 0, PACKETJ_TYPE3)); 1999 } 2000 amdgpu_ring_write(ring, mask); 2001 } 2002 2003 static void vcn_v2_0_jpeg_ring_emit_vm_flush(struct amdgpu_ring *ring, 2004 unsigned vmid, uint64_t pd_addr) 2005 { 2006 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 2007 uint32_t data0, data1, mask; 2008 2009 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 2010 2011 /* wait for register write */ 2012 data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2; 2013 data1 = lower_32_bits(pd_addr); 2014 mask = 0xffffffff; 2015 vcn_v2_0_jpeg_ring_emit_reg_wait(ring, data0, data1, mask); 2016 } 2017 2018 static void vcn_v2_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring, 2019 uint32_t reg, uint32_t val) 2020 { 2021 uint32_t reg_offset = (reg << 2); 2022 2023 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 2024 0, 0, PACKETJ_TYPE0)); 2025 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { 2026 amdgpu_ring_write(ring, 0); 2027 amdgpu_ring_write(ring, 2028 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0)); 2029 } else { 2030 amdgpu_ring_write(ring, reg_offset); 2031 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 2032 0, 0, PACKETJ_TYPE0)); 2033 } 2034 amdgpu_ring_write(ring, val); 2035 } 2036 2037 static void vcn_v2_0_jpeg_ring_nop(struct amdgpu_ring *ring, uint32_t count) 2038 { 2039 int i; 2040 2041 WARN_ON(ring->wptr % 2 || count % 2); 2042 2043 for (i = 0; i < count / 2; i++) { 2044 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); 2045 amdgpu_ring_write(ring, 0); 2046 } 2047 } 2048 2049 static int vcn_v2_0_set_interrupt_state(struct amdgpu_device *adev, 2050 struct amdgpu_irq_src *source, 2051 unsigned type, 2052 enum amdgpu_interrupt_state state) 2053 { 2054 return 0; 2055 } 2056 2057 static int vcn_v2_0_process_interrupt(struct amdgpu_device *adev, 2058 struct amdgpu_irq_src *source, 2059 struct amdgpu_iv_entry *entry) 2060 { 2061 DRM_DEBUG("IH: VCN TRAP\n"); 2062 2063 switch (entry->src_id) { 2064 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT: 2065 amdgpu_fence_process(&adev->vcn.ring_dec); 2066 break; 2067 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 2068 amdgpu_fence_process(&adev->vcn.ring_enc[0]); 2069 break; 2070 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY: 2071 amdgpu_fence_process(&adev->vcn.ring_enc[1]); 2072 break; 2073 case VCN_2_0__SRCID__JPEG_DECODE: 2074 amdgpu_fence_process(&adev->vcn.ring_jpeg); 2075 break; 2076 default: 2077 DRM_ERROR("Unhandled interrupt: %d %d\n", 2078 entry->src_id, entry->src_data[0]); 2079 break; 2080 } 2081 2082 return 0; 2083 } 2084 2085 static int vcn_v2_0_set_powergating_state(void *handle, 2086 enum amd_powergating_state state) 2087 { 2088 /* This doesn't actually powergate the VCN block. 2089 * That's done in the dpm code via the SMC. This 2090 * just re-inits the block as necessary. The actual 2091 * gating still happens in the dpm code. We should 2092 * revisit this when there is a cleaner line between 2093 * the smc and the hw blocks 2094 */ 2095 int ret; 2096 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2097 2098 if (state == adev->vcn.cur_state) 2099 return 0; 2100 2101 if (state == AMD_PG_STATE_GATE) 2102 ret = vcn_v2_0_stop(adev); 2103 else 2104 ret = vcn_v2_0_start(adev); 2105 2106 if (!ret) 2107 adev->vcn.cur_state = state; 2108 return ret; 2109 } 2110 2111 static const struct amd_ip_funcs vcn_v2_0_ip_funcs = { 2112 .name = "vcn_v2_0", 2113 .early_init = vcn_v2_0_early_init, 2114 .late_init = NULL, 2115 .sw_init = vcn_v2_0_sw_init, 2116 .sw_fini = vcn_v2_0_sw_fini, 2117 .hw_init = vcn_v2_0_hw_init, 2118 .hw_fini = vcn_v2_0_hw_fini, 2119 .suspend = vcn_v2_0_suspend, 2120 .resume = vcn_v2_0_resume, 2121 .is_idle = vcn_v2_0_is_idle, 2122 .wait_for_idle = vcn_v2_0_wait_for_idle, 2123 .check_soft_reset = NULL, 2124 .pre_soft_reset = NULL, 2125 .soft_reset = NULL, 2126 .post_soft_reset = NULL, 2127 .set_clockgating_state = vcn_v2_0_set_clockgating_state, 2128 .set_powergating_state = vcn_v2_0_set_powergating_state, 2129 }; 2130 2131 static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = { 2132 .type = AMDGPU_RING_TYPE_VCN_DEC, 2133 .align_mask = 0xf, 2134 .vmhub = AMDGPU_MMHUB, 2135 .get_rptr = vcn_v2_0_dec_ring_get_rptr, 2136 .get_wptr = vcn_v2_0_dec_ring_get_wptr, 2137 .set_wptr = vcn_v2_0_dec_ring_set_wptr, 2138 .emit_frame_size = 2139 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 2140 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 2141 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */ 2142 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */ 2143 6, 2144 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */ 2145 .emit_ib = vcn_v2_0_dec_ring_emit_ib, 2146 .emit_fence = vcn_v2_0_dec_ring_emit_fence, 2147 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush, 2148 .test_ring = amdgpu_vcn_dec_ring_test_ring, 2149 .test_ib = amdgpu_vcn_dec_ring_test_ib, 2150 .insert_nop = vcn_v2_0_dec_ring_insert_nop, 2151 .insert_start = vcn_v2_0_dec_ring_insert_start, 2152 .insert_end = vcn_v2_0_dec_ring_insert_end, 2153 .pad_ib = amdgpu_ring_generic_pad_ib, 2154 .begin_use = amdgpu_vcn_ring_begin_use, 2155 .end_use = amdgpu_vcn_ring_end_use, 2156 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg, 2157 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait, 2158 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2159 }; 2160 2161 static const struct amdgpu_ring_funcs vcn_v2_0_enc_ring_vm_funcs = { 2162 .type = AMDGPU_RING_TYPE_VCN_ENC, 2163 .align_mask = 0x3f, 2164 .nop = VCN_ENC_CMD_NO_OP, 2165 .vmhub = AMDGPU_MMHUB, 2166 .get_rptr = vcn_v2_0_enc_ring_get_rptr, 2167 .get_wptr = vcn_v2_0_enc_ring_get_wptr, 2168 .set_wptr = vcn_v2_0_enc_ring_set_wptr, 2169 .emit_frame_size = 2170 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2171 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 2172 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 2173 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 2174 1, /* vcn_v2_0_enc_ring_insert_end */ 2175 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 2176 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 2177 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 2178 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 2179 .test_ring = amdgpu_vcn_enc_ring_test_ring, 2180 .test_ib = amdgpu_vcn_enc_ring_test_ib, 2181 .insert_nop = amdgpu_ring_insert_nop, 2182 .insert_end = vcn_v2_0_enc_ring_insert_end, 2183 .pad_ib = amdgpu_ring_generic_pad_ib, 2184 .begin_use = amdgpu_vcn_ring_begin_use, 2185 .end_use = amdgpu_vcn_ring_end_use, 2186 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 2187 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 2188 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2189 }; 2190 2191 static const struct amdgpu_ring_funcs vcn_v2_0_jpeg_ring_vm_funcs = { 2192 .type = AMDGPU_RING_TYPE_VCN_JPEG, 2193 .align_mask = 0xf, 2194 .vmhub = AMDGPU_MMHUB, 2195 .get_rptr = vcn_v2_0_jpeg_ring_get_rptr, 2196 .get_wptr = vcn_v2_0_jpeg_ring_get_wptr, 2197 .set_wptr = vcn_v2_0_jpeg_ring_set_wptr, 2198 .emit_frame_size = 2199 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 2200 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 2201 8 + /* vcn_v2_0_jpeg_ring_emit_vm_flush */ 2202 18 + 18 + /* vcn_v2_0_jpeg_ring_emit_fence x2 vm fence */ 2203 8 + 16, 2204 .emit_ib_size = 22, /* vcn_v2_0_jpeg_ring_emit_ib */ 2205 .emit_ib = vcn_v2_0_jpeg_ring_emit_ib, 2206 .emit_fence = vcn_v2_0_jpeg_ring_emit_fence, 2207 .emit_vm_flush = vcn_v2_0_jpeg_ring_emit_vm_flush, 2208 .test_ring = amdgpu_vcn_jpeg_ring_test_ring, 2209 .test_ib = amdgpu_vcn_jpeg_ring_test_ib, 2210 .insert_nop = vcn_v2_0_jpeg_ring_nop, 2211 .insert_start = vcn_v2_0_jpeg_ring_insert_start, 2212 .insert_end = vcn_v2_0_jpeg_ring_insert_end, 2213 .pad_ib = amdgpu_ring_generic_pad_ib, 2214 .begin_use = amdgpu_vcn_ring_begin_use, 2215 .end_use = amdgpu_vcn_ring_end_use, 2216 .emit_wreg = vcn_v2_0_jpeg_ring_emit_wreg, 2217 .emit_reg_wait = vcn_v2_0_jpeg_ring_emit_reg_wait, 2218 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2219 }; 2220 2221 static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev) 2222 { 2223 adev->vcn.ring_dec.funcs = &vcn_v2_0_dec_ring_vm_funcs; 2224 DRM_INFO("VCN decode is enabled in VM mode\n"); 2225 } 2226 2227 static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev) 2228 { 2229 int i; 2230 2231 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 2232 adev->vcn.ring_enc[i].funcs = &vcn_v2_0_enc_ring_vm_funcs; 2233 2234 DRM_INFO("VCN encode is enabled in VM mode\n"); 2235 } 2236 2237 static void vcn_v2_0_set_jpeg_ring_funcs(struct amdgpu_device *adev) 2238 { 2239 adev->vcn.ring_jpeg.funcs = &vcn_v2_0_jpeg_ring_vm_funcs; 2240 DRM_INFO("VCN jpeg decode is enabled in VM mode\n"); 2241 } 2242 2243 static const struct amdgpu_irq_src_funcs vcn_v2_0_irq_funcs = { 2244 .set = vcn_v2_0_set_interrupt_state, 2245 .process = vcn_v2_0_process_interrupt, 2246 }; 2247 2248 static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev) 2249 { 2250 adev->vcn.irq.num_types = adev->vcn.num_enc_rings + 2; 2251 adev->vcn.irq.funcs = &vcn_v2_0_irq_funcs; 2252 } 2253 2254 const struct amdgpu_ip_block_version vcn_v2_0_ip_block = 2255 { 2256 .type = AMD_IP_BLOCK_TYPE_VCN, 2257 .major = 2, 2258 .minor = 0, 2259 .rev = 0, 2260 .funcs = &vcn_v2_0_ip_funcs, 2261 }; 2262