1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_vcn.h" 28 #include "soc15.h" 29 #include "soc15d.h" 30 #include "amdgpu_pm.h" 31 #include "amdgpu_psp.h" 32 33 #include "vcn/vcn_2_0_0_offset.h" 34 #include "vcn/vcn_2_0_0_sh_mask.h" 35 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 36 37 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x1fd 38 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x503 39 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x504 40 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x505 41 #define mmUVD_NO_OP_INTERNAL_OFFSET 0x53f 42 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x54a 43 #define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d 44 45 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x1e1 46 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x5a6 47 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x5a7 48 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x1e2 49 50 #define mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET 0x1bfff 51 #define mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET 0x4029 52 #define mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET 0x402a 53 #define mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET 0x402b 54 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40ea 55 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40eb 56 #define mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET 0x40cf 57 #define mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET 0x40d1 58 #define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40e8 59 #define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40e9 60 #define mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET 0x4082 61 #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40ec 62 #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40ed 63 #define mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET 0x4085 64 #define mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET 0x4084 65 #define mmUVD_JRBC_STATUS_INTERNAL_OFFSET 0x4089 66 #define mmUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f 67 68 #define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR 0x18000 69 70 #define mmUVD_RBC_XX_IB_REG_CHECK 0x026b 71 #define mmUVD_RBC_XX_IB_REG_CHECK_BASE_IDX 1 72 #define mmUVD_REG_XX_MASK 0x026c 73 #define mmUVD_REG_XX_MASK_BASE_IDX 1 74 75 static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev); 76 static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev); 77 static void vcn_v2_0_set_jpeg_ring_funcs(struct amdgpu_device *adev); 78 static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev); 79 static int vcn_v2_0_set_powergating_state(void *handle, 80 enum amd_powergating_state state); 81 static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev, 82 struct dpg_pause_state *new_state); 83 84 /** 85 * vcn_v2_0_early_init - set function pointers 86 * 87 * @handle: amdgpu_device pointer 88 * 89 * Set ring and irq function pointers 90 */ 91 static int vcn_v2_0_early_init(void *handle) 92 { 93 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 94 95 adev->vcn.num_vcn_inst = 1; 96 adev->vcn.num_enc_rings = 2; 97 98 vcn_v2_0_set_dec_ring_funcs(adev); 99 vcn_v2_0_set_enc_ring_funcs(adev); 100 vcn_v2_0_set_jpeg_ring_funcs(adev); 101 vcn_v2_0_set_irq_funcs(adev); 102 103 return 0; 104 } 105 106 /** 107 * vcn_v2_0_sw_init - sw init for VCN block 108 * 109 * @handle: amdgpu_device pointer 110 * 111 * Load firmware and sw initialization 112 */ 113 static int vcn_v2_0_sw_init(void *handle) 114 { 115 struct amdgpu_ring *ring; 116 int i, r; 117 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 118 119 /* VCN DEC TRAP */ 120 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 121 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, 122 &adev->vcn.inst->irq); 123 if (r) 124 return r; 125 126 /* VCN ENC TRAP */ 127 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 128 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 129 i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, 130 &adev->vcn.inst->irq); 131 if (r) 132 return r; 133 } 134 135 /* VCN JPEG TRAP */ 136 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 137 VCN_2_0__SRCID__JPEG_DECODE, &adev->vcn.inst->irq); 138 if (r) 139 return r; 140 141 r = amdgpu_vcn_sw_init(adev); 142 if (r) 143 return r; 144 145 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 146 adev->asic_type != CHIP_RENOIR) { 147 const struct common_firmware_header *hdr; 148 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 149 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN; 150 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw; 151 adev->firmware.fw_size += 152 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 153 DRM_INFO("PSP loading VCN firmware\n"); 154 } 155 156 r = amdgpu_vcn_resume(adev); 157 if (r) 158 return r; 159 160 ring = &adev->vcn.inst->ring_dec; 161 162 ring->use_doorbell = true; 163 ring->doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1 << 1; 164 165 sprintf(ring->name, "vcn_dec"); 166 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0); 167 if (r) 168 return r; 169 170 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; 171 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; 172 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; 173 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; 174 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; 175 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; 176 177 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; 178 adev->vcn.inst->external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9); 179 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; 180 adev->vcn.inst->external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0); 181 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; 182 adev->vcn.inst->external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1); 183 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; 184 adev->vcn.inst->external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD); 185 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; 186 adev->vcn.inst->external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP); 187 188 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 189 ring = &adev->vcn.inst->ring_enc[i]; 190 ring->use_doorbell = true; 191 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i; 192 sprintf(ring->name, "vcn_enc%d", i); 193 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0); 194 if (r) 195 return r; 196 } 197 198 ring = &adev->vcn.inst->ring_jpeg; 199 ring->use_doorbell = true; 200 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1; 201 sprintf(ring->name, "vcn_jpeg"); 202 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0); 203 if (r) 204 return r; 205 206 adev->vcn.pause_dpg_mode = vcn_v2_0_pause_dpg_mode; 207 208 adev->vcn.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET; 209 adev->vcn.inst->external.jpeg_pitch = SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH); 210 211 return 0; 212 } 213 214 /** 215 * vcn_v2_0_sw_fini - sw fini for VCN block 216 * 217 * @handle: amdgpu_device pointer 218 * 219 * VCN suspend and free up sw allocation 220 */ 221 static int vcn_v2_0_sw_fini(void *handle) 222 { 223 int r; 224 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 225 226 r = amdgpu_vcn_suspend(adev); 227 if (r) 228 return r; 229 230 r = amdgpu_vcn_sw_fini(adev); 231 232 return r; 233 } 234 235 /** 236 * vcn_v2_0_hw_init - start and test VCN block 237 * 238 * @handle: amdgpu_device pointer 239 * 240 * Initialize the hardware, boot up the VCPU and do some testing 241 */ 242 static int vcn_v2_0_hw_init(void *handle) 243 { 244 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 245 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 246 int i, r; 247 248 adev->nbio_funcs->vcn_doorbell_range(adev, ring->use_doorbell, 249 ring->doorbell_index, 0); 250 251 ring->sched.ready = true; 252 r = amdgpu_ring_test_ring(ring); 253 if (r) { 254 ring->sched.ready = false; 255 goto done; 256 } 257 258 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 259 ring = &adev->vcn.inst->ring_enc[i]; 260 ring->sched.ready = true; 261 r = amdgpu_ring_test_ring(ring); 262 if (r) { 263 ring->sched.ready = false; 264 goto done; 265 } 266 } 267 268 ring = &adev->vcn.inst->ring_jpeg; 269 ring->sched.ready = true; 270 r = amdgpu_ring_test_ring(ring); 271 if (r) { 272 ring->sched.ready = false; 273 goto done; 274 } 275 276 done: 277 if (!r) 278 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 279 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 280 281 return r; 282 } 283 284 /** 285 * vcn_v2_0_hw_fini - stop the hardware block 286 * 287 * @handle: amdgpu_device pointer 288 * 289 * Stop the VCN block, mark ring as not ready any more 290 */ 291 static int vcn_v2_0_hw_fini(void *handle) 292 { 293 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 294 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 295 int i; 296 297 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 298 (adev->vcn.cur_state != AMD_PG_STATE_GATE && 299 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) 300 vcn_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 301 302 ring->sched.ready = false; 303 304 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 305 ring = &adev->vcn.inst->ring_enc[i]; 306 ring->sched.ready = false; 307 } 308 309 ring = &adev->vcn.inst->ring_jpeg; 310 ring->sched.ready = false; 311 312 return 0; 313 } 314 315 /** 316 * vcn_v2_0_suspend - suspend VCN block 317 * 318 * @handle: amdgpu_device pointer 319 * 320 * HW fini and suspend VCN block 321 */ 322 static int vcn_v2_0_suspend(void *handle) 323 { 324 int r; 325 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 326 327 r = vcn_v2_0_hw_fini(adev); 328 if (r) 329 return r; 330 331 r = amdgpu_vcn_suspend(adev); 332 333 return r; 334 } 335 336 /** 337 * vcn_v2_0_resume - resume VCN block 338 * 339 * @handle: amdgpu_device pointer 340 * 341 * Resume firmware and hw init VCN block 342 */ 343 static int vcn_v2_0_resume(void *handle) 344 { 345 int r; 346 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 347 348 r = amdgpu_vcn_resume(adev); 349 if (r) 350 return r; 351 352 r = vcn_v2_0_hw_init(adev); 353 354 return r; 355 } 356 357 /** 358 * vcn_v2_0_mc_resume - memory controller programming 359 * 360 * @adev: amdgpu_device pointer 361 * 362 * Let the VCN memory controller know it's offsets 363 */ 364 static void vcn_v2_0_mc_resume(struct amdgpu_device *adev) 365 { 366 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 367 uint32_t offset; 368 369 /* cache window 0: fw */ 370 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 371 adev->asic_type != CHIP_RENOIR) { 372 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 373 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo)); 374 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 375 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi)); 376 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); 377 offset = 0; 378 } else { 379 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 380 lower_32_bits(adev->vcn.inst->gpu_addr)); 381 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 382 upper_32_bits(adev->vcn.inst->gpu_addr)); 383 offset = size; 384 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 385 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 386 } 387 388 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); 389 390 /* cache window 1: stack */ 391 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 392 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); 393 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 394 upper_32_bits(adev->vcn.inst->gpu_addr + offset)); 395 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0); 396 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 397 398 /* cache window 2: context */ 399 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 400 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 401 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 402 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 403 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0); 404 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 405 406 WREG32_SOC15(UVD, 0, mmUVD_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 407 WREG32_SOC15(UVD, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 408 } 409 410 static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirect) 411 { 412 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 413 uint32_t offset; 414 415 /* cache window 0: fw */ 416 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 417 adev->asic_type != CHIP_RENOIR) { 418 if (!indirect) { 419 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 420 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 421 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0, indirect); 422 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 423 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 424 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0, indirect); 425 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 426 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 427 } else { 428 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 429 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 430 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 431 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 432 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 433 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 434 } 435 offset = 0; 436 } else { 437 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 438 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 439 lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); 440 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 441 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 442 upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); 443 offset = size; 444 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 445 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 446 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 447 } 448 449 if (!indirect) 450 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 451 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 452 else 453 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 454 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 455 456 /* cache window 1: stack */ 457 if (!indirect) { 458 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 459 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 460 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect); 461 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 462 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 463 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect); 464 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 465 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 466 } else { 467 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 468 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 469 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 470 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 471 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 472 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 473 } 474 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 475 UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 476 477 /* cache window 2: context */ 478 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 479 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 480 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 481 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 482 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 483 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 484 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 485 UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 486 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 487 UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 488 489 /* non-cache window */ 490 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 491 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect); 492 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 493 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect); 494 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 495 UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 496 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 497 UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect); 498 499 /* VCN global tiling registers */ 500 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 501 UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 502 } 503 504 /** 505 * vcn_v2_0_disable_clock_gating - disable VCN clock gating 506 * 507 * @adev: amdgpu_device pointer 508 * @sw: enable SW clock gating 509 * 510 * Disable clock gating for VCN block 511 */ 512 static void vcn_v2_0_disable_clock_gating(struct amdgpu_device *adev) 513 { 514 uint32_t data; 515 516 /* UVD disable CGC */ 517 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 518 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 519 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 520 else 521 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 522 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 523 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 524 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 525 526 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); 527 data &= ~(UVD_CGC_GATE__SYS_MASK 528 | UVD_CGC_GATE__UDEC_MASK 529 | UVD_CGC_GATE__MPEG2_MASK 530 | UVD_CGC_GATE__REGS_MASK 531 | UVD_CGC_GATE__RBC_MASK 532 | UVD_CGC_GATE__LMI_MC_MASK 533 | UVD_CGC_GATE__LMI_UMC_MASK 534 | UVD_CGC_GATE__IDCT_MASK 535 | UVD_CGC_GATE__MPRD_MASK 536 | UVD_CGC_GATE__MPC_MASK 537 | UVD_CGC_GATE__LBSI_MASK 538 | UVD_CGC_GATE__LRBBM_MASK 539 | UVD_CGC_GATE__UDEC_RE_MASK 540 | UVD_CGC_GATE__UDEC_CM_MASK 541 | UVD_CGC_GATE__UDEC_IT_MASK 542 | UVD_CGC_GATE__UDEC_DB_MASK 543 | UVD_CGC_GATE__UDEC_MP_MASK 544 | UVD_CGC_GATE__WCB_MASK 545 | UVD_CGC_GATE__VCPU_MASK 546 | UVD_CGC_GATE__SCPU_MASK); 547 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data); 548 549 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 550 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 551 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 552 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 553 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 554 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 555 | UVD_CGC_CTRL__SYS_MODE_MASK 556 | UVD_CGC_CTRL__UDEC_MODE_MASK 557 | UVD_CGC_CTRL__MPEG2_MODE_MASK 558 | UVD_CGC_CTRL__REGS_MODE_MASK 559 | UVD_CGC_CTRL__RBC_MODE_MASK 560 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 561 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 562 | UVD_CGC_CTRL__IDCT_MODE_MASK 563 | UVD_CGC_CTRL__MPRD_MODE_MASK 564 | UVD_CGC_CTRL__MPC_MODE_MASK 565 | UVD_CGC_CTRL__LBSI_MODE_MASK 566 | UVD_CGC_CTRL__LRBBM_MODE_MASK 567 | UVD_CGC_CTRL__WCB_MODE_MASK 568 | UVD_CGC_CTRL__VCPU_MODE_MASK 569 | UVD_CGC_CTRL__SCPU_MODE_MASK); 570 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 571 572 /* turn on */ 573 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); 574 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 575 | UVD_SUVD_CGC_GATE__SIT_MASK 576 | UVD_SUVD_CGC_GATE__SMP_MASK 577 | UVD_SUVD_CGC_GATE__SCM_MASK 578 | UVD_SUVD_CGC_GATE__SDB_MASK 579 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 580 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 581 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 582 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 583 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 584 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 585 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 586 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 587 | UVD_SUVD_CGC_GATE__SCLR_MASK 588 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 589 | UVD_SUVD_CGC_GATE__ENT_MASK 590 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 591 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 592 | UVD_SUVD_CGC_GATE__SITE_MASK 593 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 594 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 595 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 596 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 597 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 598 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data); 599 600 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); 601 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 602 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 603 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 604 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 605 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 606 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 607 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 608 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 609 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 610 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 611 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); 612 } 613 614 static void vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_device *adev, 615 uint8_t sram_sel, uint8_t indirect) 616 { 617 uint32_t reg_data = 0; 618 619 /* enable sw clock gating control */ 620 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 621 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 622 else 623 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 624 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 625 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 626 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 627 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 628 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 629 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 630 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 631 UVD_CGC_CTRL__SYS_MODE_MASK | 632 UVD_CGC_CTRL__UDEC_MODE_MASK | 633 UVD_CGC_CTRL__MPEG2_MODE_MASK | 634 UVD_CGC_CTRL__REGS_MODE_MASK | 635 UVD_CGC_CTRL__RBC_MODE_MASK | 636 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 637 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 638 UVD_CGC_CTRL__IDCT_MODE_MASK | 639 UVD_CGC_CTRL__MPRD_MODE_MASK | 640 UVD_CGC_CTRL__MPC_MODE_MASK | 641 UVD_CGC_CTRL__LBSI_MODE_MASK | 642 UVD_CGC_CTRL__LRBBM_MODE_MASK | 643 UVD_CGC_CTRL__WCB_MODE_MASK | 644 UVD_CGC_CTRL__VCPU_MODE_MASK | 645 UVD_CGC_CTRL__SCPU_MODE_MASK); 646 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 647 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); 648 649 /* turn off clock gating */ 650 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 651 UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect); 652 653 /* turn on SUVD clock gating */ 654 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 655 UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 656 657 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 658 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 659 UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 660 } 661 662 /** 663 * jpeg_v2_0_start - start JPEG block 664 * 665 * @adev: amdgpu_device pointer 666 * 667 * Setup and start the JPEG block 668 */ 669 static int jpeg_v2_0_start(struct amdgpu_device *adev) 670 { 671 struct amdgpu_ring *ring = &adev->vcn.inst->ring_jpeg; 672 uint32_t tmp; 673 int r = 0; 674 675 /* disable power gating */ 676 tmp = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT; 677 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_PGFSM_CONFIG), tmp); 678 679 SOC15_WAIT_ON_RREG(VCN, 0, 680 mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON, 681 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r); 682 683 if (r) { 684 DRM_ERROR("amdgpu: JPEG disable power gating failed\n"); 685 return r; 686 } 687 688 /* Removing the anti hang mechanism to indicate the UVDJ tile is ON */ 689 tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS)) & ~0x1; 690 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS), tmp); 691 692 /* JPEG disable CGC */ 693 tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); 694 tmp |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 695 tmp |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 696 tmp |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 697 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, tmp); 698 699 tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); 700 tmp &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK 701 | JPEG_CGC_GATE__JPEG2_DEC_MASK 702 | JPEG_CGC_GATE__JPEG_ENC_MASK 703 | JPEG_CGC_GATE__JMCIF_MASK 704 | JPEG_CGC_GATE__JRBBM_MASK); 705 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, tmp); 706 707 /* enable JMI channel */ 708 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_JMI_CNTL), 0, 709 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 710 711 /* enable System Interrupt for JRBC */ 712 WREG32_P(SOC15_REG_OFFSET(VCN, 0, mmJPEG_SYS_INT_EN), 713 JPEG_SYS_INT_EN__DJRBC_MASK, 714 ~JPEG_SYS_INT_EN__DJRBC_MASK); 715 716 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0); 717 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); 718 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 719 lower_32_bits(ring->gpu_addr)); 720 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 721 upper_32_bits(ring->gpu_addr)); 722 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, 0); 723 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, 0); 724 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L); 725 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4); 726 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); 727 728 return 0; 729 } 730 731 /** 732 * jpeg_v2_0_stop - stop JPEG block 733 * 734 * @adev: amdgpu_device pointer 735 * 736 * stop the JPEG block 737 */ 738 static int jpeg_v2_0_stop(struct amdgpu_device *adev) 739 { 740 uint32_t tmp; 741 int r = 0; 742 743 /* reset JMI */ 744 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_JMI_CNTL), 745 UVD_JMI_CNTL__SOFT_RESET_MASK, 746 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 747 748 /* enable JPEG CGC */ 749 tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); 750 tmp |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 751 tmp |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 752 tmp |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 753 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, tmp); 754 755 756 tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); 757 tmp |= (JPEG_CGC_GATE__JPEG_DEC_MASK 758 |JPEG_CGC_GATE__JPEG2_DEC_MASK 759 |JPEG_CGC_GATE__JPEG_ENC_MASK 760 |JPEG_CGC_GATE__JMCIF_MASK 761 |JPEG_CGC_GATE__JRBBM_MASK); 762 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, tmp); 763 764 /* enable power gating */ 765 tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS)); 766 tmp &= ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK; 767 tmp |= 0x1; //UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_TILES_OFF; 768 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS), tmp); 769 770 tmp = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT; 771 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_PGFSM_CONFIG), tmp); 772 773 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 774 (2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT), 775 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r); 776 777 if (r) { 778 DRM_ERROR("amdgpu: JPEG enable power gating failed\n"); 779 return r; 780 } 781 782 return r; 783 } 784 785 /** 786 * vcn_v2_0_enable_clock_gating - enable VCN clock gating 787 * 788 * @adev: amdgpu_device pointer 789 * @sw: enable SW clock gating 790 * 791 * Enable clock gating for VCN block 792 */ 793 static void vcn_v2_0_enable_clock_gating(struct amdgpu_device *adev) 794 { 795 uint32_t data = 0; 796 797 /* enable UVD CGC */ 798 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 799 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 800 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 801 else 802 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 803 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 804 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 805 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 806 807 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 808 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 809 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 810 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 811 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 812 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 813 | UVD_CGC_CTRL__SYS_MODE_MASK 814 | UVD_CGC_CTRL__UDEC_MODE_MASK 815 | UVD_CGC_CTRL__MPEG2_MODE_MASK 816 | UVD_CGC_CTRL__REGS_MODE_MASK 817 | UVD_CGC_CTRL__RBC_MODE_MASK 818 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 819 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 820 | UVD_CGC_CTRL__IDCT_MODE_MASK 821 | UVD_CGC_CTRL__MPRD_MODE_MASK 822 | UVD_CGC_CTRL__MPC_MODE_MASK 823 | UVD_CGC_CTRL__LBSI_MODE_MASK 824 | UVD_CGC_CTRL__LRBBM_MODE_MASK 825 | UVD_CGC_CTRL__WCB_MODE_MASK 826 | UVD_CGC_CTRL__VCPU_MODE_MASK 827 | UVD_CGC_CTRL__SCPU_MODE_MASK); 828 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 829 830 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); 831 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 832 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 833 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 834 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 835 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 836 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 837 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 838 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 839 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 840 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 841 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); 842 } 843 844 static void vcn_v2_0_disable_static_power_gating(struct amdgpu_device *adev) 845 { 846 uint32_t data = 0; 847 int ret; 848 849 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 850 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 851 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 852 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 853 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 854 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 855 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 856 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 857 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 858 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 859 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT); 860 861 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 862 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 863 UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0, 0xFFFFF, ret); 864 } else { 865 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 866 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 867 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 868 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 869 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 870 | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 871 | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 872 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 873 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 874 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT); 875 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 876 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFF, ret); 877 } 878 879 /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS, 880 * UVDU_PWR_STATUS are 0 (power on) */ 881 882 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); 883 data &= ~0x103; 884 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 885 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 886 UVD_POWER_STATUS__UVD_PG_EN_MASK; 887 888 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); 889 } 890 891 static void vcn_v2_0_enable_static_power_gating(struct amdgpu_device *adev) 892 { 893 uint32_t data = 0; 894 int ret; 895 896 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 897 /* Before power off, this indicator has to be turned on */ 898 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); 899 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 900 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 901 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); 902 903 904 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 905 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 906 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 907 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 908 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 909 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 910 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 911 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 912 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 913 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT); 914 915 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 916 917 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 918 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 919 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 920 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 921 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 922 | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT 923 | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT 924 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 925 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 926 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT); 927 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFF, ret); 928 } 929 } 930 931 static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect) 932 { 933 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 934 uint32_t rb_bufsz, tmp; 935 936 vcn_v2_0_enable_static_power_gating(adev); 937 938 /* enable dynamic power gating mode */ 939 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); 940 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 941 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 942 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp); 943 944 if (indirect) 945 adev->vcn.dpg_sram_curr_addr = (uint32_t*)adev->vcn.dpg_sram_cpu_addr; 946 947 /* enable clock gating */ 948 vcn_v2_0_clock_gating_dpg_mode(adev, 0, indirect); 949 950 /* enable VCPU clock */ 951 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 952 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 953 tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK; 954 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 955 UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); 956 957 /* disable master interupt */ 958 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 959 UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect); 960 961 /* setup mmUVD_LMI_CTRL */ 962 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 963 UVD_LMI_CTRL__REQ_MODE_MASK | 964 UVD_LMI_CTRL__CRC_RESET_MASK | 965 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 966 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 967 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 968 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 969 0x00100000L); 970 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 971 UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect); 972 973 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 974 UVD, 0, mmUVD_MPC_CNTL), 975 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 976 977 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 978 UVD, 0, mmUVD_MPC_SET_MUXA0), 979 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 980 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 981 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 982 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 983 984 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 985 UVD, 0, mmUVD_MPC_SET_MUXB0), 986 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 987 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 988 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 989 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 990 991 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 992 UVD, 0, mmUVD_MPC_SET_MUX), 993 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 994 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 995 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 996 997 vcn_v2_0_mc_resume_dpg_mode(adev, indirect); 998 999 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 1000 UVD, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect); 1001 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 1002 UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect); 1003 1004 /* release VCPU reset to boot */ 1005 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 1006 UVD, 0, mmUVD_SOFT_RESET), 0, 0, indirect); 1007 1008 /* enable LMI MC and UMC channels */ 1009 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 1010 UVD, 0, mmUVD_LMI_CTRL2), 1011 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 0, indirect); 1012 1013 /* enable master interrupt */ 1014 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( 1015 UVD, 0, mmUVD_MASTINT_EN), 1016 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 1017 1018 if (indirect) 1019 psp_update_vcn_sram(adev, 0, adev->vcn.dpg_sram_gpu_addr, 1020 (uint32_t)((uintptr_t)adev->vcn.dpg_sram_curr_addr - 1021 (uintptr_t)adev->vcn.dpg_sram_cpu_addr)); 1022 1023 /* force RBC into idle state */ 1024 rb_bufsz = order_base_2(ring->ring_size); 1025 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1026 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1027 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1028 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1029 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1030 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 1031 1032 /* set the write pointer delay */ 1033 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); 1034 1035 /* set the wb address */ 1036 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, 1037 (upper_32_bits(ring->gpu_addr) >> 2)); 1038 1039 /* programm the RB_BASE for ring buffer */ 1040 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1041 lower_32_bits(ring->gpu_addr)); 1042 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1043 upper_32_bits(ring->gpu_addr)); 1044 1045 /* Initialize the ring buffer's read and write pointers */ 1046 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); 1047 1048 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); 1049 1050 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 1051 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1052 lower_32_bits(ring->wptr)); 1053 1054 return 0; 1055 } 1056 1057 static int vcn_v2_0_start(struct amdgpu_device *adev) 1058 { 1059 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 1060 uint32_t rb_bufsz, tmp; 1061 uint32_t lmi_swap_cntl; 1062 int i, j, r; 1063 1064 if (adev->pm.dpm_enabled) 1065 amdgpu_dpm_enable_uvd(adev, true); 1066 1067 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1068 r = vcn_v2_0_start_dpg_mode(adev, adev->vcn.indirect_sram); 1069 if (r) 1070 return r; 1071 goto jpeg; 1072 } 1073 1074 vcn_v2_0_disable_static_power_gating(adev); 1075 1076 /* set uvd status busy */ 1077 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 1078 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); 1079 1080 /*SW clock gating */ 1081 vcn_v2_0_disable_clock_gating(adev); 1082 1083 /* enable VCPU clock */ 1084 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 1085 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 1086 1087 /* disable master interrupt */ 1088 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, 1089 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1090 1091 /* setup mmUVD_LMI_CTRL */ 1092 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL); 1093 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp | 1094 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1095 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1096 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1097 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1098 1099 /* setup mmUVD_MPC_CNTL */ 1100 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL); 1101 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1102 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1103 WREG32_SOC15(VCN, 0, mmUVD_MPC_CNTL, tmp); 1104 1105 /* setup UVD_MPC_SET_MUXA0 */ 1106 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, 1107 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1108 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1109 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1110 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1111 1112 /* setup UVD_MPC_SET_MUXB0 */ 1113 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, 1114 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1115 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1116 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1117 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1118 1119 /* setup mmUVD_MPC_SET_MUX */ 1120 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, 1121 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1122 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1123 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1124 1125 vcn_v2_0_mc_resume(adev); 1126 1127 /* release VCPU reset to boot */ 1128 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 1129 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1130 1131 /* enable LMI MC and UMC channels */ 1132 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, 1133 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1134 1135 tmp = RREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET); 1136 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1137 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1138 WREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET, tmp); 1139 1140 /* disable byte swapping */ 1141 lmi_swap_cntl = 0; 1142 #ifdef __BIG_ENDIAN 1143 /* swap (8 in 32) RB and IB */ 1144 lmi_swap_cntl = 0xa; 1145 #endif 1146 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 1147 1148 for (i = 0; i < 10; ++i) { 1149 uint32_t status; 1150 1151 for (j = 0; j < 100; ++j) { 1152 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); 1153 if (status & 2) 1154 break; 1155 mdelay(10); 1156 } 1157 r = 0; 1158 if (status & 2) 1159 break; 1160 1161 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n"); 1162 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1163 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 1164 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1165 mdelay(10); 1166 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 1167 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1168 mdelay(10); 1169 r = -1; 1170 } 1171 1172 if (r) { 1173 DRM_ERROR("VCN decode not responding, giving up!!!\n"); 1174 return r; 1175 } 1176 1177 /* enable master interrupt */ 1178 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 1179 UVD_MASTINT_EN__VCPU_EN_MASK, 1180 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1181 1182 /* clear the busy bit of VCN_STATUS */ 1183 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0, 1184 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1185 1186 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_VMID, 0); 1187 1188 /* force RBC into idle state */ 1189 rb_bufsz = order_base_2(ring->ring_size); 1190 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1191 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1192 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1193 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1194 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1195 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 1196 1197 /* programm the RB_BASE for ring buffer */ 1198 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1199 lower_32_bits(ring->gpu_addr)); 1200 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1201 upper_32_bits(ring->gpu_addr)); 1202 1203 /* Initialize the ring buffer's read and write pointers */ 1204 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); 1205 1206 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 1207 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1208 lower_32_bits(ring->wptr)); 1209 1210 ring = &adev->vcn.inst->ring_enc[0]; 1211 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1212 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1213 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); 1214 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1215 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 1216 1217 ring = &adev->vcn.inst->ring_enc[1]; 1218 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1219 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1220 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1221 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1222 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); 1223 1224 jpeg: 1225 r = jpeg_v2_0_start(adev); 1226 1227 return r; 1228 } 1229 1230 static int vcn_v2_0_stop_dpg_mode(struct amdgpu_device *adev) 1231 { 1232 int ret_code = 0; 1233 uint32_t tmp; 1234 1235 /* Wait for power status to be 1 */ 1236 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1, 1237 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1238 1239 /* wait for read ptr to be equal to write ptr */ 1240 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); 1241 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF, ret_code); 1242 1243 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); 1244 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF, ret_code); 1245 1246 tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); 1247 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code); 1248 1249 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1250 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code); 1251 1252 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1, 1253 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1254 1255 /* disable dynamic power gating mode */ 1256 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0, 1257 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1258 1259 return 0; 1260 } 1261 1262 static int vcn_v2_0_stop(struct amdgpu_device *adev) 1263 { 1264 uint32_t tmp; 1265 int r; 1266 1267 r = jpeg_v2_0_stop(adev); 1268 if (r) 1269 return r; 1270 1271 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1272 r = vcn_v2_0_stop_dpg_mode(adev); 1273 if (r) 1274 return r; 1275 goto power_off; 1276 } 1277 1278 /* wait for uvd idle */ 1279 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r); 1280 if (r) 1281 return r; 1282 1283 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1284 UVD_LMI_STATUS__READ_CLEAN_MASK | 1285 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1286 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1287 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp, r); 1288 if (r) 1289 return r; 1290 1291 /* stall UMC channel */ 1292 tmp = RREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2); 1293 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1294 WREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2, tmp); 1295 1296 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK| 1297 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1298 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp, r); 1299 if (r) 1300 return r; 1301 1302 /* disable VCPU clock */ 1303 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0, 1304 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1305 1306 /* reset LMI UMC */ 1307 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1308 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK, 1309 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 1310 1311 /* reset LMI */ 1312 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1313 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK, 1314 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); 1315 1316 /* reset VCPU */ 1317 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1318 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 1319 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1320 1321 /* clear status */ 1322 WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0); 1323 1324 vcn_v2_0_enable_clock_gating(adev); 1325 vcn_v2_0_enable_static_power_gating(adev); 1326 1327 power_off: 1328 if (adev->pm.dpm_enabled) 1329 amdgpu_dpm_enable_uvd(adev, false); 1330 1331 return 0; 1332 } 1333 1334 static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev, 1335 struct dpg_pause_state *new_state) 1336 { 1337 struct amdgpu_ring *ring; 1338 uint32_t reg_data = 0; 1339 int ret_code; 1340 1341 /* pause/unpause if state is changed */ 1342 if (adev->vcn.pause_state.fw_based != new_state->fw_based) { 1343 DRM_DEBUG("dpg pause state changed %d -> %d", 1344 adev->vcn.pause_state.fw_based, new_state->fw_based); 1345 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & 1346 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1347 1348 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1349 ret_code = 0; 1350 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 0x1, 1351 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1352 1353 if (!ret_code) { 1354 /* pause DPG */ 1355 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1356 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1357 1358 /* wait for ACK */ 1359 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, 1360 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1361 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code); 1362 1363 /* Restore */ 1364 ring = &adev->vcn.inst->ring_enc[0]; 1365 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); 1366 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1367 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 1368 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1369 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1370 1371 ring = &adev->vcn.inst->ring_enc[1]; 1372 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1373 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1374 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); 1375 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1376 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1377 1378 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1379 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); 1380 1381 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1382 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, 1383 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1384 } 1385 } else { 1386 /* unpause dpg, no need to wait */ 1387 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1388 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1389 } 1390 adev->vcn.pause_state.fw_based = new_state->fw_based; 1391 } 1392 1393 return 0; 1394 } 1395 1396 static bool vcn_v2_0_is_idle(void *handle) 1397 { 1398 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1399 1400 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); 1401 } 1402 1403 static int vcn_v2_0_wait_for_idle(void *handle) 1404 { 1405 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1406 int ret = 0; 1407 1408 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 1409 UVD_STATUS__IDLE, ret); 1410 1411 return ret; 1412 } 1413 1414 static int vcn_v2_0_set_clockgating_state(void *handle, 1415 enum amd_clockgating_state state) 1416 { 1417 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1418 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 1419 1420 if (enable) { 1421 /* wait for STATUS to clear */ 1422 if (vcn_v2_0_is_idle(handle)) 1423 return -EBUSY; 1424 vcn_v2_0_enable_clock_gating(adev); 1425 } else { 1426 /* disable HW gating and enable Sw gating */ 1427 vcn_v2_0_disable_clock_gating(adev); 1428 } 1429 return 0; 1430 } 1431 1432 /** 1433 * vcn_v2_0_dec_ring_get_rptr - get read pointer 1434 * 1435 * @ring: amdgpu_ring pointer 1436 * 1437 * Returns the current hardware read pointer 1438 */ 1439 static uint64_t vcn_v2_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 1440 { 1441 struct amdgpu_device *adev = ring->adev; 1442 1443 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 1444 } 1445 1446 /** 1447 * vcn_v2_0_dec_ring_get_wptr - get write pointer 1448 * 1449 * @ring: amdgpu_ring pointer 1450 * 1451 * Returns the current hardware write pointer 1452 */ 1453 static uint64_t vcn_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 1454 { 1455 struct amdgpu_device *adev = ring->adev; 1456 1457 if (ring->use_doorbell) 1458 return adev->wb.wb[ring->wptr_offs]; 1459 else 1460 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR); 1461 } 1462 1463 /** 1464 * vcn_v2_0_dec_ring_set_wptr - set write pointer 1465 * 1466 * @ring: amdgpu_ring pointer 1467 * 1468 * Commits the write pointer to the hardware 1469 */ 1470 static void vcn_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 1471 { 1472 struct amdgpu_device *adev = ring->adev; 1473 1474 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1475 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 1476 lower_32_bits(ring->wptr) | 0x80000000); 1477 1478 if (ring->use_doorbell) { 1479 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 1480 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1481 } else { 1482 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1483 } 1484 } 1485 1486 /** 1487 * vcn_v2_0_dec_ring_insert_start - insert a start command 1488 * 1489 * @ring: amdgpu_ring pointer 1490 * 1491 * Write a start command to the ring. 1492 */ 1493 void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring) 1494 { 1495 struct amdgpu_device *adev = ring->adev; 1496 1497 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); 1498 amdgpu_ring_write(ring, 0); 1499 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); 1500 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1)); 1501 } 1502 1503 /** 1504 * vcn_v2_0_dec_ring_insert_end - insert a end command 1505 * 1506 * @ring: amdgpu_ring pointer 1507 * 1508 * Write a end command to the ring. 1509 */ 1510 void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring) 1511 { 1512 struct amdgpu_device *adev = ring->adev; 1513 1514 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); 1515 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END << 1)); 1516 } 1517 1518 /** 1519 * vcn_v2_0_dec_ring_insert_nop - insert a nop command 1520 * 1521 * @ring: amdgpu_ring pointer 1522 * 1523 * Write a nop command to the ring. 1524 */ 1525 void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 1526 { 1527 struct amdgpu_device *adev = ring->adev; 1528 int i; 1529 1530 WARN_ON(ring->wptr % 2 || count % 2); 1531 1532 for (i = 0; i < count / 2; i++) { 1533 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.nop, 0)); 1534 amdgpu_ring_write(ring, 0); 1535 } 1536 } 1537 1538 /** 1539 * vcn_v2_0_dec_ring_emit_fence - emit an fence & trap command 1540 * 1541 * @ring: amdgpu_ring pointer 1542 * @fence: fence to emit 1543 * 1544 * Write a fence and a trap command to the ring. 1545 */ 1546 void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 1547 unsigned flags) 1548 { 1549 struct amdgpu_device *adev = ring->adev; 1550 1551 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1552 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.context_id, 0)); 1553 amdgpu_ring_write(ring, seq); 1554 1555 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); 1556 amdgpu_ring_write(ring, addr & 0xffffffff); 1557 1558 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); 1559 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 1560 1561 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); 1562 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_FENCE << 1)); 1563 1564 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); 1565 amdgpu_ring_write(ring, 0); 1566 1567 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); 1568 amdgpu_ring_write(ring, 0); 1569 1570 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); 1571 1572 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_TRAP << 1)); 1573 } 1574 1575 /** 1576 * vcn_v2_0_dec_ring_emit_ib - execute indirect buffer 1577 * 1578 * @ring: amdgpu_ring pointer 1579 * @ib: indirect buffer to execute 1580 * 1581 * Write ring commands to execute the indirect buffer 1582 */ 1583 void vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring, 1584 struct amdgpu_job *job, 1585 struct amdgpu_ib *ib, 1586 uint32_t flags) 1587 { 1588 struct amdgpu_device *adev = ring->adev; 1589 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1590 1591 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_vmid, 0)); 1592 amdgpu_ring_write(ring, vmid); 1593 1594 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_low, 0)); 1595 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1596 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_high, 0)); 1597 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1598 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_size, 0)); 1599 amdgpu_ring_write(ring, ib->length_dw); 1600 } 1601 1602 void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1603 uint32_t val, uint32_t mask) 1604 { 1605 struct amdgpu_device *adev = ring->adev; 1606 1607 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); 1608 amdgpu_ring_write(ring, reg << 2); 1609 1610 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); 1611 amdgpu_ring_write(ring, val); 1612 1613 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.gp_scratch8, 0)); 1614 amdgpu_ring_write(ring, mask); 1615 1616 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); 1617 1618 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_REG_READ_COND_WAIT << 1)); 1619 } 1620 1621 void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, 1622 unsigned vmid, uint64_t pd_addr) 1623 { 1624 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1625 uint32_t data0, data1, mask; 1626 1627 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1628 1629 /* wait for register write */ 1630 data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2; 1631 data1 = lower_32_bits(pd_addr); 1632 mask = 0xffffffff; 1633 vcn_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask); 1634 } 1635 1636 void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, 1637 uint32_t reg, uint32_t val) 1638 { 1639 struct amdgpu_device *adev = ring->adev; 1640 1641 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); 1642 amdgpu_ring_write(ring, reg << 2); 1643 1644 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); 1645 amdgpu_ring_write(ring, val); 1646 1647 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); 1648 1649 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_WRITE_REG << 1)); 1650 } 1651 1652 /** 1653 * vcn_v2_0_enc_ring_get_rptr - get enc read pointer 1654 * 1655 * @ring: amdgpu_ring pointer 1656 * 1657 * Returns the current hardware enc read pointer 1658 */ 1659 static uint64_t vcn_v2_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 1660 { 1661 struct amdgpu_device *adev = ring->adev; 1662 1663 if (ring == &adev->vcn.inst->ring_enc[0]) 1664 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR); 1665 else 1666 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2); 1667 } 1668 1669 /** 1670 * vcn_v2_0_enc_ring_get_wptr - get enc write pointer 1671 * 1672 * @ring: amdgpu_ring pointer 1673 * 1674 * Returns the current hardware enc write pointer 1675 */ 1676 static uint64_t vcn_v2_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 1677 { 1678 struct amdgpu_device *adev = ring->adev; 1679 1680 if (ring == &adev->vcn.inst->ring_enc[0]) { 1681 if (ring->use_doorbell) 1682 return adev->wb.wb[ring->wptr_offs]; 1683 else 1684 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); 1685 } else { 1686 if (ring->use_doorbell) 1687 return adev->wb.wb[ring->wptr_offs]; 1688 else 1689 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); 1690 } 1691 } 1692 1693 /** 1694 * vcn_v2_0_enc_ring_set_wptr - set enc write pointer 1695 * 1696 * @ring: amdgpu_ring pointer 1697 * 1698 * Commits the enc write pointer to the hardware 1699 */ 1700 static void vcn_v2_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 1701 { 1702 struct amdgpu_device *adev = ring->adev; 1703 1704 if (ring == &adev->vcn.inst->ring_enc[0]) { 1705 if (ring->use_doorbell) { 1706 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 1707 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1708 } else { 1709 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1710 } 1711 } else { 1712 if (ring->use_doorbell) { 1713 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 1714 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1715 } else { 1716 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1717 } 1718 } 1719 } 1720 1721 /** 1722 * vcn_v2_0_enc_ring_emit_fence - emit an enc fence & trap command 1723 * 1724 * @ring: amdgpu_ring pointer 1725 * @fence: fence to emit 1726 * 1727 * Write enc a fence and a trap command to the ring. 1728 */ 1729 void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1730 u64 seq, unsigned flags) 1731 { 1732 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1733 1734 amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE); 1735 amdgpu_ring_write(ring, addr); 1736 amdgpu_ring_write(ring, upper_32_bits(addr)); 1737 amdgpu_ring_write(ring, seq); 1738 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP); 1739 } 1740 1741 void vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring *ring) 1742 { 1743 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 1744 } 1745 1746 /** 1747 * vcn_v2_0_enc_ring_emit_ib - enc execute indirect buffer 1748 * 1749 * @ring: amdgpu_ring pointer 1750 * @ib: indirect buffer to execute 1751 * 1752 * Write enc ring commands to execute the indirect buffer 1753 */ 1754 void vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring *ring, 1755 struct amdgpu_job *job, 1756 struct amdgpu_ib *ib, 1757 uint32_t flags) 1758 { 1759 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1760 1761 amdgpu_ring_write(ring, VCN_ENC_CMD_IB); 1762 amdgpu_ring_write(ring, vmid); 1763 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1764 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1765 amdgpu_ring_write(ring, ib->length_dw); 1766 } 1767 1768 void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1769 uint32_t val, uint32_t mask) 1770 { 1771 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); 1772 amdgpu_ring_write(ring, reg << 2); 1773 amdgpu_ring_write(ring, mask); 1774 amdgpu_ring_write(ring, val); 1775 } 1776 1777 void vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1778 unsigned int vmid, uint64_t pd_addr) 1779 { 1780 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1781 1782 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1783 1784 /* wait for reg writes */ 1785 vcn_v2_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2, 1786 lower_32_bits(pd_addr), 0xffffffff); 1787 } 1788 1789 void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) 1790 { 1791 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); 1792 amdgpu_ring_write(ring, reg << 2); 1793 amdgpu_ring_write(ring, val); 1794 } 1795 1796 /** 1797 * vcn_v2_0_jpeg_ring_get_rptr - get read pointer 1798 * 1799 * @ring: amdgpu_ring pointer 1800 * 1801 * Returns the current hardware read pointer 1802 */ 1803 static uint64_t vcn_v2_0_jpeg_ring_get_rptr(struct amdgpu_ring *ring) 1804 { 1805 struct amdgpu_device *adev = ring->adev; 1806 1807 return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR); 1808 } 1809 1810 /** 1811 * vcn_v2_0_jpeg_ring_get_wptr - get write pointer 1812 * 1813 * @ring: amdgpu_ring pointer 1814 * 1815 * Returns the current hardware write pointer 1816 */ 1817 static uint64_t vcn_v2_0_jpeg_ring_get_wptr(struct amdgpu_ring *ring) 1818 { 1819 struct amdgpu_device *adev = ring->adev; 1820 1821 if (ring->use_doorbell) 1822 return adev->wb.wb[ring->wptr_offs]; 1823 else 1824 return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); 1825 } 1826 1827 /** 1828 * vcn_v2_0_jpeg_ring_set_wptr - set write pointer 1829 * 1830 * @ring: amdgpu_ring pointer 1831 * 1832 * Commits the write pointer to the hardware 1833 */ 1834 static void vcn_v2_0_jpeg_ring_set_wptr(struct amdgpu_ring *ring) 1835 { 1836 struct amdgpu_device *adev = ring->adev; 1837 1838 if (ring->use_doorbell) { 1839 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 1840 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1841 } else { 1842 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); 1843 } 1844 } 1845 1846 /** 1847 * vcn_v2_0_jpeg_ring_insert_start - insert a start command 1848 * 1849 * @ring: amdgpu_ring pointer 1850 * 1851 * Write a start command to the ring. 1852 */ 1853 void vcn_v2_0_jpeg_ring_insert_start(struct amdgpu_ring *ring) 1854 { 1855 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 1856 0, 0, PACKETJ_TYPE0)); 1857 amdgpu_ring_write(ring, 0x68e04); 1858 1859 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 1860 0, 0, PACKETJ_TYPE0)); 1861 amdgpu_ring_write(ring, 0x80010000); 1862 } 1863 1864 /** 1865 * vcn_v2_0_jpeg_ring_insert_end - insert a end command 1866 * 1867 * @ring: amdgpu_ring pointer 1868 * 1869 * Write a end command to the ring. 1870 */ 1871 void vcn_v2_0_jpeg_ring_insert_end(struct amdgpu_ring *ring) 1872 { 1873 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 1874 0, 0, PACKETJ_TYPE0)); 1875 amdgpu_ring_write(ring, 0x68e04); 1876 1877 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 1878 0, 0, PACKETJ_TYPE0)); 1879 amdgpu_ring_write(ring, 0x00010000); 1880 } 1881 1882 /** 1883 * vcn_v2_0_jpeg_ring_emit_fence - emit an fence & trap command 1884 * 1885 * @ring: amdgpu_ring pointer 1886 * @fence: fence to emit 1887 * 1888 * Write a fence and a trap command to the ring. 1889 */ 1890 void vcn_v2_0_jpeg_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 1891 unsigned flags) 1892 { 1893 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1894 1895 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET, 1896 0, 0, PACKETJ_TYPE0)); 1897 amdgpu_ring_write(ring, seq); 1898 1899 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET, 1900 0, 0, PACKETJ_TYPE0)); 1901 amdgpu_ring_write(ring, seq); 1902 1903 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET, 1904 0, 0, PACKETJ_TYPE0)); 1905 amdgpu_ring_write(ring, lower_32_bits(addr)); 1906 1907 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET, 1908 0, 0, PACKETJ_TYPE0)); 1909 amdgpu_ring_write(ring, upper_32_bits(addr)); 1910 1911 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET, 1912 0, 0, PACKETJ_TYPE0)); 1913 amdgpu_ring_write(ring, 0x8); 1914 1915 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET, 1916 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4)); 1917 amdgpu_ring_write(ring, 0); 1918 1919 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 1920 0, 0, PACKETJ_TYPE0)); 1921 amdgpu_ring_write(ring, 0x3fbc); 1922 1923 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 1924 0, 0, PACKETJ_TYPE0)); 1925 amdgpu_ring_write(ring, 0x1); 1926 1927 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7)); 1928 amdgpu_ring_write(ring, 0); 1929 } 1930 1931 /** 1932 * vcn_v2_0_jpeg_ring_emit_ib - execute indirect buffer 1933 * 1934 * @ring: amdgpu_ring pointer 1935 * @ib: indirect buffer to execute 1936 * 1937 * Write ring commands to execute the indirect buffer. 1938 */ 1939 void vcn_v2_0_jpeg_ring_emit_ib(struct amdgpu_ring *ring, 1940 struct amdgpu_job *job, 1941 struct amdgpu_ib *ib, 1942 uint32_t flags) 1943 { 1944 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1945 1946 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET, 1947 0, 0, PACKETJ_TYPE0)); 1948 amdgpu_ring_write(ring, (vmid | (vmid << 4))); 1949 1950 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET, 1951 0, 0, PACKETJ_TYPE0)); 1952 amdgpu_ring_write(ring, (vmid | (vmid << 4))); 1953 1954 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET, 1955 0, 0, PACKETJ_TYPE0)); 1956 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1957 1958 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET, 1959 0, 0, PACKETJ_TYPE0)); 1960 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1961 1962 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET, 1963 0, 0, PACKETJ_TYPE0)); 1964 amdgpu_ring_write(ring, ib->length_dw); 1965 1966 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET, 1967 0, 0, PACKETJ_TYPE0)); 1968 amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr)); 1969 1970 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET, 1971 0, 0, PACKETJ_TYPE0)); 1972 amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr)); 1973 1974 amdgpu_ring_write(ring, PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2)); 1975 amdgpu_ring_write(ring, 0); 1976 1977 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET, 1978 0, 0, PACKETJ_TYPE0)); 1979 amdgpu_ring_write(ring, 0x01400200); 1980 1981 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET, 1982 0, 0, PACKETJ_TYPE0)); 1983 amdgpu_ring_write(ring, 0x2); 1984 1985 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_STATUS_INTERNAL_OFFSET, 1986 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3)); 1987 amdgpu_ring_write(ring, 0x2); 1988 } 1989 1990 void vcn_v2_0_jpeg_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1991 uint32_t val, uint32_t mask) 1992 { 1993 uint32_t reg_offset = (reg << 2); 1994 1995 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET, 1996 0, 0, PACKETJ_TYPE0)); 1997 amdgpu_ring_write(ring, 0x01400200); 1998 1999 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET, 2000 0, 0, PACKETJ_TYPE0)); 2001 amdgpu_ring_write(ring, val); 2002 2003 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 2004 0, 0, PACKETJ_TYPE0)); 2005 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { 2006 amdgpu_ring_write(ring, 0); 2007 amdgpu_ring_write(ring, 2008 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3)); 2009 } else { 2010 amdgpu_ring_write(ring, reg_offset); 2011 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 2012 0, 0, PACKETJ_TYPE3)); 2013 } 2014 amdgpu_ring_write(ring, mask); 2015 } 2016 2017 void vcn_v2_0_jpeg_ring_emit_vm_flush(struct amdgpu_ring *ring, 2018 unsigned vmid, uint64_t pd_addr) 2019 { 2020 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 2021 uint32_t data0, data1, mask; 2022 2023 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 2024 2025 /* wait for register write */ 2026 data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2; 2027 data1 = lower_32_bits(pd_addr); 2028 mask = 0xffffffff; 2029 vcn_v2_0_jpeg_ring_emit_reg_wait(ring, data0, data1, mask); 2030 } 2031 2032 void vcn_v2_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) 2033 { 2034 uint32_t reg_offset = (reg << 2); 2035 2036 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 2037 0, 0, PACKETJ_TYPE0)); 2038 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { 2039 amdgpu_ring_write(ring, 0); 2040 amdgpu_ring_write(ring, 2041 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0)); 2042 } else { 2043 amdgpu_ring_write(ring, reg_offset); 2044 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 2045 0, 0, PACKETJ_TYPE0)); 2046 } 2047 amdgpu_ring_write(ring, val); 2048 } 2049 2050 void vcn_v2_0_jpeg_ring_nop(struct amdgpu_ring *ring, uint32_t count) 2051 { 2052 int i; 2053 2054 WARN_ON(ring->wptr % 2 || count % 2); 2055 2056 for (i = 0; i < count / 2; i++) { 2057 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); 2058 amdgpu_ring_write(ring, 0); 2059 } 2060 } 2061 2062 static int vcn_v2_0_set_interrupt_state(struct amdgpu_device *adev, 2063 struct amdgpu_irq_src *source, 2064 unsigned type, 2065 enum amdgpu_interrupt_state state) 2066 { 2067 return 0; 2068 } 2069 2070 static int vcn_v2_0_process_interrupt(struct amdgpu_device *adev, 2071 struct amdgpu_irq_src *source, 2072 struct amdgpu_iv_entry *entry) 2073 { 2074 DRM_DEBUG("IH: VCN TRAP\n"); 2075 2076 switch (entry->src_id) { 2077 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT: 2078 amdgpu_fence_process(&adev->vcn.inst->ring_dec); 2079 break; 2080 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 2081 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]); 2082 break; 2083 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY: 2084 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]); 2085 break; 2086 case VCN_2_0__SRCID__JPEG_DECODE: 2087 amdgpu_fence_process(&adev->vcn.inst->ring_jpeg); 2088 break; 2089 default: 2090 DRM_ERROR("Unhandled interrupt: %d %d\n", 2091 entry->src_id, entry->src_data[0]); 2092 break; 2093 } 2094 2095 return 0; 2096 } 2097 2098 static int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring) 2099 { 2100 struct amdgpu_device *adev = ring->adev; 2101 uint32_t tmp = 0; 2102 unsigned i; 2103 int r; 2104 2105 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); 2106 r = amdgpu_ring_alloc(ring, 4); 2107 if (r) 2108 return r; 2109 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); 2110 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1)); 2111 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0)); 2112 amdgpu_ring_write(ring, 0xDEADBEEF); 2113 amdgpu_ring_commit(ring); 2114 for (i = 0; i < adev->usec_timeout; i++) { 2115 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); 2116 if (tmp == 0xDEADBEEF) 2117 break; 2118 udelay(1); 2119 } 2120 2121 if (i >= adev->usec_timeout) 2122 r = -ETIMEDOUT; 2123 2124 return r; 2125 } 2126 2127 2128 static int vcn_v2_0_set_powergating_state(void *handle, 2129 enum amd_powergating_state state) 2130 { 2131 /* This doesn't actually powergate the VCN block. 2132 * That's done in the dpm code via the SMC. This 2133 * just re-inits the block as necessary. The actual 2134 * gating still happens in the dpm code. We should 2135 * revisit this when there is a cleaner line between 2136 * the smc and the hw blocks 2137 */ 2138 int ret; 2139 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2140 2141 if (state == adev->vcn.cur_state) 2142 return 0; 2143 2144 if (state == AMD_PG_STATE_GATE) 2145 ret = vcn_v2_0_stop(adev); 2146 else 2147 ret = vcn_v2_0_start(adev); 2148 2149 if (!ret) 2150 adev->vcn.cur_state = state; 2151 return ret; 2152 } 2153 2154 static const struct amd_ip_funcs vcn_v2_0_ip_funcs = { 2155 .name = "vcn_v2_0", 2156 .early_init = vcn_v2_0_early_init, 2157 .late_init = NULL, 2158 .sw_init = vcn_v2_0_sw_init, 2159 .sw_fini = vcn_v2_0_sw_fini, 2160 .hw_init = vcn_v2_0_hw_init, 2161 .hw_fini = vcn_v2_0_hw_fini, 2162 .suspend = vcn_v2_0_suspend, 2163 .resume = vcn_v2_0_resume, 2164 .is_idle = vcn_v2_0_is_idle, 2165 .wait_for_idle = vcn_v2_0_wait_for_idle, 2166 .check_soft_reset = NULL, 2167 .pre_soft_reset = NULL, 2168 .soft_reset = NULL, 2169 .post_soft_reset = NULL, 2170 .set_clockgating_state = vcn_v2_0_set_clockgating_state, 2171 .set_powergating_state = vcn_v2_0_set_powergating_state, 2172 }; 2173 2174 static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = { 2175 .type = AMDGPU_RING_TYPE_VCN_DEC, 2176 .align_mask = 0xf, 2177 .vmhub = AMDGPU_MMHUB_0, 2178 .get_rptr = vcn_v2_0_dec_ring_get_rptr, 2179 .get_wptr = vcn_v2_0_dec_ring_get_wptr, 2180 .set_wptr = vcn_v2_0_dec_ring_set_wptr, 2181 .emit_frame_size = 2182 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 2183 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 2184 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */ 2185 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */ 2186 6, 2187 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */ 2188 .emit_ib = vcn_v2_0_dec_ring_emit_ib, 2189 .emit_fence = vcn_v2_0_dec_ring_emit_fence, 2190 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush, 2191 .test_ring = vcn_v2_0_dec_ring_test_ring, 2192 .test_ib = amdgpu_vcn_dec_ring_test_ib, 2193 .insert_nop = vcn_v2_0_dec_ring_insert_nop, 2194 .insert_start = vcn_v2_0_dec_ring_insert_start, 2195 .insert_end = vcn_v2_0_dec_ring_insert_end, 2196 .pad_ib = amdgpu_ring_generic_pad_ib, 2197 .begin_use = amdgpu_vcn_ring_begin_use, 2198 .end_use = amdgpu_vcn_ring_end_use, 2199 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg, 2200 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait, 2201 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2202 }; 2203 2204 static const struct amdgpu_ring_funcs vcn_v2_0_enc_ring_vm_funcs = { 2205 .type = AMDGPU_RING_TYPE_VCN_ENC, 2206 .align_mask = 0x3f, 2207 .nop = VCN_ENC_CMD_NO_OP, 2208 .vmhub = AMDGPU_MMHUB_0, 2209 .get_rptr = vcn_v2_0_enc_ring_get_rptr, 2210 .get_wptr = vcn_v2_0_enc_ring_get_wptr, 2211 .set_wptr = vcn_v2_0_enc_ring_set_wptr, 2212 .emit_frame_size = 2213 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2214 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 2215 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 2216 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 2217 1, /* vcn_v2_0_enc_ring_insert_end */ 2218 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 2219 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 2220 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 2221 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 2222 .test_ring = amdgpu_vcn_enc_ring_test_ring, 2223 .test_ib = amdgpu_vcn_enc_ring_test_ib, 2224 .insert_nop = amdgpu_ring_insert_nop, 2225 .insert_end = vcn_v2_0_enc_ring_insert_end, 2226 .pad_ib = amdgpu_ring_generic_pad_ib, 2227 .begin_use = amdgpu_vcn_ring_begin_use, 2228 .end_use = amdgpu_vcn_ring_end_use, 2229 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 2230 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 2231 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2232 }; 2233 2234 static const struct amdgpu_ring_funcs vcn_v2_0_jpeg_ring_vm_funcs = { 2235 .type = AMDGPU_RING_TYPE_VCN_JPEG, 2236 .align_mask = 0xf, 2237 .vmhub = AMDGPU_MMHUB_0, 2238 .get_rptr = vcn_v2_0_jpeg_ring_get_rptr, 2239 .get_wptr = vcn_v2_0_jpeg_ring_get_wptr, 2240 .set_wptr = vcn_v2_0_jpeg_ring_set_wptr, 2241 .emit_frame_size = 2242 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 2243 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 2244 8 + /* vcn_v2_0_jpeg_ring_emit_vm_flush */ 2245 18 + 18 + /* vcn_v2_0_jpeg_ring_emit_fence x2 vm fence */ 2246 8 + 16, 2247 .emit_ib_size = 22, /* vcn_v2_0_jpeg_ring_emit_ib */ 2248 .emit_ib = vcn_v2_0_jpeg_ring_emit_ib, 2249 .emit_fence = vcn_v2_0_jpeg_ring_emit_fence, 2250 .emit_vm_flush = vcn_v2_0_jpeg_ring_emit_vm_flush, 2251 .test_ring = amdgpu_vcn_jpeg_ring_test_ring, 2252 .test_ib = amdgpu_vcn_jpeg_ring_test_ib, 2253 .insert_nop = vcn_v2_0_jpeg_ring_nop, 2254 .insert_start = vcn_v2_0_jpeg_ring_insert_start, 2255 .insert_end = vcn_v2_0_jpeg_ring_insert_end, 2256 .pad_ib = amdgpu_ring_generic_pad_ib, 2257 .begin_use = amdgpu_vcn_ring_begin_use, 2258 .end_use = amdgpu_vcn_ring_end_use, 2259 .emit_wreg = vcn_v2_0_jpeg_ring_emit_wreg, 2260 .emit_reg_wait = vcn_v2_0_jpeg_ring_emit_reg_wait, 2261 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2262 }; 2263 2264 static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev) 2265 { 2266 adev->vcn.inst->ring_dec.funcs = &vcn_v2_0_dec_ring_vm_funcs; 2267 DRM_INFO("VCN decode is enabled in VM mode\n"); 2268 } 2269 2270 static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev) 2271 { 2272 int i; 2273 2274 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 2275 adev->vcn.inst->ring_enc[i].funcs = &vcn_v2_0_enc_ring_vm_funcs; 2276 2277 DRM_INFO("VCN encode is enabled in VM mode\n"); 2278 } 2279 2280 static void vcn_v2_0_set_jpeg_ring_funcs(struct amdgpu_device *adev) 2281 { 2282 adev->vcn.inst->ring_jpeg.funcs = &vcn_v2_0_jpeg_ring_vm_funcs; 2283 DRM_INFO("VCN jpeg decode is enabled in VM mode\n"); 2284 } 2285 2286 static const struct amdgpu_irq_src_funcs vcn_v2_0_irq_funcs = { 2287 .set = vcn_v2_0_set_interrupt_state, 2288 .process = vcn_v2_0_process_interrupt, 2289 }; 2290 2291 static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev) 2292 { 2293 adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 2; 2294 adev->vcn.inst->irq.funcs = &vcn_v2_0_irq_funcs; 2295 } 2296 2297 const struct amdgpu_ip_block_version vcn_v2_0_ip_block = 2298 { 2299 .type = AMD_IP_BLOCK_TYPE_VCN, 2300 .major = 2, 2301 .minor = 0, 2302 .rev = 0, 2303 .funcs = &vcn_v2_0_ip_funcs, 2304 }; 2305