1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drm_drv.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_vcn.h" 29 #include "soc15.h" 30 #include "soc15d.h" 31 #include "amdgpu_pm.h" 32 #include "amdgpu_psp.h" 33 #include "mmsch_v2_0.h" 34 #include "vcn_v2_0.h" 35 36 #include "vcn/vcn_2_0_0_offset.h" 37 #include "vcn/vcn_2_0_0_sh_mask.h" 38 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 39 40 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x1fd 41 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x503 42 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x504 43 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x505 44 #define mmUVD_NO_OP_INTERNAL_OFFSET 0x53f 45 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x54a 46 #define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d 47 48 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x1e1 49 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x5a6 50 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x5a7 51 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x1e2 52 53 static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev); 54 static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev); 55 static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev); 56 static int vcn_v2_0_set_powergating_state(void *handle, 57 enum amd_powergating_state state); 58 static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev, 59 int inst_idx, struct dpg_pause_state *new_state); 60 static int vcn_v2_0_start_sriov(struct amdgpu_device *adev); 61 /** 62 * vcn_v2_0_early_init - set function pointers 63 * 64 * @handle: amdgpu_device pointer 65 * 66 * Set ring and irq function pointers 67 */ 68 static int vcn_v2_0_early_init(void *handle) 69 { 70 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 71 72 if (amdgpu_sriov_vf(adev)) 73 adev->vcn.num_enc_rings = 1; 74 else 75 adev->vcn.num_enc_rings = 2; 76 77 vcn_v2_0_set_dec_ring_funcs(adev); 78 vcn_v2_0_set_enc_ring_funcs(adev); 79 vcn_v2_0_set_irq_funcs(adev); 80 81 return 0; 82 } 83 84 /** 85 * vcn_v2_0_sw_init - sw init for VCN block 86 * 87 * @handle: amdgpu_device pointer 88 * 89 * Load firmware and sw initialization 90 */ 91 static int vcn_v2_0_sw_init(void *handle) 92 { 93 struct amdgpu_ring *ring; 94 int i, r; 95 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 96 volatile struct amdgpu_fw_shared *fw_shared; 97 98 /* VCN DEC TRAP */ 99 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 100 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, 101 &adev->vcn.inst->irq); 102 if (r) 103 return r; 104 105 /* VCN ENC TRAP */ 106 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 107 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 108 i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, 109 &adev->vcn.inst->irq); 110 if (r) 111 return r; 112 } 113 114 r = amdgpu_vcn_sw_init(adev); 115 if (r) 116 return r; 117 118 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 119 const struct common_firmware_header *hdr; 120 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 121 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN; 122 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw; 123 adev->firmware.fw_size += 124 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 125 dev_info(adev->dev, "Will use PSP to load VCN firmware\n"); 126 } 127 128 r = amdgpu_vcn_resume(adev); 129 if (r) 130 return r; 131 132 ring = &adev->vcn.inst->ring_dec; 133 134 ring->use_doorbell = true; 135 ring->doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1 << 1; 136 137 sprintf(ring->name, "vcn_dec"); 138 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, 139 AMDGPU_RING_PRIO_DEFAULT, NULL); 140 if (r) 141 return r; 142 143 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; 144 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; 145 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; 146 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; 147 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; 148 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; 149 150 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; 151 adev->vcn.inst->external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9); 152 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; 153 adev->vcn.inst->external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0); 154 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; 155 adev->vcn.inst->external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1); 156 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; 157 adev->vcn.inst->external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD); 158 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; 159 adev->vcn.inst->external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP); 160 161 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 162 enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(i); 163 164 ring = &adev->vcn.inst->ring_enc[i]; 165 ring->use_doorbell = true; 166 if (!amdgpu_sriov_vf(adev)) 167 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i; 168 else 169 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + i; 170 sprintf(ring->name, "vcn_enc%d", i); 171 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, 172 hw_prio, NULL); 173 if (r) 174 return r; 175 } 176 177 adev->vcn.pause_dpg_mode = vcn_v2_0_pause_dpg_mode; 178 179 r = amdgpu_virt_alloc_mm_table(adev); 180 if (r) 181 return r; 182 183 fw_shared = adev->vcn.inst->fw_shared_cpu_addr; 184 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG); 185 return 0; 186 } 187 188 /** 189 * vcn_v2_0_sw_fini - sw fini for VCN block 190 * 191 * @handle: amdgpu_device pointer 192 * 193 * VCN suspend and free up sw allocation 194 */ 195 static int vcn_v2_0_sw_fini(void *handle) 196 { 197 int r, idx; 198 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 199 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared_cpu_addr; 200 201 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 202 fw_shared->present_flag_0 = 0; 203 drm_dev_exit(idx); 204 } 205 206 amdgpu_virt_free_mm_table(adev); 207 208 r = amdgpu_vcn_suspend(adev); 209 if (r) 210 return r; 211 212 r = amdgpu_vcn_sw_fini(adev); 213 214 return r; 215 } 216 217 /** 218 * vcn_v2_0_hw_init - start and test VCN block 219 * 220 * @handle: amdgpu_device pointer 221 * 222 * Initialize the hardware, boot up the VCPU and do some testing 223 */ 224 static int vcn_v2_0_hw_init(void *handle) 225 { 226 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 227 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 228 int i, r; 229 230 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 231 ring->doorbell_index, 0); 232 233 if (amdgpu_sriov_vf(adev)) 234 vcn_v2_0_start_sriov(adev); 235 236 r = amdgpu_ring_test_helper(ring); 237 if (r) 238 goto done; 239 240 //Disable vcn decode for sriov 241 if (amdgpu_sriov_vf(adev)) 242 ring->sched.ready = false; 243 244 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 245 ring = &adev->vcn.inst->ring_enc[i]; 246 r = amdgpu_ring_test_helper(ring); 247 if (r) 248 goto done; 249 } 250 251 done: 252 if (!r) 253 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 254 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 255 256 return r; 257 } 258 259 /** 260 * vcn_v2_0_hw_fini - stop the hardware block 261 * 262 * @handle: amdgpu_device pointer 263 * 264 * Stop the VCN block, mark ring as not ready any more 265 */ 266 static int vcn_v2_0_hw_fini(void *handle) 267 { 268 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 269 270 cancel_delayed_work_sync(&adev->vcn.idle_work); 271 272 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 273 (adev->vcn.cur_state != AMD_PG_STATE_GATE && 274 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) 275 vcn_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 276 277 return 0; 278 } 279 280 /** 281 * vcn_v2_0_suspend - suspend VCN block 282 * 283 * @handle: amdgpu_device pointer 284 * 285 * HW fini and suspend VCN block 286 */ 287 static int vcn_v2_0_suspend(void *handle) 288 { 289 int r; 290 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 291 292 r = vcn_v2_0_hw_fini(adev); 293 if (r) 294 return r; 295 296 r = amdgpu_vcn_suspend(adev); 297 298 return r; 299 } 300 301 /** 302 * vcn_v2_0_resume - resume VCN block 303 * 304 * @handle: amdgpu_device pointer 305 * 306 * Resume firmware and hw init VCN block 307 */ 308 static int vcn_v2_0_resume(void *handle) 309 { 310 int r; 311 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 312 313 r = amdgpu_vcn_resume(adev); 314 if (r) 315 return r; 316 317 r = vcn_v2_0_hw_init(adev); 318 319 return r; 320 } 321 322 /** 323 * vcn_v2_0_mc_resume - memory controller programming 324 * 325 * @adev: amdgpu_device pointer 326 * 327 * Let the VCN memory controller know it's offsets 328 */ 329 static void vcn_v2_0_mc_resume(struct amdgpu_device *adev) 330 { 331 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 332 uint32_t offset; 333 334 if (amdgpu_sriov_vf(adev)) 335 return; 336 337 /* cache window 0: fw */ 338 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 339 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 340 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo)); 341 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 342 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi)); 343 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); 344 offset = 0; 345 } else { 346 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 347 lower_32_bits(adev->vcn.inst->gpu_addr)); 348 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 349 upper_32_bits(adev->vcn.inst->gpu_addr)); 350 offset = size; 351 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 352 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 353 } 354 355 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); 356 357 /* cache window 1: stack */ 358 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 359 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); 360 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 361 upper_32_bits(adev->vcn.inst->gpu_addr + offset)); 362 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0); 363 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 364 365 /* cache window 2: context */ 366 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 367 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 368 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 369 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 370 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0); 371 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 372 373 /* non-cache window */ 374 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 375 lower_32_bits(adev->vcn.inst->fw_shared_gpu_addr)); 376 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 377 upper_32_bits(adev->vcn.inst->fw_shared_gpu_addr)); 378 WREG32_SOC15(UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0, 0); 379 WREG32_SOC15(UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0, 380 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); 381 382 WREG32_SOC15(UVD, 0, mmUVD_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 383 } 384 385 static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirect) 386 { 387 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 388 uint32_t offset; 389 390 /* cache window 0: fw */ 391 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 392 if (!indirect) { 393 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 394 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 395 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0, indirect); 396 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 397 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 398 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0, indirect); 399 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 400 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 401 } else { 402 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 403 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 404 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 405 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 406 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 407 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 408 } 409 offset = 0; 410 } else { 411 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 412 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 413 lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); 414 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 415 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 416 upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); 417 offset = size; 418 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 419 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 420 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 421 } 422 423 if (!indirect) 424 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 425 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 426 else 427 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 428 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 429 430 /* cache window 1: stack */ 431 if (!indirect) { 432 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 433 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 434 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect); 435 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 436 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 437 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect); 438 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 439 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 440 } else { 441 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 442 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 443 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 444 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 445 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 446 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 447 } 448 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 449 UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 450 451 /* cache window 2: context */ 452 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 453 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 454 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 455 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 456 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 457 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 458 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 459 UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 460 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 461 UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 462 463 /* non-cache window */ 464 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 465 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 466 lower_32_bits(adev->vcn.inst->fw_shared_gpu_addr), 0, indirect); 467 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 468 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 469 upper_32_bits(adev->vcn.inst->fw_shared_gpu_addr), 0, indirect); 470 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 471 UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 472 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 473 UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0), 474 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); 475 476 /* VCN global tiling registers */ 477 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 478 UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 479 } 480 481 /** 482 * vcn_v2_0_disable_clock_gating - disable VCN clock gating 483 * 484 * @adev: amdgpu_device pointer 485 * 486 * Disable clock gating for VCN block 487 */ 488 static void vcn_v2_0_disable_clock_gating(struct amdgpu_device *adev) 489 { 490 uint32_t data; 491 492 if (amdgpu_sriov_vf(adev)) 493 return; 494 495 /* UVD disable CGC */ 496 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 497 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 498 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 499 else 500 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 501 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 502 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 503 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 504 505 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); 506 data &= ~(UVD_CGC_GATE__SYS_MASK 507 | UVD_CGC_GATE__UDEC_MASK 508 | UVD_CGC_GATE__MPEG2_MASK 509 | UVD_CGC_GATE__REGS_MASK 510 | UVD_CGC_GATE__RBC_MASK 511 | UVD_CGC_GATE__LMI_MC_MASK 512 | UVD_CGC_GATE__LMI_UMC_MASK 513 | UVD_CGC_GATE__IDCT_MASK 514 | UVD_CGC_GATE__MPRD_MASK 515 | UVD_CGC_GATE__MPC_MASK 516 | UVD_CGC_GATE__LBSI_MASK 517 | UVD_CGC_GATE__LRBBM_MASK 518 | UVD_CGC_GATE__UDEC_RE_MASK 519 | UVD_CGC_GATE__UDEC_CM_MASK 520 | UVD_CGC_GATE__UDEC_IT_MASK 521 | UVD_CGC_GATE__UDEC_DB_MASK 522 | UVD_CGC_GATE__UDEC_MP_MASK 523 | UVD_CGC_GATE__WCB_MASK 524 | UVD_CGC_GATE__VCPU_MASK 525 | UVD_CGC_GATE__SCPU_MASK); 526 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data); 527 528 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 529 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 530 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 531 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 532 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 533 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 534 | UVD_CGC_CTRL__SYS_MODE_MASK 535 | UVD_CGC_CTRL__UDEC_MODE_MASK 536 | UVD_CGC_CTRL__MPEG2_MODE_MASK 537 | UVD_CGC_CTRL__REGS_MODE_MASK 538 | UVD_CGC_CTRL__RBC_MODE_MASK 539 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 540 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 541 | UVD_CGC_CTRL__IDCT_MODE_MASK 542 | UVD_CGC_CTRL__MPRD_MODE_MASK 543 | UVD_CGC_CTRL__MPC_MODE_MASK 544 | UVD_CGC_CTRL__LBSI_MODE_MASK 545 | UVD_CGC_CTRL__LRBBM_MODE_MASK 546 | UVD_CGC_CTRL__WCB_MODE_MASK 547 | UVD_CGC_CTRL__VCPU_MODE_MASK 548 | UVD_CGC_CTRL__SCPU_MODE_MASK); 549 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 550 551 /* turn on */ 552 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); 553 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 554 | UVD_SUVD_CGC_GATE__SIT_MASK 555 | UVD_SUVD_CGC_GATE__SMP_MASK 556 | UVD_SUVD_CGC_GATE__SCM_MASK 557 | UVD_SUVD_CGC_GATE__SDB_MASK 558 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 559 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 560 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 561 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 562 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 563 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 564 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 565 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 566 | UVD_SUVD_CGC_GATE__SCLR_MASK 567 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 568 | UVD_SUVD_CGC_GATE__ENT_MASK 569 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 570 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 571 | UVD_SUVD_CGC_GATE__SITE_MASK 572 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 573 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 574 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 575 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 576 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 577 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data); 578 579 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); 580 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 581 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 582 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 583 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 584 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 585 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 586 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 587 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 588 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 589 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 590 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); 591 } 592 593 static void vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_device *adev, 594 uint8_t sram_sel, uint8_t indirect) 595 { 596 uint32_t reg_data = 0; 597 598 /* enable sw clock gating control */ 599 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 600 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 601 else 602 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 603 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 604 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 605 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 606 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 607 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 608 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 609 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 610 UVD_CGC_CTRL__SYS_MODE_MASK | 611 UVD_CGC_CTRL__UDEC_MODE_MASK | 612 UVD_CGC_CTRL__MPEG2_MODE_MASK | 613 UVD_CGC_CTRL__REGS_MODE_MASK | 614 UVD_CGC_CTRL__RBC_MODE_MASK | 615 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 616 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 617 UVD_CGC_CTRL__IDCT_MODE_MASK | 618 UVD_CGC_CTRL__MPRD_MODE_MASK | 619 UVD_CGC_CTRL__MPC_MODE_MASK | 620 UVD_CGC_CTRL__LBSI_MODE_MASK | 621 UVD_CGC_CTRL__LRBBM_MODE_MASK | 622 UVD_CGC_CTRL__WCB_MODE_MASK | 623 UVD_CGC_CTRL__VCPU_MODE_MASK | 624 UVD_CGC_CTRL__SCPU_MODE_MASK); 625 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 626 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); 627 628 /* turn off clock gating */ 629 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 630 UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect); 631 632 /* turn on SUVD clock gating */ 633 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 634 UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 635 636 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 637 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 638 UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 639 } 640 641 /** 642 * vcn_v2_0_enable_clock_gating - enable VCN clock gating 643 * 644 * @adev: amdgpu_device pointer 645 * 646 * Enable clock gating for VCN block 647 */ 648 static void vcn_v2_0_enable_clock_gating(struct amdgpu_device *adev) 649 { 650 uint32_t data = 0; 651 652 if (amdgpu_sriov_vf(adev)) 653 return; 654 655 /* enable UVD CGC */ 656 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 657 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 658 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 659 else 660 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 661 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 662 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 663 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 664 665 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 666 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 667 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 668 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 669 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 670 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 671 | UVD_CGC_CTRL__SYS_MODE_MASK 672 | UVD_CGC_CTRL__UDEC_MODE_MASK 673 | UVD_CGC_CTRL__MPEG2_MODE_MASK 674 | UVD_CGC_CTRL__REGS_MODE_MASK 675 | UVD_CGC_CTRL__RBC_MODE_MASK 676 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 677 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 678 | UVD_CGC_CTRL__IDCT_MODE_MASK 679 | UVD_CGC_CTRL__MPRD_MODE_MASK 680 | UVD_CGC_CTRL__MPC_MODE_MASK 681 | UVD_CGC_CTRL__LBSI_MODE_MASK 682 | UVD_CGC_CTRL__LRBBM_MODE_MASK 683 | UVD_CGC_CTRL__WCB_MODE_MASK 684 | UVD_CGC_CTRL__VCPU_MODE_MASK 685 | UVD_CGC_CTRL__SCPU_MODE_MASK); 686 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 687 688 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); 689 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 690 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 691 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 692 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 693 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 694 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 695 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 696 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 697 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 698 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 699 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); 700 } 701 702 static void vcn_v2_0_disable_static_power_gating(struct amdgpu_device *adev) 703 { 704 uint32_t data = 0; 705 706 if (amdgpu_sriov_vf(adev)) 707 return; 708 709 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 710 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 711 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 712 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 713 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 714 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 715 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 716 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 717 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 718 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 719 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT); 720 721 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 722 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 723 UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0, 0xFFFFF); 724 } else { 725 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 726 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 727 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 728 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 729 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 730 | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 731 | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 732 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 733 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 734 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT); 735 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 736 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFF); 737 } 738 739 /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS, 740 * UVDU_PWR_STATUS are 0 (power on) */ 741 742 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); 743 data &= ~0x103; 744 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 745 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 746 UVD_POWER_STATUS__UVD_PG_EN_MASK; 747 748 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); 749 } 750 751 static void vcn_v2_0_enable_static_power_gating(struct amdgpu_device *adev) 752 { 753 uint32_t data = 0; 754 755 if (amdgpu_sriov_vf(adev)) 756 return; 757 758 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 759 /* Before power off, this indicator has to be turned on */ 760 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); 761 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 762 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 763 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); 764 765 766 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 767 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 768 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 769 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 770 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 771 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 772 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 773 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 774 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 775 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT); 776 777 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 778 779 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 780 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 781 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 782 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 783 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 784 | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT 785 | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT 786 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 787 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 788 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT); 789 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFF); 790 } 791 } 792 793 static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect) 794 { 795 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared_cpu_addr; 796 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 797 uint32_t rb_bufsz, tmp; 798 799 vcn_v2_0_enable_static_power_gating(adev); 800 801 /* enable dynamic power gating mode */ 802 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); 803 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 804 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 805 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp); 806 807 if (indirect) 808 adev->vcn.inst->dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst->dpg_sram_cpu_addr; 809 810 /* enable clock gating */ 811 vcn_v2_0_clock_gating_dpg_mode(adev, 0, indirect); 812 813 /* enable VCPU clock */ 814 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 815 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 816 tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK; 817 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 818 UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); 819 820 /* disable master interupt */ 821 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 822 UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect); 823 824 /* setup mmUVD_LMI_CTRL */ 825 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 826 UVD_LMI_CTRL__REQ_MODE_MASK | 827 UVD_LMI_CTRL__CRC_RESET_MASK | 828 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 829 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 830 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 831 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 832 0x00100000L); 833 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 834 UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect); 835 836 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 837 UVD, 0, mmUVD_MPC_CNTL), 838 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 839 840 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 841 UVD, 0, mmUVD_MPC_SET_MUXA0), 842 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 843 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 844 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 845 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 846 847 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 848 UVD, 0, mmUVD_MPC_SET_MUXB0), 849 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 850 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 851 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 852 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 853 854 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 855 UVD, 0, mmUVD_MPC_SET_MUX), 856 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 857 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 858 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 859 860 vcn_v2_0_mc_resume_dpg_mode(adev, indirect); 861 862 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 863 UVD, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect); 864 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 865 UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect); 866 867 /* release VCPU reset to boot */ 868 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 869 UVD, 0, mmUVD_SOFT_RESET), 0, 0, indirect); 870 871 /* enable LMI MC and UMC channels */ 872 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 873 UVD, 0, mmUVD_LMI_CTRL2), 874 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 0, indirect); 875 876 /* enable master interrupt */ 877 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 878 UVD, 0, mmUVD_MASTINT_EN), 879 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 880 881 if (indirect) 882 psp_update_vcn_sram(adev, 0, adev->vcn.inst->dpg_sram_gpu_addr, 883 (uint32_t)((uintptr_t)adev->vcn.inst->dpg_sram_curr_addr - 884 (uintptr_t)adev->vcn.inst->dpg_sram_cpu_addr)); 885 886 /* force RBC into idle state */ 887 rb_bufsz = order_base_2(ring->ring_size); 888 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 889 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 890 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 891 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 892 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 893 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 894 895 /* Stall DPG before WPTR/RPTR reset */ 896 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 897 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 898 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 899 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET; 900 901 /* set the write pointer delay */ 902 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); 903 904 /* set the wb address */ 905 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, 906 (upper_32_bits(ring->gpu_addr) >> 2)); 907 908 /* program the RB_BASE for ring buffer */ 909 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 910 lower_32_bits(ring->gpu_addr)); 911 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 912 upper_32_bits(ring->gpu_addr)); 913 914 /* Initialize the ring buffer's read and write pointers */ 915 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); 916 917 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); 918 919 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 920 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 921 lower_32_bits(ring->wptr)); 922 923 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET; 924 /* Unstall DPG */ 925 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 926 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 927 return 0; 928 } 929 930 static int vcn_v2_0_start(struct amdgpu_device *adev) 931 { 932 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared_cpu_addr; 933 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 934 uint32_t rb_bufsz, tmp; 935 uint32_t lmi_swap_cntl; 936 int i, j, r; 937 938 if (adev->pm.dpm_enabled) 939 amdgpu_dpm_enable_uvd(adev, true); 940 941 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 942 return vcn_v2_0_start_dpg_mode(adev, adev->vcn.indirect_sram); 943 944 vcn_v2_0_disable_static_power_gating(adev); 945 946 /* set uvd status busy */ 947 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 948 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); 949 950 /*SW clock gating */ 951 vcn_v2_0_disable_clock_gating(adev); 952 953 /* enable VCPU clock */ 954 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 955 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 956 957 /* disable master interrupt */ 958 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, 959 ~UVD_MASTINT_EN__VCPU_EN_MASK); 960 961 /* setup mmUVD_LMI_CTRL */ 962 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL); 963 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp | 964 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 965 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 966 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 967 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 968 969 /* setup mmUVD_MPC_CNTL */ 970 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL); 971 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 972 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 973 WREG32_SOC15(VCN, 0, mmUVD_MPC_CNTL, tmp); 974 975 /* setup UVD_MPC_SET_MUXA0 */ 976 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, 977 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 978 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 979 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 980 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 981 982 /* setup UVD_MPC_SET_MUXB0 */ 983 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, 984 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 985 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 986 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 987 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 988 989 /* setup mmUVD_MPC_SET_MUX */ 990 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, 991 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 992 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 993 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 994 995 vcn_v2_0_mc_resume(adev); 996 997 /* release VCPU reset to boot */ 998 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 999 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1000 1001 /* enable LMI MC and UMC channels */ 1002 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, 1003 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1004 1005 tmp = RREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET); 1006 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1007 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1008 WREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET, tmp); 1009 1010 /* disable byte swapping */ 1011 lmi_swap_cntl = 0; 1012 #ifdef __BIG_ENDIAN 1013 /* swap (8 in 32) RB and IB */ 1014 lmi_swap_cntl = 0xa; 1015 #endif 1016 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 1017 1018 for (i = 0; i < 10; ++i) { 1019 uint32_t status; 1020 1021 for (j = 0; j < 100; ++j) { 1022 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); 1023 if (status & 2) 1024 break; 1025 mdelay(10); 1026 } 1027 r = 0; 1028 if (status & 2) 1029 break; 1030 1031 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n"); 1032 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1033 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 1034 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1035 mdelay(10); 1036 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 1037 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1038 mdelay(10); 1039 r = -1; 1040 } 1041 1042 if (r) { 1043 DRM_ERROR("VCN decode not responding, giving up!!!\n"); 1044 return r; 1045 } 1046 1047 /* enable master interrupt */ 1048 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 1049 UVD_MASTINT_EN__VCPU_EN_MASK, 1050 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1051 1052 /* clear the busy bit of VCN_STATUS */ 1053 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0, 1054 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1055 1056 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_VMID, 0); 1057 1058 /* force RBC into idle state */ 1059 rb_bufsz = order_base_2(ring->ring_size); 1060 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1061 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1062 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1063 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1064 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1065 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 1066 1067 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET; 1068 /* program the RB_BASE for ring buffer */ 1069 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1070 lower_32_bits(ring->gpu_addr)); 1071 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1072 upper_32_bits(ring->gpu_addr)); 1073 1074 /* Initialize the ring buffer's read and write pointers */ 1075 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); 1076 1077 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 1078 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1079 lower_32_bits(ring->wptr)); 1080 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET; 1081 1082 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET; 1083 ring = &adev->vcn.inst->ring_enc[0]; 1084 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1085 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1086 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); 1087 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1088 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 1089 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET; 1090 1091 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET; 1092 ring = &adev->vcn.inst->ring_enc[1]; 1093 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1094 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1095 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1096 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1097 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); 1098 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET; 1099 1100 return 0; 1101 } 1102 1103 static int vcn_v2_0_stop_dpg_mode(struct amdgpu_device *adev) 1104 { 1105 uint32_t tmp; 1106 1107 /* Wait for power status to be 1 */ 1108 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1, 1109 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1110 1111 /* wait for read ptr to be equal to write ptr */ 1112 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); 1113 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1114 1115 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); 1116 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); 1117 1118 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1119 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); 1120 1121 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1, 1122 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1123 1124 /* disable dynamic power gating mode */ 1125 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0, 1126 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1127 1128 return 0; 1129 } 1130 1131 static int vcn_v2_0_stop(struct amdgpu_device *adev) 1132 { 1133 uint32_t tmp; 1134 int r; 1135 1136 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1137 r = vcn_v2_0_stop_dpg_mode(adev); 1138 if (r) 1139 return r; 1140 goto power_off; 1141 } 1142 1143 /* wait for uvd idle */ 1144 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1145 if (r) 1146 return r; 1147 1148 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1149 UVD_LMI_STATUS__READ_CLEAN_MASK | 1150 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1151 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1152 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp); 1153 if (r) 1154 return r; 1155 1156 /* stall UMC channel */ 1157 tmp = RREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2); 1158 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1159 WREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2, tmp); 1160 1161 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK| 1162 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1163 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp); 1164 if (r) 1165 return r; 1166 1167 /* disable VCPU clock */ 1168 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0, 1169 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1170 1171 /* reset LMI UMC */ 1172 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1173 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK, 1174 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 1175 1176 /* reset LMI */ 1177 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1178 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK, 1179 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); 1180 1181 /* reset VCPU */ 1182 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1183 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 1184 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1185 1186 /* clear status */ 1187 WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0); 1188 1189 vcn_v2_0_enable_clock_gating(adev); 1190 vcn_v2_0_enable_static_power_gating(adev); 1191 1192 power_off: 1193 if (adev->pm.dpm_enabled) 1194 amdgpu_dpm_enable_uvd(adev, false); 1195 1196 return 0; 1197 } 1198 1199 static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev, 1200 int inst_idx, struct dpg_pause_state *new_state) 1201 { 1202 struct amdgpu_ring *ring; 1203 uint32_t reg_data = 0; 1204 int ret_code; 1205 1206 /* pause/unpause if state is changed */ 1207 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1208 DRM_DEBUG("dpg pause state changed %d -> %d", 1209 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1210 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & 1211 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1212 1213 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1214 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 0x1, 1215 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1216 1217 if (!ret_code) { 1218 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared_cpu_addr; 1219 /* pause DPG */ 1220 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1221 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1222 1223 /* wait for ACK */ 1224 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, 1225 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1226 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1227 1228 /* Stall DPG before WPTR/RPTR reset */ 1229 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 1230 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1231 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1232 /* Restore */ 1233 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET; 1234 ring = &adev->vcn.inst->ring_enc[0]; 1235 ring->wptr = 0; 1236 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); 1237 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1238 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 1239 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1240 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1241 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET; 1242 1243 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET; 1244 ring = &adev->vcn.inst->ring_enc[1]; 1245 ring->wptr = 0; 1246 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1247 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1248 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); 1249 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1250 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1251 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET; 1252 1253 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET; 1254 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1255 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); 1256 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET; 1257 /* Unstall DPG */ 1258 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 1259 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1260 1261 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1262 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, 1263 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1264 } 1265 } else { 1266 /* unpause dpg, no need to wait */ 1267 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1268 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1269 } 1270 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1271 } 1272 1273 return 0; 1274 } 1275 1276 static bool vcn_v2_0_is_idle(void *handle) 1277 { 1278 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1279 1280 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); 1281 } 1282 1283 static int vcn_v2_0_wait_for_idle(void *handle) 1284 { 1285 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1286 int ret; 1287 1288 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 1289 UVD_STATUS__IDLE); 1290 1291 return ret; 1292 } 1293 1294 static int vcn_v2_0_set_clockgating_state(void *handle, 1295 enum amd_clockgating_state state) 1296 { 1297 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1298 bool enable = (state == AMD_CG_STATE_GATE); 1299 1300 if (amdgpu_sriov_vf(adev)) 1301 return 0; 1302 1303 if (enable) { 1304 /* wait for STATUS to clear */ 1305 if (!vcn_v2_0_is_idle(handle)) 1306 return -EBUSY; 1307 vcn_v2_0_enable_clock_gating(adev); 1308 } else { 1309 /* disable HW gating and enable Sw gating */ 1310 vcn_v2_0_disable_clock_gating(adev); 1311 } 1312 return 0; 1313 } 1314 1315 /** 1316 * vcn_v2_0_dec_ring_get_rptr - get read pointer 1317 * 1318 * @ring: amdgpu_ring pointer 1319 * 1320 * Returns the current hardware read pointer 1321 */ 1322 static uint64_t vcn_v2_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 1323 { 1324 struct amdgpu_device *adev = ring->adev; 1325 1326 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 1327 } 1328 1329 /** 1330 * vcn_v2_0_dec_ring_get_wptr - get write pointer 1331 * 1332 * @ring: amdgpu_ring pointer 1333 * 1334 * Returns the current hardware write pointer 1335 */ 1336 static uint64_t vcn_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 1337 { 1338 struct amdgpu_device *adev = ring->adev; 1339 1340 if (ring->use_doorbell) 1341 return adev->wb.wb[ring->wptr_offs]; 1342 else 1343 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR); 1344 } 1345 1346 /** 1347 * vcn_v2_0_dec_ring_set_wptr - set write pointer 1348 * 1349 * @ring: amdgpu_ring pointer 1350 * 1351 * Commits the write pointer to the hardware 1352 */ 1353 static void vcn_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 1354 { 1355 struct amdgpu_device *adev = ring->adev; 1356 1357 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1358 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 1359 lower_32_bits(ring->wptr) | 0x80000000); 1360 1361 if (ring->use_doorbell) { 1362 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 1363 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1364 } else { 1365 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1366 } 1367 } 1368 1369 /** 1370 * vcn_v2_0_dec_ring_insert_start - insert a start command 1371 * 1372 * @ring: amdgpu_ring pointer 1373 * 1374 * Write a start command to the ring. 1375 */ 1376 void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring) 1377 { 1378 struct amdgpu_device *adev = ring->adev; 1379 1380 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); 1381 amdgpu_ring_write(ring, 0); 1382 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); 1383 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1)); 1384 } 1385 1386 /** 1387 * vcn_v2_0_dec_ring_insert_end - insert a end command 1388 * 1389 * @ring: amdgpu_ring pointer 1390 * 1391 * Write a end command to the ring. 1392 */ 1393 void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring) 1394 { 1395 struct amdgpu_device *adev = ring->adev; 1396 1397 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); 1398 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END << 1)); 1399 } 1400 1401 /** 1402 * vcn_v2_0_dec_ring_insert_nop - insert a nop command 1403 * 1404 * @ring: amdgpu_ring pointer 1405 * @count: the number of NOP packets to insert 1406 * 1407 * Write a nop command to the ring. 1408 */ 1409 void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 1410 { 1411 struct amdgpu_device *adev = ring->adev; 1412 int i; 1413 1414 WARN_ON(ring->wptr % 2 || count % 2); 1415 1416 for (i = 0; i < count / 2; i++) { 1417 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.nop, 0)); 1418 amdgpu_ring_write(ring, 0); 1419 } 1420 } 1421 1422 /** 1423 * vcn_v2_0_dec_ring_emit_fence - emit an fence & trap command 1424 * 1425 * @ring: amdgpu_ring pointer 1426 * @addr: address 1427 * @seq: sequence number 1428 * @flags: fence related flags 1429 * 1430 * Write a fence and a trap command to the ring. 1431 */ 1432 void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 1433 unsigned flags) 1434 { 1435 struct amdgpu_device *adev = ring->adev; 1436 1437 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1438 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.context_id, 0)); 1439 amdgpu_ring_write(ring, seq); 1440 1441 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); 1442 amdgpu_ring_write(ring, addr & 0xffffffff); 1443 1444 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); 1445 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 1446 1447 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); 1448 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_FENCE << 1)); 1449 1450 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); 1451 amdgpu_ring_write(ring, 0); 1452 1453 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); 1454 amdgpu_ring_write(ring, 0); 1455 1456 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); 1457 1458 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_TRAP << 1)); 1459 } 1460 1461 /** 1462 * vcn_v2_0_dec_ring_emit_ib - execute indirect buffer 1463 * 1464 * @ring: amdgpu_ring pointer 1465 * @job: job to retrieve vmid from 1466 * @ib: indirect buffer to execute 1467 * @flags: unused 1468 * 1469 * Write ring commands to execute the indirect buffer 1470 */ 1471 void vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring, 1472 struct amdgpu_job *job, 1473 struct amdgpu_ib *ib, 1474 uint32_t flags) 1475 { 1476 struct amdgpu_device *adev = ring->adev; 1477 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1478 1479 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_vmid, 0)); 1480 amdgpu_ring_write(ring, vmid); 1481 1482 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_low, 0)); 1483 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1484 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_high, 0)); 1485 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1486 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_size, 0)); 1487 amdgpu_ring_write(ring, ib->length_dw); 1488 } 1489 1490 void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1491 uint32_t val, uint32_t mask) 1492 { 1493 struct amdgpu_device *adev = ring->adev; 1494 1495 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); 1496 amdgpu_ring_write(ring, reg << 2); 1497 1498 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); 1499 amdgpu_ring_write(ring, val); 1500 1501 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.gp_scratch8, 0)); 1502 amdgpu_ring_write(ring, mask); 1503 1504 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); 1505 1506 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_REG_READ_COND_WAIT << 1)); 1507 } 1508 1509 void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, 1510 unsigned vmid, uint64_t pd_addr) 1511 { 1512 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1513 uint32_t data0, data1, mask; 1514 1515 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1516 1517 /* wait for register write */ 1518 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance; 1519 data1 = lower_32_bits(pd_addr); 1520 mask = 0xffffffff; 1521 vcn_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask); 1522 } 1523 1524 void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, 1525 uint32_t reg, uint32_t val) 1526 { 1527 struct amdgpu_device *adev = ring->adev; 1528 1529 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); 1530 amdgpu_ring_write(ring, reg << 2); 1531 1532 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); 1533 amdgpu_ring_write(ring, val); 1534 1535 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); 1536 1537 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_WRITE_REG << 1)); 1538 } 1539 1540 /** 1541 * vcn_v2_0_enc_ring_get_rptr - get enc read pointer 1542 * 1543 * @ring: amdgpu_ring pointer 1544 * 1545 * Returns the current hardware enc read pointer 1546 */ 1547 static uint64_t vcn_v2_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 1548 { 1549 struct amdgpu_device *adev = ring->adev; 1550 1551 if (ring == &adev->vcn.inst->ring_enc[0]) 1552 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR); 1553 else 1554 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2); 1555 } 1556 1557 /** 1558 * vcn_v2_0_enc_ring_get_wptr - get enc write pointer 1559 * 1560 * @ring: amdgpu_ring pointer 1561 * 1562 * Returns the current hardware enc write pointer 1563 */ 1564 static uint64_t vcn_v2_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 1565 { 1566 struct amdgpu_device *adev = ring->adev; 1567 1568 if (ring == &adev->vcn.inst->ring_enc[0]) { 1569 if (ring->use_doorbell) 1570 return adev->wb.wb[ring->wptr_offs]; 1571 else 1572 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); 1573 } else { 1574 if (ring->use_doorbell) 1575 return adev->wb.wb[ring->wptr_offs]; 1576 else 1577 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); 1578 } 1579 } 1580 1581 /** 1582 * vcn_v2_0_enc_ring_set_wptr - set enc write pointer 1583 * 1584 * @ring: amdgpu_ring pointer 1585 * 1586 * Commits the enc write pointer to the hardware 1587 */ 1588 static void vcn_v2_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 1589 { 1590 struct amdgpu_device *adev = ring->adev; 1591 1592 if (ring == &adev->vcn.inst->ring_enc[0]) { 1593 if (ring->use_doorbell) { 1594 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 1595 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1596 } else { 1597 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1598 } 1599 } else { 1600 if (ring->use_doorbell) { 1601 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 1602 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1603 } else { 1604 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1605 } 1606 } 1607 } 1608 1609 /** 1610 * vcn_v2_0_enc_ring_emit_fence - emit an enc fence & trap command 1611 * 1612 * @ring: amdgpu_ring pointer 1613 * @addr: address 1614 * @seq: sequence number 1615 * @flags: fence related flags 1616 * 1617 * Write enc a fence and a trap command to the ring. 1618 */ 1619 void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1620 u64 seq, unsigned flags) 1621 { 1622 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1623 1624 amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE); 1625 amdgpu_ring_write(ring, addr); 1626 amdgpu_ring_write(ring, upper_32_bits(addr)); 1627 amdgpu_ring_write(ring, seq); 1628 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP); 1629 } 1630 1631 void vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring *ring) 1632 { 1633 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 1634 } 1635 1636 /** 1637 * vcn_v2_0_enc_ring_emit_ib - enc execute indirect buffer 1638 * 1639 * @ring: amdgpu_ring pointer 1640 * @job: job to retrive vmid from 1641 * @ib: indirect buffer to execute 1642 * @flags: unused 1643 * 1644 * Write enc ring commands to execute the indirect buffer 1645 */ 1646 void vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring *ring, 1647 struct amdgpu_job *job, 1648 struct amdgpu_ib *ib, 1649 uint32_t flags) 1650 { 1651 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1652 1653 amdgpu_ring_write(ring, VCN_ENC_CMD_IB); 1654 amdgpu_ring_write(ring, vmid); 1655 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1656 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1657 amdgpu_ring_write(ring, ib->length_dw); 1658 } 1659 1660 void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1661 uint32_t val, uint32_t mask) 1662 { 1663 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); 1664 amdgpu_ring_write(ring, reg << 2); 1665 amdgpu_ring_write(ring, mask); 1666 amdgpu_ring_write(ring, val); 1667 } 1668 1669 void vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1670 unsigned int vmid, uint64_t pd_addr) 1671 { 1672 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1673 1674 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1675 1676 /* wait for reg writes */ 1677 vcn_v2_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + 1678 vmid * hub->ctx_addr_distance, 1679 lower_32_bits(pd_addr), 0xffffffff); 1680 } 1681 1682 void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) 1683 { 1684 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); 1685 amdgpu_ring_write(ring, reg << 2); 1686 amdgpu_ring_write(ring, val); 1687 } 1688 1689 static int vcn_v2_0_set_interrupt_state(struct amdgpu_device *adev, 1690 struct amdgpu_irq_src *source, 1691 unsigned type, 1692 enum amdgpu_interrupt_state state) 1693 { 1694 return 0; 1695 } 1696 1697 static int vcn_v2_0_process_interrupt(struct amdgpu_device *adev, 1698 struct amdgpu_irq_src *source, 1699 struct amdgpu_iv_entry *entry) 1700 { 1701 DRM_DEBUG("IH: VCN TRAP\n"); 1702 1703 switch (entry->src_id) { 1704 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT: 1705 amdgpu_fence_process(&adev->vcn.inst->ring_dec); 1706 break; 1707 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1708 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]); 1709 break; 1710 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY: 1711 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]); 1712 break; 1713 default: 1714 DRM_ERROR("Unhandled interrupt: %d %d\n", 1715 entry->src_id, entry->src_data[0]); 1716 break; 1717 } 1718 1719 return 0; 1720 } 1721 1722 int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring) 1723 { 1724 struct amdgpu_device *adev = ring->adev; 1725 uint32_t tmp = 0; 1726 unsigned i; 1727 int r; 1728 1729 if (amdgpu_sriov_vf(adev)) 1730 return 0; 1731 1732 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); 1733 r = amdgpu_ring_alloc(ring, 4); 1734 if (r) 1735 return r; 1736 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); 1737 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1)); 1738 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0)); 1739 amdgpu_ring_write(ring, 0xDEADBEEF); 1740 amdgpu_ring_commit(ring); 1741 for (i = 0; i < adev->usec_timeout; i++) { 1742 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); 1743 if (tmp == 0xDEADBEEF) 1744 break; 1745 udelay(1); 1746 } 1747 1748 if (i >= adev->usec_timeout) 1749 r = -ETIMEDOUT; 1750 1751 return r; 1752 } 1753 1754 1755 static int vcn_v2_0_set_powergating_state(void *handle, 1756 enum amd_powergating_state state) 1757 { 1758 /* This doesn't actually powergate the VCN block. 1759 * That's done in the dpm code via the SMC. This 1760 * just re-inits the block as necessary. The actual 1761 * gating still happens in the dpm code. We should 1762 * revisit this when there is a cleaner line between 1763 * the smc and the hw blocks 1764 */ 1765 int ret; 1766 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1767 1768 if (amdgpu_sriov_vf(adev)) { 1769 adev->vcn.cur_state = AMD_PG_STATE_UNGATE; 1770 return 0; 1771 } 1772 1773 if (state == adev->vcn.cur_state) 1774 return 0; 1775 1776 if (state == AMD_PG_STATE_GATE) 1777 ret = vcn_v2_0_stop(adev); 1778 else 1779 ret = vcn_v2_0_start(adev); 1780 1781 if (!ret) 1782 adev->vcn.cur_state = state; 1783 return ret; 1784 } 1785 1786 static int vcn_v2_0_start_mmsch(struct amdgpu_device *adev, 1787 struct amdgpu_mm_table *table) 1788 { 1789 uint32_t data = 0, loop; 1790 uint64_t addr = table->gpu_addr; 1791 struct mmsch_v2_0_init_header *header; 1792 uint32_t size; 1793 int i; 1794 1795 header = (struct mmsch_v2_0_init_header *)table->cpu_addr; 1796 size = header->header_size + header->vcn_table_size; 1797 1798 /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr 1799 * of memory descriptor location 1800 */ 1801 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr)); 1802 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr)); 1803 1804 /* 2, update vmid of descriptor */ 1805 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID); 1806 data &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1807 /* use domain0 for MM scheduler */ 1808 data |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1809 WREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID, data); 1810 1811 /* 3, notify mmsch about the size of this descriptor */ 1812 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_SIZE, size); 1813 1814 /* 4, set resp to zero */ 1815 WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP, 0); 1816 1817 adev->vcn.inst->ring_dec.wptr = 0; 1818 adev->vcn.inst->ring_dec.wptr_old = 0; 1819 vcn_v2_0_dec_ring_set_wptr(&adev->vcn.inst->ring_dec); 1820 1821 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 1822 adev->vcn.inst->ring_enc[i].wptr = 0; 1823 adev->vcn.inst->ring_enc[i].wptr_old = 0; 1824 vcn_v2_0_enc_ring_set_wptr(&adev->vcn.inst->ring_enc[i]); 1825 } 1826 1827 /* 5, kick off the initialization and wait until 1828 * VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero 1829 */ 1830 WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_HOST, 0x10000001); 1831 1832 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP); 1833 loop = 1000; 1834 while ((data & 0x10000002) != 0x10000002) { 1835 udelay(10); 1836 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP); 1837 loop--; 1838 if (!loop) 1839 break; 1840 } 1841 1842 if (!loop) { 1843 DRM_ERROR("failed to init MMSCH, " \ 1844 "mmMMSCH_VF_MAILBOX_RESP = 0x%08x\n", data); 1845 return -EBUSY; 1846 } 1847 1848 return 0; 1849 } 1850 1851 static int vcn_v2_0_start_sriov(struct amdgpu_device *adev) 1852 { 1853 int r; 1854 uint32_t tmp; 1855 struct amdgpu_ring *ring; 1856 uint32_t offset, size; 1857 uint32_t table_size = 0; 1858 struct mmsch_v2_0_cmd_direct_write direct_wt = { {0} }; 1859 struct mmsch_v2_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} }; 1860 struct mmsch_v2_0_cmd_end end = { {0} }; 1861 struct mmsch_v2_0_init_header *header; 1862 uint32_t *init_table = adev->virt.mm_table.cpu_addr; 1863 uint8_t i = 0; 1864 1865 header = (struct mmsch_v2_0_init_header *)init_table; 1866 direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE; 1867 direct_rd_mod_wt.cmd_header.command_type = 1868 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1869 end.cmd_header.command_type = MMSCH_COMMAND__END; 1870 1871 if (header->vcn_table_offset == 0 && header->vcn_table_size == 0) { 1872 header->version = MMSCH_VERSION; 1873 header->header_size = sizeof(struct mmsch_v2_0_init_header) >> 2; 1874 1875 header->vcn_table_offset = header->header_size; 1876 1877 init_table += header->vcn_table_offset; 1878 1879 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 1880 1881 MMSCH_V2_0_INSERT_DIRECT_RD_MOD_WT( 1882 SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 1883 0xFFFFFFFF, 0x00000004); 1884 1885 /* mc resume*/ 1886 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1887 tmp = AMDGPU_UCODE_ID_VCN; 1888 MMSCH_V2_0_INSERT_DIRECT_WT( 1889 SOC15_REG_OFFSET(UVD, i, 1890 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1891 adev->firmware.ucode[tmp].tmr_mc_addr_lo); 1892 MMSCH_V2_0_INSERT_DIRECT_WT( 1893 SOC15_REG_OFFSET(UVD, i, 1894 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1895 adev->firmware.ucode[tmp].tmr_mc_addr_hi); 1896 offset = 0; 1897 } else { 1898 MMSCH_V2_0_INSERT_DIRECT_WT( 1899 SOC15_REG_OFFSET(UVD, i, 1900 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1901 lower_32_bits(adev->vcn.inst->gpu_addr)); 1902 MMSCH_V2_0_INSERT_DIRECT_WT( 1903 SOC15_REG_OFFSET(UVD, i, 1904 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1905 upper_32_bits(adev->vcn.inst->gpu_addr)); 1906 offset = size; 1907 } 1908 1909 MMSCH_V2_0_INSERT_DIRECT_WT( 1910 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0), 1911 0); 1912 MMSCH_V2_0_INSERT_DIRECT_WT( 1913 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), 1914 size); 1915 1916 MMSCH_V2_0_INSERT_DIRECT_WT( 1917 SOC15_REG_OFFSET(UVD, i, 1918 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 1919 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); 1920 MMSCH_V2_0_INSERT_DIRECT_WT( 1921 SOC15_REG_OFFSET(UVD, i, 1922 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 1923 upper_32_bits(adev->vcn.inst->gpu_addr + offset)); 1924 MMSCH_V2_0_INSERT_DIRECT_WT( 1925 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1), 1926 0); 1927 MMSCH_V2_0_INSERT_DIRECT_WT( 1928 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1), 1929 AMDGPU_VCN_STACK_SIZE); 1930 1931 MMSCH_V2_0_INSERT_DIRECT_WT( 1932 SOC15_REG_OFFSET(UVD, i, 1933 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 1934 lower_32_bits(adev->vcn.inst->gpu_addr + offset + 1935 AMDGPU_VCN_STACK_SIZE)); 1936 MMSCH_V2_0_INSERT_DIRECT_WT( 1937 SOC15_REG_OFFSET(UVD, i, 1938 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 1939 upper_32_bits(adev->vcn.inst->gpu_addr + offset + 1940 AMDGPU_VCN_STACK_SIZE)); 1941 MMSCH_V2_0_INSERT_DIRECT_WT( 1942 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2), 1943 0); 1944 MMSCH_V2_0_INSERT_DIRECT_WT( 1945 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2), 1946 AMDGPU_VCN_CONTEXT_SIZE); 1947 1948 for (r = 0; r < adev->vcn.num_enc_rings; ++r) { 1949 ring = &adev->vcn.inst->ring_enc[r]; 1950 ring->wptr = 0; 1951 MMSCH_V2_0_INSERT_DIRECT_WT( 1952 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO), 1953 lower_32_bits(ring->gpu_addr)); 1954 MMSCH_V2_0_INSERT_DIRECT_WT( 1955 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), 1956 upper_32_bits(ring->gpu_addr)); 1957 MMSCH_V2_0_INSERT_DIRECT_WT( 1958 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE), 1959 ring->ring_size / 4); 1960 } 1961 1962 ring = &adev->vcn.inst->ring_dec; 1963 ring->wptr = 0; 1964 MMSCH_V2_0_INSERT_DIRECT_WT( 1965 SOC15_REG_OFFSET(UVD, i, 1966 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW), 1967 lower_32_bits(ring->gpu_addr)); 1968 MMSCH_V2_0_INSERT_DIRECT_WT( 1969 SOC15_REG_OFFSET(UVD, i, 1970 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH), 1971 upper_32_bits(ring->gpu_addr)); 1972 /* force RBC into idle state */ 1973 tmp = order_base_2(ring->ring_size); 1974 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp); 1975 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1976 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1977 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1978 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1979 MMSCH_V2_0_INSERT_DIRECT_WT( 1980 SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp); 1981 1982 /* add end packet */ 1983 tmp = sizeof(struct mmsch_v2_0_cmd_end); 1984 memcpy((void *)init_table, &end, tmp); 1985 table_size += (tmp / 4); 1986 header->vcn_table_size = table_size; 1987 1988 } 1989 return vcn_v2_0_start_mmsch(adev, &adev->virt.mm_table); 1990 } 1991 1992 static const struct amd_ip_funcs vcn_v2_0_ip_funcs = { 1993 .name = "vcn_v2_0", 1994 .early_init = vcn_v2_0_early_init, 1995 .late_init = NULL, 1996 .sw_init = vcn_v2_0_sw_init, 1997 .sw_fini = vcn_v2_0_sw_fini, 1998 .hw_init = vcn_v2_0_hw_init, 1999 .hw_fini = vcn_v2_0_hw_fini, 2000 .suspend = vcn_v2_0_suspend, 2001 .resume = vcn_v2_0_resume, 2002 .is_idle = vcn_v2_0_is_idle, 2003 .wait_for_idle = vcn_v2_0_wait_for_idle, 2004 .check_soft_reset = NULL, 2005 .pre_soft_reset = NULL, 2006 .soft_reset = NULL, 2007 .post_soft_reset = NULL, 2008 .set_clockgating_state = vcn_v2_0_set_clockgating_state, 2009 .set_powergating_state = vcn_v2_0_set_powergating_state, 2010 }; 2011 2012 static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = { 2013 .type = AMDGPU_RING_TYPE_VCN_DEC, 2014 .align_mask = 0xf, 2015 .vmhub = AMDGPU_MMHUB_0, 2016 .get_rptr = vcn_v2_0_dec_ring_get_rptr, 2017 .get_wptr = vcn_v2_0_dec_ring_get_wptr, 2018 .set_wptr = vcn_v2_0_dec_ring_set_wptr, 2019 .emit_frame_size = 2020 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 2021 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 2022 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */ 2023 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */ 2024 6, 2025 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */ 2026 .emit_ib = vcn_v2_0_dec_ring_emit_ib, 2027 .emit_fence = vcn_v2_0_dec_ring_emit_fence, 2028 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush, 2029 .test_ring = vcn_v2_0_dec_ring_test_ring, 2030 .test_ib = amdgpu_vcn_dec_ring_test_ib, 2031 .insert_nop = vcn_v2_0_dec_ring_insert_nop, 2032 .insert_start = vcn_v2_0_dec_ring_insert_start, 2033 .insert_end = vcn_v2_0_dec_ring_insert_end, 2034 .pad_ib = amdgpu_ring_generic_pad_ib, 2035 .begin_use = amdgpu_vcn_ring_begin_use, 2036 .end_use = amdgpu_vcn_ring_end_use, 2037 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg, 2038 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait, 2039 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2040 }; 2041 2042 static const struct amdgpu_ring_funcs vcn_v2_0_enc_ring_vm_funcs = { 2043 .type = AMDGPU_RING_TYPE_VCN_ENC, 2044 .align_mask = 0x3f, 2045 .nop = VCN_ENC_CMD_NO_OP, 2046 .vmhub = AMDGPU_MMHUB_0, 2047 .get_rptr = vcn_v2_0_enc_ring_get_rptr, 2048 .get_wptr = vcn_v2_0_enc_ring_get_wptr, 2049 .set_wptr = vcn_v2_0_enc_ring_set_wptr, 2050 .emit_frame_size = 2051 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2052 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 2053 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 2054 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 2055 1, /* vcn_v2_0_enc_ring_insert_end */ 2056 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 2057 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 2058 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 2059 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 2060 .test_ring = amdgpu_vcn_enc_ring_test_ring, 2061 .test_ib = amdgpu_vcn_enc_ring_test_ib, 2062 .insert_nop = amdgpu_ring_insert_nop, 2063 .insert_end = vcn_v2_0_enc_ring_insert_end, 2064 .pad_ib = amdgpu_ring_generic_pad_ib, 2065 .begin_use = amdgpu_vcn_ring_begin_use, 2066 .end_use = amdgpu_vcn_ring_end_use, 2067 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 2068 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 2069 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2070 }; 2071 2072 static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev) 2073 { 2074 adev->vcn.inst->ring_dec.funcs = &vcn_v2_0_dec_ring_vm_funcs; 2075 DRM_INFO("VCN decode is enabled in VM mode\n"); 2076 } 2077 2078 static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev) 2079 { 2080 int i; 2081 2082 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 2083 adev->vcn.inst->ring_enc[i].funcs = &vcn_v2_0_enc_ring_vm_funcs; 2084 2085 DRM_INFO("VCN encode is enabled in VM mode\n"); 2086 } 2087 2088 static const struct amdgpu_irq_src_funcs vcn_v2_0_irq_funcs = { 2089 .set = vcn_v2_0_set_interrupt_state, 2090 .process = vcn_v2_0_process_interrupt, 2091 }; 2092 2093 static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev) 2094 { 2095 adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 1; 2096 adev->vcn.inst->irq.funcs = &vcn_v2_0_irq_funcs; 2097 } 2098 2099 const struct amdgpu_ip_block_version vcn_v2_0_ip_block = 2100 { 2101 .type = AMD_IP_BLOCK_TYPE_VCN, 2102 .major = 2, 2103 .minor = 0, 2104 .rev = 0, 2105 .funcs = &vcn_v2_0_ip_funcs, 2106 }; 2107