1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_vcn.h" 28 #include "amdgpu_pm.h" 29 #include "soc15.h" 30 #include "soc15d.h" 31 #include "soc15_common.h" 32 33 #include "vcn/vcn_1_0_offset.h" 34 #include "vcn/vcn_1_0_sh_mask.h" 35 #include "mmhub/mmhub_9_1_offset.h" 36 #include "mmhub/mmhub_9_1_sh_mask.h" 37 38 #include "ivsrcid/vcn/irqsrcs_vcn_1_0.h" 39 #include "jpeg_v1_0.h" 40 #include "vcn_v1_0.h" 41 42 #define mmUVD_RBC_XX_IB_REG_CHECK_1_0 0x05ab 43 #define mmUVD_RBC_XX_IB_REG_CHECK_1_0_BASE_IDX 1 44 #define mmUVD_REG_XX_MASK_1_0 0x05ac 45 #define mmUVD_REG_XX_MASK_1_0_BASE_IDX 1 46 47 static int vcn_v1_0_stop(struct amdgpu_device *adev); 48 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev); 49 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev); 50 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev); 51 static int vcn_v1_0_set_powergating_state(void *handle, enum amd_powergating_state state); 52 static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev, 53 int inst_idx, struct dpg_pause_state *new_state); 54 55 static void vcn_v1_0_idle_work_handler(struct work_struct *work); 56 static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring); 57 58 /** 59 * vcn_v1_0_early_init - set function pointers 60 * 61 * @handle: amdgpu_device pointer 62 * 63 * Set ring and irq function pointers 64 */ 65 static int vcn_v1_0_early_init(void *handle) 66 { 67 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 68 69 adev->vcn.num_enc_rings = 2; 70 71 vcn_v1_0_set_dec_ring_funcs(adev); 72 vcn_v1_0_set_enc_ring_funcs(adev); 73 vcn_v1_0_set_irq_funcs(adev); 74 75 jpeg_v1_0_early_init(handle); 76 77 return 0; 78 } 79 80 /** 81 * vcn_v1_0_sw_init - sw init for VCN block 82 * 83 * @handle: amdgpu_device pointer 84 * 85 * Load firmware and sw initialization 86 */ 87 static int vcn_v1_0_sw_init(void *handle) 88 { 89 struct amdgpu_ring *ring; 90 int i, r; 91 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 92 93 /* VCN DEC TRAP */ 94 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 95 VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst->irq); 96 if (r) 97 return r; 98 99 /* VCN ENC TRAP */ 100 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 101 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, i + VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE, 102 &adev->vcn.inst->irq); 103 if (r) 104 return r; 105 } 106 107 r = amdgpu_vcn_sw_init(adev); 108 if (r) 109 return r; 110 111 /* Override the work func */ 112 adev->vcn.idle_work.work.func = vcn_v1_0_idle_work_handler; 113 114 amdgpu_vcn_setup_ucode(adev); 115 116 r = amdgpu_vcn_resume(adev); 117 if (r) 118 return r; 119 120 ring = &adev->vcn.inst->ring_dec; 121 sprintf(ring->name, "vcn_dec"); 122 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, 123 AMDGPU_RING_PRIO_DEFAULT, NULL); 124 if (r) 125 return r; 126 127 adev->vcn.internal.scratch9 = adev->vcn.inst->external.scratch9 = 128 SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9); 129 adev->vcn.internal.data0 = adev->vcn.inst->external.data0 = 130 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0); 131 adev->vcn.internal.data1 = adev->vcn.inst->external.data1 = 132 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1); 133 adev->vcn.internal.cmd = adev->vcn.inst->external.cmd = 134 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD); 135 adev->vcn.internal.nop = adev->vcn.inst->external.nop = 136 SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP); 137 138 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 139 enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(i); 140 141 ring = &adev->vcn.inst->ring_enc[i]; 142 sprintf(ring->name, "vcn_enc%d", i); 143 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, 144 hw_prio, NULL); 145 if (r) 146 return r; 147 } 148 149 adev->vcn.pause_dpg_mode = vcn_v1_0_pause_dpg_mode; 150 151 r = jpeg_v1_0_sw_init(handle); 152 153 return r; 154 } 155 156 /** 157 * vcn_v1_0_sw_fini - sw fini for VCN block 158 * 159 * @handle: amdgpu_device pointer 160 * 161 * VCN suspend and free up sw allocation 162 */ 163 static int vcn_v1_0_sw_fini(void *handle) 164 { 165 int r; 166 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 167 168 r = amdgpu_vcn_suspend(adev); 169 if (r) 170 return r; 171 172 jpeg_v1_0_sw_fini(handle); 173 174 r = amdgpu_vcn_sw_fini(adev); 175 176 return r; 177 } 178 179 /** 180 * vcn_v1_0_hw_init - start and test VCN block 181 * 182 * @handle: amdgpu_device pointer 183 * 184 * Initialize the hardware, boot up the VCPU and do some testing 185 */ 186 static int vcn_v1_0_hw_init(void *handle) 187 { 188 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 189 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 190 int i, r; 191 192 r = amdgpu_ring_test_helper(ring); 193 if (r) 194 goto done; 195 196 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 197 ring = &adev->vcn.inst->ring_enc[i]; 198 r = amdgpu_ring_test_helper(ring); 199 if (r) 200 goto done; 201 } 202 203 ring = &adev->jpeg.inst->ring_dec; 204 r = amdgpu_ring_test_helper(ring); 205 if (r) 206 goto done; 207 208 done: 209 if (!r) 210 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 211 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 212 213 return r; 214 } 215 216 /** 217 * vcn_v1_0_hw_fini - stop the hardware block 218 * 219 * @handle: amdgpu_device pointer 220 * 221 * Stop the VCN block, mark ring as not ready any more 222 */ 223 static int vcn_v1_0_hw_fini(void *handle) 224 { 225 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 226 227 cancel_delayed_work_sync(&adev->vcn.idle_work); 228 229 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 230 (adev->vcn.cur_state != AMD_PG_STATE_GATE && 231 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) { 232 vcn_v1_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 233 } 234 235 return 0; 236 } 237 238 /** 239 * vcn_v1_0_suspend - suspend VCN block 240 * 241 * @handle: amdgpu_device pointer 242 * 243 * HW fini and suspend VCN block 244 */ 245 static int vcn_v1_0_suspend(void *handle) 246 { 247 int r; 248 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 249 250 r = vcn_v1_0_hw_fini(adev); 251 if (r) 252 return r; 253 254 r = amdgpu_vcn_suspend(adev); 255 256 return r; 257 } 258 259 /** 260 * vcn_v1_0_resume - resume VCN block 261 * 262 * @handle: amdgpu_device pointer 263 * 264 * Resume firmware and hw init VCN block 265 */ 266 static int vcn_v1_0_resume(void *handle) 267 { 268 int r; 269 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 270 271 r = amdgpu_vcn_resume(adev); 272 if (r) 273 return r; 274 275 r = vcn_v1_0_hw_init(adev); 276 277 return r; 278 } 279 280 /** 281 * vcn_v1_0_mc_resume_spg_mode - memory controller programming 282 * 283 * @adev: amdgpu_device pointer 284 * 285 * Let the VCN memory controller know it's offsets 286 */ 287 static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev) 288 { 289 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 290 uint32_t offset; 291 292 /* cache window 0: fw */ 293 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 294 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 295 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo)); 296 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 297 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi)); 298 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); 299 offset = 0; 300 } else { 301 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 302 lower_32_bits(adev->vcn.inst->gpu_addr)); 303 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 304 upper_32_bits(adev->vcn.inst->gpu_addr)); 305 offset = size; 306 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 307 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 308 } 309 310 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); 311 312 /* cache window 1: stack */ 313 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 314 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); 315 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 316 upper_32_bits(adev->vcn.inst->gpu_addr + offset)); 317 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0); 318 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 319 320 /* cache window 2: context */ 321 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 322 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 323 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 324 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 325 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0); 326 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 327 328 WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG, 329 adev->gfx.config.gb_addr_config); 330 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG, 331 adev->gfx.config.gb_addr_config); 332 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, 333 adev->gfx.config.gb_addr_config); 334 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG, 335 adev->gfx.config.gb_addr_config); 336 WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG, 337 adev->gfx.config.gb_addr_config); 338 WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG, 339 adev->gfx.config.gb_addr_config); 340 WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG, 341 adev->gfx.config.gb_addr_config); 342 WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG, 343 adev->gfx.config.gb_addr_config); 344 WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG, 345 adev->gfx.config.gb_addr_config); 346 WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG, 347 adev->gfx.config.gb_addr_config); 348 WREG32_SOC15(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, 349 adev->gfx.config.gb_addr_config); 350 WREG32_SOC15(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, 351 adev->gfx.config.gb_addr_config); 352 } 353 354 static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev) 355 { 356 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 357 uint32_t offset; 358 359 /* cache window 0: fw */ 360 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 361 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 362 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 363 0xFFFFFFFF, 0); 364 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 365 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 366 0xFFFFFFFF, 0); 367 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0, 368 0xFFFFFFFF, 0); 369 offset = 0; 370 } else { 371 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 372 lower_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0); 373 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 374 upper_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0); 375 offset = size; 376 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 377 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0xFFFFFFFF, 0); 378 } 379 380 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size, 0xFFFFFFFF, 0); 381 382 /* cache window 1: stack */ 383 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 384 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0); 385 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 386 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0); 387 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0, 388 0xFFFFFFFF, 0); 389 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE, 390 0xFFFFFFFF, 0); 391 392 /* cache window 2: context */ 393 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 394 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 395 0xFFFFFFFF, 0); 396 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 397 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 398 0xFFFFFFFF, 0); 399 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0); 400 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE, 401 0xFFFFFFFF, 0); 402 403 /* VCN global tiling registers */ 404 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_ADDR_CONFIG, 405 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 406 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG, 407 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 408 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, 409 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 410 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG, 411 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 412 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG, 413 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 414 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG, 415 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 416 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG, 417 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 418 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG, 419 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 420 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG, 421 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 422 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG, 423 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 424 } 425 426 /** 427 * vcn_v1_0_disable_clock_gating - disable VCN clock gating 428 * 429 * @adev: amdgpu_device pointer 430 * 431 * Disable clock gating for VCN block 432 */ 433 static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev) 434 { 435 uint32_t data; 436 437 /* JPEG disable CGC */ 438 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); 439 440 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 441 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 442 else 443 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK; 444 445 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 446 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 447 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data); 448 449 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); 450 data &= ~(JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK); 451 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data); 452 453 /* UVD disable CGC */ 454 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 455 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 456 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 457 else 458 data &= ~ UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 459 460 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 461 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 462 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 463 464 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); 465 data &= ~(UVD_CGC_GATE__SYS_MASK 466 | UVD_CGC_GATE__UDEC_MASK 467 | UVD_CGC_GATE__MPEG2_MASK 468 | UVD_CGC_GATE__REGS_MASK 469 | UVD_CGC_GATE__RBC_MASK 470 | UVD_CGC_GATE__LMI_MC_MASK 471 | UVD_CGC_GATE__LMI_UMC_MASK 472 | UVD_CGC_GATE__IDCT_MASK 473 | UVD_CGC_GATE__MPRD_MASK 474 | UVD_CGC_GATE__MPC_MASK 475 | UVD_CGC_GATE__LBSI_MASK 476 | UVD_CGC_GATE__LRBBM_MASK 477 | UVD_CGC_GATE__UDEC_RE_MASK 478 | UVD_CGC_GATE__UDEC_CM_MASK 479 | UVD_CGC_GATE__UDEC_IT_MASK 480 | UVD_CGC_GATE__UDEC_DB_MASK 481 | UVD_CGC_GATE__UDEC_MP_MASK 482 | UVD_CGC_GATE__WCB_MASK 483 | UVD_CGC_GATE__VCPU_MASK 484 | UVD_CGC_GATE__SCPU_MASK); 485 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data); 486 487 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 488 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 489 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 490 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 491 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 492 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 493 | UVD_CGC_CTRL__SYS_MODE_MASK 494 | UVD_CGC_CTRL__UDEC_MODE_MASK 495 | UVD_CGC_CTRL__MPEG2_MODE_MASK 496 | UVD_CGC_CTRL__REGS_MODE_MASK 497 | UVD_CGC_CTRL__RBC_MODE_MASK 498 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 499 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 500 | UVD_CGC_CTRL__IDCT_MODE_MASK 501 | UVD_CGC_CTRL__MPRD_MODE_MASK 502 | UVD_CGC_CTRL__MPC_MODE_MASK 503 | UVD_CGC_CTRL__LBSI_MODE_MASK 504 | UVD_CGC_CTRL__LRBBM_MODE_MASK 505 | UVD_CGC_CTRL__WCB_MODE_MASK 506 | UVD_CGC_CTRL__VCPU_MODE_MASK 507 | UVD_CGC_CTRL__SCPU_MODE_MASK); 508 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 509 510 /* turn on */ 511 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); 512 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 513 | UVD_SUVD_CGC_GATE__SIT_MASK 514 | UVD_SUVD_CGC_GATE__SMP_MASK 515 | UVD_SUVD_CGC_GATE__SCM_MASK 516 | UVD_SUVD_CGC_GATE__SDB_MASK 517 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 518 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 519 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 520 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 521 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 522 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 523 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 524 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 525 | UVD_SUVD_CGC_GATE__SCLR_MASK 526 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 527 | UVD_SUVD_CGC_GATE__ENT_MASK 528 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 529 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 530 | UVD_SUVD_CGC_GATE__SITE_MASK 531 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 532 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 533 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 534 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 535 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 536 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data); 537 538 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); 539 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 540 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 541 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 542 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 543 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 544 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 545 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 546 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 547 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 548 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 549 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); 550 } 551 552 /** 553 * vcn_v1_0_enable_clock_gating - enable VCN clock gating 554 * 555 * @adev: amdgpu_device pointer 556 * 557 * Enable clock gating for VCN block 558 */ 559 static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev) 560 { 561 uint32_t data = 0; 562 563 /* enable JPEG CGC */ 564 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); 565 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 566 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 567 else 568 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 569 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 570 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 571 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data); 572 573 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); 574 data |= (JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK); 575 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data); 576 577 /* enable UVD CGC */ 578 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 579 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 580 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 581 else 582 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 583 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 584 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 585 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 586 587 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 588 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 589 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 590 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 591 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 592 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 593 | UVD_CGC_CTRL__SYS_MODE_MASK 594 | UVD_CGC_CTRL__UDEC_MODE_MASK 595 | UVD_CGC_CTRL__MPEG2_MODE_MASK 596 | UVD_CGC_CTRL__REGS_MODE_MASK 597 | UVD_CGC_CTRL__RBC_MODE_MASK 598 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 599 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 600 | UVD_CGC_CTRL__IDCT_MODE_MASK 601 | UVD_CGC_CTRL__MPRD_MODE_MASK 602 | UVD_CGC_CTRL__MPC_MODE_MASK 603 | UVD_CGC_CTRL__LBSI_MODE_MASK 604 | UVD_CGC_CTRL__LRBBM_MODE_MASK 605 | UVD_CGC_CTRL__WCB_MODE_MASK 606 | UVD_CGC_CTRL__VCPU_MODE_MASK 607 | UVD_CGC_CTRL__SCPU_MODE_MASK); 608 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 609 610 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); 611 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 612 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 613 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 614 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 615 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 616 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 617 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 618 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 619 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 620 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 621 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); 622 } 623 624 static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel) 625 { 626 uint32_t reg_data = 0; 627 628 /* disable JPEG CGC */ 629 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 630 reg_data = 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 631 else 632 reg_data = 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 633 reg_data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 634 reg_data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 635 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); 636 637 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_GATE, 0, 0xFFFFFFFF, sram_sel); 638 639 /* enable sw clock gating control */ 640 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 641 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 642 else 643 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 644 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 645 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 646 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 647 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 648 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 649 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 650 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 651 UVD_CGC_CTRL__SYS_MODE_MASK | 652 UVD_CGC_CTRL__UDEC_MODE_MASK | 653 UVD_CGC_CTRL__MPEG2_MODE_MASK | 654 UVD_CGC_CTRL__REGS_MODE_MASK | 655 UVD_CGC_CTRL__RBC_MODE_MASK | 656 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 657 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 658 UVD_CGC_CTRL__IDCT_MODE_MASK | 659 UVD_CGC_CTRL__MPRD_MODE_MASK | 660 UVD_CGC_CTRL__MPC_MODE_MASK | 661 UVD_CGC_CTRL__LBSI_MODE_MASK | 662 UVD_CGC_CTRL__LRBBM_MODE_MASK | 663 UVD_CGC_CTRL__WCB_MODE_MASK | 664 UVD_CGC_CTRL__VCPU_MODE_MASK | 665 UVD_CGC_CTRL__SCPU_MODE_MASK); 666 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); 667 668 /* turn off clock gating */ 669 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, sram_sel); 670 671 /* turn on SUVD clock gating */ 672 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_GATE, 1, 0xFFFFFFFF, sram_sel); 673 674 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 675 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel); 676 } 677 678 static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev) 679 { 680 uint32_t data = 0; 681 682 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 683 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 684 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 685 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 686 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 687 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 688 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 689 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 690 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 691 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 692 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 693 | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); 694 695 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 696 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF); 697 } else { 698 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 699 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 700 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 701 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 702 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 703 | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 704 | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 705 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 706 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 707 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 708 | 1 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); 709 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 710 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFFFFF); 711 } 712 713 /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS , UVDU_PWR_STATUS are 0 (power on) */ 714 715 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); 716 data &= ~0x103; 717 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 718 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | UVD_POWER_STATUS__UVD_PG_EN_MASK; 719 720 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); 721 } 722 723 static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev) 724 { 725 uint32_t data = 0; 726 727 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 728 /* Before power off, this indicator has to be turned on */ 729 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); 730 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 731 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 732 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); 733 734 735 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 736 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 737 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 738 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 739 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 740 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 741 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 742 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 743 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 744 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 745 | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); 746 747 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 748 749 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 750 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 751 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 752 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 753 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 754 | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT 755 | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT 756 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 757 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 758 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 759 | 2 << UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT); 760 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF); 761 } 762 } 763 764 /** 765 * vcn_v1_0_start_spg_mode - start VCN block 766 * 767 * @adev: amdgpu_device pointer 768 * 769 * Setup and start the VCN block 770 */ 771 static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev) 772 { 773 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 774 uint32_t rb_bufsz, tmp; 775 uint32_t lmi_swap_cntl; 776 int i, j, r; 777 778 /* disable byte swapping */ 779 lmi_swap_cntl = 0; 780 781 vcn_1_0_disable_static_power_gating(adev); 782 783 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 784 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); 785 786 /* disable clock gating */ 787 vcn_v1_0_disable_clock_gating(adev); 788 789 /* disable interupt */ 790 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, 791 ~UVD_MASTINT_EN__VCPU_EN_MASK); 792 793 /* initialize VCN memory controller */ 794 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL); 795 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp | 796 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 797 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 798 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 799 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 800 801 #ifdef __BIG_ENDIAN 802 /* swap (8 in 32) RB and IB */ 803 lmi_swap_cntl = 0xa; 804 #endif 805 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 806 807 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL); 808 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 809 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 810 WREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL, tmp); 811 812 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, 813 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 814 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 815 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 816 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 817 818 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, 819 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 820 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 821 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 822 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 823 824 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, 825 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 826 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 827 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 828 829 vcn_v1_0_mc_resume_spg_mode(adev); 830 831 WREG32_SOC15(UVD, 0, mmUVD_REG_XX_MASK_1_0, 0x10); 832 WREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0, 833 RREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0) | 0x3); 834 835 /* enable VCPU clock */ 836 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK); 837 838 /* boot up the VCPU */ 839 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 840 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 841 842 /* enable UMC */ 843 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, 844 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 845 846 tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET); 847 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 848 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 849 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, tmp); 850 851 for (i = 0; i < 10; ++i) { 852 uint32_t status; 853 854 for (j = 0; j < 100; ++j) { 855 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); 856 if (status & UVD_STATUS__IDLE) 857 break; 858 mdelay(10); 859 } 860 r = 0; 861 if (status & UVD_STATUS__IDLE) 862 break; 863 864 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n"); 865 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 866 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 867 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 868 mdelay(10); 869 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 870 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 871 mdelay(10); 872 r = -1; 873 } 874 875 if (r) { 876 DRM_ERROR("VCN decode not responding, giving up!!!\n"); 877 return r; 878 } 879 /* enable master interrupt */ 880 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 881 UVD_MASTINT_EN__VCPU_EN_MASK, ~UVD_MASTINT_EN__VCPU_EN_MASK); 882 883 /* enable system interrupt for JRBC, TODO: move to set interrupt*/ 884 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN), 885 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 886 ~UVD_SYS_INT_EN__UVD_JRBC_EN_MASK); 887 888 /* clear the busy bit of UVD_STATUS */ 889 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY; 890 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); 891 892 /* force RBC into idle state */ 893 rb_bufsz = order_base_2(ring->ring_size); 894 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 895 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 896 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 897 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 898 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 899 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 900 901 /* set the write pointer delay */ 902 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); 903 904 /* set the wb address */ 905 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, 906 (upper_32_bits(ring->gpu_addr) >> 2)); 907 908 /* program the RB_BASE for ring buffer */ 909 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 910 lower_32_bits(ring->gpu_addr)); 911 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 912 upper_32_bits(ring->gpu_addr)); 913 914 /* Initialize the ring buffer's read and write pointers */ 915 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); 916 917 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); 918 919 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 920 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 921 lower_32_bits(ring->wptr)); 922 923 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, 924 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 925 926 ring = &adev->vcn.inst->ring_enc[0]; 927 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 928 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 929 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); 930 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 931 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 932 933 ring = &adev->vcn.inst->ring_enc[1]; 934 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 935 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 936 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 937 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 938 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); 939 940 jpeg_v1_0_start(adev, 0); 941 942 return 0; 943 } 944 945 static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev) 946 { 947 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 948 uint32_t rb_bufsz, tmp; 949 uint32_t lmi_swap_cntl; 950 951 /* disable byte swapping */ 952 lmi_swap_cntl = 0; 953 954 vcn_1_0_enable_static_power_gating(adev); 955 956 /* enable dynamic power gating mode */ 957 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); 958 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 959 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 960 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp); 961 962 /* enable clock gating */ 963 vcn_v1_0_clock_gating_dpg_mode(adev, 0); 964 965 /* enable VCPU clock */ 966 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 967 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 968 tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK; 969 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CNTL, tmp, 0xFFFFFFFF, 0); 970 971 /* disable interupt */ 972 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN, 973 0, UVD_MASTINT_EN__VCPU_EN_MASK, 0); 974 975 /* initialize VCN memory controller */ 976 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL, 977 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 978 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 979 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 980 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 981 UVD_LMI_CTRL__REQ_MODE_MASK | 982 UVD_LMI_CTRL__CRC_RESET_MASK | 983 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 984 0x00100000L, 0xFFFFFFFF, 0); 985 986 #ifdef __BIG_ENDIAN 987 /* swap (8 in 32) RB and IB */ 988 lmi_swap_cntl = 0xa; 989 #endif 990 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl, 0xFFFFFFFF, 0); 991 992 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_CNTL, 993 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0xFFFFFFFF, 0); 994 995 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUXA0, 996 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 997 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 998 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 999 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0xFFFFFFFF, 0); 1000 1001 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUXB0, 1002 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1003 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1004 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1005 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0xFFFFFFFF, 0); 1006 1007 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUX, 1008 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1009 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1010 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0xFFFFFFFF, 0); 1011 1012 vcn_v1_0_mc_resume_dpg_mode(adev); 1013 1014 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0xFFFFFFFF, 0); 1015 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0xFFFFFFFF, 0); 1016 1017 /* boot up the VCPU */ 1018 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0); 1019 1020 /* enable UMC */ 1021 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL2, 1022 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 1023 0xFFFFFFFF, 0); 1024 1025 /* enable master interrupt */ 1026 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN, 1027 UVD_MASTINT_EN__VCPU_EN_MASK, UVD_MASTINT_EN__VCPU_EN_MASK, 0); 1028 1029 vcn_v1_0_clock_gating_dpg_mode(adev, 1); 1030 /* setup mmUVD_LMI_CTRL */ 1031 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL, 1032 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 1033 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1034 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1035 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 1036 UVD_LMI_CTRL__REQ_MODE_MASK | 1037 UVD_LMI_CTRL__CRC_RESET_MASK | 1038 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1039 0x00100000L, 0xFFFFFFFF, 1); 1040 1041 tmp = adev->gfx.config.gb_addr_config; 1042 /* setup VCN global tiling registers */ 1043 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1); 1044 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1); 1045 1046 /* enable System Interrupt for JRBC */ 1047 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SYS_INT_EN, 1048 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 0xFFFFFFFF, 1); 1049 1050 /* force RBC into idle state */ 1051 rb_bufsz = order_base_2(ring->ring_size); 1052 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1053 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1054 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1055 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1056 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1057 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 1058 1059 /* set the write pointer delay */ 1060 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); 1061 1062 /* set the wb address */ 1063 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, 1064 (upper_32_bits(ring->gpu_addr) >> 2)); 1065 1066 /* program the RB_BASE for ring buffer */ 1067 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1068 lower_32_bits(ring->gpu_addr)); 1069 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1070 upper_32_bits(ring->gpu_addr)); 1071 1072 /* Initialize the ring buffer's read and write pointers */ 1073 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); 1074 1075 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); 1076 1077 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 1078 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1079 lower_32_bits(ring->wptr)); 1080 1081 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, 1082 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 1083 1084 jpeg_v1_0_start(adev, 1); 1085 1086 return 0; 1087 } 1088 1089 static int vcn_v1_0_start(struct amdgpu_device *adev) 1090 { 1091 int r; 1092 1093 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1094 r = vcn_v1_0_start_dpg_mode(adev); 1095 else 1096 r = vcn_v1_0_start_spg_mode(adev); 1097 return r; 1098 } 1099 1100 /** 1101 * vcn_v1_0_stop_spg_mode - stop VCN block 1102 * 1103 * @adev: amdgpu_device pointer 1104 * 1105 * stop the VCN block 1106 */ 1107 static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev) 1108 { 1109 int tmp; 1110 1111 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1112 1113 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1114 UVD_LMI_STATUS__READ_CLEAN_MASK | 1115 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1116 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1117 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp); 1118 1119 /* stall UMC channel */ 1120 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 1121 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 1122 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1123 1124 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1125 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1126 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp); 1127 1128 /* disable VCPU clock */ 1129 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0, 1130 ~UVD_VCPU_CNTL__CLK_EN_MASK); 1131 1132 /* reset LMI UMC/LMI */ 1133 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1134 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK, 1135 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 1136 1137 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1138 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK, 1139 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); 1140 1141 /* put VCPU into reset */ 1142 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1143 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 1144 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1145 1146 WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0); 1147 1148 vcn_v1_0_enable_clock_gating(adev); 1149 vcn_1_0_enable_static_power_gating(adev); 1150 return 0; 1151 } 1152 1153 static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev) 1154 { 1155 uint32_t tmp; 1156 1157 /* Wait for power status to be UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF */ 1158 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1159 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1160 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1161 1162 /* wait for read ptr to be equal to write ptr */ 1163 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); 1164 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1165 1166 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); 1167 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); 1168 1169 tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); 1170 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF); 1171 1172 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1173 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); 1174 1175 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1176 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1177 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1178 1179 /* disable dynamic power gating mode */ 1180 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0, 1181 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1182 1183 return 0; 1184 } 1185 1186 static int vcn_v1_0_stop(struct amdgpu_device *adev) 1187 { 1188 int r; 1189 1190 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1191 r = vcn_v1_0_stop_dpg_mode(adev); 1192 else 1193 r = vcn_v1_0_stop_spg_mode(adev); 1194 1195 return r; 1196 } 1197 1198 static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev, 1199 int inst_idx, struct dpg_pause_state *new_state) 1200 { 1201 int ret_code; 1202 uint32_t reg_data = 0; 1203 uint32_t reg_data2 = 0; 1204 struct amdgpu_ring *ring; 1205 1206 /* pause/unpause if state is changed */ 1207 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1208 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d", 1209 adev->vcn.inst[inst_idx].pause_state.fw_based, 1210 adev->vcn.inst[inst_idx].pause_state.jpeg, 1211 new_state->fw_based, new_state->jpeg); 1212 1213 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & 1214 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1215 1216 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1217 ret_code = 0; 1218 1219 if (!(reg_data & UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK)) 1220 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1221 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1222 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1223 1224 if (!ret_code) { 1225 /* pause DPG non-jpeg */ 1226 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1227 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1228 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, 1229 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1230 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1231 1232 /* Restore */ 1233 ring = &adev->vcn.inst->ring_enc[0]; 1234 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); 1235 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1236 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 1237 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1238 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1239 1240 ring = &adev->vcn.inst->ring_enc[1]; 1241 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1242 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1243 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); 1244 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1245 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1246 1247 ring = &adev->vcn.inst->ring_dec; 1248 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1249 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); 1250 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1251 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, 1252 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1253 } 1254 } else { 1255 /* unpause dpg non-jpeg, no need to wait */ 1256 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1257 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1258 } 1259 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1260 } 1261 1262 /* pause/unpause if state is changed */ 1263 if (adev->vcn.inst[inst_idx].pause_state.jpeg != new_state->jpeg) { 1264 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d", 1265 adev->vcn.inst[inst_idx].pause_state.fw_based, 1266 adev->vcn.inst[inst_idx].pause_state.jpeg, 1267 new_state->fw_based, new_state->jpeg); 1268 1269 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & 1270 (~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK); 1271 1272 if (new_state->jpeg == VCN_DPG_STATE__PAUSE) { 1273 ret_code = 0; 1274 1275 if (!(reg_data & UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK)) 1276 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1277 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1278 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1279 1280 if (!ret_code) { 1281 /* Make sure JPRG Snoop is disabled before sending the pause */ 1282 reg_data2 = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); 1283 reg_data2 |= UVD_POWER_STATUS__JRBC_SNOOP_DIS_MASK; 1284 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data2); 1285 1286 /* pause DPG jpeg */ 1287 reg_data |= UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK; 1288 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1289 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, 1290 UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK, 1291 UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK); 1292 1293 /* Restore */ 1294 ring = &adev->jpeg.inst->ring_dec; 1295 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0); 1296 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 1297 UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK | 1298 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); 1299 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 1300 lower_32_bits(ring->gpu_addr)); 1301 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 1302 upper_32_bits(ring->gpu_addr)); 1303 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr); 1304 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr); 1305 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 1306 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); 1307 1308 ring = &adev->vcn.inst->ring_dec; 1309 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1310 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); 1311 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1312 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, 1313 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1314 } 1315 } else { 1316 /* unpause dpg jpeg, no need to wait */ 1317 reg_data &= ~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK; 1318 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1319 } 1320 adev->vcn.inst[inst_idx].pause_state.jpeg = new_state->jpeg; 1321 } 1322 1323 return 0; 1324 } 1325 1326 static bool vcn_v1_0_is_idle(void *handle) 1327 { 1328 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1329 1330 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); 1331 } 1332 1333 static int vcn_v1_0_wait_for_idle(void *handle) 1334 { 1335 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1336 int ret; 1337 1338 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 1339 UVD_STATUS__IDLE); 1340 1341 return ret; 1342 } 1343 1344 static int vcn_v1_0_set_clockgating_state(void *handle, 1345 enum amd_clockgating_state state) 1346 { 1347 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1348 bool enable = (state == AMD_CG_STATE_GATE); 1349 1350 if (enable) { 1351 /* wait for STATUS to clear */ 1352 if (!vcn_v1_0_is_idle(handle)) 1353 return -EBUSY; 1354 vcn_v1_0_enable_clock_gating(adev); 1355 } else { 1356 /* disable HW gating and enable Sw gating */ 1357 vcn_v1_0_disable_clock_gating(adev); 1358 } 1359 return 0; 1360 } 1361 1362 /** 1363 * vcn_v1_0_dec_ring_get_rptr - get read pointer 1364 * 1365 * @ring: amdgpu_ring pointer 1366 * 1367 * Returns the current hardware read pointer 1368 */ 1369 static uint64_t vcn_v1_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 1370 { 1371 struct amdgpu_device *adev = ring->adev; 1372 1373 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 1374 } 1375 1376 /** 1377 * vcn_v1_0_dec_ring_get_wptr - get write pointer 1378 * 1379 * @ring: amdgpu_ring pointer 1380 * 1381 * Returns the current hardware write pointer 1382 */ 1383 static uint64_t vcn_v1_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 1384 { 1385 struct amdgpu_device *adev = ring->adev; 1386 1387 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR); 1388 } 1389 1390 /** 1391 * vcn_v1_0_dec_ring_set_wptr - set write pointer 1392 * 1393 * @ring: amdgpu_ring pointer 1394 * 1395 * Commits the write pointer to the hardware 1396 */ 1397 static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 1398 { 1399 struct amdgpu_device *adev = ring->adev; 1400 1401 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1402 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 1403 lower_32_bits(ring->wptr) | 0x80000000); 1404 1405 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1406 } 1407 1408 /** 1409 * vcn_v1_0_dec_ring_insert_start - insert a start command 1410 * 1411 * @ring: amdgpu_ring pointer 1412 * 1413 * Write a start command to the ring. 1414 */ 1415 static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring) 1416 { 1417 struct amdgpu_device *adev = ring->adev; 1418 1419 amdgpu_ring_write(ring, 1420 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1421 amdgpu_ring_write(ring, 0); 1422 amdgpu_ring_write(ring, 1423 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1424 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1); 1425 } 1426 1427 /** 1428 * vcn_v1_0_dec_ring_insert_end - insert a end command 1429 * 1430 * @ring: amdgpu_ring pointer 1431 * 1432 * Write a end command to the ring. 1433 */ 1434 static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring) 1435 { 1436 struct amdgpu_device *adev = ring->adev; 1437 1438 amdgpu_ring_write(ring, 1439 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1440 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1); 1441 } 1442 1443 /** 1444 * vcn_v1_0_dec_ring_emit_fence - emit an fence & trap command 1445 * 1446 * @ring: amdgpu_ring pointer 1447 * @addr: address 1448 * @seq: sequence number 1449 * @flags: fence related flags 1450 * 1451 * Write a fence and a trap command to the ring. 1452 */ 1453 static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 1454 unsigned flags) 1455 { 1456 struct amdgpu_device *adev = ring->adev; 1457 1458 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1459 1460 amdgpu_ring_write(ring, 1461 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0)); 1462 amdgpu_ring_write(ring, seq); 1463 amdgpu_ring_write(ring, 1464 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1465 amdgpu_ring_write(ring, addr & 0xffffffff); 1466 amdgpu_ring_write(ring, 1467 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1468 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 1469 amdgpu_ring_write(ring, 1470 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1471 amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1); 1472 1473 amdgpu_ring_write(ring, 1474 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1475 amdgpu_ring_write(ring, 0); 1476 amdgpu_ring_write(ring, 1477 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1478 amdgpu_ring_write(ring, 0); 1479 amdgpu_ring_write(ring, 1480 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1481 amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1); 1482 } 1483 1484 /** 1485 * vcn_v1_0_dec_ring_emit_ib - execute indirect buffer 1486 * 1487 * @ring: amdgpu_ring pointer 1488 * @job: job to retrieve vmid from 1489 * @ib: indirect buffer to execute 1490 * @flags: unused 1491 * 1492 * Write ring commands to execute the indirect buffer 1493 */ 1494 static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring, 1495 struct amdgpu_job *job, 1496 struct amdgpu_ib *ib, 1497 uint32_t flags) 1498 { 1499 struct amdgpu_device *adev = ring->adev; 1500 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1501 1502 amdgpu_ring_write(ring, 1503 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0)); 1504 amdgpu_ring_write(ring, vmid); 1505 1506 amdgpu_ring_write(ring, 1507 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0)); 1508 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1509 amdgpu_ring_write(ring, 1510 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0)); 1511 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1512 amdgpu_ring_write(ring, 1513 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0)); 1514 amdgpu_ring_write(ring, ib->length_dw); 1515 } 1516 1517 static void vcn_v1_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, 1518 uint32_t reg, uint32_t val, 1519 uint32_t mask) 1520 { 1521 struct amdgpu_device *adev = ring->adev; 1522 1523 amdgpu_ring_write(ring, 1524 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1525 amdgpu_ring_write(ring, reg << 2); 1526 amdgpu_ring_write(ring, 1527 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1528 amdgpu_ring_write(ring, val); 1529 amdgpu_ring_write(ring, 1530 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0)); 1531 amdgpu_ring_write(ring, mask); 1532 amdgpu_ring_write(ring, 1533 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1534 amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1); 1535 } 1536 1537 static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, 1538 unsigned vmid, uint64_t pd_addr) 1539 { 1540 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1541 uint32_t data0, data1, mask; 1542 1543 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1544 1545 /* wait for register write */ 1546 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance; 1547 data1 = lower_32_bits(pd_addr); 1548 mask = 0xffffffff; 1549 vcn_v1_0_dec_ring_emit_reg_wait(ring, data0, data1, mask); 1550 } 1551 1552 static void vcn_v1_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, 1553 uint32_t reg, uint32_t val) 1554 { 1555 struct amdgpu_device *adev = ring->adev; 1556 1557 amdgpu_ring_write(ring, 1558 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1559 amdgpu_ring_write(ring, reg << 2); 1560 amdgpu_ring_write(ring, 1561 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1562 amdgpu_ring_write(ring, val); 1563 amdgpu_ring_write(ring, 1564 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1565 amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1); 1566 } 1567 1568 /** 1569 * vcn_v1_0_enc_ring_get_rptr - get enc read pointer 1570 * 1571 * @ring: amdgpu_ring pointer 1572 * 1573 * Returns the current hardware enc read pointer 1574 */ 1575 static uint64_t vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 1576 { 1577 struct amdgpu_device *adev = ring->adev; 1578 1579 if (ring == &adev->vcn.inst->ring_enc[0]) 1580 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR); 1581 else 1582 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2); 1583 } 1584 1585 /** 1586 * vcn_v1_0_enc_ring_get_wptr - get enc write pointer 1587 * 1588 * @ring: amdgpu_ring pointer 1589 * 1590 * Returns the current hardware enc write pointer 1591 */ 1592 static uint64_t vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 1593 { 1594 struct amdgpu_device *adev = ring->adev; 1595 1596 if (ring == &adev->vcn.inst->ring_enc[0]) 1597 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); 1598 else 1599 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); 1600 } 1601 1602 /** 1603 * vcn_v1_0_enc_ring_set_wptr - set enc write pointer 1604 * 1605 * @ring: amdgpu_ring pointer 1606 * 1607 * Commits the enc write pointer to the hardware 1608 */ 1609 static void vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 1610 { 1611 struct amdgpu_device *adev = ring->adev; 1612 1613 if (ring == &adev->vcn.inst->ring_enc[0]) 1614 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, 1615 lower_32_bits(ring->wptr)); 1616 else 1617 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, 1618 lower_32_bits(ring->wptr)); 1619 } 1620 1621 /** 1622 * vcn_v1_0_enc_ring_emit_fence - emit an enc fence & trap command 1623 * 1624 * @ring: amdgpu_ring pointer 1625 * @addr: address 1626 * @seq: sequence number 1627 * @flags: fence related flags 1628 * 1629 * Write enc a fence and a trap command to the ring. 1630 */ 1631 static void vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1632 u64 seq, unsigned flags) 1633 { 1634 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1635 1636 amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE); 1637 amdgpu_ring_write(ring, addr); 1638 amdgpu_ring_write(ring, upper_32_bits(addr)); 1639 amdgpu_ring_write(ring, seq); 1640 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP); 1641 } 1642 1643 static void vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring *ring) 1644 { 1645 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 1646 } 1647 1648 /** 1649 * vcn_v1_0_enc_ring_emit_ib - enc execute indirect buffer 1650 * 1651 * @ring: amdgpu_ring pointer 1652 * @job: job to retrive vmid from 1653 * @ib: indirect buffer to execute 1654 * @flags: unused 1655 * 1656 * Write enc ring commands to execute the indirect buffer 1657 */ 1658 static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring, 1659 struct amdgpu_job *job, 1660 struct amdgpu_ib *ib, 1661 uint32_t flags) 1662 { 1663 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1664 1665 amdgpu_ring_write(ring, VCN_ENC_CMD_IB); 1666 amdgpu_ring_write(ring, vmid); 1667 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1668 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1669 amdgpu_ring_write(ring, ib->length_dw); 1670 } 1671 1672 static void vcn_v1_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, 1673 uint32_t reg, uint32_t val, 1674 uint32_t mask) 1675 { 1676 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); 1677 amdgpu_ring_write(ring, reg << 2); 1678 amdgpu_ring_write(ring, mask); 1679 amdgpu_ring_write(ring, val); 1680 } 1681 1682 static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1683 unsigned int vmid, uint64_t pd_addr) 1684 { 1685 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1686 1687 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1688 1689 /* wait for reg writes */ 1690 vcn_v1_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + 1691 vmid * hub->ctx_addr_distance, 1692 lower_32_bits(pd_addr), 0xffffffff); 1693 } 1694 1695 static void vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, 1696 uint32_t reg, uint32_t val) 1697 { 1698 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); 1699 amdgpu_ring_write(ring, reg << 2); 1700 amdgpu_ring_write(ring, val); 1701 } 1702 1703 static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev, 1704 struct amdgpu_irq_src *source, 1705 unsigned type, 1706 enum amdgpu_interrupt_state state) 1707 { 1708 return 0; 1709 } 1710 1711 static int vcn_v1_0_process_interrupt(struct amdgpu_device *adev, 1712 struct amdgpu_irq_src *source, 1713 struct amdgpu_iv_entry *entry) 1714 { 1715 DRM_DEBUG("IH: VCN TRAP\n"); 1716 1717 switch (entry->src_id) { 1718 case 124: 1719 amdgpu_fence_process(&adev->vcn.inst->ring_dec); 1720 break; 1721 case 119: 1722 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]); 1723 break; 1724 case 120: 1725 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]); 1726 break; 1727 default: 1728 DRM_ERROR("Unhandled interrupt: %d %d\n", 1729 entry->src_id, entry->src_data[0]); 1730 break; 1731 } 1732 1733 return 0; 1734 } 1735 1736 static void vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 1737 { 1738 struct amdgpu_device *adev = ring->adev; 1739 int i; 1740 1741 WARN_ON(ring->wptr % 2 || count % 2); 1742 1743 for (i = 0; i < count / 2; i++) { 1744 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0)); 1745 amdgpu_ring_write(ring, 0); 1746 } 1747 } 1748 1749 static int vcn_v1_0_set_powergating_state(void *handle, 1750 enum amd_powergating_state state) 1751 { 1752 /* This doesn't actually powergate the VCN block. 1753 * That's done in the dpm code via the SMC. This 1754 * just re-inits the block as necessary. The actual 1755 * gating still happens in the dpm code. We should 1756 * revisit this when there is a cleaner line between 1757 * the smc and the hw blocks 1758 */ 1759 int ret; 1760 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1761 1762 if(state == adev->vcn.cur_state) 1763 return 0; 1764 1765 if (state == AMD_PG_STATE_GATE) 1766 ret = vcn_v1_0_stop(adev); 1767 else 1768 ret = vcn_v1_0_start(adev); 1769 1770 if(!ret) 1771 adev->vcn.cur_state = state; 1772 return ret; 1773 } 1774 1775 static void vcn_v1_0_idle_work_handler(struct work_struct *work) 1776 { 1777 struct amdgpu_device *adev = 1778 container_of(work, struct amdgpu_device, vcn.idle_work.work); 1779 unsigned int fences = 0, i; 1780 1781 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 1782 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_enc[i]); 1783 1784 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1785 struct dpg_pause_state new_state; 1786 1787 if (fences) 1788 new_state.fw_based = VCN_DPG_STATE__PAUSE; 1789 else 1790 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 1791 1792 if (amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec)) 1793 new_state.jpeg = VCN_DPG_STATE__PAUSE; 1794 else 1795 new_state.jpeg = VCN_DPG_STATE__UNPAUSE; 1796 1797 adev->vcn.pause_dpg_mode(adev, 0, &new_state); 1798 } 1799 1800 fences += amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec); 1801 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_dec); 1802 1803 if (fences == 0) { 1804 amdgpu_gfx_off_ctrl(adev, true); 1805 if (adev->pm.dpm_enabled) 1806 amdgpu_dpm_enable_uvd(adev, false); 1807 else 1808 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 1809 AMD_PG_STATE_GATE); 1810 } else { 1811 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 1812 } 1813 } 1814 1815 static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring) 1816 { 1817 struct amdgpu_device *adev = ring->adev; 1818 bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work); 1819 1820 mutex_lock(&adev->vcn.vcn1_jpeg1_workaround); 1821 1822 if (amdgpu_fence_wait_empty(&ring->adev->jpeg.inst->ring_dec)) 1823 DRM_ERROR("VCN dec: jpeg dec ring may not be empty\n"); 1824 1825 vcn_v1_0_set_pg_for_begin_use(ring, set_clocks); 1826 1827 } 1828 1829 void vcn_v1_0_set_pg_for_begin_use(struct amdgpu_ring *ring, bool set_clocks) 1830 { 1831 struct amdgpu_device *adev = ring->adev; 1832 1833 if (set_clocks) { 1834 amdgpu_gfx_off_ctrl(adev, false); 1835 if (adev->pm.dpm_enabled) 1836 amdgpu_dpm_enable_uvd(adev, true); 1837 else 1838 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 1839 AMD_PG_STATE_UNGATE); 1840 } 1841 1842 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1843 struct dpg_pause_state new_state; 1844 unsigned int fences = 0, i; 1845 1846 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 1847 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_enc[i]); 1848 1849 if (fences) 1850 new_state.fw_based = VCN_DPG_STATE__PAUSE; 1851 else 1852 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 1853 1854 if (amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec)) 1855 new_state.jpeg = VCN_DPG_STATE__PAUSE; 1856 else 1857 new_state.jpeg = VCN_DPG_STATE__UNPAUSE; 1858 1859 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) 1860 new_state.fw_based = VCN_DPG_STATE__PAUSE; 1861 else if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG) 1862 new_state.jpeg = VCN_DPG_STATE__PAUSE; 1863 1864 adev->vcn.pause_dpg_mode(adev, 0, &new_state); 1865 } 1866 } 1867 1868 void vcn_v1_0_ring_end_use(struct amdgpu_ring *ring) 1869 { 1870 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 1871 mutex_unlock(&ring->adev->vcn.vcn1_jpeg1_workaround); 1872 } 1873 1874 static const struct amd_ip_funcs vcn_v1_0_ip_funcs = { 1875 .name = "vcn_v1_0", 1876 .early_init = vcn_v1_0_early_init, 1877 .late_init = NULL, 1878 .sw_init = vcn_v1_0_sw_init, 1879 .sw_fini = vcn_v1_0_sw_fini, 1880 .hw_init = vcn_v1_0_hw_init, 1881 .hw_fini = vcn_v1_0_hw_fini, 1882 .suspend = vcn_v1_0_suspend, 1883 .resume = vcn_v1_0_resume, 1884 .is_idle = vcn_v1_0_is_idle, 1885 .wait_for_idle = vcn_v1_0_wait_for_idle, 1886 .check_soft_reset = NULL /* vcn_v1_0_check_soft_reset */, 1887 .pre_soft_reset = NULL /* vcn_v1_0_pre_soft_reset */, 1888 .soft_reset = NULL /* vcn_v1_0_soft_reset */, 1889 .post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */, 1890 .set_clockgating_state = vcn_v1_0_set_clockgating_state, 1891 .set_powergating_state = vcn_v1_0_set_powergating_state, 1892 }; 1893 1894 static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = { 1895 .type = AMDGPU_RING_TYPE_VCN_DEC, 1896 .align_mask = 0xf, 1897 .support_64bit_ptrs = false, 1898 .no_user_fence = true, 1899 .vmhub = AMDGPU_MMHUB_0, 1900 .get_rptr = vcn_v1_0_dec_ring_get_rptr, 1901 .get_wptr = vcn_v1_0_dec_ring_get_wptr, 1902 .set_wptr = vcn_v1_0_dec_ring_set_wptr, 1903 .emit_frame_size = 1904 6 + 6 + /* hdp invalidate / flush */ 1905 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1906 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1907 8 + /* vcn_v1_0_dec_ring_emit_vm_flush */ 1908 14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */ 1909 6, 1910 .emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */ 1911 .emit_ib = vcn_v1_0_dec_ring_emit_ib, 1912 .emit_fence = vcn_v1_0_dec_ring_emit_fence, 1913 .emit_vm_flush = vcn_v1_0_dec_ring_emit_vm_flush, 1914 .test_ring = amdgpu_vcn_dec_ring_test_ring, 1915 .test_ib = amdgpu_vcn_dec_ring_test_ib, 1916 .insert_nop = vcn_v1_0_dec_ring_insert_nop, 1917 .insert_start = vcn_v1_0_dec_ring_insert_start, 1918 .insert_end = vcn_v1_0_dec_ring_insert_end, 1919 .pad_ib = amdgpu_ring_generic_pad_ib, 1920 .begin_use = vcn_v1_0_ring_begin_use, 1921 .end_use = vcn_v1_0_ring_end_use, 1922 .emit_wreg = vcn_v1_0_dec_ring_emit_wreg, 1923 .emit_reg_wait = vcn_v1_0_dec_ring_emit_reg_wait, 1924 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1925 }; 1926 1927 static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = { 1928 .type = AMDGPU_RING_TYPE_VCN_ENC, 1929 .align_mask = 0x3f, 1930 .nop = VCN_ENC_CMD_NO_OP, 1931 .support_64bit_ptrs = false, 1932 .no_user_fence = true, 1933 .vmhub = AMDGPU_MMHUB_0, 1934 .get_rptr = vcn_v1_0_enc_ring_get_rptr, 1935 .get_wptr = vcn_v1_0_enc_ring_get_wptr, 1936 .set_wptr = vcn_v1_0_enc_ring_set_wptr, 1937 .emit_frame_size = 1938 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1939 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1940 4 + /* vcn_v1_0_enc_ring_emit_vm_flush */ 1941 5 + 5 + /* vcn_v1_0_enc_ring_emit_fence x2 vm fence */ 1942 1, /* vcn_v1_0_enc_ring_insert_end */ 1943 .emit_ib_size = 5, /* vcn_v1_0_enc_ring_emit_ib */ 1944 .emit_ib = vcn_v1_0_enc_ring_emit_ib, 1945 .emit_fence = vcn_v1_0_enc_ring_emit_fence, 1946 .emit_vm_flush = vcn_v1_0_enc_ring_emit_vm_flush, 1947 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1948 .test_ib = amdgpu_vcn_enc_ring_test_ib, 1949 .insert_nop = amdgpu_ring_insert_nop, 1950 .insert_end = vcn_v1_0_enc_ring_insert_end, 1951 .pad_ib = amdgpu_ring_generic_pad_ib, 1952 .begin_use = vcn_v1_0_ring_begin_use, 1953 .end_use = vcn_v1_0_ring_end_use, 1954 .emit_wreg = vcn_v1_0_enc_ring_emit_wreg, 1955 .emit_reg_wait = vcn_v1_0_enc_ring_emit_reg_wait, 1956 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1957 }; 1958 1959 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev) 1960 { 1961 adev->vcn.inst->ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs; 1962 DRM_INFO("VCN decode is enabled in VM mode\n"); 1963 } 1964 1965 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev) 1966 { 1967 int i; 1968 1969 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 1970 adev->vcn.inst->ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs; 1971 1972 DRM_INFO("VCN encode is enabled in VM mode\n"); 1973 } 1974 1975 static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = { 1976 .set = vcn_v1_0_set_interrupt_state, 1977 .process = vcn_v1_0_process_interrupt, 1978 }; 1979 1980 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev) 1981 { 1982 adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 2; 1983 adev->vcn.inst->irq.funcs = &vcn_v1_0_irq_funcs; 1984 } 1985 1986 const struct amdgpu_ip_block_version vcn_v1_0_ip_block = 1987 { 1988 .type = AMD_IP_BLOCK_TYPE_VCN, 1989 .major = 1, 1990 .minor = 0, 1991 .rev = 0, 1992 .funcs = &vcn_v1_0_ip_funcs, 1993 }; 1994