1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_vcn.h" 28 #include "soc15d.h" 29 #include "soc15_common.h" 30 31 #include "vega10/soc15ip.h" 32 #include "raven1/VCN/vcn_1_0_offset.h" 33 #include "raven1/VCN/vcn_1_0_sh_mask.h" 34 #include "vega10/HDP/hdp_4_0_offset.h" 35 #include "raven1/MMHUB/mmhub_9_1_offset.h" 36 #include "raven1/MMHUB/mmhub_9_1_sh_mask.h" 37 38 static int vcn_v1_0_start(struct amdgpu_device *adev); 39 static int vcn_v1_0_stop(struct amdgpu_device *adev); 40 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev); 41 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev); 42 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev); 43 44 /** 45 * vcn_v1_0_early_init - set function pointers 46 * 47 * @handle: amdgpu_device pointer 48 * 49 * Set ring and irq function pointers 50 */ 51 static int vcn_v1_0_early_init(void *handle) 52 { 53 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 54 55 adev->vcn.num_enc_rings = 2; 56 57 vcn_v1_0_set_dec_ring_funcs(adev); 58 vcn_v1_0_set_enc_ring_funcs(adev); 59 vcn_v1_0_set_irq_funcs(adev); 60 61 return 0; 62 } 63 64 /** 65 * vcn_v1_0_sw_init - sw init for VCN block 66 * 67 * @handle: amdgpu_device pointer 68 * 69 * Load firmware and sw initialization 70 */ 71 static int vcn_v1_0_sw_init(void *handle) 72 { 73 struct amdgpu_ring *ring; 74 int i, r; 75 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 76 77 /* VCN DEC TRAP */ 78 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VCN, 124, &adev->vcn.irq); 79 if (r) 80 return r; 81 82 /* VCN ENC TRAP */ 83 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 84 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VCN, i + 119, 85 &adev->vcn.irq); 86 if (r) 87 return r; 88 } 89 90 r = amdgpu_vcn_sw_init(adev); 91 if (r) 92 return r; 93 94 r = amdgpu_vcn_resume(adev); 95 if (r) 96 return r; 97 98 ring = &adev->vcn.ring_dec; 99 sprintf(ring->name, "vcn_dec"); 100 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0); 101 if (r) 102 return r; 103 104 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 105 ring = &adev->vcn.ring_enc[i]; 106 sprintf(ring->name, "vcn_enc%d", i); 107 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0); 108 if (r) 109 return r; 110 } 111 112 return r; 113 } 114 115 /** 116 * vcn_v1_0_sw_fini - sw fini for VCN block 117 * 118 * @handle: amdgpu_device pointer 119 * 120 * VCN suspend and free up sw allocation 121 */ 122 static int vcn_v1_0_sw_fini(void *handle) 123 { 124 int r; 125 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 126 127 r = amdgpu_vcn_suspend(adev); 128 if (r) 129 return r; 130 131 r = amdgpu_vcn_sw_fini(adev); 132 133 return r; 134 } 135 136 /** 137 * vcn_v1_0_hw_init - start and test VCN block 138 * 139 * @handle: amdgpu_device pointer 140 * 141 * Initialize the hardware, boot up the VCPU and do some testing 142 */ 143 static int vcn_v1_0_hw_init(void *handle) 144 { 145 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 146 struct amdgpu_ring *ring = &adev->vcn.ring_dec; 147 int i, r; 148 149 r = vcn_v1_0_start(adev); 150 if (r) 151 goto done; 152 153 ring->ready = true; 154 r = amdgpu_ring_test_ring(ring); 155 if (r) { 156 ring->ready = false; 157 goto done; 158 } 159 160 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 161 ring = &adev->vcn.ring_enc[i]; 162 ring->ready = true; 163 r = amdgpu_ring_test_ring(ring); 164 if (r) { 165 ring->ready = false; 166 goto done; 167 } 168 } 169 170 done: 171 if (!r) 172 DRM_INFO("VCN decode and encode initialized successfully.\n"); 173 174 return r; 175 } 176 177 /** 178 * vcn_v1_0_hw_fini - stop the hardware block 179 * 180 * @handle: amdgpu_device pointer 181 * 182 * Stop the VCN block, mark ring as not ready any more 183 */ 184 static int vcn_v1_0_hw_fini(void *handle) 185 { 186 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 187 struct amdgpu_ring *ring = &adev->vcn.ring_dec; 188 int r; 189 190 r = vcn_v1_0_stop(adev); 191 if (r) 192 return r; 193 194 ring->ready = false; 195 196 return 0; 197 } 198 199 /** 200 * vcn_v1_0_suspend - suspend VCN block 201 * 202 * @handle: amdgpu_device pointer 203 * 204 * HW fini and suspend VCN block 205 */ 206 static int vcn_v1_0_suspend(void *handle) 207 { 208 int r; 209 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 210 211 r = vcn_v1_0_hw_fini(adev); 212 if (r) 213 return r; 214 215 r = amdgpu_vcn_suspend(adev); 216 217 return r; 218 } 219 220 /** 221 * vcn_v1_0_resume - resume VCN block 222 * 223 * @handle: amdgpu_device pointer 224 * 225 * Resume firmware and hw init VCN block 226 */ 227 static int vcn_v1_0_resume(void *handle) 228 { 229 int r; 230 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 231 232 r = amdgpu_vcn_resume(adev); 233 if (r) 234 return r; 235 236 r = vcn_v1_0_hw_init(adev); 237 238 return r; 239 } 240 241 /** 242 * vcn_v1_0_mc_resume - memory controller programming 243 * 244 * @adev: amdgpu_device pointer 245 * 246 * Let the VCN memory controller know it's offsets 247 */ 248 static void vcn_v1_0_mc_resume(struct amdgpu_device *adev) 249 { 250 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 251 252 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 253 lower_32_bits(adev->vcn.gpu_addr)); 254 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 255 upper_32_bits(adev->vcn.gpu_addr)); 256 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 257 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 258 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size); 259 260 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 261 lower_32_bits(adev->vcn.gpu_addr + size)); 262 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 263 upper_32_bits(adev->vcn.gpu_addr + size)); 264 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0); 265 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_HEAP_SIZE); 266 267 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 268 lower_32_bits(adev->vcn.gpu_addr + size + AMDGPU_VCN_HEAP_SIZE)); 269 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 270 upper_32_bits(adev->vcn.gpu_addr + size + AMDGPU_VCN_HEAP_SIZE)); 271 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0); 272 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE2), 273 AMDGPU_VCN_STACK_SIZE + (AMDGPU_VCN_SESSION_SIZE * 40)); 274 275 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_UDEC_ADDR_CONFIG), 276 adev->gfx.config.gb_addr_config); 277 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG), 278 adev->gfx.config.gb_addr_config); 279 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG), 280 adev->gfx.config.gb_addr_config); 281 } 282 283 /** 284 * vcn_v1_0_disable_clock_gating - disable VCN clock gating 285 * 286 * @adev: amdgpu_device pointer 287 * @sw: enable SW clock gating 288 * 289 * Disable clock gating for VCN block 290 */ 291 static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev, bool sw) 292 { 293 uint32_t data; 294 295 /* JPEG disable CGC */ 296 data = RREG32(SOC15_REG_OFFSET(VCN, 0, mmJPEG_CGC_CTRL)); 297 298 if (sw) 299 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 300 else 301 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK; 302 303 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 304 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 305 WREG32(SOC15_REG_OFFSET(VCN, 0, mmJPEG_CGC_CTRL), data); 306 307 data = RREG32(SOC15_REG_OFFSET(VCN, 0, mmJPEG_CGC_GATE)); 308 data &= ~(JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK); 309 WREG32(SOC15_REG_OFFSET(VCN, 0, mmJPEG_CGC_GATE), data); 310 311 /* UVD disable CGC */ 312 data = RREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_CGC_CTRL)); 313 if (sw) 314 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 315 else 316 data &= ~ UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 317 318 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 319 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 320 WREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_CGC_CTRL), data); 321 322 data = RREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_CGC_GATE)); 323 data &= ~(UVD_CGC_GATE__SYS_MASK 324 | UVD_CGC_GATE__UDEC_MASK 325 | UVD_CGC_GATE__MPEG2_MASK 326 | UVD_CGC_GATE__REGS_MASK 327 | UVD_CGC_GATE__RBC_MASK 328 | UVD_CGC_GATE__LMI_MC_MASK 329 | UVD_CGC_GATE__LMI_UMC_MASK 330 | UVD_CGC_GATE__IDCT_MASK 331 | UVD_CGC_GATE__MPRD_MASK 332 | UVD_CGC_GATE__MPC_MASK 333 | UVD_CGC_GATE__LBSI_MASK 334 | UVD_CGC_GATE__LRBBM_MASK 335 | UVD_CGC_GATE__UDEC_RE_MASK 336 | UVD_CGC_GATE__UDEC_CM_MASK 337 | UVD_CGC_GATE__UDEC_IT_MASK 338 | UVD_CGC_GATE__UDEC_DB_MASK 339 | UVD_CGC_GATE__UDEC_MP_MASK 340 | UVD_CGC_GATE__WCB_MASK 341 | UVD_CGC_GATE__VCPU_MASK 342 | UVD_CGC_GATE__SCPU_MASK); 343 WREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_CGC_GATE), data); 344 345 data = RREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_CGC_CTRL)); 346 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 347 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 348 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 349 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 350 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 351 | UVD_CGC_CTRL__SYS_MODE_MASK 352 | UVD_CGC_CTRL__UDEC_MODE_MASK 353 | UVD_CGC_CTRL__MPEG2_MODE_MASK 354 | UVD_CGC_CTRL__REGS_MODE_MASK 355 | UVD_CGC_CTRL__RBC_MODE_MASK 356 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 357 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 358 | UVD_CGC_CTRL__IDCT_MODE_MASK 359 | UVD_CGC_CTRL__MPRD_MODE_MASK 360 | UVD_CGC_CTRL__MPC_MODE_MASK 361 | UVD_CGC_CTRL__LBSI_MODE_MASK 362 | UVD_CGC_CTRL__LRBBM_MODE_MASK 363 | UVD_CGC_CTRL__WCB_MODE_MASK 364 | UVD_CGC_CTRL__VCPU_MODE_MASK 365 | UVD_CGC_CTRL__SCPU_MODE_MASK); 366 WREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_CGC_CTRL), data); 367 368 /* turn on */ 369 data = RREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_SUVD_CGC_GATE)); 370 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 371 | UVD_SUVD_CGC_GATE__SIT_MASK 372 | UVD_SUVD_CGC_GATE__SMP_MASK 373 | UVD_SUVD_CGC_GATE__SCM_MASK 374 | UVD_SUVD_CGC_GATE__SDB_MASK 375 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 376 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 377 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 378 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 379 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 380 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 381 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 382 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 383 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 384 | UVD_SUVD_CGC_GATE__SCLR_MASK 385 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 386 | UVD_SUVD_CGC_GATE__ENT_MASK 387 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 388 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 389 | UVD_SUVD_CGC_GATE__SITE_MASK 390 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 391 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 392 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 393 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 394 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 395 WREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_SUVD_CGC_GATE), data); 396 397 data = RREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_SUVD_CGC_CTRL)); 398 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 399 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 400 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 401 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 402 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 403 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 404 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 405 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 406 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 407 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 408 WREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_SUVD_CGC_CTRL), data); 409 } 410 411 /** 412 * vcn_v1_0_enable_clock_gating - enable VCN clock gating 413 * 414 * @adev: amdgpu_device pointer 415 * @sw: enable SW clock gating 416 * 417 * Enable clock gating for VCN block 418 */ 419 static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev, bool sw) 420 { 421 uint32_t data = 0; 422 423 /* enable JPEG CGC */ 424 data = RREG32(SOC15_REG_OFFSET(VCN, 0, mmJPEG_CGC_CTRL)); 425 if (sw) 426 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 427 else 428 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 429 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 430 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 431 WREG32(SOC15_REG_OFFSET(VCN, 0, mmJPEG_CGC_CTRL), data); 432 433 data = RREG32(SOC15_REG_OFFSET(VCN, 0, mmJPEG_CGC_GATE)); 434 data |= (JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK); 435 WREG32(SOC15_REG_OFFSET(VCN, 0, mmJPEG_CGC_GATE), data); 436 437 /* enable UVD CGC */ 438 data = RREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_CGC_CTRL)); 439 if (sw) 440 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 441 else 442 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 443 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 444 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 445 WREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_CGC_CTRL), data); 446 447 data = RREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_CGC_CTRL)); 448 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 449 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 450 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 451 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 452 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 453 | UVD_CGC_CTRL__SYS_MODE_MASK 454 | UVD_CGC_CTRL__UDEC_MODE_MASK 455 | UVD_CGC_CTRL__MPEG2_MODE_MASK 456 | UVD_CGC_CTRL__REGS_MODE_MASK 457 | UVD_CGC_CTRL__RBC_MODE_MASK 458 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 459 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 460 | UVD_CGC_CTRL__IDCT_MODE_MASK 461 | UVD_CGC_CTRL__MPRD_MODE_MASK 462 | UVD_CGC_CTRL__MPC_MODE_MASK 463 | UVD_CGC_CTRL__LBSI_MODE_MASK 464 | UVD_CGC_CTRL__LRBBM_MODE_MASK 465 | UVD_CGC_CTRL__WCB_MODE_MASK 466 | UVD_CGC_CTRL__VCPU_MODE_MASK 467 | UVD_CGC_CTRL__SCPU_MODE_MASK); 468 WREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_CGC_CTRL), data); 469 470 data = RREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_SUVD_CGC_CTRL)); 471 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 472 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 473 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 474 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 475 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 476 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 477 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 478 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 479 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 480 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 481 WREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_SUVD_CGC_CTRL), data); 482 } 483 484 /** 485 * vcn_v1_0_start - start VCN block 486 * 487 * @adev: amdgpu_device pointer 488 * 489 * Setup and start the VCN block 490 */ 491 static int vcn_v1_0_start(struct amdgpu_device *adev) 492 { 493 struct amdgpu_ring *ring = &adev->vcn.ring_dec; 494 uint32_t rb_bufsz, tmp; 495 uint32_t lmi_swap_cntl; 496 int i, j, r; 497 498 /* disable byte swapping */ 499 lmi_swap_cntl = 0; 500 501 vcn_v1_0_mc_resume(adev); 502 503 /* disable clock gating */ 504 vcn_v1_0_disable_clock_gating(adev, true); 505 506 /* disable interupt */ 507 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, 508 ~UVD_MASTINT_EN__VCPU_EN_MASK); 509 510 /* stall UMC and register bus before resetting VCPU */ 511 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 512 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 513 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 514 mdelay(1); 515 516 /* put LMI, VCPU, RBC etc... into reset */ 517 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 518 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 519 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | 520 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 521 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | 522 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 523 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | 524 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 525 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 526 mdelay(5); 527 528 /* initialize VCN memory controller */ 529 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL), 530 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 531 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 532 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 533 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 534 UVD_LMI_CTRL__REQ_MODE_MASK | 535 0x00100000L); 536 537 #ifdef __BIG_ENDIAN 538 /* swap (8 in 32) RB and IB */ 539 lmi_swap_cntl = 0xa; 540 #endif 541 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_SWAP_CNTL), lmi_swap_cntl); 542 543 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXA0), 0x40c2040); 544 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXA1), 0x0); 545 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXB0), 0x40c2040); 546 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXB1), 0x0); 547 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_ALU), 0); 548 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUX), 0x88); 549 550 /* take all subblocks out of reset, except VCPU */ 551 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 552 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 553 mdelay(5); 554 555 /* enable VCPU clock */ 556 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 557 UVD_VCPU_CNTL__CLK_EN_MASK); 558 559 /* enable UMC */ 560 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, 561 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 562 563 /* boot up the VCPU */ 564 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0); 565 mdelay(10); 566 567 for (i = 0; i < 10; ++i) { 568 uint32_t status; 569 570 for (j = 0; j < 100; ++j) { 571 status = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS)); 572 if (status & 2) 573 break; 574 mdelay(10); 575 } 576 r = 0; 577 if (status & 2) 578 break; 579 580 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n"); 581 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 582 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 583 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 584 mdelay(10); 585 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 586 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 587 mdelay(10); 588 r = -1; 589 } 590 591 if (r) { 592 DRM_ERROR("VCN decode not responding, giving up!!!\n"); 593 return r; 594 } 595 /* enable master interrupt */ 596 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 597 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), 598 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK)); 599 600 /* clear the bit 4 of VCN_STATUS */ 601 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0, 602 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 603 604 /* force RBC into idle state */ 605 rb_bufsz = order_base_2(ring->ring_size); 606 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 607 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 608 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 609 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); 610 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 611 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 612 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), tmp); 613 614 /* set the write pointer delay */ 615 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL), 0); 616 617 /* set the wb address */ 618 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR), 619 (upper_32_bits(ring->gpu_addr) >> 2)); 620 621 /* programm the RB_BASE for ring buffer */ 622 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW), 623 lower_32_bits(ring->gpu_addr)); 624 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH), 625 upper_32_bits(ring->gpu_addr)); 626 627 /* Initialize the ring buffer's read and write pointers */ 628 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_RPTR), 0); 629 630 ring->wptr = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_RPTR)); 631 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_WPTR), 632 lower_32_bits(ring->wptr)); 633 634 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, 635 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 636 637 ring = &adev->vcn.ring_enc[0]; 638 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_RPTR), lower_32_bits(ring->wptr)); 639 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR), lower_32_bits(ring->wptr)); 640 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_LO), ring->gpu_addr); 641 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr)); 642 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_SIZE), ring->ring_size / 4); 643 644 ring = &adev->vcn.ring_enc[1]; 645 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_RPTR2), lower_32_bits(ring->wptr)); 646 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR2), lower_32_bits(ring->wptr)); 647 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_LO2), ring->gpu_addr); 648 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_HI2), upper_32_bits(ring->gpu_addr)); 649 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_SIZE2), ring->ring_size / 4); 650 651 return 0; 652 } 653 654 /** 655 * vcn_v1_0_stop - stop VCN block 656 * 657 * @adev: amdgpu_device pointer 658 * 659 * stop the VCN block 660 */ 661 static int vcn_v1_0_stop(struct amdgpu_device *adev) 662 { 663 /* force RBC into idle state */ 664 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0x11010101); 665 666 /* Stall UMC and register bus before resetting VCPU */ 667 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 668 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 669 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 670 mdelay(1); 671 672 /* put VCPU into reset */ 673 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 674 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 675 mdelay(5); 676 677 /* disable VCPU clock */ 678 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0x0); 679 680 /* Unstall UMC and register bus */ 681 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, 682 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 683 684 /* enable clock gating */ 685 vcn_v1_0_enable_clock_gating(adev, true); 686 687 return 0; 688 } 689 690 static int vcn_v1_0_set_clockgating_state(void *handle, 691 enum amd_clockgating_state state) 692 { 693 /* needed for driver unload*/ 694 return 0; 695 } 696 697 /** 698 * vcn_v1_0_dec_ring_get_rptr - get read pointer 699 * 700 * @ring: amdgpu_ring pointer 701 * 702 * Returns the current hardware read pointer 703 */ 704 static uint64_t vcn_v1_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 705 { 706 struct amdgpu_device *adev = ring->adev; 707 708 return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_RPTR)); 709 } 710 711 /** 712 * vcn_v1_0_dec_ring_get_wptr - get write pointer 713 * 714 * @ring: amdgpu_ring pointer 715 * 716 * Returns the current hardware write pointer 717 */ 718 static uint64_t vcn_v1_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 719 { 720 struct amdgpu_device *adev = ring->adev; 721 722 return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_WPTR)); 723 } 724 725 /** 726 * vcn_v1_0_dec_ring_set_wptr - set write pointer 727 * 728 * @ring: amdgpu_ring pointer 729 * 730 * Commits the write pointer to the hardware 731 */ 732 static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 733 { 734 struct amdgpu_device *adev = ring->adev; 735 736 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_WPTR), lower_32_bits(ring->wptr)); 737 } 738 739 /** 740 * vcn_v1_0_dec_ring_insert_start - insert a start command 741 * 742 * @ring: amdgpu_ring pointer 743 * 744 * Write a start command to the ring. 745 */ 746 static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring) 747 { 748 amdgpu_ring_write(ring, 749 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 750 amdgpu_ring_write(ring, 0); 751 amdgpu_ring_write(ring, 752 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 753 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1); 754 } 755 756 /** 757 * vcn_v1_0_dec_ring_insert_end - insert a end command 758 * 759 * @ring: amdgpu_ring pointer 760 * 761 * Write a end command to the ring. 762 */ 763 static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring) 764 { 765 amdgpu_ring_write(ring, 766 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 767 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1); 768 } 769 770 /** 771 * vcn_v1_0_dec_ring_emit_fence - emit an fence & trap command 772 * 773 * @ring: amdgpu_ring pointer 774 * @fence: fence to emit 775 * 776 * Write a fence and a trap command to the ring. 777 */ 778 static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 779 unsigned flags) 780 { 781 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 782 783 amdgpu_ring_write(ring, 784 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0)); 785 amdgpu_ring_write(ring, seq); 786 amdgpu_ring_write(ring, 787 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 788 amdgpu_ring_write(ring, addr & 0xffffffff); 789 amdgpu_ring_write(ring, 790 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 791 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 792 amdgpu_ring_write(ring, 793 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 794 amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1); 795 796 amdgpu_ring_write(ring, 797 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 798 amdgpu_ring_write(ring, 0); 799 amdgpu_ring_write(ring, 800 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 801 amdgpu_ring_write(ring, 0); 802 amdgpu_ring_write(ring, 803 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 804 amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1); 805 } 806 807 /** 808 * vcn_v1_0_dec_ring_hdp_invalidate - emit an hdp invalidate 809 * 810 * @ring: amdgpu_ring pointer 811 * 812 * Emits an hdp invalidate. 813 */ 814 static void vcn_v1_0_dec_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) 815 { 816 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 0)); 817 amdgpu_ring_write(ring, 1); 818 } 819 820 /** 821 * vcn_v1_0_dec_ring_emit_ib - execute indirect buffer 822 * 823 * @ring: amdgpu_ring pointer 824 * @ib: indirect buffer to execute 825 * 826 * Write ring commands to execute the indirect buffer 827 */ 828 static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring, 829 struct amdgpu_ib *ib, 830 unsigned vm_id, bool ctx_switch) 831 { 832 amdgpu_ring_write(ring, 833 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0)); 834 amdgpu_ring_write(ring, vm_id); 835 836 amdgpu_ring_write(ring, 837 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0)); 838 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 839 amdgpu_ring_write(ring, 840 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0)); 841 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 842 amdgpu_ring_write(ring, 843 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0)); 844 amdgpu_ring_write(ring, ib->length_dw); 845 } 846 847 static void vcn_v1_0_dec_vm_reg_write(struct amdgpu_ring *ring, 848 uint32_t data0, uint32_t data1) 849 { 850 amdgpu_ring_write(ring, 851 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 852 amdgpu_ring_write(ring, data0); 853 amdgpu_ring_write(ring, 854 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 855 amdgpu_ring_write(ring, data1); 856 amdgpu_ring_write(ring, 857 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 858 amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1); 859 } 860 861 static void vcn_v1_0_dec_vm_reg_wait(struct amdgpu_ring *ring, 862 uint32_t data0, uint32_t data1, uint32_t mask) 863 { 864 amdgpu_ring_write(ring, 865 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 866 amdgpu_ring_write(ring, data0); 867 amdgpu_ring_write(ring, 868 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 869 amdgpu_ring_write(ring, data1); 870 amdgpu_ring_write(ring, 871 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0)); 872 amdgpu_ring_write(ring, mask); 873 amdgpu_ring_write(ring, 874 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 875 amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1); 876 } 877 878 static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, 879 unsigned vm_id, uint64_t pd_addr) 880 { 881 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 882 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id); 883 uint32_t data0, data1, mask; 884 unsigned eng = ring->vm_inv_eng; 885 886 pd_addr = pd_addr | 0x1; /* valid bit */ 887 /* now only use physical base address of PDE and valid */ 888 BUG_ON(pd_addr & 0xFFFF00000000003EULL); 889 890 data0 = (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2; 891 data1 = upper_32_bits(pd_addr); 892 vcn_v1_0_dec_vm_reg_write(ring, data0, data1); 893 894 data0 = (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2; 895 data1 = lower_32_bits(pd_addr); 896 vcn_v1_0_dec_vm_reg_write(ring, data0, data1); 897 898 data0 = (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2; 899 data1 = lower_32_bits(pd_addr); 900 mask = 0xffffffff; 901 vcn_v1_0_dec_vm_reg_wait(ring, data0, data1, mask); 902 903 /* flush TLB */ 904 data0 = (hub->vm_inv_eng0_req + eng) << 2; 905 data1 = req; 906 vcn_v1_0_dec_vm_reg_write(ring, data0, data1); 907 908 /* wait for flush */ 909 data0 = (hub->vm_inv_eng0_ack + eng) << 2; 910 data1 = 1 << vm_id; 911 mask = 1 << vm_id; 912 vcn_v1_0_dec_vm_reg_wait(ring, data0, data1, mask); 913 } 914 915 /** 916 * vcn_v1_0_enc_ring_get_rptr - get enc read pointer 917 * 918 * @ring: amdgpu_ring pointer 919 * 920 * Returns the current hardware enc read pointer 921 */ 922 static uint64_t vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 923 { 924 struct amdgpu_device *adev = ring->adev; 925 926 if (ring == &adev->vcn.ring_enc[0]) 927 return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_RPTR)); 928 else 929 return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_RPTR2)); 930 } 931 932 /** 933 * vcn_v1_0_enc_ring_get_wptr - get enc write pointer 934 * 935 * @ring: amdgpu_ring pointer 936 * 937 * Returns the current hardware enc write pointer 938 */ 939 static uint64_t vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 940 { 941 struct amdgpu_device *adev = ring->adev; 942 943 if (ring == &adev->vcn.ring_enc[0]) 944 return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR)); 945 else 946 return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR2)); 947 } 948 949 /** 950 * vcn_v1_0_enc_ring_set_wptr - set enc write pointer 951 * 952 * @ring: amdgpu_ring pointer 953 * 954 * Commits the enc write pointer to the hardware 955 */ 956 static void vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 957 { 958 struct amdgpu_device *adev = ring->adev; 959 960 if (ring == &adev->vcn.ring_enc[0]) 961 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR), 962 lower_32_bits(ring->wptr)); 963 else 964 WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR2), 965 lower_32_bits(ring->wptr)); 966 } 967 968 /** 969 * vcn_v1_0_enc_ring_emit_fence - emit an enc fence & trap command 970 * 971 * @ring: amdgpu_ring pointer 972 * @fence: fence to emit 973 * 974 * Write enc a fence and a trap command to the ring. 975 */ 976 static void vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 977 u64 seq, unsigned flags) 978 { 979 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 980 981 amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE); 982 amdgpu_ring_write(ring, addr); 983 amdgpu_ring_write(ring, upper_32_bits(addr)); 984 amdgpu_ring_write(ring, seq); 985 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP); 986 } 987 988 static void vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring *ring) 989 { 990 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 991 } 992 993 /** 994 * vcn_v1_0_enc_ring_emit_ib - enc execute indirect buffer 995 * 996 * @ring: amdgpu_ring pointer 997 * @ib: indirect buffer to execute 998 * 999 * Write enc ring commands to execute the indirect buffer 1000 */ 1001 static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring, 1002 struct amdgpu_ib *ib, unsigned int vm_id, bool ctx_switch) 1003 { 1004 amdgpu_ring_write(ring, VCN_ENC_CMD_IB); 1005 amdgpu_ring_write(ring, vm_id); 1006 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1007 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1008 amdgpu_ring_write(ring, ib->length_dw); 1009 } 1010 1011 static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1012 unsigned int vm_id, uint64_t pd_addr) 1013 { 1014 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1015 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id); 1016 unsigned eng = ring->vm_inv_eng; 1017 1018 pd_addr = pd_addr | 0x1; /* valid bit */ 1019 /* now only use physical base address of PDE and valid */ 1020 BUG_ON(pd_addr & 0xFFFF00000000003EULL); 1021 1022 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); 1023 amdgpu_ring_write(ring, 1024 (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2); 1025 amdgpu_ring_write(ring, upper_32_bits(pd_addr)); 1026 1027 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); 1028 amdgpu_ring_write(ring, 1029 (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2); 1030 amdgpu_ring_write(ring, lower_32_bits(pd_addr)); 1031 1032 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); 1033 amdgpu_ring_write(ring, 1034 (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2); 1035 amdgpu_ring_write(ring, 0xffffffff); 1036 amdgpu_ring_write(ring, lower_32_bits(pd_addr)); 1037 1038 /* flush TLB */ 1039 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); 1040 amdgpu_ring_write(ring, (hub->vm_inv_eng0_req + eng) << 2); 1041 amdgpu_ring_write(ring, req); 1042 1043 /* wait for flush */ 1044 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); 1045 amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2); 1046 amdgpu_ring_write(ring, 1 << vm_id); 1047 amdgpu_ring_write(ring, 1 << vm_id); 1048 } 1049 1050 static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev, 1051 struct amdgpu_irq_src *source, 1052 unsigned type, 1053 enum amdgpu_interrupt_state state) 1054 { 1055 return 0; 1056 } 1057 1058 static int vcn_v1_0_process_interrupt(struct amdgpu_device *adev, 1059 struct amdgpu_irq_src *source, 1060 struct amdgpu_iv_entry *entry) 1061 { 1062 DRM_DEBUG("IH: VCN TRAP\n"); 1063 1064 switch (entry->src_id) { 1065 case 124: 1066 amdgpu_fence_process(&adev->vcn.ring_dec); 1067 break; 1068 case 119: 1069 amdgpu_fence_process(&adev->vcn.ring_enc[0]); 1070 break; 1071 case 120: 1072 amdgpu_fence_process(&adev->vcn.ring_enc[1]); 1073 break; 1074 default: 1075 DRM_ERROR("Unhandled interrupt: %d %d\n", 1076 entry->src_id, entry->src_data[0]); 1077 break; 1078 } 1079 1080 return 0; 1081 } 1082 1083 static const struct amd_ip_funcs vcn_v1_0_ip_funcs = { 1084 .name = "vcn_v1_0", 1085 .early_init = vcn_v1_0_early_init, 1086 .late_init = NULL, 1087 .sw_init = vcn_v1_0_sw_init, 1088 .sw_fini = vcn_v1_0_sw_fini, 1089 .hw_init = vcn_v1_0_hw_init, 1090 .hw_fini = vcn_v1_0_hw_fini, 1091 .suspend = vcn_v1_0_suspend, 1092 .resume = vcn_v1_0_resume, 1093 .is_idle = NULL /* vcn_v1_0_is_idle */, 1094 .wait_for_idle = NULL /* vcn_v1_0_wait_for_idle */, 1095 .check_soft_reset = NULL /* vcn_v1_0_check_soft_reset */, 1096 .pre_soft_reset = NULL /* vcn_v1_0_pre_soft_reset */, 1097 .soft_reset = NULL /* vcn_v1_0_soft_reset */, 1098 .post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */, 1099 .set_clockgating_state = vcn_v1_0_set_clockgating_state, 1100 .set_powergating_state = NULL /* vcn_v1_0_set_powergating_state */, 1101 }; 1102 1103 static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = { 1104 .type = AMDGPU_RING_TYPE_VCN_DEC, 1105 .align_mask = 0xf, 1106 .nop = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0), 1107 .support_64bit_ptrs = false, 1108 .get_rptr = vcn_v1_0_dec_ring_get_rptr, 1109 .get_wptr = vcn_v1_0_dec_ring_get_wptr, 1110 .set_wptr = vcn_v1_0_dec_ring_set_wptr, 1111 .emit_frame_size = 1112 2 + /* vcn_v1_0_dec_ring_emit_hdp_invalidate */ 1113 34 * AMDGPU_MAX_VMHUBS + /* vcn_v1_0_dec_ring_emit_vm_flush */ 1114 14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */ 1115 6, 1116 .emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */ 1117 .emit_ib = vcn_v1_0_dec_ring_emit_ib, 1118 .emit_fence = vcn_v1_0_dec_ring_emit_fence, 1119 .emit_vm_flush = vcn_v1_0_dec_ring_emit_vm_flush, 1120 .emit_hdp_invalidate = vcn_v1_0_dec_ring_emit_hdp_invalidate, 1121 .test_ring = amdgpu_vcn_dec_ring_test_ring, 1122 .test_ib = amdgpu_vcn_dec_ring_test_ib, 1123 .insert_nop = amdgpu_ring_insert_nop, 1124 .insert_start = vcn_v1_0_dec_ring_insert_start, 1125 .insert_end = vcn_v1_0_dec_ring_insert_end, 1126 .pad_ib = amdgpu_ring_generic_pad_ib, 1127 .begin_use = amdgpu_vcn_ring_begin_use, 1128 .end_use = amdgpu_vcn_ring_end_use, 1129 }; 1130 1131 static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = { 1132 .type = AMDGPU_RING_TYPE_VCN_ENC, 1133 .align_mask = 0x3f, 1134 .nop = VCN_ENC_CMD_NO_OP, 1135 .support_64bit_ptrs = false, 1136 .get_rptr = vcn_v1_0_enc_ring_get_rptr, 1137 .get_wptr = vcn_v1_0_enc_ring_get_wptr, 1138 .set_wptr = vcn_v1_0_enc_ring_set_wptr, 1139 .emit_frame_size = 1140 17 * AMDGPU_MAX_VMHUBS + /* vcn_v1_0_enc_ring_emit_vm_flush */ 1141 5 + 5 + /* vcn_v1_0_enc_ring_emit_fence x2 vm fence */ 1142 1, /* vcn_v1_0_enc_ring_insert_end */ 1143 .emit_ib_size = 5, /* vcn_v1_0_enc_ring_emit_ib */ 1144 .emit_ib = vcn_v1_0_enc_ring_emit_ib, 1145 .emit_fence = vcn_v1_0_enc_ring_emit_fence, 1146 .emit_vm_flush = vcn_v1_0_enc_ring_emit_vm_flush, 1147 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1148 .test_ib = amdgpu_vcn_enc_ring_test_ib, 1149 .insert_nop = amdgpu_ring_insert_nop, 1150 .insert_end = vcn_v1_0_enc_ring_insert_end, 1151 .pad_ib = amdgpu_ring_generic_pad_ib, 1152 .begin_use = amdgpu_vcn_ring_begin_use, 1153 .end_use = amdgpu_vcn_ring_end_use, 1154 }; 1155 1156 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev) 1157 { 1158 adev->vcn.ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs; 1159 DRM_INFO("VCN decode is enabled in VM mode\n"); 1160 } 1161 1162 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev) 1163 { 1164 int i; 1165 1166 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 1167 adev->vcn.ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs; 1168 1169 DRM_INFO("VCN encode is enabled in VM mode\n"); 1170 } 1171 1172 static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = { 1173 .set = vcn_v1_0_set_interrupt_state, 1174 .process = vcn_v1_0_process_interrupt, 1175 }; 1176 1177 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev) 1178 { 1179 adev->uvd.irq.num_types = adev->vcn.num_enc_rings + 1; 1180 adev->vcn.irq.funcs = &vcn_v1_0_irq_funcs; 1181 } 1182 1183 const struct amdgpu_ip_block_version vcn_v1_0_ip_block = 1184 { 1185 .type = AMD_IP_BLOCK_TYPE_VCN, 1186 .major = 1, 1187 .minor = 0, 1188 .rev = 0, 1189 .funcs = &vcn_v1_0_ip_funcs, 1190 }; 1191